2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 #include <linux/kthread.h>
29 #include <linux/console.h>
30 #include <linux/slab.h>
32 #include <drm/drm_crtc_helper.h>
33 #include <drm/drm_atomic_helper.h>
34 #include <drm/amdgpu_drm.h>
35 #include <linux/vgaarb.h>
36 #include <linux/vga_switcheroo.h>
37 #include <linux/efi.h>
39 #include "amdgpu_trace.h"
40 #include "amdgpu_i2c.h"
42 #include "amdgpu_atombios.h"
43 #include "amdgpu_atomfirmware.h"
45 #ifdef CONFIG_DRM_AMDGPU_SI
48 #ifdef CONFIG_DRM_AMDGPU_CIK
53 #include "bif/bif_4_1_d.h"
54 #include <linux/pci.h>
55 #include <linux/firmware.h>
56 #include "amdgpu_vf_error.h"
58 #include "amdgpu_amdkfd.h"
59 #include "amdgpu_pm.h"
61 MODULE_FIRMWARE("amdgpu/vega10_gpu_info.bin");
62 MODULE_FIRMWARE("amdgpu/raven_gpu_info.bin");
64 #define AMDGPU_RESUME_MS 2000
66 static const char *amdgpu_asic_name[] = {
90 bool amdgpu_device_is_px(struct drm_device *dev)
92 struct amdgpu_device *adev = dev->dev_private;
94 if (adev->flags & AMD_IS_PX)
100 * MMIO register access helper functions.
102 uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg,
107 if (!(acc_flags & AMDGPU_REGS_NO_KIQ) && amdgpu_sriov_runtime(adev))
108 return amdgpu_virt_kiq_rreg(adev, reg);
110 if ((reg * 4) < adev->rmmio_size && !(acc_flags & AMDGPU_REGS_IDX))
111 ret = readl(((void __iomem *)adev->rmmio) + (reg * 4));
115 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
116 writel((reg * 4), ((void __iomem *)adev->rmmio) + (mmMM_INDEX * 4));
117 ret = readl(((void __iomem *)adev->rmmio) + (mmMM_DATA * 4));
118 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
120 trace_amdgpu_mm_rreg(adev->pdev->device, reg, ret);
124 void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v,
127 trace_amdgpu_mm_wreg(adev->pdev->device, reg, v);
129 if (adev->asic_type >= CHIP_VEGA10 && reg == 0) {
130 adev->last_mm_index = v;
133 if (!(acc_flags & AMDGPU_REGS_NO_KIQ) && amdgpu_sriov_runtime(adev))
134 return amdgpu_virt_kiq_wreg(adev, reg, v);
136 if ((reg * 4) < adev->rmmio_size && !(acc_flags & AMDGPU_REGS_IDX))
137 writel(v, ((void __iomem *)adev->rmmio) + (reg * 4));
141 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
142 writel((reg * 4), ((void __iomem *)adev->rmmio) + (mmMM_INDEX * 4));
143 writel(v, ((void __iomem *)adev->rmmio) + (mmMM_DATA * 4));
144 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
147 if (adev->asic_type >= CHIP_VEGA10 && reg == 1 && adev->last_mm_index == 0x5702C) {
152 u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg)
154 if ((reg * 4) < adev->rio_mem_size)
155 return ioread32(adev->rio_mem + (reg * 4));
157 iowrite32((reg * 4), adev->rio_mem + (mmMM_INDEX * 4));
158 return ioread32(adev->rio_mem + (mmMM_DATA * 4));
162 void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
164 if (adev->asic_type >= CHIP_VEGA10 && reg == 0) {
165 adev->last_mm_index = v;
168 if ((reg * 4) < adev->rio_mem_size)
169 iowrite32(v, adev->rio_mem + (reg * 4));
171 iowrite32((reg * 4), adev->rio_mem + (mmMM_INDEX * 4));
172 iowrite32(v, adev->rio_mem + (mmMM_DATA * 4));
175 if (adev->asic_type >= CHIP_VEGA10 && reg == 1 && adev->last_mm_index == 0x5702C) {
181 * amdgpu_mm_rdoorbell - read a doorbell dword
183 * @adev: amdgpu_device pointer
184 * @index: doorbell index
186 * Returns the value in the doorbell aperture at the
187 * requested doorbell index (CIK).
189 u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index)
191 if (index < adev->doorbell.num_doorbells) {
192 return readl(adev->doorbell.ptr + index);
194 DRM_ERROR("reading beyond doorbell aperture: 0x%08x!\n", index);
200 * amdgpu_mm_wdoorbell - write a doorbell dword
202 * @adev: amdgpu_device pointer
203 * @index: doorbell index
206 * Writes @v to the doorbell aperture at the
207 * requested doorbell index (CIK).
209 void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v)
211 if (index < adev->doorbell.num_doorbells) {
212 writel(v, adev->doorbell.ptr + index);
214 DRM_ERROR("writing beyond doorbell aperture: 0x%08x!\n", index);
219 * amdgpu_mm_rdoorbell64 - read a doorbell Qword
221 * @adev: amdgpu_device pointer
222 * @index: doorbell index
224 * Returns the value in the doorbell aperture at the
225 * requested doorbell index (VEGA10+).
227 u64 amdgpu_mm_rdoorbell64(struct amdgpu_device *adev, u32 index)
229 if (index < adev->doorbell.num_doorbells) {
230 return atomic64_read((atomic64_t *)(adev->doorbell.ptr + index));
232 DRM_ERROR("reading beyond doorbell aperture: 0x%08x!\n", index);
238 * amdgpu_mm_wdoorbell64 - write a doorbell Qword
240 * @adev: amdgpu_device pointer
241 * @index: doorbell index
244 * Writes @v to the doorbell aperture at the
245 * requested doorbell index (VEGA10+).
247 void amdgpu_mm_wdoorbell64(struct amdgpu_device *adev, u32 index, u64 v)
249 if (index < adev->doorbell.num_doorbells) {
250 atomic64_set((atomic64_t *)(adev->doorbell.ptr + index), v);
252 DRM_ERROR("writing beyond doorbell aperture: 0x%08x!\n", index);
257 * amdgpu_invalid_rreg - dummy reg read function
259 * @adev: amdgpu device pointer
260 * @reg: offset of register
262 * Dummy register read function. Used for register blocks
263 * that certain asics don't have (all asics).
264 * Returns the value in the register.
266 static uint32_t amdgpu_invalid_rreg(struct amdgpu_device *adev, uint32_t reg)
268 DRM_ERROR("Invalid callback to read register 0x%04X\n", reg);
274 * amdgpu_invalid_wreg - dummy reg write function
276 * @adev: amdgpu device pointer
277 * @reg: offset of register
278 * @v: value to write to the register
280 * Dummy register read function. Used for register blocks
281 * that certain asics don't have (all asics).
283 static void amdgpu_invalid_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v)
285 DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n",
291 * amdgpu_block_invalid_rreg - dummy reg read function
293 * @adev: amdgpu device pointer
294 * @block: offset of instance
295 * @reg: offset of register
297 * Dummy register read function. Used for register blocks
298 * that certain asics don't have (all asics).
299 * Returns the value in the register.
301 static uint32_t amdgpu_block_invalid_rreg(struct amdgpu_device *adev,
302 uint32_t block, uint32_t reg)
304 DRM_ERROR("Invalid callback to read register 0x%04X in block 0x%04X\n",
311 * amdgpu_block_invalid_wreg - dummy reg write function
313 * @adev: amdgpu device pointer
314 * @block: offset of instance
315 * @reg: offset of register
316 * @v: value to write to the register
318 * Dummy register read function. Used for register blocks
319 * that certain asics don't have (all asics).
321 static void amdgpu_block_invalid_wreg(struct amdgpu_device *adev,
323 uint32_t reg, uint32_t v)
325 DRM_ERROR("Invalid block callback to write register 0x%04X in block 0x%04X with 0x%08X\n",
330 static int amdgpu_device_vram_scratch_init(struct amdgpu_device *adev)
332 return amdgpu_bo_create_kernel(adev, AMDGPU_GPU_PAGE_SIZE,
333 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
334 &adev->vram_scratch.robj,
335 &adev->vram_scratch.gpu_addr,
336 (void **)&adev->vram_scratch.ptr);
339 static void amdgpu_device_vram_scratch_fini(struct amdgpu_device *adev)
341 amdgpu_bo_free_kernel(&adev->vram_scratch.robj, NULL, NULL);
345 * amdgpu_program_register_sequence - program an array of registers.
347 * @adev: amdgpu_device pointer
348 * @registers: pointer to the register array
349 * @array_size: size of the register array
351 * Programs an array or registers with and and or masks.
352 * This is a helper for setting golden registers.
354 void amdgpu_program_register_sequence(struct amdgpu_device *adev,
355 const u32 *registers,
356 const u32 array_size)
358 u32 tmp, reg, and_mask, or_mask;
364 for (i = 0; i < array_size; i +=3) {
365 reg = registers[i + 0];
366 and_mask = registers[i + 1];
367 or_mask = registers[i + 2];
369 if (and_mask == 0xffffffff) {
380 void amdgpu_pci_config_reset(struct amdgpu_device *adev)
382 pci_write_config_dword(adev->pdev, 0x7c, AMDGPU_ASIC_RESET_DATA);
386 * GPU doorbell aperture helpers function.
389 * amdgpu_device_doorbell_init - Init doorbell driver information.
391 * @adev: amdgpu_device pointer
393 * Init doorbell driver information (CIK)
394 * Returns 0 on success, error on failure.
396 static int amdgpu_device_doorbell_init(struct amdgpu_device *adev)
398 /* No doorbell on SI hardware generation */
399 if (adev->asic_type < CHIP_BONAIRE) {
400 adev->doorbell.base = 0;
401 adev->doorbell.size = 0;
402 adev->doorbell.num_doorbells = 0;
403 adev->doorbell.ptr = NULL;
407 if (pci_resource_flags(adev->pdev, 2) & IORESOURCE_UNSET)
410 /* doorbell bar mapping */
411 adev->doorbell.base = pci_resource_start(adev->pdev, 2);
412 adev->doorbell.size = pci_resource_len(adev->pdev, 2);
414 adev->doorbell.num_doorbells = min_t(u32, adev->doorbell.size / sizeof(u32),
415 AMDGPU_DOORBELL_MAX_ASSIGNMENT+1);
416 if (adev->doorbell.num_doorbells == 0)
419 adev->doorbell.ptr = ioremap(adev->doorbell.base,
420 adev->doorbell.num_doorbells *
422 if (adev->doorbell.ptr == NULL)
429 * amdgpu_device_doorbell_fini - Tear down doorbell driver information.
431 * @adev: amdgpu_device pointer
433 * Tear down doorbell driver information (CIK)
435 static void amdgpu_device_doorbell_fini(struct amdgpu_device *adev)
437 iounmap(adev->doorbell.ptr);
438 adev->doorbell.ptr = NULL;
442 * amdgpu_doorbell_get_kfd_info - Report doorbell configuration required to
445 * @adev: amdgpu_device pointer
446 * @aperture_base: output returning doorbell aperture base physical address
447 * @aperture_size: output returning doorbell aperture size in bytes
448 * @start_offset: output returning # of doorbell bytes reserved for amdgpu.
450 * amdgpu and amdkfd share the doorbell aperture. amdgpu sets it up,
451 * takes doorbells required for its own rings and reports the setup to amdkfd.
452 * amdgpu reserved doorbells are at the start of the doorbell aperture.
454 void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev,
455 phys_addr_t *aperture_base,
456 size_t *aperture_size,
457 size_t *start_offset)
460 * The first num_doorbells are used by amdgpu.
461 * amdkfd takes whatever's left in the aperture.
463 if (adev->doorbell.size > adev->doorbell.num_doorbells * sizeof(u32)) {
464 *aperture_base = adev->doorbell.base;
465 *aperture_size = adev->doorbell.size;
466 *start_offset = adev->doorbell.num_doorbells * sizeof(u32);
475 * amdgpu_device_wb_*()
476 * Writeback is the method by which the GPU updates special pages in memory
477 * with the status of certain GPU events (fences, ring pointers,etc.).
481 * amdgpu_device_wb_fini - Disable Writeback and free memory
483 * @adev: amdgpu_device pointer
485 * Disables Writeback and frees the Writeback memory (all asics).
486 * Used at driver shutdown.
488 static void amdgpu_device_wb_fini(struct amdgpu_device *adev)
490 if (adev->wb.wb_obj) {
491 amdgpu_bo_free_kernel(&adev->wb.wb_obj,
493 (void **)&adev->wb.wb);
494 adev->wb.wb_obj = NULL;
499 * amdgpu_device_wb_init- Init Writeback driver info and allocate memory
501 * @adev: amdgpu_device pointer
503 * Initializes writeback and allocates writeback memory (all asics).
504 * Used at driver startup.
505 * Returns 0 on success or an -error on failure.
507 static int amdgpu_device_wb_init(struct amdgpu_device *adev)
511 if (adev->wb.wb_obj == NULL) {
512 /* AMDGPU_MAX_WB * sizeof(uint32_t) * 8 = AMDGPU_MAX_WB 256bit slots */
513 r = amdgpu_bo_create_kernel(adev, AMDGPU_MAX_WB * sizeof(uint32_t) * 8,
514 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
515 &adev->wb.wb_obj, &adev->wb.gpu_addr,
516 (void **)&adev->wb.wb);
518 dev_warn(adev->dev, "(%d) create WB bo failed\n", r);
522 adev->wb.num_wb = AMDGPU_MAX_WB;
523 memset(&adev->wb.used, 0, sizeof(adev->wb.used));
525 /* clear wb memory */
526 memset((char *)adev->wb.wb, 0, AMDGPU_MAX_WB * sizeof(uint32_t));
533 * amdgpu_device_wb_get - Allocate a wb entry
535 * @adev: amdgpu_device pointer
538 * Allocate a wb slot for use by the driver (all asics).
539 * Returns 0 on success or -EINVAL on failure.
541 int amdgpu_device_wb_get(struct amdgpu_device *adev, u32 *wb)
543 unsigned long offset = find_first_zero_bit(adev->wb.used, adev->wb.num_wb);
545 if (offset < adev->wb.num_wb) {
546 __set_bit(offset, adev->wb.used);
547 *wb = offset << 3; /* convert to dw offset */
555 * amdgpu_device_wb_free - Free a wb entry
557 * @adev: amdgpu_device pointer
560 * Free a wb slot allocated for use by the driver (all asics)
562 void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb)
564 if (wb < adev->wb.num_wb)
565 __clear_bit(wb >> 3, adev->wb.used);
569 * amdgpu_vram_location - try to find VRAM location
570 * @adev: amdgpu device structure holding all necessary informations
571 * @mc: memory controller structure holding memory informations
572 * @base: base address at which to put VRAM
574 * Function will try to place VRAM at base address provided
577 void amdgpu_vram_location(struct amdgpu_device *adev, struct amdgpu_mc *mc, u64 base)
579 uint64_t limit = (uint64_t)amdgpu_vram_limit << 20;
581 mc->vram_start = base;
582 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
583 if (limit && limit < mc->real_vram_size)
584 mc->real_vram_size = limit;
585 dev_info(adev->dev, "VRAM: %lluM 0x%016llX - 0x%016llX (%lluM used)\n",
586 mc->mc_vram_size >> 20, mc->vram_start,
587 mc->vram_end, mc->real_vram_size >> 20);
591 * amdgpu_gart_location - try to find GTT location
592 * @adev: amdgpu device structure holding all necessary informations
593 * @mc: memory controller structure holding memory informations
595 * Function will place try to place GTT before or after VRAM.
597 * If GTT size is bigger than space left then we ajust GTT size.
598 * Thus function will never fails.
600 * FIXME: when reducing GTT size align new size on power of 2.
602 void amdgpu_gart_location(struct amdgpu_device *adev, struct amdgpu_mc *mc)
604 u64 size_af, size_bf;
606 size_af = adev->mc.mc_mask - mc->vram_end;
607 size_bf = mc->vram_start;
608 if (size_bf > size_af) {
609 if (mc->gart_size > size_bf) {
610 dev_warn(adev->dev, "limiting GTT\n");
611 mc->gart_size = size_bf;
615 if (mc->gart_size > size_af) {
616 dev_warn(adev->dev, "limiting GTT\n");
617 mc->gart_size = size_af;
619 /* VCE doesn't like it when BOs cross a 4GB segment, so align
620 * the GART base on a 4GB boundary as well.
622 mc->gart_start = ALIGN(mc->vram_end + 1, 0x100000000ULL);
624 mc->gart_end = mc->gart_start + mc->gart_size - 1;
625 dev_info(adev->dev, "GTT: %lluM 0x%016llX - 0x%016llX\n",
626 mc->gart_size >> 20, mc->gart_start, mc->gart_end);
630 * Firmware Reservation functions
633 * amdgpu_fw_reserve_vram_fini - free fw reserved vram
635 * @adev: amdgpu_device pointer
637 * free fw reserved vram if it has been reserved.
639 void amdgpu_fw_reserve_vram_fini(struct amdgpu_device *adev)
641 amdgpu_bo_free_kernel(&adev->fw_vram_usage.reserved_bo,
642 NULL, &adev->fw_vram_usage.va);
646 * amdgpu_fw_reserve_vram_init - create bo vram reservation from fw
648 * @adev: amdgpu_device pointer
650 * create bo vram reservation from fw.
652 int amdgpu_fw_reserve_vram_init(struct amdgpu_device *adev)
654 struct ttm_operation_ctx ctx = { false, false };
657 u64 vram_size = adev->mc.visible_vram_size;
658 u64 offset = adev->fw_vram_usage.start_offset;
659 u64 size = adev->fw_vram_usage.size;
660 struct amdgpu_bo *bo;
662 adev->fw_vram_usage.va = NULL;
663 adev->fw_vram_usage.reserved_bo = NULL;
665 if (adev->fw_vram_usage.size > 0 &&
666 adev->fw_vram_usage.size <= vram_size) {
668 r = amdgpu_bo_create(adev, adev->fw_vram_usage.size,
669 PAGE_SIZE, true, AMDGPU_GEM_DOMAIN_VRAM,
670 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
671 AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS, NULL, NULL, 0,
672 &adev->fw_vram_usage.reserved_bo);
676 r = amdgpu_bo_reserve(adev->fw_vram_usage.reserved_bo, false);
680 /* remove the original mem node and create a new one at the
683 bo = adev->fw_vram_usage.reserved_bo;
684 offset = ALIGN(offset, PAGE_SIZE);
685 for (i = 0; i < bo->placement.num_placement; ++i) {
686 bo->placements[i].fpfn = offset >> PAGE_SHIFT;
687 bo->placements[i].lpfn = (offset + size) >> PAGE_SHIFT;
690 ttm_bo_mem_put(&bo->tbo, &bo->tbo.mem);
691 r = ttm_bo_mem_space(&bo->tbo, &bo->placement,
696 r = amdgpu_bo_pin_restricted(adev->fw_vram_usage.reserved_bo,
697 AMDGPU_GEM_DOMAIN_VRAM,
698 adev->fw_vram_usage.start_offset,
699 (adev->fw_vram_usage.start_offset +
700 adev->fw_vram_usage.size), NULL);
703 r = amdgpu_bo_kmap(adev->fw_vram_usage.reserved_bo,
704 &adev->fw_vram_usage.va);
708 amdgpu_bo_unreserve(adev->fw_vram_usage.reserved_bo);
713 amdgpu_bo_unpin(adev->fw_vram_usage.reserved_bo);
715 amdgpu_bo_unreserve(adev->fw_vram_usage.reserved_bo);
717 amdgpu_bo_unref(&adev->fw_vram_usage.reserved_bo);
719 adev->fw_vram_usage.va = NULL;
720 adev->fw_vram_usage.reserved_bo = NULL;
725 * amdgpu_device_resize_fb_bar - try to resize FB BAR
727 * @adev: amdgpu_device pointer
729 * Try to resize FB BAR to make all VRAM CPU accessible. We try very hard not
730 * to fail, but if any of the BARs is not accessible after the size we abort
731 * driver loading by returning -ENODEV.
733 int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev)
735 u64 space_needed = roundup_pow_of_two(adev->mc.real_vram_size);
736 u32 rbar_size = order_base_2(((space_needed >> 20) | 1)) - 1;
737 struct pci_bus *root;
738 struct resource *res;
744 if (amdgpu_sriov_vf(adev))
747 /* Check if the root BUS has 64bit memory resources */
748 root = adev->pdev->bus;
752 pci_bus_for_each_resource(root, res, i) {
753 if (res && res->flags & IORESOURCE_MEM_64 &&
754 res->start > 0x100000000ull)
758 /* Trying to resize is pointless without a root hub window above 4GB */
762 /* Disable memory decoding while we change the BAR addresses and size */
763 pci_read_config_word(adev->pdev, PCI_COMMAND, &cmd);
764 pci_write_config_word(adev->pdev, PCI_COMMAND,
765 cmd & ~PCI_COMMAND_MEMORY);
767 /* Free the VRAM and doorbell BAR, we most likely need to move both. */
768 amdgpu_device_doorbell_fini(adev);
769 if (adev->asic_type >= CHIP_BONAIRE)
770 pci_release_resource(adev->pdev, 2);
772 pci_release_resource(adev->pdev, 0);
774 r = pci_resize_resource(adev->pdev, 0, rbar_size);
776 DRM_INFO("Not enough PCI address space for a large BAR.");
777 else if (r && r != -ENOTSUPP)
778 DRM_ERROR("Problem resizing BAR0 (%d).", r);
780 pci_assign_unassigned_bus_resources(adev->pdev->bus);
782 /* When the doorbell or fb BAR isn't available we have no chance of
785 r = amdgpu_device_doorbell_init(adev);
786 if (r || (pci_resource_flags(adev->pdev, 0) & IORESOURCE_UNSET))
789 pci_write_config_word(adev->pdev, PCI_COMMAND, cmd);
795 * GPU helpers function.
798 * amdgpu_need_post - check if the hw need post or not
800 * @adev: amdgpu_device pointer
802 * Check if the asic has been initialized (all asics) at driver startup
803 * or post is needed if hw reset is performed.
804 * Returns true if need or false if not.
806 bool amdgpu_need_post(struct amdgpu_device *adev)
810 if (amdgpu_sriov_vf(adev))
813 if (amdgpu_passthrough(adev)) {
814 /* for FIJI: In whole GPU pass-through virtualization case, after VM reboot
815 * some old smc fw still need driver do vPost otherwise gpu hang, while
816 * those smc fw version above 22.15 doesn't have this flaw, so we force
817 * vpost executed for smc version below 22.15
819 if (adev->asic_type == CHIP_FIJI) {
822 err = request_firmware(&adev->pm.fw, "amdgpu/fiji_smc.bin", adev->dev);
823 /* force vPost if error occured */
827 fw_ver = *((uint32_t *)adev->pm.fw->data + 69);
828 if (fw_ver < 0x00160e00)
833 if (adev->has_hw_reset) {
834 adev->has_hw_reset = false;
838 /* bios scratch used on CIK+ */
839 if (adev->asic_type >= CHIP_BONAIRE)
840 return amdgpu_atombios_scratch_need_asic_init(adev);
842 /* check MEM_SIZE for older asics */
843 reg = amdgpu_asic_get_config_memsize(adev);
845 if ((reg != 0) && (reg != 0xffffffff))
852 * amdgpu_dummy_page_init - init dummy page used by the driver
854 * @adev: amdgpu_device pointer
856 * Allocate the dummy page used by the driver (all asics).
857 * This dummy page is used by the driver as a filler for gart entries
858 * when pages are taken out of the GART
859 * Returns 0 on sucess, -ENOMEM on failure.
861 int amdgpu_dummy_page_init(struct amdgpu_device *adev)
863 if (adev->dummy_page.page)
865 adev->dummy_page.page = alloc_page(GFP_DMA32 | GFP_KERNEL | __GFP_ZERO);
866 if (adev->dummy_page.page == NULL)
868 adev->dummy_page.addr = pci_map_page(adev->pdev, adev->dummy_page.page,
869 0, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
870 if (pci_dma_mapping_error(adev->pdev, adev->dummy_page.addr)) {
871 dev_err(&adev->pdev->dev, "Failed to DMA MAP the dummy page\n");
872 __free_page(adev->dummy_page.page);
873 adev->dummy_page.page = NULL;
880 * amdgpu_dummy_page_fini - free dummy page used by the driver
882 * @adev: amdgpu_device pointer
884 * Frees the dummy page used by the driver (all asics).
886 void amdgpu_dummy_page_fini(struct amdgpu_device *adev)
888 if (adev->dummy_page.page == NULL)
890 pci_unmap_page(adev->pdev, adev->dummy_page.addr,
891 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
892 __free_page(adev->dummy_page.page);
893 adev->dummy_page.page = NULL;
896 /* if we get transitioned to only one device, take VGA back */
898 * amdgpu_device_vga_set_decode - enable/disable vga decode
900 * @cookie: amdgpu_device pointer
901 * @state: enable/disable vga decode
903 * Enable/disable vga decode (all asics).
904 * Returns VGA resource flags.
906 static unsigned int amdgpu_device_vga_set_decode(void *cookie, bool state)
908 struct amdgpu_device *adev = cookie;
909 amdgpu_asic_set_vga_state(adev, state);
911 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
912 VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
914 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
917 static void amdgpu_device_check_block_size(struct amdgpu_device *adev)
919 /* defines number of bits in page table versus page directory,
920 * a page is 4KB so we have 12 bits offset, minimum 9 bits in the
921 * page table and the remaining bits are in the page directory */
922 if (amdgpu_vm_block_size == -1)
925 if (amdgpu_vm_block_size < 9) {
926 dev_warn(adev->dev, "VM page table size (%d) too small\n",
927 amdgpu_vm_block_size);
928 amdgpu_vm_block_size = -1;
932 static void amdgpu_device_check_vm_size(struct amdgpu_device *adev)
934 /* no need to check the default value */
935 if (amdgpu_vm_size == -1)
938 if (amdgpu_vm_size < 1) {
939 dev_warn(adev->dev, "VM size (%d) too small, min is 1GB\n",
946 * amdgpu_device_check_arguments - validate module params
948 * @adev: amdgpu_device pointer
950 * Validates certain module parameters and updates
951 * the associated values used by the driver (all asics).
953 static void amdgpu_device_check_arguments(struct amdgpu_device *adev)
955 if (amdgpu_sched_jobs < 4) {
956 dev_warn(adev->dev, "sched jobs (%d) must be at least 4\n",
958 amdgpu_sched_jobs = 4;
959 } else if (!is_power_of_2(amdgpu_sched_jobs)){
960 dev_warn(adev->dev, "sched jobs (%d) must be a power of 2\n",
962 amdgpu_sched_jobs = roundup_pow_of_two(amdgpu_sched_jobs);
965 if (amdgpu_gart_size != -1 && amdgpu_gart_size < 32) {
966 /* gart size must be greater or equal to 32M */
967 dev_warn(adev->dev, "gart size (%d) too small\n",
969 amdgpu_gart_size = -1;
972 if (amdgpu_gtt_size != -1 && amdgpu_gtt_size < 32) {
973 /* gtt size must be greater or equal to 32M */
974 dev_warn(adev->dev, "gtt size (%d) too small\n",
976 amdgpu_gtt_size = -1;
979 /* valid range is between 4 and 9 inclusive */
980 if (amdgpu_vm_fragment_size != -1 &&
981 (amdgpu_vm_fragment_size > 9 || amdgpu_vm_fragment_size < 4)) {
982 dev_warn(adev->dev, "valid range is between 4 and 9\n");
983 amdgpu_vm_fragment_size = -1;
986 amdgpu_device_check_vm_size(adev);
988 amdgpu_device_check_block_size(adev);
990 if (amdgpu_vram_page_split != -1 && (amdgpu_vram_page_split < 16 ||
991 !is_power_of_2(amdgpu_vram_page_split))) {
992 dev_warn(adev->dev, "invalid VRAM page split (%d)\n",
993 amdgpu_vram_page_split);
994 amdgpu_vram_page_split = 1024;
997 if (amdgpu_lockup_timeout == 0) {
998 dev_warn(adev->dev, "lockup_timeout msut be > 0, adjusting to 10000\n");
999 amdgpu_lockup_timeout = 10000;
1004 * amdgpu_switcheroo_set_state - set switcheroo state
1006 * @pdev: pci dev pointer
1007 * @state: vga_switcheroo state
1009 * Callback for the switcheroo driver. Suspends or resumes the
1010 * the asics before or after it is powered up using ACPI methods.
1012 static void amdgpu_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
1014 struct drm_device *dev = pci_get_drvdata(pdev);
1016 if (amdgpu_device_is_px(dev) && state == VGA_SWITCHEROO_OFF)
1019 if (state == VGA_SWITCHEROO_ON) {
1020 pr_info("amdgpu: switched on\n");
1021 /* don't suspend or resume card normally */
1022 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1024 amdgpu_device_resume(dev, true, true);
1026 dev->switch_power_state = DRM_SWITCH_POWER_ON;
1027 drm_kms_helper_poll_enable(dev);
1029 pr_info("amdgpu: switched off\n");
1030 drm_kms_helper_poll_disable(dev);
1031 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1032 amdgpu_device_suspend(dev, true, true);
1033 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
1038 * amdgpu_switcheroo_can_switch - see if switcheroo state can change
1040 * @pdev: pci dev pointer
1042 * Callback for the switcheroo driver. Check of the switcheroo
1043 * state can be changed.
1044 * Returns true if the state can be changed, false if not.
1046 static bool amdgpu_switcheroo_can_switch(struct pci_dev *pdev)
1048 struct drm_device *dev = pci_get_drvdata(pdev);
1051 * FIXME: open_count is protected by drm_global_mutex but that would lead to
1052 * locking inversion with the driver load path. And the access here is
1053 * completely racy anyway. So don't bother with locking for now.
1055 return dev->open_count == 0;
1058 static const struct vga_switcheroo_client_ops amdgpu_switcheroo_ops = {
1059 .set_gpu_state = amdgpu_switcheroo_set_state,
1061 .can_switch = amdgpu_switcheroo_can_switch,
1064 int amdgpu_set_clockgating_state(struct amdgpu_device *adev,
1065 enum amd_ip_block_type block_type,
1066 enum amd_clockgating_state state)
1070 for (i = 0; i < adev->num_ip_blocks; i++) {
1071 if (!adev->ip_blocks[i].status.valid)
1073 if (adev->ip_blocks[i].version->type != block_type)
1075 if (!adev->ip_blocks[i].version->funcs->set_clockgating_state)
1077 r = adev->ip_blocks[i].version->funcs->set_clockgating_state(
1078 (void *)adev, state);
1080 DRM_ERROR("set_clockgating_state of IP block <%s> failed %d\n",
1081 adev->ip_blocks[i].version->funcs->name, r);
1086 int amdgpu_set_powergating_state(struct amdgpu_device *adev,
1087 enum amd_ip_block_type block_type,
1088 enum amd_powergating_state state)
1092 for (i = 0; i < adev->num_ip_blocks; i++) {
1093 if (!adev->ip_blocks[i].status.valid)
1095 if (adev->ip_blocks[i].version->type != block_type)
1097 if (!adev->ip_blocks[i].version->funcs->set_powergating_state)
1099 r = adev->ip_blocks[i].version->funcs->set_powergating_state(
1100 (void *)adev, state);
1102 DRM_ERROR("set_powergating_state of IP block <%s> failed %d\n",
1103 adev->ip_blocks[i].version->funcs->name, r);
1108 void amdgpu_get_clockgating_state(struct amdgpu_device *adev, u32 *flags)
1112 for (i = 0; i < adev->num_ip_blocks; i++) {
1113 if (!adev->ip_blocks[i].status.valid)
1115 if (adev->ip_blocks[i].version->funcs->get_clockgating_state)
1116 adev->ip_blocks[i].version->funcs->get_clockgating_state((void *)adev, flags);
1120 int amdgpu_wait_for_idle(struct amdgpu_device *adev,
1121 enum amd_ip_block_type block_type)
1125 for (i = 0; i < adev->num_ip_blocks; i++) {
1126 if (!adev->ip_blocks[i].status.valid)
1128 if (adev->ip_blocks[i].version->type == block_type) {
1129 r = adev->ip_blocks[i].version->funcs->wait_for_idle((void *)adev);
1139 bool amdgpu_is_idle(struct amdgpu_device *adev,
1140 enum amd_ip_block_type block_type)
1144 for (i = 0; i < adev->num_ip_blocks; i++) {
1145 if (!adev->ip_blocks[i].status.valid)
1147 if (adev->ip_blocks[i].version->type == block_type)
1148 return adev->ip_blocks[i].version->funcs->is_idle((void *)adev);
1154 struct amdgpu_ip_block * amdgpu_get_ip_block(struct amdgpu_device *adev,
1155 enum amd_ip_block_type type)
1159 for (i = 0; i < adev->num_ip_blocks; i++)
1160 if (adev->ip_blocks[i].version->type == type)
1161 return &adev->ip_blocks[i];
1167 * amdgpu_ip_block_version_cmp
1169 * @adev: amdgpu_device pointer
1170 * @type: enum amd_ip_block_type
1171 * @major: major version
1172 * @minor: minor version
1174 * return 0 if equal or greater
1175 * return 1 if smaller or the ip_block doesn't exist
1177 int amdgpu_ip_block_version_cmp(struct amdgpu_device *adev,
1178 enum amd_ip_block_type type,
1179 u32 major, u32 minor)
1181 struct amdgpu_ip_block *ip_block = amdgpu_get_ip_block(adev, type);
1183 if (ip_block && ((ip_block->version->major > major) ||
1184 ((ip_block->version->major == major) &&
1185 (ip_block->version->minor >= minor))))
1192 * amdgpu_ip_block_add
1194 * @adev: amdgpu_device pointer
1195 * @ip_block_version: pointer to the IP to add
1197 * Adds the IP block driver information to the collection of IPs
1200 int amdgpu_ip_block_add(struct amdgpu_device *adev,
1201 const struct amdgpu_ip_block_version *ip_block_version)
1203 if (!ip_block_version)
1206 DRM_DEBUG("add ip block number %d <%s>\n", adev->num_ip_blocks,
1207 ip_block_version->funcs->name);
1209 adev->ip_blocks[adev->num_ip_blocks++].version = ip_block_version;
1214 static void amdgpu_device_enable_virtual_display(struct amdgpu_device *adev)
1216 adev->enable_virtual_display = false;
1218 if (amdgpu_virtual_display) {
1219 struct drm_device *ddev = adev->ddev;
1220 const char *pci_address_name = pci_name(ddev->pdev);
1221 char *pciaddstr, *pciaddstr_tmp, *pciaddname_tmp, *pciaddname;
1223 pciaddstr = kstrdup(amdgpu_virtual_display, GFP_KERNEL);
1224 pciaddstr_tmp = pciaddstr;
1225 while ((pciaddname_tmp = strsep(&pciaddstr_tmp, ";"))) {
1226 pciaddname = strsep(&pciaddname_tmp, ",");
1227 if (!strcmp("all", pciaddname)
1228 || !strcmp(pci_address_name, pciaddname)) {
1232 adev->enable_virtual_display = true;
1235 res = kstrtol(pciaddname_tmp, 10,
1243 adev->mode_info.num_crtc = num_crtc;
1245 adev->mode_info.num_crtc = 1;
1251 DRM_INFO("virtual display string:%s, %s:virtual_display:%d, num_crtc:%d\n",
1252 amdgpu_virtual_display, pci_address_name,
1253 adev->enable_virtual_display, adev->mode_info.num_crtc);
1259 static int amdgpu_device_parse_gpu_info_fw(struct amdgpu_device *adev)
1261 const char *chip_name;
1264 const struct gpu_info_firmware_header_v1_0 *hdr;
1266 adev->firmware.gpu_info_fw = NULL;
1268 switch (adev->asic_type) {
1272 case CHIP_POLARIS11:
1273 case CHIP_POLARIS10:
1274 case CHIP_POLARIS12:
1277 #ifdef CONFIG_DRM_AMDGPU_SI
1284 #ifdef CONFIG_DRM_AMDGPU_CIK
1294 chip_name = "vega10";
1297 chip_name = "raven";
1301 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_gpu_info.bin", chip_name);
1302 err = request_firmware(&adev->firmware.gpu_info_fw, fw_name, adev->dev);
1305 "Failed to load gpu_info firmware \"%s\"\n",
1309 err = amdgpu_ucode_validate(adev->firmware.gpu_info_fw);
1312 "Failed to validate gpu_info firmware \"%s\"\n",
1317 hdr = (const struct gpu_info_firmware_header_v1_0 *)adev->firmware.gpu_info_fw->data;
1318 amdgpu_ucode_print_gpu_info_hdr(&hdr->header);
1320 switch (hdr->version_major) {
1323 const struct gpu_info_firmware_v1_0 *gpu_info_fw =
1324 (const struct gpu_info_firmware_v1_0 *)(adev->firmware.gpu_info_fw->data +
1325 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
1327 adev->gfx.config.max_shader_engines = le32_to_cpu(gpu_info_fw->gc_num_se);
1328 adev->gfx.config.max_cu_per_sh = le32_to_cpu(gpu_info_fw->gc_num_cu_per_sh);
1329 adev->gfx.config.max_sh_per_se = le32_to_cpu(gpu_info_fw->gc_num_sh_per_se);
1330 adev->gfx.config.max_backends_per_se = le32_to_cpu(gpu_info_fw->gc_num_rb_per_se);
1331 adev->gfx.config.max_texture_channel_caches =
1332 le32_to_cpu(gpu_info_fw->gc_num_tccs);
1333 adev->gfx.config.max_gprs = le32_to_cpu(gpu_info_fw->gc_num_gprs);
1334 adev->gfx.config.max_gs_threads = le32_to_cpu(gpu_info_fw->gc_num_max_gs_thds);
1335 adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gpu_info_fw->gc_gs_table_depth);
1336 adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gpu_info_fw->gc_gsprim_buff_depth);
1337 adev->gfx.config.double_offchip_lds_buf =
1338 le32_to_cpu(gpu_info_fw->gc_double_offchip_lds_buffer);
1339 adev->gfx.cu_info.wave_front_size = le32_to_cpu(gpu_info_fw->gc_wave_size);
1340 adev->gfx.cu_info.max_waves_per_simd =
1341 le32_to_cpu(gpu_info_fw->gc_max_waves_per_simd);
1342 adev->gfx.cu_info.max_scratch_slots_per_cu =
1343 le32_to_cpu(gpu_info_fw->gc_max_scratch_slots_per_cu);
1344 adev->gfx.cu_info.lds_size = le32_to_cpu(gpu_info_fw->gc_lds_size);
1349 "Unsupported gpu_info table %d\n", hdr->header.ucode_version);
1357 static int amdgpu_device_ip_early_init(struct amdgpu_device *adev)
1361 amdgpu_device_enable_virtual_display(adev);
1363 switch (adev->asic_type) {
1367 case CHIP_POLARIS11:
1368 case CHIP_POLARIS10:
1369 case CHIP_POLARIS12:
1372 if (adev->asic_type == CHIP_CARRIZO || adev->asic_type == CHIP_STONEY)
1373 adev->family = AMDGPU_FAMILY_CZ;
1375 adev->family = AMDGPU_FAMILY_VI;
1377 r = vi_set_ip_blocks(adev);
1381 #ifdef CONFIG_DRM_AMDGPU_SI
1387 adev->family = AMDGPU_FAMILY_SI;
1388 r = si_set_ip_blocks(adev);
1393 #ifdef CONFIG_DRM_AMDGPU_CIK
1399 if ((adev->asic_type == CHIP_BONAIRE) || (adev->asic_type == CHIP_HAWAII))
1400 adev->family = AMDGPU_FAMILY_CI;
1402 adev->family = AMDGPU_FAMILY_KV;
1404 r = cik_set_ip_blocks(adev);
1411 if (adev->asic_type == CHIP_RAVEN)
1412 adev->family = AMDGPU_FAMILY_RV;
1414 adev->family = AMDGPU_FAMILY_AI;
1416 r = soc15_set_ip_blocks(adev);
1421 /* FIXME: not supported yet */
1425 r = amdgpu_device_parse_gpu_info_fw(adev);
1429 amdgpu_amdkfd_device_probe(adev);
1431 if (amdgpu_sriov_vf(adev)) {
1432 r = amdgpu_virt_request_full_gpu(adev, true);
1437 for (i = 0; i < adev->num_ip_blocks; i++) {
1438 if ((amdgpu_ip_block_mask & (1 << i)) == 0) {
1439 DRM_ERROR("disabled ip block: %d <%s>\n",
1440 i, adev->ip_blocks[i].version->funcs->name);
1441 adev->ip_blocks[i].status.valid = false;
1443 if (adev->ip_blocks[i].version->funcs->early_init) {
1444 r = adev->ip_blocks[i].version->funcs->early_init((void *)adev);
1446 adev->ip_blocks[i].status.valid = false;
1448 DRM_ERROR("early_init of IP block <%s> failed %d\n",
1449 adev->ip_blocks[i].version->funcs->name, r);
1452 adev->ip_blocks[i].status.valid = true;
1455 adev->ip_blocks[i].status.valid = true;
1460 adev->cg_flags &= amdgpu_cg_mask;
1461 adev->pg_flags &= amdgpu_pg_mask;
1466 static int amdgpu_device_ip_init(struct amdgpu_device *adev)
1470 for (i = 0; i < adev->num_ip_blocks; i++) {
1471 if (!adev->ip_blocks[i].status.valid)
1473 r = adev->ip_blocks[i].version->funcs->sw_init((void *)adev);
1475 DRM_ERROR("sw_init of IP block <%s> failed %d\n",
1476 adev->ip_blocks[i].version->funcs->name, r);
1479 adev->ip_blocks[i].status.sw = true;
1480 /* need to do gmc hw init early so we can allocate gpu mem */
1481 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) {
1482 r = amdgpu_device_vram_scratch_init(adev);
1484 DRM_ERROR("amdgpu_vram_scratch_init failed %d\n", r);
1487 r = adev->ip_blocks[i].version->funcs->hw_init((void *)adev);
1489 DRM_ERROR("hw_init %d failed %d\n", i, r);
1492 r = amdgpu_device_wb_init(adev);
1494 DRM_ERROR("amdgpu_device_wb_init failed %d\n", r);
1497 adev->ip_blocks[i].status.hw = true;
1499 /* right after GMC hw init, we create CSA */
1500 if (amdgpu_sriov_vf(adev)) {
1501 r = amdgpu_allocate_static_csa(adev);
1503 DRM_ERROR("allocate CSA failed %d\n", r);
1510 for (i = 0; i < adev->num_ip_blocks; i++) {
1511 if (!adev->ip_blocks[i].status.sw)
1513 /* gmc hw init is done early */
1514 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC)
1516 r = adev->ip_blocks[i].version->funcs->hw_init((void *)adev);
1518 DRM_ERROR("hw_init of IP block <%s> failed %d\n",
1519 adev->ip_blocks[i].version->funcs->name, r);
1522 adev->ip_blocks[i].status.hw = true;
1525 amdgpu_amdkfd_device_init(adev);
1527 if (amdgpu_sriov_vf(adev))
1528 amdgpu_virt_release_full_gpu(adev, true);
1533 static void amdgpu_device_fill_reset_magic(struct amdgpu_device *adev)
1535 memcpy(adev->reset_magic, adev->gart.ptr, AMDGPU_RESET_MAGIC_NUM);
1538 static bool amdgpu_device_check_vram_lost(struct amdgpu_device *adev)
1540 return !!memcmp(adev->gart.ptr, adev->reset_magic,
1541 AMDGPU_RESET_MAGIC_NUM);
1544 static int amdgpu_device_ip_late_set_cg_state(struct amdgpu_device *adev)
1548 for (i = 0; i < adev->num_ip_blocks; i++) {
1549 if (!adev->ip_blocks[i].status.valid)
1551 /* skip CG for VCE/UVD, it's handled specially */
1552 if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_UVD &&
1553 adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCE) {
1554 /* enable clockgating to save power */
1555 r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev,
1558 DRM_ERROR("set_clockgating_state(gate) of IP block <%s> failed %d\n",
1559 adev->ip_blocks[i].version->funcs->name, r);
1567 static int amdgpu_device_ip_late_init(struct amdgpu_device *adev)
1571 for (i = 0; i < adev->num_ip_blocks; i++) {
1572 if (!adev->ip_blocks[i].status.valid)
1574 if (adev->ip_blocks[i].version->funcs->late_init) {
1575 r = adev->ip_blocks[i].version->funcs->late_init((void *)adev);
1577 DRM_ERROR("late_init of IP block <%s> failed %d\n",
1578 adev->ip_blocks[i].version->funcs->name, r);
1581 adev->ip_blocks[i].status.late_initialized = true;
1585 mod_delayed_work(system_wq, &adev->late_init_work,
1586 msecs_to_jiffies(AMDGPU_RESUME_MS));
1588 amdgpu_device_fill_reset_magic(adev);
1593 static int amdgpu_device_ip_fini(struct amdgpu_device *adev)
1597 amdgpu_amdkfd_device_fini(adev);
1598 /* need to disable SMC first */
1599 for (i = 0; i < adev->num_ip_blocks; i++) {
1600 if (!adev->ip_blocks[i].status.hw)
1602 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) {
1603 /* ungate blocks before hw fini so that we can shutdown the blocks safely */
1604 r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev,
1605 AMD_CG_STATE_UNGATE);
1607 DRM_ERROR("set_clockgating_state(ungate) of IP block <%s> failed %d\n",
1608 adev->ip_blocks[i].version->funcs->name, r);
1611 r = adev->ip_blocks[i].version->funcs->hw_fini((void *)adev);
1612 /* XXX handle errors */
1614 DRM_DEBUG("hw_fini of IP block <%s> failed %d\n",
1615 adev->ip_blocks[i].version->funcs->name, r);
1617 adev->ip_blocks[i].status.hw = false;
1622 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
1623 if (!adev->ip_blocks[i].status.hw)
1625 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) {
1626 amdgpu_free_static_csa(adev);
1627 amdgpu_device_wb_fini(adev);
1628 amdgpu_device_vram_scratch_fini(adev);
1631 if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_UVD &&
1632 adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCE) {
1633 /* ungate blocks before hw fini so that we can shutdown the blocks safely */
1634 r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev,
1635 AMD_CG_STATE_UNGATE);
1637 DRM_ERROR("set_clockgating_state(ungate) of IP block <%s> failed %d\n",
1638 adev->ip_blocks[i].version->funcs->name, r);
1643 r = adev->ip_blocks[i].version->funcs->hw_fini((void *)adev);
1644 /* XXX handle errors */
1646 DRM_DEBUG("hw_fini of IP block <%s> failed %d\n",
1647 adev->ip_blocks[i].version->funcs->name, r);
1650 adev->ip_blocks[i].status.hw = false;
1653 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
1654 if (!adev->ip_blocks[i].status.sw)
1656 r = adev->ip_blocks[i].version->funcs->sw_fini((void *)adev);
1657 /* XXX handle errors */
1659 DRM_DEBUG("sw_fini of IP block <%s> failed %d\n",
1660 adev->ip_blocks[i].version->funcs->name, r);
1662 adev->ip_blocks[i].status.sw = false;
1663 adev->ip_blocks[i].status.valid = false;
1666 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
1667 if (!adev->ip_blocks[i].status.late_initialized)
1669 if (adev->ip_blocks[i].version->funcs->late_fini)
1670 adev->ip_blocks[i].version->funcs->late_fini((void *)adev);
1671 adev->ip_blocks[i].status.late_initialized = false;
1674 if (amdgpu_sriov_vf(adev))
1675 if (amdgpu_virt_release_full_gpu(adev, false))
1676 DRM_ERROR("failed to release exclusive mode on fini\n");
1681 static void amdgpu_device_ip_late_init_func_handler(struct work_struct *work)
1683 struct amdgpu_device *adev =
1684 container_of(work, struct amdgpu_device, late_init_work.work);
1685 amdgpu_device_ip_late_set_cg_state(adev);
1688 int amdgpu_device_ip_suspend(struct amdgpu_device *adev)
1692 if (amdgpu_sriov_vf(adev))
1693 amdgpu_virt_request_full_gpu(adev, false);
1695 /* ungate SMC block first */
1696 r = amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_SMC,
1697 AMD_CG_STATE_UNGATE);
1699 DRM_ERROR("set_clockgating_state(ungate) SMC failed %d\n",r);
1702 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
1703 if (!adev->ip_blocks[i].status.valid)
1705 /* ungate blocks so that suspend can properly shut them down */
1706 if (i != AMD_IP_BLOCK_TYPE_SMC) {
1707 r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev,
1708 AMD_CG_STATE_UNGATE);
1710 DRM_ERROR("set_clockgating_state(ungate) of IP block <%s> failed %d\n",
1711 adev->ip_blocks[i].version->funcs->name, r);
1714 /* XXX handle errors */
1715 r = adev->ip_blocks[i].version->funcs->suspend(adev);
1716 /* XXX handle errors */
1718 DRM_ERROR("suspend of IP block <%s> failed %d\n",
1719 adev->ip_blocks[i].version->funcs->name, r);
1723 if (amdgpu_sriov_vf(adev))
1724 amdgpu_virt_release_full_gpu(adev, false);
1729 static int amdgpu_device_ip_reinit_early_sriov(struct amdgpu_device *adev)
1733 static enum amd_ip_block_type ip_order[] = {
1734 AMD_IP_BLOCK_TYPE_GMC,
1735 AMD_IP_BLOCK_TYPE_COMMON,
1736 AMD_IP_BLOCK_TYPE_IH,
1739 for (i = 0; i < ARRAY_SIZE(ip_order); i++) {
1741 struct amdgpu_ip_block *block;
1743 for (j = 0; j < adev->num_ip_blocks; j++) {
1744 block = &adev->ip_blocks[j];
1746 if (block->version->type != ip_order[i] ||
1747 !block->status.valid)
1750 r = block->version->funcs->hw_init(adev);
1751 DRM_INFO("RE-INIT: %s %s\n", block->version->funcs->name, r?"failed":"successed");
1758 static int amdgpu_device_ip_reinit_late_sriov(struct amdgpu_device *adev)
1762 static enum amd_ip_block_type ip_order[] = {
1763 AMD_IP_BLOCK_TYPE_SMC,
1764 AMD_IP_BLOCK_TYPE_PSP,
1765 AMD_IP_BLOCK_TYPE_DCE,
1766 AMD_IP_BLOCK_TYPE_GFX,
1767 AMD_IP_BLOCK_TYPE_SDMA,
1768 AMD_IP_BLOCK_TYPE_UVD,
1769 AMD_IP_BLOCK_TYPE_VCE
1772 for (i = 0; i < ARRAY_SIZE(ip_order); i++) {
1774 struct amdgpu_ip_block *block;
1776 for (j = 0; j < adev->num_ip_blocks; j++) {
1777 block = &adev->ip_blocks[j];
1779 if (block->version->type != ip_order[i] ||
1780 !block->status.valid)
1783 r = block->version->funcs->hw_init(adev);
1784 DRM_INFO("RE-INIT: %s %s\n", block->version->funcs->name, r?"failed":"successed");
1791 static int amdgpu_device_ip_resume_phase1(struct amdgpu_device *adev)
1795 for (i = 0; i < adev->num_ip_blocks; i++) {
1796 if (!adev->ip_blocks[i].status.valid)
1798 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON ||
1799 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC ||
1800 adev->ip_blocks[i].version->type ==
1801 AMD_IP_BLOCK_TYPE_IH) {
1802 r = adev->ip_blocks[i].version->funcs->resume(adev);
1804 DRM_ERROR("resume of IP block <%s> failed %d\n",
1805 adev->ip_blocks[i].version->funcs->name, r);
1814 static int amdgpu_device_ip_resume_phase2(struct amdgpu_device *adev)
1818 for (i = 0; i < adev->num_ip_blocks; i++) {
1819 if (!adev->ip_blocks[i].status.valid)
1821 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON ||
1822 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC ||
1823 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH )
1825 r = adev->ip_blocks[i].version->funcs->resume(adev);
1827 DRM_ERROR("resume of IP block <%s> failed %d\n",
1828 adev->ip_blocks[i].version->funcs->name, r);
1836 static int amdgpu_device_ip_resume(struct amdgpu_device *adev)
1840 r = amdgpu_device_ip_resume_phase1(adev);
1843 r = amdgpu_device_ip_resume_phase2(adev);
1848 static void amdgpu_device_detect_sriov_bios(struct amdgpu_device *adev)
1850 if (amdgpu_sriov_vf(adev)) {
1851 if (adev->is_atom_fw) {
1852 if (amdgpu_atomfirmware_gpu_supports_virtualization(adev))
1853 adev->virt.caps |= AMDGPU_SRIOV_CAPS_SRIOV_VBIOS;
1855 if (amdgpu_atombios_has_gpu_virtualization_table(adev))
1856 adev->virt.caps |= AMDGPU_SRIOV_CAPS_SRIOV_VBIOS;
1859 if (!(adev->virt.caps & AMDGPU_SRIOV_CAPS_SRIOV_VBIOS))
1860 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_NO_VBIOS, 0, 0);
1864 bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type)
1866 switch (asic_type) {
1867 #if defined(CONFIG_DRM_AMD_DC)
1873 case CHIP_POLARIS11:
1874 case CHIP_POLARIS10:
1875 case CHIP_POLARIS12:
1878 #if defined(CONFIG_DRM_AMD_DC_PRE_VEGA)
1879 return amdgpu_dc != 0;
1883 return amdgpu_dc > 0;
1885 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
1888 return amdgpu_dc != 0;
1896 * amdgpu_device_has_dc_support - check if dc is supported
1898 * @adev: amdgpu_device_pointer
1900 * Returns true for supported, false for not supported
1902 bool amdgpu_device_has_dc_support(struct amdgpu_device *adev)
1904 if (amdgpu_sriov_vf(adev))
1907 return amdgpu_device_asic_has_dc_support(adev->asic_type);
1911 * amdgpu_device_init - initialize the driver
1913 * @adev: amdgpu_device pointer
1914 * @pdev: drm dev pointer
1915 * @pdev: pci dev pointer
1916 * @flags: driver flags
1918 * Initializes the driver info and hw (all asics).
1919 * Returns 0 for success or an error on failure.
1920 * Called at driver startup.
1922 int amdgpu_device_init(struct amdgpu_device *adev,
1923 struct drm_device *ddev,
1924 struct pci_dev *pdev,
1928 bool runtime = false;
1931 adev->shutdown = false;
1932 adev->dev = &pdev->dev;
1935 adev->flags = flags;
1936 adev->asic_type = flags & AMD_ASIC_MASK;
1937 adev->usec_timeout = AMDGPU_MAX_USEC_TIMEOUT;
1938 adev->mc.gart_size = 512 * 1024 * 1024;
1939 adev->accel_working = false;
1940 adev->num_rings = 0;
1941 adev->mman.buffer_funcs = NULL;
1942 adev->mman.buffer_funcs_ring = NULL;
1943 adev->vm_manager.vm_pte_funcs = NULL;
1944 adev->vm_manager.vm_pte_num_rings = 0;
1945 adev->gart.gart_funcs = NULL;
1946 adev->fence_context = dma_fence_context_alloc(AMDGPU_MAX_RINGS);
1947 bitmap_zero(adev->gfx.pipe_reserve_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
1949 adev->smc_rreg = &amdgpu_invalid_rreg;
1950 adev->smc_wreg = &amdgpu_invalid_wreg;
1951 adev->pcie_rreg = &amdgpu_invalid_rreg;
1952 adev->pcie_wreg = &amdgpu_invalid_wreg;
1953 adev->pciep_rreg = &amdgpu_invalid_rreg;
1954 adev->pciep_wreg = &amdgpu_invalid_wreg;
1955 adev->uvd_ctx_rreg = &amdgpu_invalid_rreg;
1956 adev->uvd_ctx_wreg = &amdgpu_invalid_wreg;
1957 adev->didt_rreg = &amdgpu_invalid_rreg;
1958 adev->didt_wreg = &amdgpu_invalid_wreg;
1959 adev->gc_cac_rreg = &amdgpu_invalid_rreg;
1960 adev->gc_cac_wreg = &amdgpu_invalid_wreg;
1961 adev->audio_endpt_rreg = &amdgpu_block_invalid_rreg;
1962 adev->audio_endpt_wreg = &amdgpu_block_invalid_wreg;
1964 DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X 0x%04X:0x%04X 0x%02X).\n",
1965 amdgpu_asic_name[adev->asic_type], pdev->vendor, pdev->device,
1966 pdev->subsystem_vendor, pdev->subsystem_device, pdev->revision);
1968 /* mutex initialization are all done here so we
1969 * can recall function without having locking issues */
1970 atomic_set(&adev->irq.ih.lock, 0);
1971 mutex_init(&adev->firmware.mutex);
1972 mutex_init(&adev->pm.mutex);
1973 mutex_init(&adev->gfx.gpu_clock_mutex);
1974 mutex_init(&adev->srbm_mutex);
1975 mutex_init(&adev->gfx.pipe_reserve_mutex);
1976 mutex_init(&adev->grbm_idx_mutex);
1977 mutex_init(&adev->mn_lock);
1978 mutex_init(&adev->virt.vf_errors.lock);
1979 hash_init(adev->mn_hash);
1980 mutex_init(&adev->lock_reset);
1982 amdgpu_device_check_arguments(adev);
1984 spin_lock_init(&adev->mmio_idx_lock);
1985 spin_lock_init(&adev->smc_idx_lock);
1986 spin_lock_init(&adev->pcie_idx_lock);
1987 spin_lock_init(&adev->uvd_ctx_idx_lock);
1988 spin_lock_init(&adev->didt_idx_lock);
1989 spin_lock_init(&adev->gc_cac_idx_lock);
1990 spin_lock_init(&adev->se_cac_idx_lock);
1991 spin_lock_init(&adev->audio_endpt_idx_lock);
1992 spin_lock_init(&adev->mm_stats.lock);
1994 INIT_LIST_HEAD(&adev->shadow_list);
1995 mutex_init(&adev->shadow_list_lock);
1997 INIT_LIST_HEAD(&adev->ring_lru_list);
1998 spin_lock_init(&adev->ring_lru_list_lock);
2000 INIT_DELAYED_WORK(&adev->late_init_work,
2001 amdgpu_device_ip_late_init_func_handler);
2003 /* Registers mapping */
2004 /* TODO: block userspace mapping of io register */
2005 if (adev->asic_type >= CHIP_BONAIRE) {
2006 adev->rmmio_base = pci_resource_start(adev->pdev, 5);
2007 adev->rmmio_size = pci_resource_len(adev->pdev, 5);
2009 adev->rmmio_base = pci_resource_start(adev->pdev, 2);
2010 adev->rmmio_size = pci_resource_len(adev->pdev, 2);
2013 adev->rmmio = ioremap(adev->rmmio_base, adev->rmmio_size);
2014 if (adev->rmmio == NULL) {
2017 DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)adev->rmmio_base);
2018 DRM_INFO("register mmio size: %u\n", (unsigned)adev->rmmio_size);
2020 /* doorbell bar mapping */
2021 amdgpu_device_doorbell_init(adev);
2023 /* io port mapping */
2024 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
2025 if (pci_resource_flags(adev->pdev, i) & IORESOURCE_IO) {
2026 adev->rio_mem_size = pci_resource_len(adev->pdev, i);
2027 adev->rio_mem = pci_iomap(adev->pdev, i, adev->rio_mem_size);
2031 if (adev->rio_mem == NULL)
2032 DRM_INFO("PCI I/O BAR is not found.\n");
2034 /* early init functions */
2035 r = amdgpu_device_ip_early_init(adev);
2039 /* if we have > 1 VGA cards, then disable the amdgpu VGA resources */
2040 /* this will fail for cards that aren't VGA class devices, just
2042 vga_client_register(adev->pdev, adev, NULL, amdgpu_device_vga_set_decode);
2044 if (amdgpu_runtime_pm == 1)
2046 if (amdgpu_device_is_px(ddev))
2048 if (!pci_is_thunderbolt_attached(adev->pdev))
2049 vga_switcheroo_register_client(adev->pdev,
2050 &amdgpu_switcheroo_ops, runtime);
2052 vga_switcheroo_init_domain_pm_ops(adev->dev, &adev->vga_pm_domain);
2055 if (!amdgpu_get_bios(adev)) {
2060 r = amdgpu_atombios_init(adev);
2062 dev_err(adev->dev, "amdgpu_atombios_init failed\n");
2063 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_ATOMBIOS_INIT_FAIL, 0, 0);
2067 /* detect if we are with an SRIOV vbios */
2068 amdgpu_device_detect_sriov_bios(adev);
2070 /* Post card if necessary */
2071 if (amdgpu_need_post(adev)) {
2073 dev_err(adev->dev, "no vBIOS found\n");
2077 DRM_INFO("GPU posting now...\n");
2078 r = amdgpu_atom_asic_init(adev->mode_info.atom_context);
2080 dev_err(adev->dev, "gpu post error!\n");
2085 if (adev->is_atom_fw) {
2086 /* Initialize clocks */
2087 r = amdgpu_atomfirmware_get_clock_info(adev);
2089 dev_err(adev->dev, "amdgpu_atomfirmware_get_clock_info failed\n");
2090 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_ATOMBIOS_GET_CLOCK_FAIL, 0, 0);
2094 /* Initialize clocks */
2095 r = amdgpu_atombios_get_clock_info(adev);
2097 dev_err(adev->dev, "amdgpu_atombios_get_clock_info failed\n");
2098 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_ATOMBIOS_GET_CLOCK_FAIL, 0, 0);
2101 /* init i2c buses */
2102 if (!amdgpu_device_has_dc_support(adev))
2103 amdgpu_atombios_i2c_init(adev);
2107 r = amdgpu_fence_driver_init(adev);
2109 dev_err(adev->dev, "amdgpu_fence_driver_init failed\n");
2110 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_FENCE_INIT_FAIL, 0, 0);
2114 /* init the mode config */
2115 drm_mode_config_init(adev->ddev);
2117 r = amdgpu_device_ip_init(adev);
2119 /* failed in exclusive mode due to timeout */
2120 if (amdgpu_sriov_vf(adev) &&
2121 !amdgpu_sriov_runtime(adev) &&
2122 amdgpu_virt_mmio_blocked(adev) &&
2123 !amdgpu_virt_wait_reset(adev)) {
2124 dev_err(adev->dev, "VF exclusive mode timeout\n");
2125 /* Don't send request since VF is inactive. */
2126 adev->virt.caps &= ~AMDGPU_SRIOV_CAPS_RUNTIME;
2127 adev->virt.ops = NULL;
2131 dev_err(adev->dev, "amdgpu_device_ip_init failed\n");
2132 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_AMDGPU_INIT_FAIL, 0, 0);
2133 amdgpu_device_ip_fini(adev);
2137 adev->accel_working = true;
2139 amdgpu_vm_check_compute_bug(adev);
2141 /* Initialize the buffer migration limit. */
2142 if (amdgpu_moverate >= 0)
2143 max_MBps = amdgpu_moverate;
2145 max_MBps = 8; /* Allow 8 MB/s. */
2146 /* Get a log2 for easy divisions. */
2147 adev->mm_stats.log2_max_MBps = ilog2(max(1u, max_MBps));
2149 r = amdgpu_ib_pool_init(adev);
2151 dev_err(adev->dev, "IB initialization failed (%d).\n", r);
2152 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_IB_INIT_FAIL, 0, r);
2156 r = amdgpu_ib_ring_tests(adev);
2158 DRM_ERROR("ib ring test failed (%d).\n", r);
2160 if (amdgpu_sriov_vf(adev))
2161 amdgpu_virt_init_data_exchange(adev);
2163 amdgpu_fbdev_init(adev);
2165 r = amdgpu_pm_sysfs_init(adev);
2167 DRM_ERROR("registering pm debugfs failed (%d).\n", r);
2169 r = amdgpu_debugfs_gem_init(adev);
2171 DRM_ERROR("registering gem debugfs failed (%d).\n", r);
2173 r = amdgpu_debugfs_regs_init(adev);
2175 DRM_ERROR("registering register debugfs failed (%d).\n", r);
2177 r = amdgpu_debugfs_firmware_init(adev);
2179 DRM_ERROR("registering firmware debugfs failed (%d).\n", r);
2181 r = amdgpu_debugfs_init(adev);
2183 DRM_ERROR("Creating debugfs files failed (%d).\n", r);
2185 if ((amdgpu_testing & 1)) {
2186 if (adev->accel_working)
2187 amdgpu_test_moves(adev);
2189 DRM_INFO("amdgpu: acceleration disabled, skipping move tests\n");
2191 if (amdgpu_benchmarking) {
2192 if (adev->accel_working)
2193 amdgpu_benchmark(adev, amdgpu_benchmarking);
2195 DRM_INFO("amdgpu: acceleration disabled, skipping benchmarks\n");
2198 /* enable clockgating, etc. after ib tests, etc. since some blocks require
2199 * explicit gating rather than handling it automatically.
2201 r = amdgpu_device_ip_late_init(adev);
2203 dev_err(adev->dev, "amdgpu_device_ip_late_init failed\n");
2204 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_AMDGPU_LATE_INIT_FAIL, 0, r);
2211 amdgpu_vf_error_trans_all(adev);
2213 vga_switcheroo_fini_domain_pm_ops(adev->dev);
2219 * amdgpu_device_fini - tear down the driver
2221 * @adev: amdgpu_device pointer
2223 * Tear down the driver info (all asics).
2224 * Called at driver shutdown.
2226 void amdgpu_device_fini(struct amdgpu_device *adev)
2230 DRM_INFO("amdgpu: finishing device.\n");
2231 adev->shutdown = true;
2232 if (adev->mode_info.mode_config_initialized)
2233 drm_crtc_force_disable_all(adev->ddev);
2235 amdgpu_ib_pool_fini(adev);
2236 amdgpu_fence_driver_fini(adev);
2237 amdgpu_fbdev_fini(adev);
2238 r = amdgpu_device_ip_fini(adev);
2239 if (adev->firmware.gpu_info_fw) {
2240 release_firmware(adev->firmware.gpu_info_fw);
2241 adev->firmware.gpu_info_fw = NULL;
2243 adev->accel_working = false;
2244 cancel_delayed_work_sync(&adev->late_init_work);
2245 /* free i2c buses */
2246 if (!amdgpu_device_has_dc_support(adev))
2247 amdgpu_i2c_fini(adev);
2248 amdgpu_atombios_fini(adev);
2251 if (!pci_is_thunderbolt_attached(adev->pdev))
2252 vga_switcheroo_unregister_client(adev->pdev);
2253 if (adev->flags & AMD_IS_PX)
2254 vga_switcheroo_fini_domain_pm_ops(adev->dev);
2255 vga_client_register(adev->pdev, NULL, NULL, NULL);
2257 pci_iounmap(adev->pdev, adev->rio_mem);
2258 adev->rio_mem = NULL;
2259 iounmap(adev->rmmio);
2261 amdgpu_device_doorbell_fini(adev);
2262 amdgpu_pm_sysfs_fini(adev);
2263 amdgpu_debugfs_regs_cleanup(adev);
2271 * amdgpu_device_suspend - initiate device suspend
2273 * @pdev: drm dev pointer
2274 * @state: suspend state
2276 * Puts the hw in the suspend state (all asics).
2277 * Returns 0 for success or an error on failure.
2278 * Called at driver suspend.
2280 int amdgpu_device_suspend(struct drm_device *dev, bool suspend, bool fbcon)
2282 struct amdgpu_device *adev;
2283 struct drm_crtc *crtc;
2284 struct drm_connector *connector;
2287 if (dev == NULL || dev->dev_private == NULL) {
2291 adev = dev->dev_private;
2293 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2296 drm_kms_helper_poll_disable(dev);
2298 if (!amdgpu_device_has_dc_support(adev)) {
2299 /* turn off display hw */
2300 drm_modeset_lock_all(dev);
2301 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
2302 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF);
2304 drm_modeset_unlock_all(dev);
2307 amdgpu_amdkfd_suspend(adev);
2309 /* unpin the front buffers and cursors */
2310 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2311 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2312 struct amdgpu_framebuffer *rfb = to_amdgpu_framebuffer(crtc->primary->fb);
2313 struct amdgpu_bo *robj;
2315 if (amdgpu_crtc->cursor_bo) {
2316 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
2317 r = amdgpu_bo_reserve(aobj, true);
2319 amdgpu_bo_unpin(aobj);
2320 amdgpu_bo_unreserve(aobj);
2324 if (rfb == NULL || rfb->obj == NULL) {
2327 robj = gem_to_amdgpu_bo(rfb->obj);
2328 /* don't unpin kernel fb objects */
2329 if (!amdgpu_fbdev_robj_is_fb(adev, robj)) {
2330 r = amdgpu_bo_reserve(robj, true);
2332 amdgpu_bo_unpin(robj);
2333 amdgpu_bo_unreserve(robj);
2337 /* evict vram memory */
2338 amdgpu_bo_evict_vram(adev);
2340 amdgpu_fence_driver_suspend(adev);
2342 r = amdgpu_device_ip_suspend(adev);
2344 /* evict remaining vram memory
2345 * This second call to evict vram is to evict the gart page table
2348 amdgpu_bo_evict_vram(adev);
2350 pci_save_state(dev->pdev);
2352 /* Shut down the device */
2353 pci_disable_device(dev->pdev);
2354 pci_set_power_state(dev->pdev, PCI_D3hot);
2356 r = amdgpu_asic_reset(adev);
2358 DRM_ERROR("amdgpu asic reset failed\n");
2363 amdgpu_fbdev_set_suspend(adev, 1);
2370 * amdgpu_device_resume - initiate device resume
2372 * @pdev: drm dev pointer
2374 * Bring the hw back to operating state (all asics).
2375 * Returns 0 for success or an error on failure.
2376 * Called at driver resume.
2378 int amdgpu_device_resume(struct drm_device *dev, bool resume, bool fbcon)
2380 struct drm_connector *connector;
2381 struct amdgpu_device *adev = dev->dev_private;
2382 struct drm_crtc *crtc;
2385 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2392 pci_set_power_state(dev->pdev, PCI_D0);
2393 pci_restore_state(dev->pdev);
2394 r = pci_enable_device(dev->pdev);
2400 if (amdgpu_need_post(adev)) {
2401 r = amdgpu_atom_asic_init(adev->mode_info.atom_context);
2403 DRM_ERROR("amdgpu asic init failed\n");
2406 r = amdgpu_device_ip_resume(adev);
2408 DRM_ERROR("amdgpu_device_ip_resume failed (%d).\n", r);
2411 amdgpu_fence_driver_resume(adev);
2414 r = amdgpu_ib_ring_tests(adev);
2416 DRM_ERROR("ib ring test failed (%d).\n", r);
2419 r = amdgpu_device_ip_late_init(adev);
2424 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2425 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2427 if (amdgpu_crtc->cursor_bo) {
2428 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
2429 r = amdgpu_bo_reserve(aobj, true);
2431 r = amdgpu_bo_pin(aobj,
2432 AMDGPU_GEM_DOMAIN_VRAM,
2433 &amdgpu_crtc->cursor_addr);
2435 DRM_ERROR("Failed to pin cursor BO (%d)\n", r);
2436 amdgpu_bo_unreserve(aobj);
2440 r = amdgpu_amdkfd_resume(adev);
2444 /* blat the mode back in */
2446 if (!amdgpu_device_has_dc_support(adev)) {
2448 drm_helper_resume_force_mode(dev);
2450 /* turn on display hw */
2451 drm_modeset_lock_all(dev);
2452 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
2453 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON);
2455 drm_modeset_unlock_all(dev);
2458 * There is no equivalent atomic helper to turn on
2459 * display, so we defined our own function for this,
2460 * once suspend resume is supported by the atomic
2461 * framework this will be reworked
2463 amdgpu_dm_display_resume(adev);
2467 drm_kms_helper_poll_enable(dev);
2470 * Most of the connector probing functions try to acquire runtime pm
2471 * refs to ensure that the GPU is powered on when connector polling is
2472 * performed. Since we're calling this from a runtime PM callback,
2473 * trying to acquire rpm refs will cause us to deadlock.
2475 * Since we're guaranteed to be holding the rpm lock, it's safe to
2476 * temporarily disable the rpm helpers so this doesn't deadlock us.
2479 dev->dev->power.disable_depth++;
2481 if (!amdgpu_device_has_dc_support(adev))
2482 drm_helper_hpd_irq_event(dev);
2484 drm_kms_helper_hotplug_event(dev);
2486 dev->dev->power.disable_depth--;
2490 amdgpu_fbdev_set_suspend(adev, 0);
2499 static bool amdgpu_device_ip_check_soft_reset(struct amdgpu_device *adev)
2502 bool asic_hang = false;
2504 if (amdgpu_sriov_vf(adev))
2507 for (i = 0; i < adev->num_ip_blocks; i++) {
2508 if (!adev->ip_blocks[i].status.valid)
2510 if (adev->ip_blocks[i].version->funcs->check_soft_reset)
2511 adev->ip_blocks[i].status.hang =
2512 adev->ip_blocks[i].version->funcs->check_soft_reset(adev);
2513 if (adev->ip_blocks[i].status.hang) {
2514 DRM_INFO("IP block:%s is hung!\n", adev->ip_blocks[i].version->funcs->name);
2521 static int amdgpu_device_ip_pre_soft_reset(struct amdgpu_device *adev)
2525 for (i = 0; i < adev->num_ip_blocks; i++) {
2526 if (!adev->ip_blocks[i].status.valid)
2528 if (adev->ip_blocks[i].status.hang &&
2529 adev->ip_blocks[i].version->funcs->pre_soft_reset) {
2530 r = adev->ip_blocks[i].version->funcs->pre_soft_reset(adev);
2539 static bool amdgpu_device_ip_need_full_reset(struct amdgpu_device *adev)
2543 for (i = 0; i < adev->num_ip_blocks; i++) {
2544 if (!adev->ip_blocks[i].status.valid)
2546 if ((adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) ||
2547 (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) ||
2548 (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_ACP) ||
2549 (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_DCE) ||
2550 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP) {
2551 if (adev->ip_blocks[i].status.hang) {
2552 DRM_INFO("Some block need full reset!\n");
2560 static int amdgpu_device_ip_soft_reset(struct amdgpu_device *adev)
2564 for (i = 0; i < adev->num_ip_blocks; i++) {
2565 if (!adev->ip_blocks[i].status.valid)
2567 if (adev->ip_blocks[i].status.hang &&
2568 adev->ip_blocks[i].version->funcs->soft_reset) {
2569 r = adev->ip_blocks[i].version->funcs->soft_reset(adev);
2578 static int amdgpu_device_ip_post_soft_reset(struct amdgpu_device *adev)
2582 for (i = 0; i < adev->num_ip_blocks; i++) {
2583 if (!adev->ip_blocks[i].status.valid)
2585 if (adev->ip_blocks[i].status.hang &&
2586 adev->ip_blocks[i].version->funcs->post_soft_reset)
2587 r = adev->ip_blocks[i].version->funcs->post_soft_reset(adev);
2595 bool amdgpu_need_backup(struct amdgpu_device *adev)
2597 if (adev->flags & AMD_IS_APU)
2600 return amdgpu_gpu_recovery;
2603 static int amdgpu_device_recover_vram_from_shadow(struct amdgpu_device *adev,
2604 struct amdgpu_ring *ring,
2605 struct amdgpu_bo *bo,
2606 struct dma_fence **fence)
2614 r = amdgpu_bo_reserve(bo, true);
2617 domain = amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type);
2618 /* if bo has been evicted, then no need to recover */
2619 if (domain == AMDGPU_GEM_DOMAIN_VRAM) {
2620 r = amdgpu_bo_validate(bo->shadow);
2622 DRM_ERROR("bo validate failed!\n");
2626 r = amdgpu_bo_restore_from_shadow(adev, ring, bo,
2629 DRM_ERROR("recover page table failed!\n");
2634 amdgpu_bo_unreserve(bo);
2639 * amdgpu_device_reset - reset ASIC/GPU for bare-metal or passthrough
2641 * @adev: amdgpu device pointer
2642 * @reset_flags: output param tells caller the reset result
2644 * attempt to do soft-reset or full-reset and reinitialize Asic
2645 * return 0 means successed otherwise failed
2647 static int amdgpu_device_reset(struct amdgpu_device *adev,
2648 uint64_t* reset_flags)
2650 bool need_full_reset, vram_lost = 0;
2653 need_full_reset = amdgpu_device_ip_need_full_reset(adev);
2655 if (!need_full_reset) {
2656 amdgpu_device_ip_pre_soft_reset(adev);
2657 r = amdgpu_device_ip_soft_reset(adev);
2658 amdgpu_device_ip_post_soft_reset(adev);
2659 if (r || amdgpu_device_ip_check_soft_reset(adev)) {
2660 DRM_INFO("soft reset failed, will fallback to full reset!\n");
2661 need_full_reset = true;
2666 if (need_full_reset) {
2667 r = amdgpu_device_ip_suspend(adev);
2670 r = amdgpu_asic_reset(adev);
2672 amdgpu_atom_asic_init(adev->mode_info.atom_context);
2675 dev_info(adev->dev, "GPU reset succeeded, trying to resume\n");
2676 r = amdgpu_device_ip_resume_phase1(adev);
2680 vram_lost = amdgpu_device_check_vram_lost(adev);
2682 DRM_ERROR("VRAM is lost!\n");
2683 atomic_inc(&adev->vram_lost_counter);
2686 r = amdgpu_gtt_mgr_recover(
2687 &adev->mman.bdev.man[TTM_PL_TT]);
2691 r = amdgpu_device_ip_resume_phase2(adev);
2696 amdgpu_device_fill_reset_magic(adev);
2702 amdgpu_irq_gpu_reset_resume_helper(adev);
2703 r = amdgpu_ib_ring_tests(adev);
2705 dev_err(adev->dev, "ib ring test failed (%d).\n", r);
2706 r = amdgpu_device_ip_suspend(adev);
2707 need_full_reset = true;
2714 (*reset_flags) |= AMDGPU_RESET_INFO_VRAM_LOST;
2716 if (need_full_reset)
2717 (*reset_flags) |= AMDGPU_RESET_INFO_FULLRESET;
2724 * amdgpu_device_reset_sriov - reset ASIC for SR-IOV vf
2726 * @adev: amdgpu device pointer
2727 * @reset_flags: output param tells caller the reset result
2729 * do VF FLR and reinitialize Asic
2730 * return 0 means successed otherwise failed
2732 static int amdgpu_device_reset_sriov(struct amdgpu_device *adev,
2733 uint64_t *reset_flags,
2734 bool from_hypervisor)
2738 if (from_hypervisor)
2739 r = amdgpu_virt_request_full_gpu(adev, true);
2741 r = amdgpu_virt_reset_gpu(adev);
2745 /* Resume IP prior to SMC */
2746 r = amdgpu_device_ip_reinit_early_sriov(adev);
2750 /* we need recover gart prior to run SMC/CP/SDMA resume */
2751 amdgpu_gtt_mgr_recover(&adev->mman.bdev.man[TTM_PL_TT]);
2753 /* now we are okay to resume SMC/CP/SDMA */
2754 r = amdgpu_device_ip_reinit_late_sriov(adev);
2758 amdgpu_irq_gpu_reset_resume_helper(adev);
2759 r = amdgpu_ib_ring_tests(adev);
2761 dev_err(adev->dev, "[GPU_RESET] ib ring test failed (%d).\n", r);
2764 /* release full control of GPU after ib test */
2765 amdgpu_virt_release_full_gpu(adev, true);
2768 if (adev->virt.gim_feature & AMDGIM_FEATURE_GIM_FLR_VRAMLOST) {
2769 (*reset_flags) |= AMDGPU_RESET_INFO_VRAM_LOST;
2770 atomic_inc(&adev->vram_lost_counter);
2773 /* VF FLR or hotlink reset is always full-reset */
2774 (*reset_flags) |= AMDGPU_RESET_INFO_FULLRESET;
2781 * amdgpu_gpu_recover - reset the asic and recover scheduler
2783 * @adev: amdgpu device pointer
2784 * @job: which job trigger hang
2785 * @force forces reset regardless of amdgpu_gpu_recovery
2787 * Attempt to reset the GPU if it has hung (all asics).
2788 * Returns 0 for success or an error on failure.
2790 int amdgpu_gpu_recover(struct amdgpu_device *adev, struct amdgpu_job *job, bool force)
2792 struct drm_atomic_state *state = NULL;
2793 uint64_t reset_flags = 0;
2796 if (!amdgpu_device_ip_check_soft_reset(adev)) {
2797 DRM_INFO("No hardware hang detected. Did some blocks stall?\n");
2801 if (!force && (amdgpu_gpu_recovery == 0 ||
2802 (amdgpu_gpu_recovery == -1 && !amdgpu_sriov_vf(adev)))) {
2803 DRM_INFO("GPU recovery disabled.\n");
2807 dev_info(adev->dev, "GPU reset begin!\n");
2809 mutex_lock(&adev->lock_reset);
2810 atomic_inc(&adev->gpu_reset_counter);
2811 adev->in_gpu_reset = 1;
2814 resched = ttm_bo_lock_delayed_workqueue(&adev->mman.bdev);
2815 /* store modesetting */
2816 if (amdgpu_device_has_dc_support(adev))
2817 state = drm_atomic_helper_suspend(adev->ddev);
2819 /* block scheduler */
2820 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
2821 struct amdgpu_ring *ring = adev->rings[i];
2823 if (!ring || !ring->sched.thread)
2826 /* only focus on the ring hit timeout if &job not NULL */
2827 if (job && job->ring->idx != i)
2830 kthread_park(ring->sched.thread);
2831 drm_sched_hw_job_reset(&ring->sched, &job->base);
2833 /* after all hw jobs are reset, hw fence is meaningless, so force_completion */
2834 amdgpu_fence_driver_force_completion(ring);
2837 if (amdgpu_sriov_vf(adev))
2838 r = amdgpu_device_reset_sriov(adev, &reset_flags, job ? false : true);
2840 r = amdgpu_device_reset(adev, &reset_flags);
2843 if (((reset_flags & AMDGPU_RESET_INFO_FULLRESET) && !(adev->flags & AMD_IS_APU)) ||
2844 (reset_flags & AMDGPU_RESET_INFO_VRAM_LOST)) {
2845 struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
2846 struct amdgpu_bo *bo, *tmp;
2847 struct dma_fence *fence = NULL, *next = NULL;
2849 DRM_INFO("recover vram bo from shadow\n");
2850 mutex_lock(&adev->shadow_list_lock);
2851 list_for_each_entry_safe(bo, tmp, &adev->shadow_list, shadow_list) {
2853 amdgpu_device_recover_vram_from_shadow(adev, ring, bo, &next);
2855 r = dma_fence_wait(fence, false);
2857 WARN(r, "recovery from shadow isn't completed\n");
2862 dma_fence_put(fence);
2865 mutex_unlock(&adev->shadow_list_lock);
2867 r = dma_fence_wait(fence, false);
2869 WARN(r, "recovery from shadow isn't completed\n");
2871 dma_fence_put(fence);
2874 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
2875 struct amdgpu_ring *ring = adev->rings[i];
2877 if (!ring || !ring->sched.thread)
2880 /* only focus on the ring hit timeout if &job not NULL */
2881 if (job && job->ring->idx != i)
2884 drm_sched_job_recovery(&ring->sched);
2885 kthread_unpark(ring->sched.thread);
2888 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
2889 struct amdgpu_ring *ring = adev->rings[i];
2891 if (!ring || !ring->sched.thread)
2894 /* only focus on the ring hit timeout if &job not NULL */
2895 if (job && job->ring->idx != i)
2898 kthread_unpark(adev->rings[i]->sched.thread);
2902 if (amdgpu_device_has_dc_support(adev)) {
2903 if (drm_atomic_helper_resume(adev->ddev, state))
2904 dev_info(adev->dev, "drm resume failed:%d\n", r);
2905 amdgpu_dm_display_resume(adev);
2907 drm_helper_resume_force_mode(adev->ddev);
2910 ttm_bo_unlock_delayed_workqueue(&adev->mman.bdev, resched);
2913 /* bad news, how to tell it to userspace ? */
2914 dev_info(adev->dev, "GPU reset(%d) failed\n", atomic_read(&adev->gpu_reset_counter));
2915 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_GPU_RESET_FAIL, 0, r);
2917 dev_info(adev->dev, "GPU reset(%d) successed!\n",atomic_read(&adev->gpu_reset_counter));
2920 amdgpu_vf_error_trans_all(adev);
2921 adev->in_gpu_reset = 0;
2922 mutex_unlock(&adev->lock_reset);
2926 void amdgpu_get_pcie_info(struct amdgpu_device *adev)
2931 if (amdgpu_pcie_gen_cap)
2932 adev->pm.pcie_gen_mask = amdgpu_pcie_gen_cap;
2934 if (amdgpu_pcie_lane_cap)
2935 adev->pm.pcie_mlw_mask = amdgpu_pcie_lane_cap;
2937 /* covers APUs as well */
2938 if (pci_is_root_bus(adev->pdev->bus)) {
2939 if (adev->pm.pcie_gen_mask == 0)
2940 adev->pm.pcie_gen_mask = AMDGPU_DEFAULT_PCIE_GEN_MASK;
2941 if (adev->pm.pcie_mlw_mask == 0)
2942 adev->pm.pcie_mlw_mask = AMDGPU_DEFAULT_PCIE_MLW_MASK;
2946 if (adev->pm.pcie_gen_mask == 0) {
2947 ret = drm_pcie_get_speed_cap_mask(adev->ddev, &mask);
2949 adev->pm.pcie_gen_mask = (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
2950 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 |
2951 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3);
2953 if (mask & DRM_PCIE_SPEED_25)
2954 adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1;
2955 if (mask & DRM_PCIE_SPEED_50)
2956 adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2;
2957 if (mask & DRM_PCIE_SPEED_80)
2958 adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3;
2960 adev->pm.pcie_gen_mask = AMDGPU_DEFAULT_PCIE_GEN_MASK;
2963 if (adev->pm.pcie_mlw_mask == 0) {
2964 ret = drm_pcie_get_max_link_width(adev->ddev, &mask);
2968 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X32 |
2969 CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 |
2970 CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
2971 CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
2972 CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
2973 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
2974 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
2977 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 |
2978 CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
2979 CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
2980 CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
2981 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
2982 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
2985 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
2986 CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
2987 CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
2988 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
2989 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
2992 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
2993 CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
2994 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
2995 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
2998 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
2999 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
3000 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
3003 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
3004 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
3007 adev->pm.pcie_mlw_mask = CAIL_PCIE_LINK_WIDTH_SUPPORT_X1;
3013 adev->pm.pcie_mlw_mask = AMDGPU_DEFAULT_PCIE_MLW_MASK;