2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 #include <linux/console.h>
29 #include <linux/slab.h>
30 #include <linux/debugfs.h>
32 #include <drm/drm_crtc_helper.h>
33 #include <drm/amdgpu_drm.h>
34 #include <linux/vgaarb.h>
35 #include <linux/vga_switcheroo.h>
36 #include <linux/efi.h>
38 #include "amdgpu_i2c.h"
40 #include "amdgpu_atombios.h"
41 #ifdef CONFIG_DRM_AMDGPU_CIK
45 #include "bif/bif_4_1_d.h"
47 static int amdgpu_debugfs_regs_init(struct amdgpu_device *adev);
48 static void amdgpu_debugfs_regs_cleanup(struct amdgpu_device *adev);
50 static const char *amdgpu_asic_name[] = {
64 bool amdgpu_device_is_px(struct drm_device *dev)
66 struct amdgpu_device *adev = dev->dev_private;
68 if (adev->flags & AMD_IS_PX)
74 * MMIO register access helper functions.
76 uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg,
79 if ((reg * 4) < adev->rmmio_size && !always_indirect)
80 return readl(((void __iomem *)adev->rmmio) + (reg * 4));
85 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
86 writel((reg * 4), ((void __iomem *)adev->rmmio) + (mmMM_INDEX * 4));
87 ret = readl(((void __iomem *)adev->rmmio) + (mmMM_DATA * 4));
88 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
94 void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v,
97 if ((reg * 4) < adev->rmmio_size && !always_indirect)
98 writel(v, ((void __iomem *)adev->rmmio) + (reg * 4));
102 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
103 writel((reg * 4), ((void __iomem *)adev->rmmio) + (mmMM_INDEX * 4));
104 writel(v, ((void __iomem *)adev->rmmio) + (mmMM_DATA * 4));
105 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
109 u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg)
111 if ((reg * 4) < adev->rio_mem_size)
112 return ioread32(adev->rio_mem + (reg * 4));
114 iowrite32((reg * 4), adev->rio_mem + (mmMM_INDEX * 4));
115 return ioread32(adev->rio_mem + (mmMM_DATA * 4));
119 void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
122 if ((reg * 4) < adev->rio_mem_size)
123 iowrite32(v, adev->rio_mem + (reg * 4));
125 iowrite32((reg * 4), adev->rio_mem + (mmMM_INDEX * 4));
126 iowrite32(v, adev->rio_mem + (mmMM_DATA * 4));
131 * amdgpu_mm_rdoorbell - read a doorbell dword
133 * @adev: amdgpu_device pointer
134 * @index: doorbell index
136 * Returns the value in the doorbell aperture at the
137 * requested doorbell index (CIK).
139 u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index)
141 if (index < adev->doorbell.num_doorbells) {
142 return readl(adev->doorbell.ptr + index);
144 DRM_ERROR("reading beyond doorbell aperture: 0x%08x!\n", index);
150 * amdgpu_mm_wdoorbell - write a doorbell dword
152 * @adev: amdgpu_device pointer
153 * @index: doorbell index
156 * Writes @v to the doorbell aperture at the
157 * requested doorbell index (CIK).
159 void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v)
161 if (index < adev->doorbell.num_doorbells) {
162 writel(v, adev->doorbell.ptr + index);
164 DRM_ERROR("writing beyond doorbell aperture: 0x%08x!\n", index);
169 * amdgpu_invalid_rreg - dummy reg read function
171 * @adev: amdgpu device pointer
172 * @reg: offset of register
174 * Dummy register read function. Used for register blocks
175 * that certain asics don't have (all asics).
176 * Returns the value in the register.
178 static uint32_t amdgpu_invalid_rreg(struct amdgpu_device *adev, uint32_t reg)
180 DRM_ERROR("Invalid callback to read register 0x%04X\n", reg);
186 * amdgpu_invalid_wreg - dummy reg write function
188 * @adev: amdgpu device pointer
189 * @reg: offset of register
190 * @v: value to write to the register
192 * Dummy register read function. Used for register blocks
193 * that certain asics don't have (all asics).
195 static void amdgpu_invalid_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v)
197 DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n",
203 * amdgpu_block_invalid_rreg - dummy reg read function
205 * @adev: amdgpu device pointer
206 * @block: offset of instance
207 * @reg: offset of register
209 * Dummy register read function. Used for register blocks
210 * that certain asics don't have (all asics).
211 * Returns the value in the register.
213 static uint32_t amdgpu_block_invalid_rreg(struct amdgpu_device *adev,
214 uint32_t block, uint32_t reg)
216 DRM_ERROR("Invalid callback to read register 0x%04X in block 0x%04X\n",
223 * amdgpu_block_invalid_wreg - dummy reg write function
225 * @adev: amdgpu device pointer
226 * @block: offset of instance
227 * @reg: offset of register
228 * @v: value to write to the register
230 * Dummy register read function. Used for register blocks
231 * that certain asics don't have (all asics).
233 static void amdgpu_block_invalid_wreg(struct amdgpu_device *adev,
235 uint32_t reg, uint32_t v)
237 DRM_ERROR("Invalid block callback to write register 0x%04X in block 0x%04X with 0x%08X\n",
242 static int amdgpu_vram_scratch_init(struct amdgpu_device *adev)
246 if (adev->vram_scratch.robj == NULL) {
247 r = amdgpu_bo_create(adev, AMDGPU_GPU_PAGE_SIZE,
248 PAGE_SIZE, true, AMDGPU_GEM_DOMAIN_VRAM,
249 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
250 NULL, NULL, &adev->vram_scratch.robj);
256 r = amdgpu_bo_reserve(adev->vram_scratch.robj, false);
257 if (unlikely(r != 0))
259 r = amdgpu_bo_pin(adev->vram_scratch.robj,
260 AMDGPU_GEM_DOMAIN_VRAM, &adev->vram_scratch.gpu_addr);
262 amdgpu_bo_unreserve(adev->vram_scratch.robj);
265 r = amdgpu_bo_kmap(adev->vram_scratch.robj,
266 (void **)&adev->vram_scratch.ptr);
268 amdgpu_bo_unpin(adev->vram_scratch.robj);
269 amdgpu_bo_unreserve(adev->vram_scratch.robj);
274 static void amdgpu_vram_scratch_fini(struct amdgpu_device *adev)
278 if (adev->vram_scratch.robj == NULL) {
281 r = amdgpu_bo_reserve(adev->vram_scratch.robj, false);
282 if (likely(r == 0)) {
283 amdgpu_bo_kunmap(adev->vram_scratch.robj);
284 amdgpu_bo_unpin(adev->vram_scratch.robj);
285 amdgpu_bo_unreserve(adev->vram_scratch.robj);
287 amdgpu_bo_unref(&adev->vram_scratch.robj);
291 * amdgpu_program_register_sequence - program an array of registers.
293 * @adev: amdgpu_device pointer
294 * @registers: pointer to the register array
295 * @array_size: size of the register array
297 * Programs an array or registers with and and or masks.
298 * This is a helper for setting golden registers.
300 void amdgpu_program_register_sequence(struct amdgpu_device *adev,
301 const u32 *registers,
302 const u32 array_size)
304 u32 tmp, reg, and_mask, or_mask;
310 for (i = 0; i < array_size; i +=3) {
311 reg = registers[i + 0];
312 and_mask = registers[i + 1];
313 or_mask = registers[i + 2];
315 if (and_mask == 0xffffffff) {
326 void amdgpu_pci_config_reset(struct amdgpu_device *adev)
328 pci_write_config_dword(adev->pdev, 0x7c, AMDGPU_ASIC_RESET_DATA);
332 * GPU doorbell aperture helpers function.
335 * amdgpu_doorbell_init - Init doorbell driver information.
337 * @adev: amdgpu_device pointer
339 * Init doorbell driver information (CIK)
340 * Returns 0 on success, error on failure.
342 static int amdgpu_doorbell_init(struct amdgpu_device *adev)
344 /* doorbell bar mapping */
345 adev->doorbell.base = pci_resource_start(adev->pdev, 2);
346 adev->doorbell.size = pci_resource_len(adev->pdev, 2);
348 adev->doorbell.num_doorbells = min_t(u32, adev->doorbell.size / sizeof(u32),
349 AMDGPU_DOORBELL_MAX_ASSIGNMENT+1);
350 if (adev->doorbell.num_doorbells == 0)
353 adev->doorbell.ptr = ioremap(adev->doorbell.base, adev->doorbell.num_doorbells * sizeof(u32));
354 if (adev->doorbell.ptr == NULL) {
357 DRM_INFO("doorbell mmio base: 0x%08X\n", (uint32_t)adev->doorbell.base);
358 DRM_INFO("doorbell mmio size: %u\n", (unsigned)adev->doorbell.size);
364 * amdgpu_doorbell_fini - Tear down doorbell driver information.
366 * @adev: amdgpu_device pointer
368 * Tear down doorbell driver information (CIK)
370 static void amdgpu_doorbell_fini(struct amdgpu_device *adev)
372 iounmap(adev->doorbell.ptr);
373 adev->doorbell.ptr = NULL;
377 * amdgpu_doorbell_get_kfd_info - Report doorbell configuration required to
380 * @adev: amdgpu_device pointer
381 * @aperture_base: output returning doorbell aperture base physical address
382 * @aperture_size: output returning doorbell aperture size in bytes
383 * @start_offset: output returning # of doorbell bytes reserved for amdgpu.
385 * amdgpu and amdkfd share the doorbell aperture. amdgpu sets it up,
386 * takes doorbells required for its own rings and reports the setup to amdkfd.
387 * amdgpu reserved doorbells are at the start of the doorbell aperture.
389 void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev,
390 phys_addr_t *aperture_base,
391 size_t *aperture_size,
392 size_t *start_offset)
395 * The first num_doorbells are used by amdgpu.
396 * amdkfd takes whatever's left in the aperture.
398 if (adev->doorbell.size > adev->doorbell.num_doorbells * sizeof(u32)) {
399 *aperture_base = adev->doorbell.base;
400 *aperture_size = adev->doorbell.size;
401 *start_offset = adev->doorbell.num_doorbells * sizeof(u32);
411 * Writeback is the the method by which the the GPU updates special pages
412 * in memory with the status of certain GPU events (fences, ring pointers,
417 * amdgpu_wb_fini - Disable Writeback and free memory
419 * @adev: amdgpu_device pointer
421 * Disables Writeback and frees the Writeback memory (all asics).
422 * Used at driver shutdown.
424 static void amdgpu_wb_fini(struct amdgpu_device *adev)
426 if (adev->wb.wb_obj) {
427 if (!amdgpu_bo_reserve(adev->wb.wb_obj, false)) {
428 amdgpu_bo_kunmap(adev->wb.wb_obj);
429 amdgpu_bo_unpin(adev->wb.wb_obj);
430 amdgpu_bo_unreserve(adev->wb.wb_obj);
432 amdgpu_bo_unref(&adev->wb.wb_obj);
434 adev->wb.wb_obj = NULL;
439 * amdgpu_wb_init- Init Writeback driver info and allocate memory
441 * @adev: amdgpu_device pointer
443 * Disables Writeback and frees the Writeback memory (all asics).
444 * Used at driver startup.
445 * Returns 0 on success or an -error on failure.
447 static int amdgpu_wb_init(struct amdgpu_device *adev)
451 if (adev->wb.wb_obj == NULL) {
452 r = amdgpu_bo_create(adev, AMDGPU_MAX_WB * 4, PAGE_SIZE, true,
453 AMDGPU_GEM_DOMAIN_GTT, 0, NULL, NULL,
456 dev_warn(adev->dev, "(%d) create WB bo failed\n", r);
459 r = amdgpu_bo_reserve(adev->wb.wb_obj, false);
460 if (unlikely(r != 0)) {
461 amdgpu_wb_fini(adev);
464 r = amdgpu_bo_pin(adev->wb.wb_obj, AMDGPU_GEM_DOMAIN_GTT,
467 amdgpu_bo_unreserve(adev->wb.wb_obj);
468 dev_warn(adev->dev, "(%d) pin WB bo failed\n", r);
469 amdgpu_wb_fini(adev);
472 r = amdgpu_bo_kmap(adev->wb.wb_obj, (void **)&adev->wb.wb);
473 amdgpu_bo_unreserve(adev->wb.wb_obj);
475 dev_warn(adev->dev, "(%d) map WB bo failed\n", r);
476 amdgpu_wb_fini(adev);
480 adev->wb.num_wb = AMDGPU_MAX_WB;
481 memset(&adev->wb.used, 0, sizeof(adev->wb.used));
483 /* clear wb memory */
484 memset((char *)adev->wb.wb, 0, AMDGPU_GPU_PAGE_SIZE);
491 * amdgpu_wb_get - Allocate a wb entry
493 * @adev: amdgpu_device pointer
496 * Allocate a wb slot for use by the driver (all asics).
497 * Returns 0 on success or -EINVAL on failure.
499 int amdgpu_wb_get(struct amdgpu_device *adev, u32 *wb)
501 unsigned long offset = find_first_zero_bit(adev->wb.used, adev->wb.num_wb);
502 if (offset < adev->wb.num_wb) {
503 __set_bit(offset, adev->wb.used);
512 * amdgpu_wb_free - Free a wb entry
514 * @adev: amdgpu_device pointer
517 * Free a wb slot allocated for use by the driver (all asics)
519 void amdgpu_wb_free(struct amdgpu_device *adev, u32 wb)
521 if (wb < adev->wb.num_wb)
522 __clear_bit(wb, adev->wb.used);
526 * amdgpu_vram_location - try to find VRAM location
527 * @adev: amdgpu device structure holding all necessary informations
528 * @mc: memory controller structure holding memory informations
529 * @base: base address at which to put VRAM
531 * Function will place try to place VRAM at base address provided
532 * as parameter (which is so far either PCI aperture address or
533 * for IGP TOM base address).
535 * If there is not enough space to fit the unvisible VRAM in the 32bits
536 * address space then we limit the VRAM size to the aperture.
538 * Note: We don't explicitly enforce VRAM start to be aligned on VRAM size,
539 * this shouldn't be a problem as we are using the PCI aperture as a reference.
540 * Otherwise this would be needed for rv280, all r3xx, and all r4xx, but
543 * Note: we use mc_vram_size as on some board we need to program the mc to
544 * cover the whole aperture even if VRAM size is inferior to aperture size
545 * Novell bug 204882 + along with lots of ubuntu ones
547 * Note: when limiting vram it's safe to overwritte real_vram_size because
548 * we are not in case where real_vram_size is inferior to mc_vram_size (ie
549 * note afected by bogus hw of Novell bug 204882 + along with lots of ubuntu
552 * Note: IGP TOM addr should be the same as the aperture addr, we don't
553 * explicitly check for that thought.
555 * FIXME: when reducing VRAM size align new size on power of 2.
557 void amdgpu_vram_location(struct amdgpu_device *adev, struct amdgpu_mc *mc, u64 base)
559 uint64_t limit = (uint64_t)amdgpu_vram_limit << 20;
561 mc->vram_start = base;
562 if (mc->mc_vram_size > (adev->mc.mc_mask - base + 1)) {
563 dev_warn(adev->dev, "limiting VRAM to PCI aperture size\n");
564 mc->real_vram_size = mc->aper_size;
565 mc->mc_vram_size = mc->aper_size;
567 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
568 if (limit && limit < mc->real_vram_size)
569 mc->real_vram_size = limit;
570 dev_info(adev->dev, "VRAM: %lluM 0x%016llX - 0x%016llX (%lluM used)\n",
571 mc->mc_vram_size >> 20, mc->vram_start,
572 mc->vram_end, mc->real_vram_size >> 20);
576 * amdgpu_gtt_location - try to find GTT location
577 * @adev: amdgpu device structure holding all necessary informations
578 * @mc: memory controller structure holding memory informations
580 * Function will place try to place GTT before or after VRAM.
582 * If GTT size is bigger than space left then we ajust GTT size.
583 * Thus function will never fails.
585 * FIXME: when reducing GTT size align new size on power of 2.
587 void amdgpu_gtt_location(struct amdgpu_device *adev, struct amdgpu_mc *mc)
589 u64 size_af, size_bf;
591 size_af = ((adev->mc.mc_mask - mc->vram_end) + mc->gtt_base_align) & ~mc->gtt_base_align;
592 size_bf = mc->vram_start & ~mc->gtt_base_align;
593 if (size_bf > size_af) {
594 if (mc->gtt_size > size_bf) {
595 dev_warn(adev->dev, "limiting GTT\n");
596 mc->gtt_size = size_bf;
598 mc->gtt_start = (mc->vram_start & ~mc->gtt_base_align) - mc->gtt_size;
600 if (mc->gtt_size > size_af) {
601 dev_warn(adev->dev, "limiting GTT\n");
602 mc->gtt_size = size_af;
604 mc->gtt_start = (mc->vram_end + 1 + mc->gtt_base_align) & ~mc->gtt_base_align;
606 mc->gtt_end = mc->gtt_start + mc->gtt_size - 1;
607 dev_info(adev->dev, "GTT: %lluM 0x%016llX - 0x%016llX\n",
608 mc->gtt_size >> 20, mc->gtt_start, mc->gtt_end);
612 * GPU helpers function.
615 * amdgpu_card_posted - check if the hw has already been initialized
617 * @adev: amdgpu_device pointer
619 * Check if the asic has been initialized (all asics).
620 * Used at driver startup.
621 * Returns true if initialized or false if not.
623 bool amdgpu_card_posted(struct amdgpu_device *adev)
627 /* then check MEM_SIZE, in case the crtcs are off */
628 reg = RREG32(mmCONFIG_MEMSIZE);
638 * amdgpu_boot_test_post_card - check and possibly initialize the hw
640 * @adev: amdgpu_device pointer
642 * Check if the asic is initialized and if not, attempt to initialize
644 * Returns true if initialized or false if not.
646 bool amdgpu_boot_test_post_card(struct amdgpu_device *adev)
648 if (amdgpu_card_posted(adev))
652 DRM_INFO("GPU not posted. posting now...\n");
653 if (adev->is_atom_bios)
654 amdgpu_atom_asic_init(adev->mode_info.atom_context);
657 dev_err(adev->dev, "Card not posted and no BIOS - ignoring\n");
663 * amdgpu_dummy_page_init - init dummy page used by the driver
665 * @adev: amdgpu_device pointer
667 * Allocate the dummy page used by the driver (all asics).
668 * This dummy page is used by the driver as a filler for gart entries
669 * when pages are taken out of the GART
670 * Returns 0 on sucess, -ENOMEM on failure.
672 int amdgpu_dummy_page_init(struct amdgpu_device *adev)
674 if (adev->dummy_page.page)
676 adev->dummy_page.page = alloc_page(GFP_DMA32 | GFP_KERNEL | __GFP_ZERO);
677 if (adev->dummy_page.page == NULL)
679 adev->dummy_page.addr = pci_map_page(adev->pdev, adev->dummy_page.page,
680 0, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
681 if (pci_dma_mapping_error(adev->pdev, adev->dummy_page.addr)) {
682 dev_err(&adev->pdev->dev, "Failed to DMA MAP the dummy page\n");
683 __free_page(adev->dummy_page.page);
684 adev->dummy_page.page = NULL;
691 * amdgpu_dummy_page_fini - free dummy page used by the driver
693 * @adev: amdgpu_device pointer
695 * Frees the dummy page used by the driver (all asics).
697 void amdgpu_dummy_page_fini(struct amdgpu_device *adev)
699 if (adev->dummy_page.page == NULL)
701 pci_unmap_page(adev->pdev, adev->dummy_page.addr,
702 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
703 __free_page(adev->dummy_page.page);
704 adev->dummy_page.page = NULL;
708 /* ATOM accessor methods */
710 * ATOM is an interpreted byte code stored in tables in the vbios. The
711 * driver registers callbacks to access registers and the interpreter
712 * in the driver parses the tables and executes then to program specific
713 * actions (set display modes, asic init, etc.). See amdgpu_atombios.c,
714 * atombios.h, and atom.c
718 * cail_pll_read - read PLL register
720 * @info: atom card_info pointer
721 * @reg: PLL register offset
723 * Provides a PLL register accessor for the atom interpreter (r4xx+).
724 * Returns the value of the PLL register.
726 static uint32_t cail_pll_read(struct card_info *info, uint32_t reg)
732 * cail_pll_write - write PLL register
734 * @info: atom card_info pointer
735 * @reg: PLL register offset
736 * @val: value to write to the pll register
738 * Provides a PLL register accessor for the atom interpreter (r4xx+).
740 static void cail_pll_write(struct card_info *info, uint32_t reg, uint32_t val)
746 * cail_mc_read - read MC (Memory Controller) register
748 * @info: atom card_info pointer
749 * @reg: MC register offset
751 * Provides an MC register accessor for the atom interpreter (r4xx+).
752 * Returns the value of the MC register.
754 static uint32_t cail_mc_read(struct card_info *info, uint32_t reg)
760 * cail_mc_write - write MC (Memory Controller) register
762 * @info: atom card_info pointer
763 * @reg: MC register offset
764 * @val: value to write to the pll register
766 * Provides a MC register accessor for the atom interpreter (r4xx+).
768 static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val)
774 * cail_reg_write - write MMIO register
776 * @info: atom card_info pointer
777 * @reg: MMIO register offset
778 * @val: value to write to the pll register
780 * Provides a MMIO register accessor for the atom interpreter (r4xx+).
782 static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val)
784 struct amdgpu_device *adev = info->dev->dev_private;
790 * cail_reg_read - read MMIO register
792 * @info: atom card_info pointer
793 * @reg: MMIO register offset
795 * Provides an MMIO register accessor for the atom interpreter (r4xx+).
796 * Returns the value of the MMIO register.
798 static uint32_t cail_reg_read(struct card_info *info, uint32_t reg)
800 struct amdgpu_device *adev = info->dev->dev_private;
808 * cail_ioreg_write - write IO register
810 * @info: atom card_info pointer
811 * @reg: IO register offset
812 * @val: value to write to the pll register
814 * Provides a IO register accessor for the atom interpreter (r4xx+).
816 static void cail_ioreg_write(struct card_info *info, uint32_t reg, uint32_t val)
818 struct amdgpu_device *adev = info->dev->dev_private;
824 * cail_ioreg_read - read IO register
826 * @info: atom card_info pointer
827 * @reg: IO register offset
829 * Provides an IO register accessor for the atom interpreter (r4xx+).
830 * Returns the value of the IO register.
832 static uint32_t cail_ioreg_read(struct card_info *info, uint32_t reg)
834 struct amdgpu_device *adev = info->dev->dev_private;
842 * amdgpu_atombios_fini - free the driver info and callbacks for atombios
844 * @adev: amdgpu_device pointer
846 * Frees the driver info and register access callbacks for the ATOM
847 * interpreter (r4xx+).
848 * Called at driver shutdown.
850 static void amdgpu_atombios_fini(struct amdgpu_device *adev)
852 if (adev->mode_info.atom_context)
853 kfree(adev->mode_info.atom_context->scratch);
854 kfree(adev->mode_info.atom_context);
855 adev->mode_info.atom_context = NULL;
856 kfree(adev->mode_info.atom_card_info);
857 adev->mode_info.atom_card_info = NULL;
861 * amdgpu_atombios_init - init the driver info and callbacks for atombios
863 * @adev: amdgpu_device pointer
865 * Initializes the driver info and register access callbacks for the
866 * ATOM interpreter (r4xx+).
867 * Returns 0 on sucess, -ENOMEM on failure.
868 * Called at driver startup.
870 static int amdgpu_atombios_init(struct amdgpu_device *adev)
872 struct card_info *atom_card_info =
873 kzalloc(sizeof(struct card_info), GFP_KERNEL);
878 adev->mode_info.atom_card_info = atom_card_info;
879 atom_card_info->dev = adev->ddev;
880 atom_card_info->reg_read = cail_reg_read;
881 atom_card_info->reg_write = cail_reg_write;
882 /* needed for iio ops */
884 atom_card_info->ioreg_read = cail_ioreg_read;
885 atom_card_info->ioreg_write = cail_ioreg_write;
887 DRM_ERROR("Unable to find PCI I/O BAR; using MMIO for ATOM IIO\n");
888 atom_card_info->ioreg_read = cail_reg_read;
889 atom_card_info->ioreg_write = cail_reg_write;
891 atom_card_info->mc_read = cail_mc_read;
892 atom_card_info->mc_write = cail_mc_write;
893 atom_card_info->pll_read = cail_pll_read;
894 atom_card_info->pll_write = cail_pll_write;
896 adev->mode_info.atom_context = amdgpu_atom_parse(atom_card_info, adev->bios);
897 if (!adev->mode_info.atom_context) {
898 amdgpu_atombios_fini(adev);
902 mutex_init(&adev->mode_info.atom_context->mutex);
903 amdgpu_atombios_scratch_regs_init(adev);
904 amdgpu_atom_allocate_fb_scratch(adev->mode_info.atom_context);
908 /* if we get transitioned to only one device, take VGA back */
910 * amdgpu_vga_set_decode - enable/disable vga decode
912 * @cookie: amdgpu_device pointer
913 * @state: enable/disable vga decode
915 * Enable/disable vga decode (all asics).
916 * Returns VGA resource flags.
918 static unsigned int amdgpu_vga_set_decode(void *cookie, bool state)
920 struct amdgpu_device *adev = cookie;
921 amdgpu_asic_set_vga_state(adev, state);
923 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
924 VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
926 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
930 * amdgpu_check_pot_argument - check that argument is a power of two
932 * @arg: value to check
934 * Validates that a certain argument is a power of two (all asics).
935 * Returns true if argument is valid.
937 static bool amdgpu_check_pot_argument(int arg)
939 return (arg & (arg - 1)) == 0;
943 * amdgpu_check_arguments - validate module params
945 * @adev: amdgpu_device pointer
947 * Validates certain module parameters and updates
948 * the associated values used by the driver (all asics).
950 static void amdgpu_check_arguments(struct amdgpu_device *adev)
952 /* vramlimit must be a power of two */
953 if (!amdgpu_check_pot_argument(amdgpu_vram_limit)) {
954 dev_warn(adev->dev, "vram limit (%d) must be a power of 2\n",
956 amdgpu_vram_limit = 0;
959 if (amdgpu_gart_size != -1) {
960 /* gtt size must be power of two and greater or equal to 32M */
961 if (amdgpu_gart_size < 32) {
962 dev_warn(adev->dev, "gart size (%d) too small\n",
964 amdgpu_gart_size = -1;
965 } else if (!amdgpu_check_pot_argument(amdgpu_gart_size)) {
966 dev_warn(adev->dev, "gart size (%d) must be a power of 2\n",
968 amdgpu_gart_size = -1;
972 if (!amdgpu_check_pot_argument(amdgpu_vm_size)) {
973 dev_warn(adev->dev, "VM size (%d) must be a power of 2\n",
978 if (amdgpu_vm_size < 1) {
979 dev_warn(adev->dev, "VM size (%d) too small, min is 1GB\n",
985 * Max GPUVM size for Cayman, SI and CI are 40 bits.
987 if (amdgpu_vm_size > 1024) {
988 dev_warn(adev->dev, "VM size (%d) too large, max is 1TB\n",
993 /* defines number of bits in page table versus page directory,
994 * a page is 4KB so we have 12 bits offset, minimum 9 bits in the
995 * page table and the remaining bits are in the page directory */
996 if (amdgpu_vm_block_size == -1) {
998 /* Total bits covered by PD + PTs */
999 unsigned bits = ilog2(amdgpu_vm_size) + 18;
1001 /* Make sure the PD is 4K in size up to 8GB address space.
1002 Above that split equal between PD and PTs */
1003 if (amdgpu_vm_size <= 8)
1004 amdgpu_vm_block_size = bits - 9;
1006 amdgpu_vm_block_size = (bits + 3) / 2;
1008 } else if (amdgpu_vm_block_size < 9) {
1009 dev_warn(adev->dev, "VM page table size (%d) too small\n",
1010 amdgpu_vm_block_size);
1011 amdgpu_vm_block_size = 9;
1014 if (amdgpu_vm_block_size > 24 ||
1015 (amdgpu_vm_size * 1024) < (1ull << amdgpu_vm_block_size)) {
1016 dev_warn(adev->dev, "VM page table size (%d) too large\n",
1017 amdgpu_vm_block_size);
1018 amdgpu_vm_block_size = 9;
1023 * amdgpu_switcheroo_set_state - set switcheroo state
1025 * @pdev: pci dev pointer
1026 * @state: vga_switcheroo state
1028 * Callback for the switcheroo driver. Suspends or resumes the
1029 * the asics before or after it is powered up using ACPI methods.
1031 static void amdgpu_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
1033 struct drm_device *dev = pci_get_drvdata(pdev);
1035 if (amdgpu_device_is_px(dev) && state == VGA_SWITCHEROO_OFF)
1038 if (state == VGA_SWITCHEROO_ON) {
1039 unsigned d3_delay = dev->pdev->d3_delay;
1041 printk(KERN_INFO "amdgpu: switched on\n");
1042 /* don't suspend or resume card normally */
1043 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1045 amdgpu_resume_kms(dev, true, true);
1047 dev->pdev->d3_delay = d3_delay;
1049 dev->switch_power_state = DRM_SWITCH_POWER_ON;
1050 drm_kms_helper_poll_enable(dev);
1052 printk(KERN_INFO "amdgpu: switched off\n");
1053 drm_kms_helper_poll_disable(dev);
1054 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1055 amdgpu_suspend_kms(dev, true, true);
1056 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
1061 * amdgpu_switcheroo_can_switch - see if switcheroo state can change
1063 * @pdev: pci dev pointer
1065 * Callback for the switcheroo driver. Check of the switcheroo
1066 * state can be changed.
1067 * Returns true if the state can be changed, false if not.
1069 static bool amdgpu_switcheroo_can_switch(struct pci_dev *pdev)
1071 struct drm_device *dev = pci_get_drvdata(pdev);
1074 * FIXME: open_count is protected by drm_global_mutex but that would lead to
1075 * locking inversion with the driver load path. And the access here is
1076 * completely racy anyway. So don't bother with locking for now.
1078 return dev->open_count == 0;
1081 static const struct vga_switcheroo_client_ops amdgpu_switcheroo_ops = {
1082 .set_gpu_state = amdgpu_switcheroo_set_state,
1084 .can_switch = amdgpu_switcheroo_can_switch,
1087 int amdgpu_set_clockgating_state(struct amdgpu_device *adev,
1088 enum amd_ip_block_type block_type,
1089 enum amd_clockgating_state state)
1093 for (i = 0; i < adev->num_ip_blocks; i++) {
1094 if (adev->ip_blocks[i].type == block_type) {
1095 r = adev->ip_blocks[i].funcs->set_clockgating_state((void *)adev,
1104 int amdgpu_set_powergating_state(struct amdgpu_device *adev,
1105 enum amd_ip_block_type block_type,
1106 enum amd_powergating_state state)
1110 for (i = 0; i < adev->num_ip_blocks; i++) {
1111 if (adev->ip_blocks[i].type == block_type) {
1112 r = adev->ip_blocks[i].funcs->set_powergating_state((void *)adev,
1121 const struct amdgpu_ip_block_version * amdgpu_get_ip_block(
1122 struct amdgpu_device *adev,
1123 enum amd_ip_block_type type)
1127 for (i = 0; i < adev->num_ip_blocks; i++)
1128 if (adev->ip_blocks[i].type == type)
1129 return &adev->ip_blocks[i];
1135 * amdgpu_ip_block_version_cmp
1137 * @adev: amdgpu_device pointer
1138 * @type: enum amd_ip_block_type
1139 * @major: major version
1140 * @minor: minor version
1142 * return 0 if equal or greater
1143 * return 1 if smaller or the ip_block doesn't exist
1145 int amdgpu_ip_block_version_cmp(struct amdgpu_device *adev,
1146 enum amd_ip_block_type type,
1147 u32 major, u32 minor)
1149 const struct amdgpu_ip_block_version *ip_block;
1150 ip_block = amdgpu_get_ip_block(adev, type);
1152 if (ip_block && ((ip_block->major > major) ||
1153 ((ip_block->major == major) &&
1154 (ip_block->minor >= minor))))
1160 static int amdgpu_early_init(struct amdgpu_device *adev)
1164 switch (adev->asic_type) {
1170 if (adev->asic_type == CHIP_CARRIZO || adev->asic_type == CHIP_STONEY)
1171 adev->family = AMDGPU_FAMILY_CZ;
1173 adev->family = AMDGPU_FAMILY_VI;
1175 r = vi_set_ip_blocks(adev);
1179 #ifdef CONFIG_DRM_AMDGPU_CIK
1185 if ((adev->asic_type == CHIP_BONAIRE) || (adev->asic_type == CHIP_HAWAII))
1186 adev->family = AMDGPU_FAMILY_CI;
1188 adev->family = AMDGPU_FAMILY_KV;
1190 r = cik_set_ip_blocks(adev);
1196 /* FIXME: not supported yet */
1200 adev->ip_block_status = kcalloc(adev->num_ip_blocks,
1201 sizeof(struct amdgpu_ip_block_status), GFP_KERNEL);
1202 if (adev->ip_block_status == NULL)
1205 if (adev->ip_blocks == NULL) {
1206 DRM_ERROR("No IP blocks found!\n");
1210 for (i = 0; i < adev->num_ip_blocks; i++) {
1211 if ((amdgpu_ip_block_mask & (1 << i)) == 0) {
1212 DRM_ERROR("disabled ip block: %d\n", i);
1213 adev->ip_block_status[i].valid = false;
1215 if (adev->ip_blocks[i].funcs->early_init) {
1216 r = adev->ip_blocks[i].funcs->early_init((void *)adev);
1218 adev->ip_block_status[i].valid = false;
1220 DRM_ERROR("early_init %d failed %d\n", i, r);
1223 adev->ip_block_status[i].valid = true;
1226 adev->ip_block_status[i].valid = true;
1234 static int amdgpu_init(struct amdgpu_device *adev)
1238 for (i = 0; i < adev->num_ip_blocks; i++) {
1239 if (!adev->ip_block_status[i].valid)
1241 r = adev->ip_blocks[i].funcs->sw_init((void *)adev);
1243 DRM_ERROR("sw_init %d failed %d\n", i, r);
1246 adev->ip_block_status[i].sw = true;
1247 /* need to do gmc hw init early so we can allocate gpu mem */
1248 if (adev->ip_blocks[i].type == AMD_IP_BLOCK_TYPE_GMC) {
1249 r = amdgpu_vram_scratch_init(adev);
1251 DRM_ERROR("amdgpu_vram_scratch_init failed %d\n", r);
1254 r = adev->ip_blocks[i].funcs->hw_init((void *)adev);
1256 DRM_ERROR("hw_init %d failed %d\n", i, r);
1259 r = amdgpu_wb_init(adev);
1261 DRM_ERROR("amdgpu_wb_init failed %d\n", r);
1264 adev->ip_block_status[i].hw = true;
1268 for (i = 0; i < adev->num_ip_blocks; i++) {
1269 if (!adev->ip_block_status[i].sw)
1271 /* gmc hw init is done early */
1272 if (adev->ip_blocks[i].type == AMD_IP_BLOCK_TYPE_GMC)
1274 r = adev->ip_blocks[i].funcs->hw_init((void *)adev);
1276 DRM_ERROR("hw_init %d failed %d\n", i, r);
1279 adev->ip_block_status[i].hw = true;
1285 static int amdgpu_late_init(struct amdgpu_device *adev)
1289 for (i = 0; i < adev->num_ip_blocks; i++) {
1290 if (!adev->ip_block_status[i].valid)
1292 /* enable clockgating to save power */
1293 r = adev->ip_blocks[i].funcs->set_clockgating_state((void *)adev,
1296 DRM_ERROR("set_clockgating_state(gate) %d failed %d\n", i, r);
1299 if (adev->ip_blocks[i].funcs->late_init) {
1300 r = adev->ip_blocks[i].funcs->late_init((void *)adev);
1302 DRM_ERROR("late_init %d failed %d\n", i, r);
1311 static int amdgpu_fini(struct amdgpu_device *adev)
1315 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
1316 if (!adev->ip_block_status[i].hw)
1318 if (adev->ip_blocks[i].type == AMD_IP_BLOCK_TYPE_GMC) {
1319 amdgpu_wb_fini(adev);
1320 amdgpu_vram_scratch_fini(adev);
1322 /* ungate blocks before hw fini so that we can shutdown the blocks safely */
1323 r = adev->ip_blocks[i].funcs->set_clockgating_state((void *)adev,
1324 AMD_CG_STATE_UNGATE);
1326 DRM_ERROR("set_clockgating_state(ungate) %d failed %d\n", i, r);
1329 r = adev->ip_blocks[i].funcs->hw_fini((void *)adev);
1330 /* XXX handle errors */
1332 DRM_DEBUG("hw_fini %d failed %d\n", i, r);
1334 adev->ip_block_status[i].hw = false;
1337 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
1338 if (!adev->ip_block_status[i].sw)
1340 r = adev->ip_blocks[i].funcs->sw_fini((void *)adev);
1341 /* XXX handle errors */
1343 DRM_DEBUG("sw_fini %d failed %d\n", i, r);
1345 adev->ip_block_status[i].sw = false;
1346 adev->ip_block_status[i].valid = false;
1352 static int amdgpu_suspend(struct amdgpu_device *adev)
1356 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
1357 if (!adev->ip_block_status[i].valid)
1359 /* ungate blocks so that suspend can properly shut them down */
1360 r = adev->ip_blocks[i].funcs->set_clockgating_state((void *)adev,
1361 AMD_CG_STATE_UNGATE);
1363 DRM_ERROR("set_clockgating_state(ungate) %d failed %d\n", i, r);
1365 /* XXX handle errors */
1366 r = adev->ip_blocks[i].funcs->suspend(adev);
1367 /* XXX handle errors */
1369 DRM_ERROR("suspend %d failed %d\n", i, r);
1376 static int amdgpu_resume(struct amdgpu_device *adev)
1380 for (i = 0; i < adev->num_ip_blocks; i++) {
1381 if (!adev->ip_block_status[i].valid)
1383 r = adev->ip_blocks[i].funcs->resume(adev);
1385 DRM_ERROR("resume %d failed %d\n", i, r);
1394 * amdgpu_device_init - initialize the driver
1396 * @adev: amdgpu_device pointer
1397 * @pdev: drm dev pointer
1398 * @pdev: pci dev pointer
1399 * @flags: driver flags
1401 * Initializes the driver info and hw (all asics).
1402 * Returns 0 for success or an error on failure.
1403 * Called at driver startup.
1405 int amdgpu_device_init(struct amdgpu_device *adev,
1406 struct drm_device *ddev,
1407 struct pci_dev *pdev,
1411 bool runtime = false;
1413 adev->shutdown = false;
1414 adev->dev = &pdev->dev;
1417 adev->flags = flags;
1418 adev->asic_type = flags & AMD_ASIC_MASK;
1419 adev->is_atom_bios = false;
1420 adev->usec_timeout = AMDGPU_MAX_USEC_TIMEOUT;
1421 adev->mc.gtt_size = 512 * 1024 * 1024;
1422 adev->accel_working = false;
1423 adev->num_rings = 0;
1424 adev->mman.buffer_funcs = NULL;
1425 adev->mman.buffer_funcs_ring = NULL;
1426 adev->vm_manager.vm_pte_funcs = NULL;
1427 adev->vm_manager.vm_pte_funcs_ring = NULL;
1428 adev->gart.gart_funcs = NULL;
1429 adev->fence_context = fence_context_alloc(AMDGPU_MAX_RINGS);
1431 adev->smc_rreg = &amdgpu_invalid_rreg;
1432 adev->smc_wreg = &amdgpu_invalid_wreg;
1433 adev->pcie_rreg = &amdgpu_invalid_rreg;
1434 adev->pcie_wreg = &amdgpu_invalid_wreg;
1435 adev->uvd_ctx_rreg = &amdgpu_invalid_rreg;
1436 adev->uvd_ctx_wreg = &amdgpu_invalid_wreg;
1437 adev->didt_rreg = &amdgpu_invalid_rreg;
1438 adev->didt_wreg = &amdgpu_invalid_wreg;
1439 adev->audio_endpt_rreg = &amdgpu_block_invalid_rreg;
1440 adev->audio_endpt_wreg = &amdgpu_block_invalid_wreg;
1442 DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X 0x%04X:0x%04X 0x%02X).\n",
1443 amdgpu_asic_name[adev->asic_type], pdev->vendor, pdev->device,
1444 pdev->subsystem_vendor, pdev->subsystem_device, pdev->revision);
1446 /* mutex initialization are all done here so we
1447 * can recall function without having locking issues */
1448 mutex_init(&adev->ring_lock);
1449 atomic_set(&adev->irq.ih.lock, 0);
1450 mutex_init(&adev->gem.mutex);
1451 mutex_init(&adev->pm.mutex);
1452 mutex_init(&adev->gfx.gpu_clock_mutex);
1453 mutex_init(&adev->srbm_mutex);
1454 mutex_init(&adev->grbm_idx_mutex);
1455 mutex_init(&adev->mn_lock);
1456 hash_init(adev->mn_hash);
1458 amdgpu_check_arguments(adev);
1460 /* Registers mapping */
1461 /* TODO: block userspace mapping of io register */
1462 spin_lock_init(&adev->mmio_idx_lock);
1463 spin_lock_init(&adev->smc_idx_lock);
1464 spin_lock_init(&adev->pcie_idx_lock);
1465 spin_lock_init(&adev->uvd_ctx_idx_lock);
1466 spin_lock_init(&adev->didt_idx_lock);
1467 spin_lock_init(&adev->audio_endpt_idx_lock);
1469 adev->rmmio_base = pci_resource_start(adev->pdev, 5);
1470 adev->rmmio_size = pci_resource_len(adev->pdev, 5);
1471 adev->rmmio = ioremap(adev->rmmio_base, adev->rmmio_size);
1472 if (adev->rmmio == NULL) {
1475 DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)adev->rmmio_base);
1476 DRM_INFO("register mmio size: %u\n", (unsigned)adev->rmmio_size);
1478 /* doorbell bar mapping */
1479 amdgpu_doorbell_init(adev);
1481 /* io port mapping */
1482 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
1483 if (pci_resource_flags(adev->pdev, i) & IORESOURCE_IO) {
1484 adev->rio_mem_size = pci_resource_len(adev->pdev, i);
1485 adev->rio_mem = pci_iomap(adev->pdev, i, adev->rio_mem_size);
1489 if (adev->rio_mem == NULL)
1490 DRM_ERROR("Unable to find PCI I/O BAR\n");
1492 /* early init functions */
1493 r = amdgpu_early_init(adev);
1497 /* if we have > 1 VGA cards, then disable the amdgpu VGA resources */
1498 /* this will fail for cards that aren't VGA class devices, just
1500 vga_client_register(adev->pdev, adev, NULL, amdgpu_vga_set_decode);
1502 if (amdgpu_runtime_pm == 1)
1504 if (amdgpu_device_is_px(ddev))
1506 vga_switcheroo_register_client(adev->pdev, &amdgpu_switcheroo_ops, runtime);
1508 vga_switcheroo_init_domain_pm_ops(adev->dev, &adev->vga_pm_domain);
1511 if (!amdgpu_get_bios(adev))
1513 /* Must be an ATOMBIOS */
1514 if (!adev->is_atom_bios) {
1515 dev_err(adev->dev, "Expecting atombios for GPU\n");
1518 r = amdgpu_atombios_init(adev);
1520 dev_err(adev->dev, "amdgpu_atombios_init failed\n");
1524 /* Post card if necessary */
1525 if (!amdgpu_card_posted(adev)) {
1527 dev_err(adev->dev, "Card not posted and no BIOS - ignoring\n");
1530 DRM_INFO("GPU not posted. posting now...\n");
1531 amdgpu_atom_asic_init(adev->mode_info.atom_context);
1534 /* Initialize clocks */
1535 r = amdgpu_atombios_get_clock_info(adev);
1537 dev_err(adev->dev, "amdgpu_atombios_get_clock_info failed\n");
1540 /* init i2c buses */
1541 amdgpu_atombios_i2c_init(adev);
1544 r = amdgpu_fence_driver_init(adev);
1546 dev_err(adev->dev, "amdgpu_fence_driver_init failed\n");
1550 /* init the mode config */
1551 drm_mode_config_init(adev->ddev);
1553 r = amdgpu_init(adev);
1555 dev_err(adev->dev, "amdgpu_init failed\n");
1560 adev->accel_working = true;
1562 amdgpu_fbdev_init(adev);
1564 r = amdgpu_ib_pool_init(adev);
1566 dev_err(adev->dev, "IB initialization failed (%d).\n", r);
1570 r = amdgpu_ctx_init(adev, AMD_SCHED_PRIORITY_KERNEL, &adev->kernel_ctx);
1572 dev_err(adev->dev, "failed to create kernel context (%d).\n", r);
1575 r = amdgpu_ib_ring_tests(adev);
1577 DRM_ERROR("ib ring test failed (%d).\n", r);
1579 r = amdgpu_gem_debugfs_init(adev);
1581 DRM_ERROR("registering gem debugfs failed (%d).\n", r);
1584 r = amdgpu_debugfs_regs_init(adev);
1586 DRM_ERROR("registering register debugfs failed (%d).\n", r);
1589 if ((amdgpu_testing & 1)) {
1590 if (adev->accel_working)
1591 amdgpu_test_moves(adev);
1593 DRM_INFO("amdgpu: acceleration disabled, skipping move tests\n");
1595 if ((amdgpu_testing & 2)) {
1596 if (adev->accel_working)
1597 amdgpu_test_syncing(adev);
1599 DRM_INFO("amdgpu: acceleration disabled, skipping sync tests\n");
1601 if (amdgpu_benchmarking) {
1602 if (adev->accel_working)
1603 amdgpu_benchmark(adev, amdgpu_benchmarking);
1605 DRM_INFO("amdgpu: acceleration disabled, skipping benchmarks\n");
1608 /* enable clockgating, etc. after ib tests, etc. since some blocks require
1609 * explicit gating rather than handling it automatically.
1611 r = amdgpu_late_init(adev);
1613 dev_err(adev->dev, "amdgpu_late_init failed\n");
1620 static void amdgpu_debugfs_remove_files(struct amdgpu_device *adev);
1623 * amdgpu_device_fini - tear down the driver
1625 * @adev: amdgpu_device pointer
1627 * Tear down the driver info (all asics).
1628 * Called at driver shutdown.
1630 void amdgpu_device_fini(struct amdgpu_device *adev)
1634 DRM_INFO("amdgpu: finishing device.\n");
1635 adev->shutdown = true;
1636 /* evict vram memory */
1637 amdgpu_bo_evict_vram(adev);
1638 amdgpu_ctx_fini(&adev->kernel_ctx);
1639 amdgpu_ib_pool_fini(adev);
1640 amdgpu_fence_driver_fini(adev);
1641 amdgpu_fbdev_fini(adev);
1642 r = amdgpu_fini(adev);
1643 kfree(adev->ip_block_status);
1644 adev->ip_block_status = NULL;
1645 adev->accel_working = false;
1646 /* free i2c buses */
1647 amdgpu_i2c_fini(adev);
1648 amdgpu_atombios_fini(adev);
1651 vga_switcheroo_unregister_client(adev->pdev);
1652 vga_client_register(adev->pdev, NULL, NULL, NULL);
1654 pci_iounmap(adev->pdev, adev->rio_mem);
1655 adev->rio_mem = NULL;
1656 iounmap(adev->rmmio);
1658 amdgpu_doorbell_fini(adev);
1659 amdgpu_debugfs_regs_cleanup(adev);
1660 amdgpu_debugfs_remove_files(adev);
1668 * amdgpu_suspend_kms - initiate device suspend
1670 * @pdev: drm dev pointer
1671 * @state: suspend state
1673 * Puts the hw in the suspend state (all asics).
1674 * Returns 0 for success or an error on failure.
1675 * Called at driver suspend.
1677 int amdgpu_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon)
1679 struct amdgpu_device *adev;
1680 struct drm_crtc *crtc;
1681 struct drm_connector *connector;
1684 if (dev == NULL || dev->dev_private == NULL) {
1688 adev = dev->dev_private;
1690 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1693 drm_kms_helper_poll_disable(dev);
1695 /* turn off display hw */
1696 drm_modeset_lock_all(dev);
1697 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1698 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF);
1700 drm_modeset_unlock_all(dev);
1702 /* unpin the front buffers and cursors */
1703 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
1704 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1705 struct amdgpu_framebuffer *rfb = to_amdgpu_framebuffer(crtc->primary->fb);
1706 struct amdgpu_bo *robj;
1708 if (amdgpu_crtc->cursor_bo) {
1709 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
1710 r = amdgpu_bo_reserve(aobj, false);
1712 amdgpu_bo_unpin(aobj);
1713 amdgpu_bo_unreserve(aobj);
1717 if (rfb == NULL || rfb->obj == NULL) {
1720 robj = gem_to_amdgpu_bo(rfb->obj);
1721 /* don't unpin kernel fb objects */
1722 if (!amdgpu_fbdev_robj_is_fb(adev, robj)) {
1723 r = amdgpu_bo_reserve(robj, false);
1725 amdgpu_bo_unpin(robj);
1726 amdgpu_bo_unreserve(robj);
1730 /* evict vram memory */
1731 amdgpu_bo_evict_vram(adev);
1733 amdgpu_fence_driver_suspend(adev);
1735 r = amdgpu_suspend(adev);
1737 /* evict remaining vram memory */
1738 amdgpu_bo_evict_vram(adev);
1740 pci_save_state(dev->pdev);
1742 /* Shut down the device */
1743 pci_disable_device(dev->pdev);
1744 pci_set_power_state(dev->pdev, PCI_D3hot);
1749 amdgpu_fbdev_set_suspend(adev, 1);
1756 * amdgpu_resume_kms - initiate device resume
1758 * @pdev: drm dev pointer
1760 * Bring the hw back to operating state (all asics).
1761 * Returns 0 for success or an error on failure.
1762 * Called at driver resume.
1764 int amdgpu_resume_kms(struct drm_device *dev, bool resume, bool fbcon)
1766 struct drm_connector *connector;
1767 struct amdgpu_device *adev = dev->dev_private;
1768 struct drm_crtc *crtc;
1771 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1778 pci_set_power_state(dev->pdev, PCI_D0);
1779 pci_restore_state(dev->pdev);
1780 if (pci_enable_device(dev->pdev)) {
1788 amdgpu_atom_asic_init(adev->mode_info.atom_context);
1790 r = amdgpu_resume(adev);
1792 amdgpu_fence_driver_resume(adev);
1794 r = amdgpu_ib_ring_tests(adev);
1796 DRM_ERROR("ib ring test failed (%d).\n", r);
1798 r = amdgpu_late_init(adev);
1803 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
1804 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1806 if (amdgpu_crtc->cursor_bo) {
1807 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
1808 r = amdgpu_bo_reserve(aobj, false);
1810 r = amdgpu_bo_pin(aobj,
1811 AMDGPU_GEM_DOMAIN_VRAM,
1812 &amdgpu_crtc->cursor_addr);
1814 DRM_ERROR("Failed to pin cursor BO (%d)\n", r);
1815 amdgpu_bo_unreserve(aobj);
1820 /* blat the mode back in */
1822 drm_helper_resume_force_mode(dev);
1823 /* turn on display hw */
1824 drm_modeset_lock_all(dev);
1825 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1826 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON);
1828 drm_modeset_unlock_all(dev);
1831 drm_kms_helper_poll_enable(dev);
1832 drm_helper_hpd_irq_event(dev);
1835 amdgpu_fbdev_set_suspend(adev, 0);
1843 * amdgpu_gpu_reset - reset the asic
1845 * @adev: amdgpu device pointer
1847 * Attempt the reset the GPU if it has hung (all asics).
1848 * Returns 0 for success or an error on failure.
1850 int amdgpu_gpu_reset(struct amdgpu_device *adev)
1852 unsigned ring_sizes[AMDGPU_MAX_RINGS];
1853 uint32_t *ring_data[AMDGPU_MAX_RINGS];
1860 atomic_inc(&adev->gpu_reset_counter);
1863 resched = ttm_bo_lock_delayed_workqueue(&adev->mman.bdev);
1865 r = amdgpu_suspend(adev);
1867 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
1868 struct amdgpu_ring *ring = adev->rings[i];
1872 ring_sizes[i] = amdgpu_ring_backup(ring, &ring_data[i]);
1873 if (ring_sizes[i]) {
1875 dev_info(adev->dev, "Saved %d dwords of commands "
1876 "on ring %d.\n", ring_sizes[i], i);
1881 r = amdgpu_asic_reset(adev);
1883 dev_info(adev->dev, "GPU reset succeeded, trying to resume\n");
1884 r = amdgpu_resume(adev);
1888 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
1889 struct amdgpu_ring *ring = adev->rings[i];
1893 amdgpu_ring_restore(ring, ring_sizes[i], ring_data[i]);
1895 ring_data[i] = NULL;
1898 r = amdgpu_ib_ring_tests(adev);
1900 dev_err(adev->dev, "ib ring test failed (%d).\n", r);
1903 r = amdgpu_suspend(adev);
1908 amdgpu_fence_driver_force_completion(adev);
1909 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
1911 kfree(ring_data[i]);
1915 drm_helper_resume_force_mode(adev->ddev);
1917 ttm_bo_unlock_delayed_workqueue(&adev->mman.bdev, resched);
1919 /* bad news, how to tell it to userspace ? */
1920 dev_info(adev->dev, "GPU reset failed\n");
1930 int amdgpu_debugfs_add_files(struct amdgpu_device *adev,
1931 struct drm_info_list *files,
1936 for (i = 0; i < adev->debugfs_count; i++) {
1937 if (adev->debugfs[i].files == files) {
1938 /* Already registered */
1943 i = adev->debugfs_count + 1;
1944 if (i > AMDGPU_DEBUGFS_MAX_COMPONENTS) {
1945 DRM_ERROR("Reached maximum number of debugfs components.\n");
1946 DRM_ERROR("Report so we increase "
1947 "AMDGPU_DEBUGFS_MAX_COMPONENTS.\n");
1950 adev->debugfs[adev->debugfs_count].files = files;
1951 adev->debugfs[adev->debugfs_count].num_files = nfiles;
1952 adev->debugfs_count = i;
1953 #if defined(CONFIG_DEBUG_FS)
1954 drm_debugfs_create_files(files, nfiles,
1955 adev->ddev->control->debugfs_root,
1956 adev->ddev->control);
1957 drm_debugfs_create_files(files, nfiles,
1958 adev->ddev->primary->debugfs_root,
1959 adev->ddev->primary);
1964 static void amdgpu_debugfs_remove_files(struct amdgpu_device *adev)
1966 #if defined(CONFIG_DEBUG_FS)
1969 for (i = 0; i < adev->debugfs_count; i++) {
1970 drm_debugfs_remove_files(adev->debugfs[i].files,
1971 adev->debugfs[i].num_files,
1972 adev->ddev->control);
1973 drm_debugfs_remove_files(adev->debugfs[i].files,
1974 adev->debugfs[i].num_files,
1975 adev->ddev->primary);
1980 #if defined(CONFIG_DEBUG_FS)
1982 static ssize_t amdgpu_debugfs_regs_read(struct file *f, char __user *buf,
1983 size_t size, loff_t *pos)
1985 struct amdgpu_device *adev = f->f_inode->i_private;
1989 if (size & 0x3 || *pos & 0x3)
1995 if (*pos > adev->rmmio_size)
1998 value = RREG32(*pos >> 2);
1999 r = put_user(value, (uint32_t *)buf);
2012 static ssize_t amdgpu_debugfs_regs_write(struct file *f, const char __user *buf,
2013 size_t size, loff_t *pos)
2015 struct amdgpu_device *adev = f->f_inode->i_private;
2019 if (size & 0x3 || *pos & 0x3)
2025 if (*pos > adev->rmmio_size)
2028 r = get_user(value, (uint32_t *)buf);
2032 WREG32(*pos >> 2, value);
2043 static const struct file_operations amdgpu_debugfs_regs_fops = {
2044 .owner = THIS_MODULE,
2045 .read = amdgpu_debugfs_regs_read,
2046 .write = amdgpu_debugfs_regs_write,
2047 .llseek = default_llseek
2050 static int amdgpu_debugfs_regs_init(struct amdgpu_device *adev)
2052 struct drm_minor *minor = adev->ddev->primary;
2053 struct dentry *ent, *root = minor->debugfs_root;
2055 ent = debugfs_create_file("amdgpu_regs", S_IFREG | S_IRUGO, root,
2056 adev, &amdgpu_debugfs_regs_fops);
2058 return PTR_ERR(ent);
2059 i_size_write(ent->d_inode, adev->rmmio_size);
2060 adev->debugfs_regs = ent;
2065 static void amdgpu_debugfs_regs_cleanup(struct amdgpu_device *adev)
2067 debugfs_remove(adev->debugfs_regs);
2068 adev->debugfs_regs = NULL;
2071 int amdgpu_debugfs_init(struct drm_minor *minor)
2076 void amdgpu_debugfs_cleanup(struct drm_minor *minor)
2080 static int amdgpu_debugfs_regs_init(struct amdgpu_device *adev)
2084 static void amdgpu_debugfs_regs_cleanup(struct amdgpu_device *adev) { }