2 * Copyright 2018 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
23 #ifndef __AMDGPU_CTX_H__
24 #define __AMDGPU_CTX_H__
26 #include "amdgpu_ring.h"
32 #define AMDGPU_MAX_ENTITY_NUM 4
34 struct amdgpu_ctx_entity {
36 struct drm_sched_entity entity;
37 struct dma_fence *fences[];
42 struct amdgpu_device *adev;
43 unsigned reset_counter;
44 unsigned reset_counter_query;
45 uint32_t vram_lost_counter;
47 struct amdgpu_ctx_entity *entities[AMDGPU_HW_IP_NUM][AMDGPU_MAX_ENTITY_NUM];
48 bool preamble_presented;
49 enum drm_sched_priority init_priority;
50 enum drm_sched_priority override_priority;
53 unsigned long ras_counter_ce;
54 unsigned long ras_counter_ue;
57 struct amdgpu_ctx_mgr {
58 struct amdgpu_device *adev;
60 /* protected by lock */
61 struct idr ctx_handles;
64 extern const unsigned int amdgpu_ctx_num_entities[AMDGPU_HW_IP_NUM];
66 struct amdgpu_ctx *amdgpu_ctx_get(struct amdgpu_fpriv *fpriv, uint32_t id);
67 int amdgpu_ctx_put(struct amdgpu_ctx *ctx);
69 int amdgpu_ctx_get_entity(struct amdgpu_ctx *ctx, u32 hw_ip, u32 instance,
70 u32 ring, struct drm_sched_entity **entity);
71 void amdgpu_ctx_add_fence(struct amdgpu_ctx *ctx,
72 struct drm_sched_entity *entity,
73 struct dma_fence *fence, uint64_t *seq);
74 struct dma_fence *amdgpu_ctx_get_fence(struct amdgpu_ctx *ctx,
75 struct drm_sched_entity *entity,
77 void amdgpu_ctx_priority_override(struct amdgpu_ctx *ctx,
78 enum drm_sched_priority priority);
80 int amdgpu_ctx_ioctl(struct drm_device *dev, void *data,
81 struct drm_file *filp);
83 int amdgpu_ctx_wait_prev_fence(struct amdgpu_ctx *ctx,
84 struct drm_sched_entity *entity);
86 void amdgpu_ctx_mgr_init(struct amdgpu_ctx_mgr *mgr);
87 void amdgpu_ctx_mgr_entity_fini(struct amdgpu_ctx_mgr *mgr);
88 long amdgpu_ctx_mgr_entity_flush(struct amdgpu_ctx_mgr *mgr, long timeout);
89 void amdgpu_ctx_mgr_fini(struct amdgpu_ctx_mgr *mgr);
90 ktime_t amdgpu_ctx_mgr_fence_usage(struct amdgpu_ctx_mgr *mgr, uint32_t hwip,
91 uint32_t idx, uint64_t *elapsed);
92 void amdgpu_ctx_fence_time(struct amdgpu_ctx *ctx, struct amdgpu_ctx_entity *centity,
93 ktime_t *total, ktime_t *max);