2 * Copyright 2008 Jerome Glisse.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
25 * Jerome Glisse <glisse@freedesktop.org>
28 #include <linux/file.h>
29 #include <linux/pagemap.h>
30 #include <linux/sync_file.h>
31 #include <linux/dma-buf.h>
33 #include <drm/amdgpu_drm.h>
34 #include <drm/drm_syncobj.h>
35 #include "amdgpu_cs.h"
37 #include "amdgpu_trace.h"
38 #include "amdgpu_gmc.h"
39 #include "amdgpu_gem.h"
40 #include "amdgpu_ras.h"
42 static int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p,
43 struct amdgpu_device *adev,
44 struct drm_file *filp,
45 union drm_amdgpu_cs *cs)
47 struct amdgpu_fpriv *fpriv = filp->driver_priv;
49 if (cs->in.num_chunks == 0)
52 memset(p, 0, sizeof(*p));
56 p->ctx = amdgpu_ctx_get(fpriv, cs->in.ctx_id);
60 if (atomic_read(&p->ctx->guilty)) {
61 amdgpu_ctx_put(p->ctx);
65 amdgpu_sync_create(&p->sync);
69 static int amdgpu_cs_job_idx(struct amdgpu_cs_parser *p,
70 struct drm_amdgpu_cs_chunk_ib *chunk_ib)
72 struct drm_sched_entity *entity;
76 r = amdgpu_ctx_get_entity(p->ctx, chunk_ib->ip_type,
77 chunk_ib->ip_instance,
78 chunk_ib->ring, &entity);
83 * Abort if there is no run queue associated with this entity.
84 * Possibly because of disabled HW IP.
86 if (entity->rq == NULL)
89 /* Check if we can add this IB to some existing job */
90 for (i = 0; i < p->gang_size; ++i)
91 if (p->entities[i] == entity)
94 /* If not increase the gang size if possible */
95 if (i == AMDGPU_CS_GANG_SIZE)
98 p->entities[i] = entity;
103 static int amdgpu_cs_p1_ib(struct amdgpu_cs_parser *p,
104 struct drm_amdgpu_cs_chunk_ib *chunk_ib,
105 unsigned int *num_ibs)
109 r = amdgpu_cs_job_idx(p, chunk_ib);
114 p->gang_leader_idx = r;
118 static int amdgpu_cs_p1_user_fence(struct amdgpu_cs_parser *p,
119 struct drm_amdgpu_cs_chunk_fence *data,
122 struct drm_gem_object *gobj;
123 struct amdgpu_bo *bo;
127 gobj = drm_gem_object_lookup(p->filp, data->handle);
131 bo = amdgpu_bo_ref(gem_to_amdgpu_bo(gobj));
132 p->uf_entry.priority = 0;
133 p->uf_entry.tv.bo = &bo->tbo;
134 /* One for TTM and two for the CS job */
135 p->uf_entry.tv.num_shared = 3;
137 drm_gem_object_put(gobj);
139 size = amdgpu_bo_size(bo);
140 if (size != PAGE_SIZE || (data->offset + 8) > size) {
145 if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm)) {
150 *offset = data->offset;
155 amdgpu_bo_unref(&bo);
159 static int amdgpu_cs_p1_bo_handles(struct amdgpu_cs_parser *p,
160 struct drm_amdgpu_bo_list_in *data)
162 struct drm_amdgpu_bo_list_entry *info;
165 r = amdgpu_bo_create_list_entry_array(data, &info);
169 r = amdgpu_bo_list_create(p->adev, p->filp, info, data->bo_number,
183 /* Copy the data from userspace and go over it the first time */
184 static int amdgpu_cs_pass1(struct amdgpu_cs_parser *p,
185 union drm_amdgpu_cs *cs)
187 struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
188 unsigned int num_ibs[AMDGPU_CS_GANG_SIZE] = { };
189 struct amdgpu_vm *vm = &fpriv->vm;
190 uint64_t *chunk_array_user;
191 uint64_t *chunk_array;
192 uint32_t uf_offset = 0;
197 chunk_array = kvmalloc_array(cs->in.num_chunks, sizeof(uint64_t),
203 chunk_array_user = u64_to_user_ptr(cs->in.chunks);
204 if (copy_from_user(chunk_array, chunk_array_user,
205 sizeof(uint64_t)*cs->in.num_chunks)) {
210 p->nchunks = cs->in.num_chunks;
211 p->chunks = kvmalloc_array(p->nchunks, sizeof(struct amdgpu_cs_chunk),
218 for (i = 0; i < p->nchunks; i++) {
219 struct drm_amdgpu_cs_chunk __user **chunk_ptr = NULL;
220 struct drm_amdgpu_cs_chunk user_chunk;
221 uint32_t __user *cdata;
223 chunk_ptr = u64_to_user_ptr(chunk_array[i]);
224 if (copy_from_user(&user_chunk, chunk_ptr,
225 sizeof(struct drm_amdgpu_cs_chunk))) {
228 goto free_partial_kdata;
230 p->chunks[i].chunk_id = user_chunk.chunk_id;
231 p->chunks[i].length_dw = user_chunk.length_dw;
233 size = p->chunks[i].length_dw;
234 cdata = u64_to_user_ptr(user_chunk.chunk_data);
236 p->chunks[i].kdata = kvmalloc_array(size, sizeof(uint32_t),
238 if (p->chunks[i].kdata == NULL) {
241 goto free_partial_kdata;
243 size *= sizeof(uint32_t);
244 if (copy_from_user(p->chunks[i].kdata, cdata, size)) {
246 goto free_partial_kdata;
249 /* Assume the worst on the following checks */
251 switch (p->chunks[i].chunk_id) {
252 case AMDGPU_CHUNK_ID_IB:
253 if (size < sizeof(struct drm_amdgpu_cs_chunk_ib))
254 goto free_partial_kdata;
256 ret = amdgpu_cs_p1_ib(p, p->chunks[i].kdata, num_ibs);
258 goto free_partial_kdata;
261 case AMDGPU_CHUNK_ID_FENCE:
262 if (size < sizeof(struct drm_amdgpu_cs_chunk_fence))
263 goto free_partial_kdata;
265 ret = amdgpu_cs_p1_user_fence(p, p->chunks[i].kdata,
268 goto free_partial_kdata;
271 case AMDGPU_CHUNK_ID_BO_HANDLES:
272 if (size < sizeof(struct drm_amdgpu_bo_list_in))
273 goto free_partial_kdata;
275 ret = amdgpu_cs_p1_bo_handles(p, p->chunks[i].kdata);
277 goto free_partial_kdata;
280 case AMDGPU_CHUNK_ID_DEPENDENCIES:
281 case AMDGPU_CHUNK_ID_SYNCOBJ_IN:
282 case AMDGPU_CHUNK_ID_SYNCOBJ_OUT:
283 case AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES:
284 case AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT:
285 case AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL:
289 goto free_partial_kdata;
295 goto free_partial_kdata;
298 for (i = 0; i < p->gang_size; ++i) {
299 ret = amdgpu_job_alloc(p->adev, vm, p->entities[i], vm,
300 num_ibs[i], &p->jobs[i]);
304 p->gang_leader = p->jobs[p->gang_leader_idx];
306 if (p->ctx->vram_lost_counter != p->gang_leader->vram_lost_counter) {
311 if (p->uf_entry.tv.bo)
312 p->gang_leader->uf_addr = uf_offset;
315 /* Use this opportunity to fill in task info for the vm */
316 amdgpu_vm_set_task_info(vm);
324 kvfree(p->chunks[i].kdata);
334 static int amdgpu_cs_p2_ib(struct amdgpu_cs_parser *p,
335 struct amdgpu_cs_chunk *chunk,
336 unsigned int *ce_preempt,
337 unsigned int *de_preempt)
339 struct drm_amdgpu_cs_chunk_ib *chunk_ib = chunk->kdata;
340 struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
341 struct amdgpu_vm *vm = &fpriv->vm;
342 struct amdgpu_ring *ring;
343 struct amdgpu_job *job;
344 struct amdgpu_ib *ib;
347 r = amdgpu_cs_job_idx(p, chunk_ib);
352 ring = amdgpu_job_ring(job);
353 ib = &job->ibs[job->num_ibs++];
355 /* MM engine doesn't support user fences */
356 if (p->uf_entry.tv.bo && ring->funcs->no_user_fence)
359 if (chunk_ib->ip_type == AMDGPU_HW_IP_GFX &&
360 chunk_ib->flags & AMDGPU_IB_FLAG_PREEMPT) {
361 if (chunk_ib->flags & AMDGPU_IB_FLAG_CE)
366 /* Each GFX command submit allows only 1 IB max
367 * preemptible for CE & DE */
368 if (*ce_preempt > 1 || *de_preempt > 1)
372 if (chunk_ib->flags & AMDGPU_IB_FLAG_PREAMBLE)
373 job->preamble_status |= AMDGPU_PREAMBLE_IB_PRESENT;
375 r = amdgpu_ib_get(p->adev, vm, ring->funcs->parse_cs ?
376 chunk_ib->ib_bytes : 0,
377 AMDGPU_IB_POOL_DELAYED, ib);
379 DRM_ERROR("Failed to get ib !\n");
383 ib->gpu_addr = chunk_ib->va_start;
384 ib->length_dw = chunk_ib->ib_bytes / 4;
385 ib->flags = chunk_ib->flags;
389 static int amdgpu_cs_p2_dependencies(struct amdgpu_cs_parser *p,
390 struct amdgpu_cs_chunk *chunk)
392 struct drm_amdgpu_cs_chunk_dep *deps = chunk->kdata;
393 struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
397 num_deps = chunk->length_dw * 4 /
398 sizeof(struct drm_amdgpu_cs_chunk_dep);
400 for (i = 0; i < num_deps; ++i) {
401 struct amdgpu_ctx *ctx;
402 struct drm_sched_entity *entity;
403 struct dma_fence *fence;
405 ctx = amdgpu_ctx_get(fpriv, deps[i].ctx_id);
409 r = amdgpu_ctx_get_entity(ctx, deps[i].ip_type,
411 deps[i].ring, &entity);
417 fence = amdgpu_ctx_get_fence(ctx, entity, deps[i].handle);
421 return PTR_ERR(fence);
425 if (chunk->chunk_id == AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES) {
426 struct drm_sched_fence *s_fence;
427 struct dma_fence *old = fence;
429 s_fence = to_drm_sched_fence(fence);
430 fence = dma_fence_get(&s_fence->scheduled);
434 r = amdgpu_sync_fence(&p->sync, fence);
435 dma_fence_put(fence);
442 static int amdgpu_syncobj_lookup_and_add(struct amdgpu_cs_parser *p,
443 uint32_t handle, u64 point,
446 struct dma_fence *fence;
449 r = drm_syncobj_find_fence(p->filp, handle, point, flags, &fence);
451 DRM_ERROR("syncobj %u failed to find fence @ %llu (%d)!\n",
456 r = amdgpu_sync_fence(&p->sync, fence);
457 dma_fence_put(fence);
461 static int amdgpu_cs_p2_syncobj_in(struct amdgpu_cs_parser *p,
462 struct amdgpu_cs_chunk *chunk)
464 struct drm_amdgpu_cs_chunk_sem *deps = chunk->kdata;
468 num_deps = chunk->length_dw * 4 /
469 sizeof(struct drm_amdgpu_cs_chunk_sem);
470 for (i = 0; i < num_deps; ++i) {
471 r = amdgpu_syncobj_lookup_and_add(p, deps[i].handle, 0, 0);
479 static int amdgpu_cs_p2_syncobj_timeline_wait(struct amdgpu_cs_parser *p,
480 struct amdgpu_cs_chunk *chunk)
482 struct drm_amdgpu_cs_chunk_syncobj *syncobj_deps = chunk->kdata;
486 num_deps = chunk->length_dw * 4 /
487 sizeof(struct drm_amdgpu_cs_chunk_syncobj);
488 for (i = 0; i < num_deps; ++i) {
489 r = amdgpu_syncobj_lookup_and_add(p, syncobj_deps[i].handle,
490 syncobj_deps[i].point,
491 syncobj_deps[i].flags);
499 static int amdgpu_cs_p2_syncobj_out(struct amdgpu_cs_parser *p,
500 struct amdgpu_cs_chunk *chunk)
502 struct drm_amdgpu_cs_chunk_sem *deps = chunk->kdata;
506 num_deps = chunk->length_dw * 4 /
507 sizeof(struct drm_amdgpu_cs_chunk_sem);
512 p->post_deps = kmalloc_array(num_deps, sizeof(*p->post_deps),
514 p->num_post_deps = 0;
520 for (i = 0; i < num_deps; ++i) {
521 p->post_deps[i].syncobj =
522 drm_syncobj_find(p->filp, deps[i].handle);
523 if (!p->post_deps[i].syncobj)
525 p->post_deps[i].chain = NULL;
526 p->post_deps[i].point = 0;
533 static int amdgpu_cs_p2_syncobj_timeline_signal(struct amdgpu_cs_parser *p,
534 struct amdgpu_cs_chunk *chunk)
536 struct drm_amdgpu_cs_chunk_syncobj *syncobj_deps = chunk->kdata;
540 num_deps = chunk->length_dw * 4 /
541 sizeof(struct drm_amdgpu_cs_chunk_syncobj);
546 p->post_deps = kmalloc_array(num_deps, sizeof(*p->post_deps),
548 p->num_post_deps = 0;
553 for (i = 0; i < num_deps; ++i) {
554 struct amdgpu_cs_post_dep *dep = &p->post_deps[i];
557 if (syncobj_deps[i].point) {
558 dep->chain = dma_fence_chain_alloc();
563 dep->syncobj = drm_syncobj_find(p->filp,
564 syncobj_deps[i].handle);
566 dma_fence_chain_free(dep->chain);
569 dep->point = syncobj_deps[i].point;
576 static int amdgpu_cs_pass2(struct amdgpu_cs_parser *p)
578 unsigned int ce_preempt = 0, de_preempt = 0;
581 for (i = 0; i < p->nchunks; ++i) {
582 struct amdgpu_cs_chunk *chunk;
584 chunk = &p->chunks[i];
586 switch (chunk->chunk_id) {
587 case AMDGPU_CHUNK_ID_IB:
588 r = amdgpu_cs_p2_ib(p, chunk, &ce_preempt, &de_preempt);
592 case AMDGPU_CHUNK_ID_DEPENDENCIES:
593 case AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES:
594 r = amdgpu_cs_p2_dependencies(p, chunk);
598 case AMDGPU_CHUNK_ID_SYNCOBJ_IN:
599 r = amdgpu_cs_p2_syncobj_in(p, chunk);
603 case AMDGPU_CHUNK_ID_SYNCOBJ_OUT:
604 r = amdgpu_cs_p2_syncobj_out(p, chunk);
608 case AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT:
609 r = amdgpu_cs_p2_syncobj_timeline_wait(p, chunk);
613 case AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL:
614 r = amdgpu_cs_p2_syncobj_timeline_signal(p, chunk);
624 /* Convert microseconds to bytes. */
625 static u64 us_to_bytes(struct amdgpu_device *adev, s64 us)
627 if (us <= 0 || !adev->mm_stats.log2_max_MBps)
630 /* Since accum_us is incremented by a million per second, just
631 * multiply it by the number of MB/s to get the number of bytes.
633 return us << adev->mm_stats.log2_max_MBps;
636 static s64 bytes_to_us(struct amdgpu_device *adev, u64 bytes)
638 if (!adev->mm_stats.log2_max_MBps)
641 return bytes >> adev->mm_stats.log2_max_MBps;
644 /* Returns how many bytes TTM can move right now. If no bytes can be moved,
645 * it returns 0. If it returns non-zero, it's OK to move at least one buffer,
646 * which means it can go over the threshold once. If that happens, the driver
647 * will be in debt and no other buffer migrations can be done until that debt
650 * This approach allows moving a buffer of any size (it's important to allow
653 * The currency is simply time in microseconds and it increases as the clock
654 * ticks. The accumulated microseconds (us) are converted to bytes and
657 static void amdgpu_cs_get_threshold_for_moves(struct amdgpu_device *adev,
661 s64 time_us, increment_us;
662 u64 free_vram, total_vram, used_vram;
663 /* Allow a maximum of 200 accumulated ms. This is basically per-IB
666 * It means that in order to get full max MBps, at least 5 IBs per
667 * second must be submitted and not more than 200ms apart from each
670 const s64 us_upper_bound = 200000;
672 if (!adev->mm_stats.log2_max_MBps) {
678 total_vram = adev->gmc.real_vram_size - atomic64_read(&adev->vram_pin_size);
679 used_vram = ttm_resource_manager_usage(&adev->mman.vram_mgr.manager);
680 free_vram = used_vram >= total_vram ? 0 : total_vram - used_vram;
682 spin_lock(&adev->mm_stats.lock);
684 /* Increase the amount of accumulated us. */
685 time_us = ktime_to_us(ktime_get());
686 increment_us = time_us - adev->mm_stats.last_update_us;
687 adev->mm_stats.last_update_us = time_us;
688 adev->mm_stats.accum_us = min(adev->mm_stats.accum_us + increment_us,
691 /* This prevents the short period of low performance when the VRAM
692 * usage is low and the driver is in debt or doesn't have enough
693 * accumulated us to fill VRAM quickly.
695 * The situation can occur in these cases:
696 * - a lot of VRAM is freed by userspace
697 * - the presence of a big buffer causes a lot of evictions
698 * (solution: split buffers into smaller ones)
700 * If 128 MB or 1/8th of VRAM is free, start filling it now by setting
701 * accum_us to a positive number.
703 if (free_vram >= 128 * 1024 * 1024 || free_vram >= total_vram / 8) {
706 /* Be more aggressive on dGPUs. Try to fill a portion of free
709 if (!(adev->flags & AMD_IS_APU))
710 min_us = bytes_to_us(adev, free_vram / 4);
712 min_us = 0; /* Reset accum_us on APUs. */
714 adev->mm_stats.accum_us = max(min_us, adev->mm_stats.accum_us);
717 /* This is set to 0 if the driver is in debt to disallow (optional)
720 *max_bytes = us_to_bytes(adev, adev->mm_stats.accum_us);
722 /* Do the same for visible VRAM if half of it is free */
723 if (!amdgpu_gmc_vram_full_visible(&adev->gmc)) {
724 u64 total_vis_vram = adev->gmc.visible_vram_size;
726 amdgpu_vram_mgr_vis_usage(&adev->mman.vram_mgr);
728 if (used_vis_vram < total_vis_vram) {
729 u64 free_vis_vram = total_vis_vram - used_vis_vram;
730 adev->mm_stats.accum_us_vis = min(adev->mm_stats.accum_us_vis +
731 increment_us, us_upper_bound);
733 if (free_vis_vram >= total_vis_vram / 2)
734 adev->mm_stats.accum_us_vis =
735 max(bytes_to_us(adev, free_vis_vram / 2),
736 adev->mm_stats.accum_us_vis);
739 *max_vis_bytes = us_to_bytes(adev, adev->mm_stats.accum_us_vis);
744 spin_unlock(&adev->mm_stats.lock);
747 /* Report how many bytes have really been moved for the last command
748 * submission. This can result in a debt that can stop buffer migrations
751 void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes,
754 spin_lock(&adev->mm_stats.lock);
755 adev->mm_stats.accum_us -= bytes_to_us(adev, num_bytes);
756 adev->mm_stats.accum_us_vis -= bytes_to_us(adev, num_vis_bytes);
757 spin_unlock(&adev->mm_stats.lock);
760 static int amdgpu_cs_bo_validate(void *param, struct amdgpu_bo *bo)
762 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
763 struct amdgpu_cs_parser *p = param;
764 struct ttm_operation_ctx ctx = {
765 .interruptible = true,
766 .no_wait_gpu = false,
767 .resv = bo->tbo.base.resv
772 if (bo->tbo.pin_count)
775 /* Don't move this buffer if we have depleted our allowance
776 * to move it. Don't move anything if the threshold is zero.
778 if (p->bytes_moved < p->bytes_moved_threshold &&
779 (!bo->tbo.base.dma_buf ||
780 list_empty(&bo->tbo.base.dma_buf->attachments))) {
781 if (!amdgpu_gmc_vram_full_visible(&adev->gmc) &&
782 (bo->flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED)) {
783 /* And don't move a CPU_ACCESS_REQUIRED BO to limited
784 * visible VRAM if we've depleted our allowance to do
787 if (p->bytes_moved_vis < p->bytes_moved_vis_threshold)
788 domain = bo->preferred_domains;
790 domain = bo->allowed_domains;
792 domain = bo->preferred_domains;
795 domain = bo->allowed_domains;
799 amdgpu_bo_placement_from_domain(bo, domain);
800 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
802 p->bytes_moved += ctx.bytes_moved;
803 if (!amdgpu_gmc_vram_full_visible(&adev->gmc) &&
804 amdgpu_bo_in_cpu_visible_vram(bo))
805 p->bytes_moved_vis += ctx.bytes_moved;
807 if (unlikely(r == -ENOMEM) && domain != bo->allowed_domains) {
808 domain = bo->allowed_domains;
815 static int amdgpu_cs_list_validate(struct amdgpu_cs_parser *p,
816 struct list_head *validated)
818 struct ttm_operation_ctx ctx = { true, false };
819 struct amdgpu_bo_list_entry *lobj;
822 list_for_each_entry(lobj, validated, tv.head) {
823 struct amdgpu_bo *bo = ttm_to_amdgpu_bo(lobj->tv.bo);
824 struct mm_struct *usermm;
826 usermm = amdgpu_ttm_tt_get_usermm(bo->tbo.ttm);
827 if (usermm && usermm != current->mm)
830 if (amdgpu_ttm_tt_is_userptr(bo->tbo.ttm) &&
831 lobj->user_invalidated && lobj->user_pages) {
832 amdgpu_bo_placement_from_domain(bo,
833 AMDGPU_GEM_DOMAIN_CPU);
834 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
838 amdgpu_ttm_tt_set_user_pages(bo->tbo.ttm,
842 r = amdgpu_cs_bo_validate(p, bo);
846 kvfree(lobj->user_pages);
847 lobj->user_pages = NULL;
852 static int amdgpu_cs_parser_bos(struct amdgpu_cs_parser *p,
853 union drm_amdgpu_cs *cs)
855 struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
856 struct amdgpu_vm *vm = &fpriv->vm;
857 struct amdgpu_bo_list_entry *e;
858 struct list_head duplicates;
862 INIT_LIST_HEAD(&p->validated);
864 /* p->bo_list could already be assigned if AMDGPU_CHUNK_ID_BO_HANDLES is present */
865 if (cs->in.bo_list_handle) {
869 r = amdgpu_bo_list_get(fpriv, cs->in.bo_list_handle,
873 } else if (!p->bo_list) {
874 /* Create a empty bo_list when no handle is provided */
875 r = amdgpu_bo_list_create(p->adev, p->filp, NULL, 0,
881 mutex_lock(&p->bo_list->bo_list_mutex);
883 /* One for TTM and one for the CS job */
884 amdgpu_bo_list_for_each_entry(e, p->bo_list)
885 e->tv.num_shared = 2;
887 amdgpu_bo_list_get_list(p->bo_list, &p->validated);
889 INIT_LIST_HEAD(&duplicates);
890 amdgpu_vm_get_pd_bo(&fpriv->vm, &p->validated, &p->vm_pd);
892 if (p->uf_entry.tv.bo && !ttm_to_amdgpu_bo(p->uf_entry.tv.bo)->parent)
893 list_add(&p->uf_entry.tv.head, &p->validated);
895 /* Get userptr backing pages. If pages are updated after registered
896 * in amdgpu_gem_userptr_ioctl(), amdgpu_cs_list_validate() will do
897 * amdgpu_ttm_backend_bind() to flush and invalidate new pages
899 amdgpu_bo_list_for_each_userptr_entry(e, p->bo_list) {
900 struct amdgpu_bo *bo = ttm_to_amdgpu_bo(e->tv.bo);
901 bool userpage_invalidated = false;
904 e->user_pages = kvmalloc_array(bo->tbo.ttm->num_pages,
905 sizeof(struct page *),
906 GFP_KERNEL | __GFP_ZERO);
907 if (!e->user_pages) {
908 DRM_ERROR("kvmalloc_array failure\n");
910 goto out_free_user_pages;
913 r = amdgpu_ttm_tt_get_user_pages(bo, e->user_pages, &e->range);
915 kvfree(e->user_pages);
916 e->user_pages = NULL;
917 goto out_free_user_pages;
920 for (i = 0; i < bo->tbo.ttm->num_pages; i++) {
921 if (bo->tbo.ttm->pages[i] != e->user_pages[i]) {
922 userpage_invalidated = true;
926 e->user_invalidated = userpage_invalidated;
929 r = ttm_eu_reserve_buffers(&p->ticket, &p->validated, true,
931 if (unlikely(r != 0)) {
932 if (r != -ERESTARTSYS)
933 DRM_ERROR("ttm_eu_reserve_buffers failed.\n");
934 goto out_free_user_pages;
937 amdgpu_bo_list_for_each_entry(e, p->bo_list) {
938 struct amdgpu_bo *bo = ttm_to_amdgpu_bo(e->tv.bo);
940 e->bo_va = amdgpu_vm_bo_find(vm, bo);
943 amdgpu_cs_get_threshold_for_moves(p->adev, &p->bytes_moved_threshold,
944 &p->bytes_moved_vis_threshold);
946 p->bytes_moved_vis = 0;
948 r = amdgpu_vm_validate_pt_bos(p->adev, &fpriv->vm,
949 amdgpu_cs_bo_validate, p);
951 DRM_ERROR("amdgpu_vm_validate_pt_bos() failed.\n");
955 r = amdgpu_cs_list_validate(p, &duplicates);
959 r = amdgpu_cs_list_validate(p, &p->validated);
963 if (p->uf_entry.tv.bo) {
964 struct amdgpu_bo *uf = ttm_to_amdgpu_bo(p->uf_entry.tv.bo);
966 r = amdgpu_ttm_alloc_gart(&uf->tbo);
970 p->gang_leader->uf_addr += amdgpu_bo_gpu_offset(uf);
973 amdgpu_cs_report_moved_bytes(p->adev, p->bytes_moved,
976 for (i = 0; i < p->gang_size; ++i)
977 amdgpu_job_set_resources(p->jobs[i], p->bo_list->gds_obj,
983 ttm_eu_backoff_reservation(&p->ticket, &p->validated);
986 amdgpu_bo_list_for_each_userptr_entry(e, p->bo_list) {
987 struct amdgpu_bo *bo = ttm_to_amdgpu_bo(e->tv.bo);
991 amdgpu_ttm_tt_get_user_pages_done(bo->tbo.ttm, e->range);
992 kvfree(e->user_pages);
993 e->user_pages = NULL;
996 mutex_unlock(&p->bo_list->bo_list_mutex);
1000 static void trace_amdgpu_cs_ibs(struct amdgpu_cs_parser *p)
1004 if (!trace_amdgpu_cs_enabled())
1007 for (i = 0; i < p->gang_size; ++i) {
1008 struct amdgpu_job *job = p->jobs[i];
1010 for (j = 0; j < job->num_ibs; ++j)
1011 trace_amdgpu_cs(p, job, &job->ibs[j]);
1015 static int amdgpu_cs_patch_ibs(struct amdgpu_cs_parser *p,
1016 struct amdgpu_job *job)
1018 struct amdgpu_ring *ring = amdgpu_job_ring(job);
1022 /* Only for UVD/VCE VM emulation */
1023 if (!ring->funcs->parse_cs && !ring->funcs->patch_cs_in_place)
1026 for (i = 0; i < job->num_ibs; ++i) {
1027 struct amdgpu_ib *ib = &job->ibs[i];
1028 struct amdgpu_bo_va_mapping *m;
1029 struct amdgpu_bo *aobj;
1033 va_start = ib->gpu_addr & AMDGPU_GMC_HOLE_MASK;
1034 r = amdgpu_cs_find_mapping(p, va_start, &aobj, &m);
1036 DRM_ERROR("IB va_start is invalid\n");
1040 if ((va_start + ib->length_dw * 4) >
1041 (m->last + 1) * AMDGPU_GPU_PAGE_SIZE) {
1042 DRM_ERROR("IB va_start+ib_bytes is invalid\n");
1046 /* the IB should be reserved at this point */
1047 r = amdgpu_bo_kmap(aobj, (void **)&kptr);
1052 kptr += va_start - (m->start * AMDGPU_GPU_PAGE_SIZE);
1054 if (ring->funcs->parse_cs) {
1055 memcpy(ib->ptr, kptr, ib->length_dw * 4);
1056 amdgpu_bo_kunmap(aobj);
1058 r = amdgpu_ring_parse_cs(ring, p, job, ib);
1062 ib->ptr = (uint32_t *)kptr;
1063 r = amdgpu_ring_patch_cs_in_place(ring, p, job, ib);
1064 amdgpu_bo_kunmap(aobj);
1073 static int amdgpu_cs_patch_jobs(struct amdgpu_cs_parser *p)
1078 for (i = 0; i < p->gang_size; ++i) {
1079 r = amdgpu_cs_patch_ibs(p, p->jobs[i]);
1086 static int amdgpu_cs_vm_handling(struct amdgpu_cs_parser *p)
1088 struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
1089 struct amdgpu_job *job = p->gang_leader;
1090 struct amdgpu_device *adev = p->adev;
1091 struct amdgpu_vm *vm = &fpriv->vm;
1092 struct amdgpu_bo_list_entry *e;
1093 struct amdgpu_bo_va *bo_va;
1094 struct amdgpu_bo *bo;
1098 r = amdgpu_vm_clear_freed(adev, vm, NULL);
1102 r = amdgpu_vm_bo_update(adev, fpriv->prt_va, false);
1106 r = amdgpu_sync_fence(&p->sync, fpriv->prt_va->last_pt_update);
1110 if (fpriv->csa_va) {
1111 bo_va = fpriv->csa_va;
1113 r = amdgpu_vm_bo_update(adev, bo_va, false);
1117 r = amdgpu_sync_fence(&p->sync, bo_va->last_pt_update);
1122 amdgpu_bo_list_for_each_entry(e, p->bo_list) {
1123 /* ignore duplicates */
1124 bo = ttm_to_amdgpu_bo(e->tv.bo);
1132 r = amdgpu_vm_bo_update(adev, bo_va, false);
1136 r = amdgpu_sync_fence(&p->sync, bo_va->last_pt_update);
1141 r = amdgpu_vm_handle_moved(adev, vm);
1145 r = amdgpu_vm_update_pdes(adev, vm, false);
1149 r = amdgpu_sync_fence(&p->sync, vm->last_update);
1153 for (i = 0; i < p->gang_size; ++i) {
1159 job->vm_pd_addr = amdgpu_gmc_pd_addr(vm->root.bo);
1162 if (amdgpu_vm_debug) {
1163 /* Invalidate all BOs to test for userspace bugs */
1164 amdgpu_bo_list_for_each_entry(e, p->bo_list) {
1165 struct amdgpu_bo *bo = ttm_to_amdgpu_bo(e->tv.bo);
1167 /* ignore duplicates */
1171 amdgpu_vm_bo_invalidate(adev, bo, false);
1178 static int amdgpu_cs_sync_rings(struct amdgpu_cs_parser *p)
1180 struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
1181 struct drm_gpu_scheduler *sched;
1182 struct amdgpu_bo_list_entry *e;
1183 struct dma_fence *fence;
1187 r = amdgpu_ctx_wait_prev_fence(p->ctx, p->entities[p->gang_leader_idx]);
1189 if (r != -ERESTARTSYS)
1190 DRM_ERROR("amdgpu_ctx_wait_prev_fence failed.\n");
1194 list_for_each_entry(e, &p->validated, tv.head) {
1195 struct amdgpu_bo *bo = ttm_to_amdgpu_bo(e->tv.bo);
1196 struct dma_resv *resv = bo->tbo.base.resv;
1197 enum amdgpu_sync_mode sync_mode;
1199 sync_mode = amdgpu_bo_explicit_sync(bo) ?
1200 AMDGPU_SYNC_EXPLICIT : AMDGPU_SYNC_NE_OWNER;
1201 r = amdgpu_sync_resv(p->adev, &p->sync, resv, sync_mode,
1207 for (i = 0; i < p->gang_size; ++i) {
1208 r = amdgpu_sync_push_to_job(&p->sync, p->jobs[i]);
1213 sched = p->gang_leader->base.entity->rq->sched;
1214 while ((fence = amdgpu_sync_get_fence(&p->sync))) {
1215 struct drm_sched_fence *s_fence = to_drm_sched_fence(fence);
1218 * When we have an dependency it might be necessary to insert a
1219 * pipeline sync to make sure that all caches etc are flushed and the
1220 * next job actually sees the results from the previous one
1221 * before we start executing on the same scheduler ring.
1223 if (!s_fence || s_fence->sched != sched)
1226 r = amdgpu_sync_fence(&p->gang_leader->explicit_sync, fence);
1233 static void amdgpu_cs_post_dependencies(struct amdgpu_cs_parser *p)
1237 for (i = 0; i < p->num_post_deps; ++i) {
1238 if (p->post_deps[i].chain && p->post_deps[i].point) {
1239 drm_syncobj_add_point(p->post_deps[i].syncobj,
1240 p->post_deps[i].chain,
1241 p->fence, p->post_deps[i].point);
1242 p->post_deps[i].chain = NULL;
1244 drm_syncobj_replace_fence(p->post_deps[i].syncobj,
1250 static int amdgpu_cs_submit(struct amdgpu_cs_parser *p,
1251 union drm_amdgpu_cs *cs)
1253 struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
1254 struct amdgpu_job *leader = p->gang_leader;
1255 struct amdgpu_bo_list_entry *e;
1260 for (i = 0; i < p->gang_size; ++i)
1261 drm_sched_job_arm(&p->jobs[i]->base);
1263 for (i = 0; i < p->gang_size; ++i) {
1264 struct dma_fence *fence;
1266 if (p->jobs[i] == leader)
1269 fence = &p->jobs[i]->base.s_fence->scheduled;
1270 dma_fence_get(fence);
1271 r = drm_sched_job_add_dependency(&leader->base, fence);
1273 dma_fence_put(fence);
1278 if (p->gang_size > 1) {
1279 for (i = 0; i < p->gang_size; ++i)
1280 amdgpu_job_set_gang_leader(p->jobs[i], leader);
1283 /* No memory allocation is allowed while holding the notifier lock.
1284 * The lock is held until amdgpu_cs_submit is finished and fence is
1287 mutex_lock(&p->adev->notifier_lock);
1289 /* If userptr are invalidated after amdgpu_cs_parser_bos(), return
1290 * -EAGAIN, drmIoctl in libdrm will restart the amdgpu_cs_ioctl.
1293 amdgpu_bo_list_for_each_userptr_entry(e, p->bo_list) {
1294 struct amdgpu_bo *bo = ttm_to_amdgpu_bo(e->tv.bo);
1296 r |= !amdgpu_ttm_tt_get_user_pages_done(bo->tbo.ttm, e->range);
1304 p->fence = dma_fence_get(&leader->base.s_fence->finished);
1305 list_for_each_entry(e, &p->validated, tv.head) {
1307 /* Everybody except for the gang leader uses READ */
1308 for (i = 0; i < p->gang_size; ++i) {
1309 if (p->jobs[i] == leader)
1312 dma_resv_add_fence(e->tv.bo->base.resv,
1313 &p->jobs[i]->base.s_fence->finished,
1314 DMA_RESV_USAGE_READ);
1317 /* The gang leader is remembered as writer */
1318 e->tv.num_shared = 0;
1321 seq = amdgpu_ctx_add_fence(p->ctx, p->entities[p->gang_leader_idx],
1323 amdgpu_cs_post_dependencies(p);
1325 if ((leader->preamble_status & AMDGPU_PREAMBLE_IB_PRESENT) &&
1326 !p->ctx->preamble_presented) {
1327 leader->preamble_status |= AMDGPU_PREAMBLE_IB_PRESENT_FIRST;
1328 p->ctx->preamble_presented = true;
1331 cs->out.handle = seq;
1332 leader->uf_sequence = seq;
1334 amdgpu_vm_bo_trace_cs(&fpriv->vm, &p->ticket);
1335 for (i = 0; i < p->gang_size; ++i) {
1336 amdgpu_job_free_resources(p->jobs[i]);
1337 trace_amdgpu_cs_ioctl(p->jobs[i]);
1338 drm_sched_entity_push_job(&p->jobs[i]->base);
1342 amdgpu_vm_move_to_lru_tail(p->adev, &fpriv->vm);
1343 ttm_eu_fence_buffer_objects(&p->ticket, &p->validated, p->fence);
1345 mutex_unlock(&p->adev->notifier_lock);
1346 mutex_unlock(&p->bo_list->bo_list_mutex);
1350 mutex_unlock(&p->adev->notifier_lock);
1353 for (i = 0; i < p->gang_size; ++i)
1354 drm_sched_job_cleanup(&p->jobs[i]->base);
1358 /* Cleanup the parser structure */
1359 static void amdgpu_cs_parser_fini(struct amdgpu_cs_parser *parser)
1363 amdgpu_sync_free(&parser->sync);
1364 for (i = 0; i < parser->num_post_deps; i++) {
1365 drm_syncobj_put(parser->post_deps[i].syncobj);
1366 kfree(parser->post_deps[i].chain);
1368 kfree(parser->post_deps);
1370 dma_fence_put(parser->fence);
1373 amdgpu_ctx_put(parser->ctx);
1374 if (parser->bo_list)
1375 amdgpu_bo_list_put(parser->bo_list);
1377 for (i = 0; i < parser->nchunks; i++)
1378 kvfree(parser->chunks[i].kdata);
1379 kvfree(parser->chunks);
1380 for (i = 0; i < parser->gang_size; ++i) {
1381 if (parser->jobs[i])
1382 amdgpu_job_free(parser->jobs[i]);
1384 if (parser->uf_entry.tv.bo) {
1385 struct amdgpu_bo *uf = ttm_to_amdgpu_bo(parser->uf_entry.tv.bo);
1387 amdgpu_bo_unref(&uf);
1391 int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
1393 struct amdgpu_device *adev = drm_to_adev(dev);
1394 struct amdgpu_cs_parser parser;
1397 if (amdgpu_ras_intr_triggered())
1400 if (!adev->accel_working)
1403 r = amdgpu_cs_parser_init(&parser, adev, filp, data);
1405 if (printk_ratelimit())
1406 DRM_ERROR("Failed to initialize parser %d!\n", r);
1410 r = amdgpu_cs_pass1(&parser, data);
1414 r = amdgpu_cs_pass2(&parser);
1418 r = amdgpu_cs_parser_bos(&parser, data);
1421 DRM_ERROR("Not enough memory for command submission!\n");
1422 else if (r != -ERESTARTSYS && r != -EAGAIN)
1423 DRM_ERROR("Failed to process the buffer list %d!\n", r);
1427 r = amdgpu_cs_patch_jobs(&parser);
1431 r = amdgpu_cs_vm_handling(&parser);
1435 r = amdgpu_cs_sync_rings(&parser);
1439 trace_amdgpu_cs_ibs(&parser);
1441 r = amdgpu_cs_submit(&parser, data);
1445 amdgpu_cs_parser_fini(&parser);
1449 ttm_eu_backoff_reservation(&parser.ticket, &parser.validated);
1450 mutex_unlock(&parser.bo_list->bo_list_mutex);
1453 amdgpu_cs_parser_fini(&parser);
1458 * amdgpu_cs_wait_ioctl - wait for a command submission to finish
1461 * @data: data from userspace
1462 * @filp: file private
1464 * Wait for the command submission identified by handle to finish.
1466 int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data,
1467 struct drm_file *filp)
1469 union drm_amdgpu_wait_cs *wait = data;
1470 unsigned long timeout = amdgpu_gem_timeout(wait->in.timeout);
1471 struct drm_sched_entity *entity;
1472 struct amdgpu_ctx *ctx;
1473 struct dma_fence *fence;
1476 ctx = amdgpu_ctx_get(filp->driver_priv, wait->in.ctx_id);
1480 r = amdgpu_ctx_get_entity(ctx, wait->in.ip_type, wait->in.ip_instance,
1481 wait->in.ring, &entity);
1483 amdgpu_ctx_put(ctx);
1487 fence = amdgpu_ctx_get_fence(ctx, entity, wait->in.handle);
1491 r = dma_fence_wait_timeout(fence, true, timeout);
1492 if (r > 0 && fence->error)
1494 dma_fence_put(fence);
1498 amdgpu_ctx_put(ctx);
1502 memset(wait, 0, sizeof(*wait));
1503 wait->out.status = (r == 0);
1509 * amdgpu_cs_get_fence - helper to get fence from drm_amdgpu_fence
1511 * @adev: amdgpu device
1512 * @filp: file private
1513 * @user: drm_amdgpu_fence copied from user space
1515 static struct dma_fence *amdgpu_cs_get_fence(struct amdgpu_device *adev,
1516 struct drm_file *filp,
1517 struct drm_amdgpu_fence *user)
1519 struct drm_sched_entity *entity;
1520 struct amdgpu_ctx *ctx;
1521 struct dma_fence *fence;
1524 ctx = amdgpu_ctx_get(filp->driver_priv, user->ctx_id);
1526 return ERR_PTR(-EINVAL);
1528 r = amdgpu_ctx_get_entity(ctx, user->ip_type, user->ip_instance,
1529 user->ring, &entity);
1531 amdgpu_ctx_put(ctx);
1535 fence = amdgpu_ctx_get_fence(ctx, entity, user->seq_no);
1536 amdgpu_ctx_put(ctx);
1541 int amdgpu_cs_fence_to_handle_ioctl(struct drm_device *dev, void *data,
1542 struct drm_file *filp)
1544 struct amdgpu_device *adev = drm_to_adev(dev);
1545 union drm_amdgpu_fence_to_handle *info = data;
1546 struct dma_fence *fence;
1547 struct drm_syncobj *syncobj;
1548 struct sync_file *sync_file;
1551 fence = amdgpu_cs_get_fence(adev, filp, &info->in.fence);
1553 return PTR_ERR(fence);
1556 fence = dma_fence_get_stub();
1558 switch (info->in.what) {
1559 case AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ:
1560 r = drm_syncobj_create(&syncobj, 0, fence);
1561 dma_fence_put(fence);
1564 r = drm_syncobj_get_handle(filp, syncobj, &info->out.handle);
1565 drm_syncobj_put(syncobj);
1568 case AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ_FD:
1569 r = drm_syncobj_create(&syncobj, 0, fence);
1570 dma_fence_put(fence);
1573 r = drm_syncobj_get_fd(syncobj, (int *)&info->out.handle);
1574 drm_syncobj_put(syncobj);
1577 case AMDGPU_FENCE_TO_HANDLE_GET_SYNC_FILE_FD:
1578 fd = get_unused_fd_flags(O_CLOEXEC);
1580 dma_fence_put(fence);
1584 sync_file = sync_file_create(fence);
1585 dma_fence_put(fence);
1591 fd_install(fd, sync_file->file);
1592 info->out.handle = fd;
1596 dma_fence_put(fence);
1602 * amdgpu_cs_wait_all_fences - wait on all fences to signal
1604 * @adev: amdgpu device
1605 * @filp: file private
1606 * @wait: wait parameters
1607 * @fences: array of drm_amdgpu_fence
1609 static int amdgpu_cs_wait_all_fences(struct amdgpu_device *adev,
1610 struct drm_file *filp,
1611 union drm_amdgpu_wait_fences *wait,
1612 struct drm_amdgpu_fence *fences)
1614 uint32_t fence_count = wait->in.fence_count;
1618 for (i = 0; i < fence_count; i++) {
1619 struct dma_fence *fence;
1620 unsigned long timeout = amdgpu_gem_timeout(wait->in.timeout_ns);
1622 fence = amdgpu_cs_get_fence(adev, filp, &fences[i]);
1624 return PTR_ERR(fence);
1628 r = dma_fence_wait_timeout(fence, true, timeout);
1629 dma_fence_put(fence);
1637 return fence->error;
1640 memset(wait, 0, sizeof(*wait));
1641 wait->out.status = (r > 0);
1647 * amdgpu_cs_wait_any_fence - wait on any fence to signal
1649 * @adev: amdgpu device
1650 * @filp: file private
1651 * @wait: wait parameters
1652 * @fences: array of drm_amdgpu_fence
1654 static int amdgpu_cs_wait_any_fence(struct amdgpu_device *adev,
1655 struct drm_file *filp,
1656 union drm_amdgpu_wait_fences *wait,
1657 struct drm_amdgpu_fence *fences)
1659 unsigned long timeout = amdgpu_gem_timeout(wait->in.timeout_ns);
1660 uint32_t fence_count = wait->in.fence_count;
1661 uint32_t first = ~0;
1662 struct dma_fence **array;
1666 /* Prepare the fence array */
1667 array = kcalloc(fence_count, sizeof(struct dma_fence *), GFP_KERNEL);
1672 for (i = 0; i < fence_count; i++) {
1673 struct dma_fence *fence;
1675 fence = amdgpu_cs_get_fence(adev, filp, &fences[i]);
1676 if (IS_ERR(fence)) {
1678 goto err_free_fence_array;
1681 } else { /* NULL, the fence has been already signaled */
1688 r = dma_fence_wait_any_timeout(array, fence_count, true, timeout,
1691 goto err_free_fence_array;
1694 memset(wait, 0, sizeof(*wait));
1695 wait->out.status = (r > 0);
1696 wait->out.first_signaled = first;
1698 if (first < fence_count && array[first])
1699 r = array[first]->error;
1703 err_free_fence_array:
1704 for (i = 0; i < fence_count; i++)
1705 dma_fence_put(array[i]);
1712 * amdgpu_cs_wait_fences_ioctl - wait for multiple command submissions to finish
1715 * @data: data from userspace
1716 * @filp: file private
1718 int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data,
1719 struct drm_file *filp)
1721 struct amdgpu_device *adev = drm_to_adev(dev);
1722 union drm_amdgpu_wait_fences *wait = data;
1723 uint32_t fence_count = wait->in.fence_count;
1724 struct drm_amdgpu_fence *fences_user;
1725 struct drm_amdgpu_fence *fences;
1728 /* Get the fences from userspace */
1729 fences = kmalloc_array(fence_count, sizeof(struct drm_amdgpu_fence),
1734 fences_user = u64_to_user_ptr(wait->in.fences);
1735 if (copy_from_user(fences, fences_user,
1736 sizeof(struct drm_amdgpu_fence) * fence_count)) {
1738 goto err_free_fences;
1741 if (wait->in.wait_all)
1742 r = amdgpu_cs_wait_all_fences(adev, filp, wait, fences);
1744 r = amdgpu_cs_wait_any_fence(adev, filp, wait, fences);
1753 * amdgpu_cs_find_mapping - find bo_va for VM address
1755 * @parser: command submission parser context
1757 * @bo: resulting BO of the mapping found
1758 * @map: Placeholder to return found BO mapping
1760 * Search the buffer objects in the command submission context for a certain
1761 * virtual memory address. Returns allocation structure when found, NULL
1764 int amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser,
1765 uint64_t addr, struct amdgpu_bo **bo,
1766 struct amdgpu_bo_va_mapping **map)
1768 struct amdgpu_fpriv *fpriv = parser->filp->driver_priv;
1769 struct ttm_operation_ctx ctx = { false, false };
1770 struct amdgpu_vm *vm = &fpriv->vm;
1771 struct amdgpu_bo_va_mapping *mapping;
1774 addr /= AMDGPU_GPU_PAGE_SIZE;
1776 mapping = amdgpu_vm_bo_lookup_mapping(vm, addr);
1777 if (!mapping || !mapping->bo_va || !mapping->bo_va->base.bo)
1780 *bo = mapping->bo_va->base.bo;
1783 /* Double check that the BO is reserved by this CS */
1784 if (dma_resv_locking_ctx((*bo)->tbo.base.resv) != &parser->ticket)
1787 if (!((*bo)->flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS)) {
1788 (*bo)->flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
1789 amdgpu_bo_placement_from_domain(*bo, (*bo)->allowed_domains);
1790 r = ttm_bo_validate(&(*bo)->tbo, &(*bo)->placement, &ctx);
1795 return amdgpu_ttm_alloc_gart(&(*bo)->tbo);