2 * Copyright 2008 Jerome Glisse.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
25 * Jerome Glisse <glisse@freedesktop.org>
27 #include <linux/list_sort.h>
29 #include <drm/amdgpu_drm.h>
31 #include "amdgpu_trace.h"
33 #define AMDGPU_CS_MAX_PRIORITY 32u
34 #define AMDGPU_CS_NUM_BUCKETS (AMDGPU_CS_MAX_PRIORITY + 1)
36 /* This is based on the bucket sort with O(n) time complexity.
37 * An item with priority "i" is added to bucket[i]. The lists are then
38 * concatenated in descending order.
40 struct amdgpu_cs_buckets {
41 struct list_head bucket[AMDGPU_CS_NUM_BUCKETS];
44 static void amdgpu_cs_buckets_init(struct amdgpu_cs_buckets *b)
48 for (i = 0; i < AMDGPU_CS_NUM_BUCKETS; i++)
49 INIT_LIST_HEAD(&b->bucket[i]);
52 static void amdgpu_cs_buckets_add(struct amdgpu_cs_buckets *b,
53 struct list_head *item, unsigned priority)
55 /* Since buffers which appear sooner in the relocation list are
56 * likely to be used more often than buffers which appear later
57 * in the list, the sort mustn't change the ordering of buffers
58 * with the same priority, i.e. it must be stable.
60 list_add_tail(item, &b->bucket[min(priority, AMDGPU_CS_MAX_PRIORITY)]);
63 static void amdgpu_cs_buckets_get_list(struct amdgpu_cs_buckets *b,
64 struct list_head *out_list)
68 /* Connect the sorted buckets in the output list. */
69 for (i = 0; i < AMDGPU_CS_NUM_BUCKETS; i++) {
70 list_splice(&b->bucket[i], out_list);
74 int amdgpu_cs_get_ring(struct amdgpu_device *adev, u32 ip_type,
75 u32 ip_instance, u32 ring,
76 struct amdgpu_ring **out_ring)
78 /* Right now all IPs have only one instance - multiple rings. */
79 if (ip_instance != 0) {
80 DRM_ERROR("invalid ip instance: %d\n", ip_instance);
86 DRM_ERROR("unknown ip type: %d\n", ip_type);
88 case AMDGPU_HW_IP_GFX:
89 if (ring < adev->gfx.num_gfx_rings) {
90 *out_ring = &adev->gfx.gfx_ring[ring];
92 DRM_ERROR("only %d gfx rings are supported now\n",
93 adev->gfx.num_gfx_rings);
97 case AMDGPU_HW_IP_COMPUTE:
98 if (ring < adev->gfx.num_compute_rings) {
99 *out_ring = &adev->gfx.compute_ring[ring];
101 DRM_ERROR("only %d compute rings are supported now\n",
102 adev->gfx.num_compute_rings);
106 case AMDGPU_HW_IP_DMA:
108 *out_ring = &adev->sdma[ring].ring;
110 DRM_ERROR("only two SDMA rings are supported\n");
114 case AMDGPU_HW_IP_UVD:
115 *out_ring = &adev->uvd.ring;
117 case AMDGPU_HW_IP_VCE:
119 *out_ring = &adev->vce.ring[ring];
121 DRM_ERROR("only two VCE rings are supported\n");
129 int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, void *data)
131 union drm_amdgpu_cs *cs = data;
132 uint64_t *chunk_array_user;
133 uint64_t *chunk_array = NULL;
134 struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
138 if (!cs->in.num_chunks)
141 p->ctx_id = cs->in.ctx_id;
142 p->bo_list = amdgpu_bo_list_get(fpriv, cs->in.bo_list_handle);
145 INIT_LIST_HEAD(&p->validated);
146 chunk_array = kcalloc(cs->in.num_chunks, sizeof(uint64_t), GFP_KERNEL);
147 if (chunk_array == NULL) {
152 chunk_array_user = (uint64_t *)(unsigned long)(cs->in.chunks);
153 if (copy_from_user(chunk_array, chunk_array_user,
154 sizeof(uint64_t)*cs->in.num_chunks)) {
159 p->nchunks = cs->in.num_chunks;
160 p->chunks = kcalloc(p->nchunks, sizeof(struct amdgpu_cs_chunk),
162 if (p->chunks == NULL) {
167 for (i = 0; i < p->nchunks; i++) {
168 struct drm_amdgpu_cs_chunk __user **chunk_ptr = NULL;
169 struct drm_amdgpu_cs_chunk user_chunk;
170 uint32_t __user *cdata;
172 chunk_ptr = (void __user *)(unsigned long)chunk_array[i];
173 if (copy_from_user(&user_chunk, chunk_ptr,
174 sizeof(struct drm_amdgpu_cs_chunk))) {
178 p->chunks[i].chunk_id = user_chunk.chunk_id;
179 p->chunks[i].length_dw = user_chunk.length_dw;
180 if (p->chunks[i].chunk_id == AMDGPU_CHUNK_ID_IB)
183 size = p->chunks[i].length_dw;
184 cdata = (void __user *)(unsigned long)user_chunk.chunk_data;
185 p->chunks[i].user_ptr = cdata;
187 p->chunks[i].kdata = drm_malloc_ab(size, sizeof(uint32_t));
188 if (p->chunks[i].kdata == NULL) {
192 size *= sizeof(uint32_t);
193 if (copy_from_user(p->chunks[i].kdata, cdata, size)) {
198 if (p->chunks[i].chunk_id == AMDGPU_CHUNK_ID_FENCE) {
199 size = sizeof(struct drm_amdgpu_cs_chunk_fence);
200 if (p->chunks[i].length_dw * sizeof(uint32_t) >= size) {
202 struct drm_gem_object *gobj;
203 struct drm_amdgpu_cs_chunk_fence *fence_data;
205 fence_data = (void *)p->chunks[i].kdata;
206 handle = fence_data->handle;
207 gobj = drm_gem_object_lookup(p->adev->ddev,
214 p->uf.bo = gem_to_amdgpu_bo(gobj);
215 p->uf.offset = fence_data->offset;
223 p->ibs = kcalloc(p->num_ibs, sizeof(struct amdgpu_ib), GFP_KERNEL);
229 p->ib_bos = kcalloc(p->num_ibs, sizeof(struct amdgpu_bo_list_entry),
239 /* Returns how many bytes TTM can move per IB.
241 static u64 amdgpu_cs_get_threshold_for_moves(struct amdgpu_device *adev)
243 u64 real_vram_size = adev->mc.real_vram_size;
244 u64 vram_usage = atomic64_read(&adev->vram_usage);
246 /* This function is based on the current VRAM usage.
248 * - If all of VRAM is free, allow relocating the number of bytes that
249 * is equal to 1/4 of the size of VRAM for this IB.
251 * - If more than one half of VRAM is occupied, only allow relocating
252 * 1 MB of data for this IB.
254 * - From 0 to one half of used VRAM, the threshold decreases
269 * Note: It's a threshold, not a limit. The threshold must be crossed
270 * for buffer relocations to stop, so any buffer of an arbitrary size
271 * can be moved as long as the threshold isn't crossed before
272 * the relocation takes place. We don't want to disable buffer
273 * relocations completely.
275 * The idea is that buffers should be placed in VRAM at creation time
276 * and TTM should only do a minimum number of relocations during
277 * command submission. In practice, you need to submit at least
278 * a dozen IBs to move all buffers to VRAM if they are in GTT.
280 * Also, things can get pretty crazy under memory pressure and actual
281 * VRAM usage can change a lot, so playing safe even at 50% does
282 * consistently increase performance.
285 u64 half_vram = real_vram_size >> 1;
286 u64 half_free_vram = vram_usage >= half_vram ? 0 : half_vram - vram_usage;
287 u64 bytes_moved_threshold = half_free_vram >> 1;
288 return max(bytes_moved_threshold, 1024*1024ull);
291 int amdgpu_cs_list_validate(struct amdgpu_cs_parser *p)
293 struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
294 struct amdgpu_vm *vm = &fpriv->vm;
295 struct amdgpu_device *adev = p->adev;
296 struct amdgpu_bo_list_entry *lobj;
297 struct list_head duplicates;
298 struct amdgpu_bo *bo;
299 u64 bytes_moved = 0, initial_bytes_moved;
300 u64 bytes_moved_threshold = amdgpu_cs_get_threshold_for_moves(adev);
303 INIT_LIST_HEAD(&duplicates);
304 r = ttm_eu_reserve_buffers(&p->ticket, &p->validated, true, &duplicates);
305 if (unlikely(r != 0)) {
309 list_for_each_entry(lobj, &p->validated, tv.head) {
311 if (!bo->pin_count) {
312 u32 domain = lobj->prefered_domains;
314 amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type);
316 /* Check if this buffer will be moved and don't move it
317 * if we have moved too many buffers for this IB already.
319 * Note that this allows moving at least one buffer of
320 * any size, because it doesn't take the current "bo"
321 * into account. We don't want to disallow buffer moves
324 if (current_domain != AMDGPU_GEM_DOMAIN_CPU &&
325 (domain & current_domain) == 0 && /* will be moved */
326 bytes_moved > bytes_moved_threshold) {
328 domain = current_domain;
332 amdgpu_ttm_placement_from_domain(bo, domain);
333 initial_bytes_moved = atomic64_read(&adev->num_bytes_moved);
334 r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false);
335 bytes_moved += atomic64_read(&adev->num_bytes_moved) -
339 if (r != -ERESTARTSYS && domain != lobj->allowed_domains) {
340 domain = lobj->allowed_domains;
343 ttm_eu_backoff_reservation(&p->ticket, &p->validated);
347 lobj->bo_va = amdgpu_vm_bo_find(vm, bo);
352 static int amdgpu_cs_parser_relocs(struct amdgpu_cs_parser *p)
354 struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
355 struct amdgpu_cs_buckets buckets;
359 if (p->bo_list == NULL)
362 need_mmap_lock = p->bo_list->has_userptr;
363 amdgpu_cs_buckets_init(&buckets);
364 for (i = 0; i < p->bo_list->num_entries; i++)
365 amdgpu_cs_buckets_add(&buckets, &p->bo_list->array[i].tv.head,
366 p->bo_list->array[i].priority);
368 amdgpu_cs_buckets_get_list(&buckets, &p->validated);
369 p->vm_bos = amdgpu_vm_get_bos(p->adev, &fpriv->vm,
372 for (i = 0; i < p->num_ibs; i++) {
373 if (!p->ib_bos[i].robj)
376 list_add(&p->ib_bos[i].tv.head, &p->validated);
380 down_read(¤t->mm->mmap_sem);
382 r = amdgpu_cs_list_validate(p);
385 up_read(¤t->mm->mmap_sem);
390 static int amdgpu_cs_sync_rings(struct amdgpu_cs_parser *p)
392 struct amdgpu_bo_list_entry *e;
395 list_for_each_entry(e, &p->validated, tv.head) {
396 struct reservation_object *resv = e->robj->tbo.resv;
397 r = amdgpu_sync_resv(p->adev, &p->ibs[0].sync, resv, p->filp);
405 static int cmp_size_smaller_first(void *priv, struct list_head *a,
408 struct amdgpu_bo_list_entry *la = list_entry(a, struct amdgpu_bo_list_entry, tv.head);
409 struct amdgpu_bo_list_entry *lb = list_entry(b, struct amdgpu_bo_list_entry, tv.head);
411 /* Sort A before B if A is smaller. */
412 return (int)la->robj->tbo.num_pages - (int)lb->robj->tbo.num_pages;
416 * cs_parser_fini() - clean parser states
417 * @parser: parser structure holding parsing context.
418 * @error: error number
420 * If error is set than unvalidate buffer, otherwise just free memory
421 * used by parsing context.
423 static void amdgpu_cs_parser_fini(struct amdgpu_cs_parser *parser, int error, bool backoff)
428 /* Sort the buffer list from the smallest to largest buffer,
429 * which affects the order of buffers in the LRU list.
430 * This assures that the smallest buffers are added first
431 * to the LRU list, so they are likely to be later evicted
432 * first, instead of large buffers whose eviction is more
435 * This slightly lowers the number of bytes moved by TTM
436 * per frame under memory pressure.
438 list_sort(NULL, &parser->validated, cmp_size_smaller_first);
440 ttm_eu_fence_buffer_objects(&parser->ticket,
442 &parser->ibs[parser->num_ibs-1].fence->base);
443 } else if (backoff) {
444 ttm_eu_backoff_reservation(&parser->ticket,
449 amdgpu_bo_list_put(parser->bo_list);
450 drm_free_large(parser->vm_bos);
451 for (i = 0; i < parser->nchunks; i++)
452 drm_free_large(parser->chunks[i].kdata);
453 kfree(parser->chunks);
454 for (i = 0; i < parser->num_ibs; i++) {
455 struct amdgpu_bo *bo = parser->ib_bos[i].robj;
456 amdgpu_ib_free(parser->adev, &parser->ibs[i]);
459 drm_gem_object_unreference_unlocked(&bo->gem_base);
462 kfree(parser->ib_bos);
464 drm_gem_object_unreference_unlocked(&parser->uf.bo->gem_base);
467 static int amdgpu_bo_vm_update_pte(struct amdgpu_cs_parser *p,
468 struct amdgpu_vm *vm)
470 struct amdgpu_device *adev = p->adev;
471 struct amdgpu_bo_va *bo_va;
472 struct amdgpu_bo *bo;
475 r = amdgpu_vm_update_page_directory(adev, vm);
479 r = amdgpu_vm_clear_freed(adev, vm);
484 for (i = 0; i < p->bo_list->num_entries; i++) {
485 /* ignore duplicates */
486 bo = p->bo_list->array[i].robj;
490 bo_va = p->bo_list->array[i].bo_va;
494 r = amdgpu_vm_bo_update(adev, bo_va, &bo->tbo.mem);
498 amdgpu_sync_fence(&p->ibs[0].sync, bo_va->last_pt_update);
502 for (i = 0; i < p->num_ibs; i++) {
503 bo = p->ib_bos[i].robj;
507 bo_va = p->ib_bos[i].bo_va;
511 r = amdgpu_vm_bo_update(adev, bo_va, &bo->tbo.mem);
515 amdgpu_sync_fence(&p->ibs[0].sync, bo_va->last_pt_update);
517 return amdgpu_vm_clear_invalids(adev, vm);
520 static int amdgpu_cs_ib_vm_chunk(struct amdgpu_device *adev,
521 struct amdgpu_cs_parser *parser)
523 struct amdgpu_fpriv *fpriv = parser->filp->driver_priv;
524 struct amdgpu_vm *vm = &fpriv->vm;
525 struct amdgpu_ring *ring;
528 if (parser->num_ibs == 0)
531 /* Only for UVD/VCE VM emulation */
532 for (i = 0; i < parser->num_ibs; i++) {
533 ring = parser->ibs[i].ring;
534 if (ring->funcs->parse_cs) {
535 r = amdgpu_ring_parse_cs(ring, parser, i);
541 mutex_lock(&vm->mutex);
542 r = amdgpu_bo_vm_update_pte(parser, vm);
546 amdgpu_cs_sync_rings(parser);
548 r = amdgpu_ib_schedule(adev, parser->num_ibs, parser->ibs,
552 mutex_unlock(&vm->mutex);
556 static int amdgpu_cs_handle_lockup(struct amdgpu_device *adev, int r)
559 r = amdgpu_gpu_reset(adev);
566 static int amdgpu_cs_ib_fill(struct amdgpu_device *adev,
567 struct amdgpu_cs_parser *parser)
569 struct amdgpu_fpriv *fpriv = parser->filp->driver_priv;
570 struct amdgpu_vm *vm = &fpriv->vm;
574 for (i = 0, j = 0; i < parser->nchunks && j < parser->num_ibs; i++) {
575 struct amdgpu_cs_chunk *chunk;
576 struct amdgpu_ib *ib;
577 struct drm_amdgpu_cs_chunk_ib *chunk_ib;
578 struct amdgpu_bo_list_entry *ib_bo;
579 struct amdgpu_ring *ring;
580 struct drm_gem_object *gobj;
581 struct amdgpu_bo *aobj;
584 chunk = &parser->chunks[i];
585 ib = &parser->ibs[j];
586 chunk_ib = (struct drm_amdgpu_cs_chunk_ib *)chunk->kdata;
588 if (chunk->chunk_id != AMDGPU_CHUNK_ID_IB)
591 gobj = drm_gem_object_lookup(adev->ddev, parser->filp, chunk_ib->handle);
594 aobj = gem_to_amdgpu_bo(gobj);
596 r = amdgpu_cs_get_ring(adev, chunk_ib->ip_type,
597 chunk_ib->ip_instance, chunk_ib->ring,
600 drm_gem_object_unreference_unlocked(gobj);
604 if (ring->funcs->parse_cs) {
605 r = amdgpu_bo_reserve(aobj, false);
607 drm_gem_object_unreference_unlocked(gobj);
611 r = amdgpu_bo_kmap(aobj, &kptr);
613 amdgpu_bo_unreserve(aobj);
614 drm_gem_object_unreference_unlocked(gobj);
618 r = amdgpu_ib_get(ring, NULL, chunk_ib->ib_bytes, ib);
620 DRM_ERROR("Failed to get ib !\n");
621 amdgpu_bo_unreserve(aobj);
622 drm_gem_object_unreference_unlocked(gobj);
626 memcpy(ib->ptr, kptr, chunk_ib->ib_bytes);
627 amdgpu_bo_kunmap(aobj);
628 amdgpu_bo_unreserve(aobj);
630 r = amdgpu_ib_get(ring, vm, 0, ib);
632 DRM_ERROR("Failed to get ib !\n");
633 drm_gem_object_unreference_unlocked(gobj);
637 ib->gpu_addr = chunk_ib->va_start;
639 ib->length_dw = chunk_ib->ib_bytes / 4;
641 if (chunk_ib->flags & AMDGPU_IB_FLAG_CE)
642 ib->is_const_ib = true;
643 if (chunk_ib->flags & AMDGPU_IB_FLAG_GDS)
644 ib->gds_needed = true;
645 if (ib->ring->current_filp != parser->filp) {
646 ib->ring->need_ctx_switch = true;
647 ib->ring->current_filp = parser->filp;
650 ib_bo = &parser->ib_bos[j];
652 ib_bo->prefered_domains = aobj->initial_domain;
653 ib_bo->allowed_domains = aobj->initial_domain;
655 ib_bo->tv.bo = &aobj->tbo;
656 ib_bo->tv.shared = true;
660 if (!parser->num_ibs)
663 /* add GDS resources to first IB */
664 if (parser->bo_list) {
665 struct amdgpu_bo *gds = parser->bo_list->gds_obj;
666 struct amdgpu_bo *gws = parser->bo_list->gws_obj;
667 struct amdgpu_bo *oa = parser->bo_list->oa_obj;
668 struct amdgpu_ib *ib = &parser->ibs[0];
671 ib->gds_base = amdgpu_bo_gpu_offset(gds);
672 ib->gds_size = amdgpu_bo_size(gds);
675 ib->gws_base = amdgpu_bo_gpu_offset(gws);
676 ib->gws_size = amdgpu_bo_size(gws);
679 ib->oa_base = amdgpu_bo_gpu_offset(oa);
680 ib->oa_size = amdgpu_bo_size(oa);
684 /* wrap the last IB with user fence */
686 struct amdgpu_ib *ib = &parser->ibs[parser->num_ibs - 1];
688 /* UVD & VCE fw doesn't support user fences */
689 if (ib->ring->type == AMDGPU_RING_TYPE_UVD ||
690 ib->ring->type == AMDGPU_RING_TYPE_VCE)
693 ib->user = &parser->uf;
699 int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
701 struct amdgpu_device *adev = dev->dev_private;
702 union drm_amdgpu_cs *cs = data;
703 struct amdgpu_cs_parser parser;
706 down_read(&adev->exclusive_lock);
707 if (!adev->accel_working) {
708 up_read(&adev->exclusive_lock);
711 /* initialize parser */
712 memset(&parser, 0, sizeof(struct amdgpu_cs_parser));
715 r = amdgpu_cs_parser_init(&parser, data);
717 DRM_ERROR("Failed to initialize parser !\n");
718 amdgpu_cs_parser_fini(&parser, r, false);
719 up_read(&adev->exclusive_lock);
720 r = amdgpu_cs_handle_lockup(adev, r);
724 r = amdgpu_cs_ib_fill(adev, &parser);
726 r = amdgpu_cs_parser_relocs(&parser);
727 if (r && r != -ERESTARTSYS)
728 DRM_ERROR("Failed to parse relocation %d!\n", r);
732 amdgpu_cs_parser_fini(&parser, r, false);
733 up_read(&adev->exclusive_lock);
734 r = amdgpu_cs_handle_lockup(adev, r);
738 for (i = 0; i < parser.num_ibs; i++)
739 trace_amdgpu_cs(&parser, i);
741 r = amdgpu_cs_ib_vm_chunk(adev, &parser);
746 cs->out.handle = parser.ibs[parser.num_ibs - 1].fence->seq;
748 amdgpu_cs_parser_fini(&parser, r, true);
749 up_read(&adev->exclusive_lock);
750 r = amdgpu_cs_handle_lockup(adev, r);
755 * amdgpu_cs_wait_ioctl - wait for a command submission to finish
758 * @data: data from userspace
759 * @filp: file private
761 * Wait for the command submission identified by handle to finish.
763 int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data,
764 struct drm_file *filp)
766 union drm_amdgpu_wait_cs *wait = data;
767 struct amdgpu_device *adev = dev->dev_private;
768 uint64_t seq[AMDGPU_MAX_RINGS] = {0};
769 struct amdgpu_ring *ring = NULL;
770 unsigned long timeout = amdgpu_gem_timeout(wait->in.timeout);
773 r = amdgpu_cs_get_ring(adev, wait->in.ip_type, wait->in.ip_instance,
774 wait->in.ring, &ring);
778 seq[ring->idx] = wait->in.handle;
780 r = amdgpu_fence_wait_seq_timeout(adev, seq, true, timeout);
784 memset(wait, 0, sizeof(*wait));
785 wait->out.status = (r == 0);
791 * amdgpu_cs_find_bo_va - find bo_va for VM address
793 * @parser: command submission parser context
795 * @bo: resulting BO of the mapping found
797 * Search the buffer objects in the command submission context for a certain
798 * virtual memory address. Returns allocation structure when found, NULL
801 struct amdgpu_bo_va_mapping *
802 amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser,
803 uint64_t addr, struct amdgpu_bo **bo)
805 struct amdgpu_bo_list_entry *reloc;
806 struct amdgpu_bo_va_mapping *mapping;
808 addr /= AMDGPU_GPU_PAGE_SIZE;
810 list_for_each_entry(reloc, &parser->validated, tv.head) {
814 list_for_each_entry(mapping, &reloc->bo_va->mappings, list) {
815 if (mapping->it.start > addr ||
816 addr > mapping->it.last)
819 *bo = reloc->bo_va->bo;