drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c

   1 /*
   2  * Copyright 2007-8 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: Dave Airlie
  24  *          Alex Deucher
  25  */
  26
  27 #include <drm/display/drm_dp_helper.h>
  28 #include <drm/drm_crtc_helper.h>
  29 #include <drm/drm_edid.h>
  30 #include <drm/drm_modeset_helper_vtables.h>
  31 #include <drm/drm_probe_helper.h>
  32 #include <drm/amdgpu_drm.h>
  33 #include "amdgpu.h"
  34 #include "atom.h"
  35 #include "atombios_encoders.h"
  36 #include "atombios_dp.h"
  37 #include "amdgpu_connectors.h"
  38 #include "amdgpu_i2c.h"
  39 #include "amdgpu_display.h"
  40
  41 #include <linux/pm_runtime.h>
  42
  43 void amdgpu_connector_hotplug(struct drm_connector *connector)
  44 {
  45         struct drm_device *dev = connector->dev;
  46         struct amdgpu_device *adev = drm_to_adev(dev);
  47         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
  48
  49         /* bail if the connector does not have hpd pin, e.g.,
  50          * VGA, TV, etc.
  51          */
  52         if (amdgpu_connector->hpd.hpd == AMDGPU_HPD_NONE)
  53                 return;
  54
  55         amdgpu_display_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd);
  56
  57         /* if the connector is already off, don't turn it back on */
  58         if (connector->dpms != DRM_MODE_DPMS_ON)
  59                 return;
  60
  61         /* just deal with DP (not eDP) here. */
  62         if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) {
  63                 struct amdgpu_connector_atom_dig *dig_connector =
  64                         amdgpu_connector->con_priv;
  65
  66                 /* if existing sink type was not DP no need to retrain */
  67                 if (dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_DISPLAYPORT)
  68                         return;
  69
  70                 /* first get sink type as it may be reset after (un)plug */
  71                 dig_connector->dp_sink_type = amdgpu_atombios_dp_get_sinktype(amdgpu_connector);
  72                 /* don't do anything if sink is not display port, i.e.,
  73                  * passive dp->(dvi|hdmi) adaptor
  74                  */
  75                 if (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT &&
  76                     amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd) &&
  77                     amdgpu_atombios_dp_needs_link_train(amdgpu_connector)) {
  78                         /* Don't start link training before we have the DPCD */
  79                         if (amdgpu_atombios_dp_get_dpcd(amdgpu_connector))
  80                                 return;
  81
  82                         /* Turn the connector off and back on immediately, which
  83                          * will trigger link training
  84                          */
  85                         drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF);
  86                         drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON);
  87                 }
  88         }
  89 }
  90
  91 static void amdgpu_connector_property_change_mode(struct drm_encoder *encoder)
  92 {
  93         struct drm_crtc *crtc = encoder->crtc;
  94
  95         if (crtc && crtc->enabled) {
  96                 drm_crtc_helper_set_mode(crtc, &crtc->mode,
  97                                          crtc->x, crtc->y, crtc->primary->fb);
  98         }
  99 }
 100
 101 int amdgpu_connector_get_monitor_bpc(struct drm_connector *connector)
 102 {
 103         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 104         struct amdgpu_connector_atom_dig *dig_connector;
 105         int bpc = 8;
 106         unsigned int mode_clock, max_tmds_clock;
 107
 108         switch (connector->connector_type) {
 109         case DRM_MODE_CONNECTOR_DVII:
 110         case DRM_MODE_CONNECTOR_HDMIB:
 111                 if (amdgpu_connector->use_digital) {
 112                         if (connector->display_info.is_hdmi) {
 113                                 if (connector->display_info.bpc)
 114                                         bpc = connector->display_info.bpc;
 115                         }
 116                 }
 117                 break;
 118         case DRM_MODE_CONNECTOR_DVID:
 119         case DRM_MODE_CONNECTOR_HDMIA:
 120                 if (connector->display_info.is_hdmi) {
 121                         if (connector->display_info.bpc)
 122                                 bpc = connector->display_info.bpc;
 123                 }
 124                 break;
 125         case DRM_MODE_CONNECTOR_DisplayPort:
 126                 dig_connector = amdgpu_connector->con_priv;
 127                 if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
 128                     (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) ||
 129                     connector->display_info.is_hdmi) {
 130                         if (connector->display_info.bpc)
 131                                 bpc = connector->display_info.bpc;
 132                 }
 133                 break;
 134         case DRM_MODE_CONNECTOR_eDP:
 135         case DRM_MODE_CONNECTOR_LVDS:
 136                 if (connector->display_info.bpc)
 137                         bpc = connector->display_info.bpc;
 138                 else {
 139                         const struct drm_connector_helper_funcs *connector_funcs =
 140                                 connector->helper_private;
 141                         struct drm_encoder *encoder = connector_funcs->best_encoder(connector);
 142                         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
 143                         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
 144
 145                         if (dig->lcd_misc & ATOM_PANEL_MISC_V13_6BIT_PER_COLOR)
 146                                 bpc = 6;
 147                         else if (dig->lcd_misc & ATOM_PANEL_MISC_V13_8BIT_PER_COLOR)
 148                                 bpc = 8;
 149                 }
 150                 break;
 151         }
 152
 153         if (connector->display_info.is_hdmi) {
 154                 /*
 155                  * Pre DCE-8 hw can't handle > 12 bpc, and more than 12 bpc doesn't make
 156                  * much sense without support for > 12 bpc framebuffers. RGB 4:4:4 at
 157                  * 12 bpc is always supported on hdmi deep color sinks, as this is
 158                  * required by the HDMI-1.3 spec. Clamp to a safe 12 bpc maximum.
 159                  */
 160                 if (bpc > 12) {
 161                         DRM_DEBUG("%s: HDMI deep color %d bpc unsupported. Using 12 bpc.\n",
 162                                   connector->name, bpc);
 163                         bpc = 12;
 164                 }
 165
 166                 /* Any defined maximum tmds clock limit we must not exceed? */
 167                 if (connector->display_info.max_tmds_clock > 0) {
 168                         /* mode_clock is clock in kHz for mode to be modeset on this connector */
 169                         mode_clock = amdgpu_connector->pixelclock_for_modeset;
 170
 171                         /* Maximum allowable input clock in kHz */
 172                         max_tmds_clock = connector->display_info.max_tmds_clock;
 173
 174                         DRM_DEBUG("%s: hdmi mode dotclock %d kHz, max tmds input clock %d kHz.\n",
 175                                   connector->name, mode_clock, max_tmds_clock);
 176
 177                         /* Check if bpc is within clock limit. Try to degrade gracefully otherwise */
 178                         if ((bpc == 12) && (mode_clock * 3/2 > max_tmds_clock)) {
 179                                 if ((connector->display_info.edid_hdmi_rgb444_dc_modes & DRM_EDID_HDMI_DC_30) &&
 180                                     (mode_clock * 5/4 <= max_tmds_clock))
 181                                         bpc = 10;
 182                                 else
 183                                         bpc = 8;
 184
 185                                 DRM_DEBUG("%s: HDMI deep color 12 bpc exceeds max tmds clock. Using %d bpc.\n",
 186                                           connector->name, bpc);
 187                         }
 188
 189                         if ((bpc == 10) && (mode_clock * 5/4 > max_tmds_clock)) {
 190                                 bpc = 8;
 191                                 DRM_DEBUG("%s: HDMI deep color 10 bpc exceeds max tmds clock. Using %d bpc.\n",
 192                                           connector->name, bpc);
 193                         }
 194                 } else if (bpc > 8) {
 195                         /* max_tmds_clock missing, but hdmi spec mandates it for deep color. */
 196                         DRM_DEBUG("%s: Required max tmds clock for HDMI deep color missing. Using 8 bpc.\n",
 197                                   connector->name);
 198                         bpc = 8;
 199                 }
 200         }
 201
 202         if ((amdgpu_deep_color == 0) && (bpc > 8)) {
 203                 DRM_DEBUG("%s: Deep color disabled. Set amdgpu module param deep_color=1 to enable.\n",
 204                           connector->name);
 205                 bpc = 8;
 206         }
 207
 208         DRM_DEBUG("%s: Display bpc=%d, returned bpc=%d\n",
 209                   connector->name, connector->display_info.bpc, bpc);
 210
 211         return bpc;
 212 }
 213
 214 static void
 215 amdgpu_connector_update_scratch_regs(struct drm_connector *connector,
 216                                       enum drm_connector_status status)
 217 {
 218         struct drm_encoder *best_encoder;
 219         struct drm_encoder *encoder;
 220         const struct drm_connector_helper_funcs *connector_funcs = connector->helper_private;
 221         bool connected;
 222
 223         best_encoder = connector_funcs->best_encoder(connector);
 224
 225         drm_connector_for_each_possible_encoder(connector, encoder) {
 226                 if ((encoder == best_encoder) && (status == connector_status_connected))
 227                         connected = true;
 228                 else
 229                         connected = false;
 230
 231                 amdgpu_atombios_encoder_set_bios_scratch_regs(connector, encoder, connected);
 232         }
 233 }
 234
 235 static struct drm_encoder *
 236 amdgpu_connector_find_encoder(struct drm_connector *connector,
 237                                int encoder_type)
 238 {
 239         struct drm_encoder *encoder;
 240
 241         drm_connector_for_each_possible_encoder(connector, encoder) {
 242                 if (encoder->encoder_type == encoder_type)
 243                         return encoder;
 244         }
 245
 246         return NULL;
 247 }
 248
 249 static struct edid *
 250 amdgpu_connector_get_hardcoded_edid(struct amdgpu_device *adev)
 251 {
 252         return drm_edid_duplicate(drm_edid_raw(adev->mode_info.bios_hardcoded_edid));
 253 }
 254
 255 static void amdgpu_connector_get_edid(struct drm_connector *connector)
 256 {
 257         struct drm_device *dev = connector->dev;
 258         struct amdgpu_device *adev = drm_to_adev(dev);
 259         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 260
 261         if (amdgpu_connector->edid)
 262                 return;
 263
 264         /* on hw with routers, select right port */
 265         if (amdgpu_connector->router.ddc_valid)
 266                 amdgpu_i2c_router_select_ddc_port(amdgpu_connector);
 267
 268         if ((amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) !=
 269              ENCODER_OBJECT_ID_NONE) &&
 270             amdgpu_connector->ddc_bus->has_aux) {
 271                 amdgpu_connector->edid = drm_get_edid(connector,
 272                                                       &amdgpu_connector->ddc_bus->aux.ddc);
 273         } else if ((connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) ||
 274                    (connector->connector_type == DRM_MODE_CONNECTOR_eDP)) {
 275                 struct amdgpu_connector_atom_dig *dig = amdgpu_connector->con_priv;
 276
 277                 if ((dig->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT ||
 278                      dig->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) &&
 279                     amdgpu_connector->ddc_bus->has_aux)
 280                         amdgpu_connector->edid = drm_get_edid(connector,
 281                                                               &amdgpu_connector->ddc_bus->aux.ddc);
 282                 else if (amdgpu_connector->ddc_bus)
 283                         amdgpu_connector->edid = drm_get_edid(connector,
 284                                                               &amdgpu_connector->ddc_bus->adapter);
 285         } else if (amdgpu_connector->ddc_bus) {
 286                 amdgpu_connector->edid = drm_get_edid(connector,
 287                                                       &amdgpu_connector->ddc_bus->adapter);
 288         }
 289
 290         if (!amdgpu_connector->edid) {
 291                 /* some laptops provide a hardcoded edid in rom for LCDs */
 292                 if (((connector->connector_type == DRM_MODE_CONNECTOR_LVDS) ||
 293                      (connector->connector_type == DRM_MODE_CONNECTOR_eDP))) {
 294                         amdgpu_connector->edid = amdgpu_connector_get_hardcoded_edid(adev);
 295                         drm_connector_update_edid_property(connector, amdgpu_connector->edid);
 296                 }
 297         }
 298 }
 299
 300 static void amdgpu_connector_free_edid(struct drm_connector *connector)
 301 {
 302         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 303
 304         kfree(amdgpu_connector->edid);
 305         amdgpu_connector->edid = NULL;
 306 }
 307
 308 static int amdgpu_connector_ddc_get_modes(struct drm_connector *connector)
 309 {
 310         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 311         int ret;
 312
 313         if (amdgpu_connector->edid) {
 314                 drm_connector_update_edid_property(connector, amdgpu_connector->edid);
 315                 ret = drm_add_edid_modes(connector, amdgpu_connector->edid);
 316                 return ret;
 317         }
 318         drm_connector_update_edid_property(connector, NULL);
 319         return 0;
 320 }
 321
 322 static struct drm_encoder *
 323 amdgpu_connector_best_single_encoder(struct drm_connector *connector)
 324 {
 325         struct drm_encoder *encoder;
 326
 327         /* pick the first one */
 328         drm_connector_for_each_possible_encoder(connector, encoder)
 329                 return encoder;
 330
 331         return NULL;
 332 }
 333
 334 static void amdgpu_get_native_mode(struct drm_connector *connector)
 335 {
 336         struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector);
 337         struct amdgpu_encoder *amdgpu_encoder;
 338
 339         if (encoder == NULL)
 340                 return;
 341
 342         amdgpu_encoder = to_amdgpu_encoder(encoder);
 343
 344         if (!list_empty(&connector->probed_modes)) {
 345                 struct drm_display_mode *preferred_mode =
 346                         list_first_entry(&connector->probed_modes,
 347                                          struct drm_display_mode, head);
 348
 349                 amdgpu_encoder->native_mode = *preferred_mode;
 350         } else {
 351                 amdgpu_encoder->native_mode.clock = 0;
 352         }
 353 }
 354
 355 static struct drm_display_mode *
 356 amdgpu_connector_lcd_native_mode(struct drm_encoder *encoder)
 357 {
 358         struct drm_device *dev = encoder->dev;
 359         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
 360         struct drm_display_mode *mode = NULL;
 361         struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
 362
 363         if (native_mode->hdisplay != 0 &&
 364             native_mode->vdisplay != 0 &&
 365             native_mode->clock != 0) {
 366                 mode = drm_mode_duplicate(dev, native_mode);
 367                 if (!mode)
 368                         return NULL;
 369
 370                 mode->type = DRM_MODE_TYPE_PREFERRED | DRM_MODE_TYPE_DRIVER;
 371                 drm_mode_set_name(mode);
 372
 373                 DRM_DEBUG_KMS("Adding native panel mode %s\n", mode->name);
 374         } else if (native_mode->hdisplay != 0 &&
 375                    native_mode->vdisplay != 0) {
 376                 /* mac laptops without an edid */
 377                 /* Note that this is not necessarily the exact panel mode,
 378                  * but an approximation based on the cvt formula.  For these
 379                  * systems we should ideally read the mode info out of the
 380                  * registers or add a mode table, but this works and is much
 381                  * simpler.
 382                  */
 383                 mode = drm_cvt_mode(dev, native_mode->hdisplay, native_mode->vdisplay, 60, true, false, false);
 384                 if (!mode)
 385                         return NULL;
 386
 387                 mode->type = DRM_MODE_TYPE_PREFERRED | DRM_MODE_TYPE_DRIVER;
 388                 DRM_DEBUG_KMS("Adding cvt approximation of native panel mode %s\n", mode->name);
 389         }
 390         return mode;
 391 }
 392
 393 static void amdgpu_connector_add_common_modes(struct drm_encoder *encoder,
 394                                                struct drm_connector *connector)
 395 {
 396         struct drm_device *dev = encoder->dev;
 397         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
 398         struct drm_display_mode *mode = NULL;
 399         struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
 400         int i;
 401         static const struct mode_size {
 402                 int w;
 403                 int h;
 404         } common_modes[17] = {
 405                 { 640,  480},
 406                 { 720,  480},
 407                 { 800,  600},
 408                 { 848,  480},
 409                 {1024,  768},
 410                 {1152,  768},
 411                 {1280,  720},
 412                 {1280,  800},
 413                 {1280,  854},
 414                 {1280,  960},
 415                 {1280, 1024},
 416                 {1440,  900},
 417                 {1400, 1050},
 418                 {1680, 1050},
 419                 {1600, 1200},
 420                 {1920, 1080},
 421                 {1920, 1200}
 422         };
 423
 424         for (i = 0; i < 17; i++) {
 425                 if (amdgpu_encoder->devices & (ATOM_DEVICE_TV_SUPPORT)) {
 426                         if (common_modes[i].w > 1024 ||
 427                             common_modes[i].h > 768)
 428                                 continue;
 429                 }
 430                 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
 431                         if (common_modes[i].w > native_mode->hdisplay ||
 432                             common_modes[i].h > native_mode->vdisplay ||
 433                             (common_modes[i].w == native_mode->hdisplay &&
 434                              common_modes[i].h == native_mode->vdisplay))
 435                                 continue;
 436                 }
 437                 if (common_modes[i].w < 320 || common_modes[i].h < 200)
 438                         continue;
 439
 440                 mode = drm_cvt_mode(dev, common_modes[i].w, common_modes[i].h, 60, false, false, false);
 441                 if (!mode)
 442                         return;
 443
 444                 drm_mode_probed_add(connector, mode);
 445         }
 446 }
 447
 448 static int amdgpu_connector_set_property(struct drm_connector *connector,
 449                                           struct drm_property *property,
 450                                           uint64_t val)
 451 {
 452         struct drm_device *dev = connector->dev;
 453         struct amdgpu_device *adev = drm_to_adev(dev);
 454         struct drm_encoder *encoder;
 455         struct amdgpu_encoder *amdgpu_encoder;
 456
 457         if (property == adev->mode_info.coherent_mode_property) {
 458                 struct amdgpu_encoder_atom_dig *dig;
 459                 bool new_coherent_mode;
 460
 461                 /* need to find digital encoder on connector */
 462                 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS);
 463                 if (!encoder)
 464                         return 0;
 465
 466                 amdgpu_encoder = to_amdgpu_encoder(encoder);
 467
 468                 if (!amdgpu_encoder->enc_priv)
 469                         return 0;
 470
 471                 dig = amdgpu_encoder->enc_priv;
 472                 new_coherent_mode = val ? true : false;
 473                 if (dig->coherent_mode != new_coherent_mode) {
 474                         dig->coherent_mode = new_coherent_mode;
 475                         amdgpu_connector_property_change_mode(&amdgpu_encoder->base);
 476                 }
 477         }
 478
 479         if (property == adev->mode_info.audio_property) {
 480                 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 481                 /* need to find digital encoder on connector */
 482                 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS);
 483                 if (!encoder)
 484                         return 0;
 485
 486                 amdgpu_encoder = to_amdgpu_encoder(encoder);
 487
 488                 if (amdgpu_connector->audio != val) {
 489                         amdgpu_connector->audio = val;
 490                         amdgpu_connector_property_change_mode(&amdgpu_encoder->base);
 491                 }
 492         }
 493
 494         if (property == adev->mode_info.dither_property) {
 495                 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 496                 /* need to find digital encoder on connector */
 497                 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS);
 498                 if (!encoder)
 499                         return 0;
 500
 501                 amdgpu_encoder = to_amdgpu_encoder(encoder);
 502
 503                 if (amdgpu_connector->dither != val) {
 504                         amdgpu_connector->dither = val;
 505                         amdgpu_connector_property_change_mode(&amdgpu_encoder->base);
 506                 }
 507         }
 508
 509         if (property == adev->mode_info.underscan_property) {
 510                 /* need to find digital encoder on connector */
 511                 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS);
 512                 if (!encoder)
 513                         return 0;
 514
 515                 amdgpu_encoder = to_amdgpu_encoder(encoder);
 516
 517                 if (amdgpu_encoder->underscan_type != val) {
 518                         amdgpu_encoder->underscan_type = val;
 519                         amdgpu_connector_property_change_mode(&amdgpu_encoder->base);
 520                 }
 521         }
 522
 523         if (property == adev->mode_info.underscan_hborder_property) {
 524                 /* need to find digital encoder on connector */
 525                 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS);
 526                 if (!encoder)
 527                         return 0;
 528
 529                 amdgpu_encoder = to_amdgpu_encoder(encoder);
 530
 531                 if (amdgpu_encoder->underscan_hborder != val) {
 532                         amdgpu_encoder->underscan_hborder = val;
 533                         amdgpu_connector_property_change_mode(&amdgpu_encoder->base);
 534                 }
 535         }
 536
 537         if (property == adev->mode_info.underscan_vborder_property) {
 538                 /* need to find digital encoder on connector */
 539                 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS);
 540                 if (!encoder)
 541                         return 0;
 542
 543                 amdgpu_encoder = to_amdgpu_encoder(encoder);
 544
 545                 if (amdgpu_encoder->underscan_vborder != val) {
 546                         amdgpu_encoder->underscan_vborder = val;
 547                         amdgpu_connector_property_change_mode(&amdgpu_encoder->base);
 548                 }
 549         }
 550
 551         if (property == adev->mode_info.load_detect_property) {
 552                 struct amdgpu_connector *amdgpu_connector =
 553                         to_amdgpu_connector(connector);
 554
 555                 if (val == 0)
 556                         amdgpu_connector->dac_load_detect = false;
 557                 else
 558                         amdgpu_connector->dac_load_detect = true;
 559         }
 560
 561         if (property == dev->mode_config.scaling_mode_property) {
 562                 enum amdgpu_rmx_type rmx_type;
 563
 564                 if (connector->encoder) {
 565                         amdgpu_encoder = to_amdgpu_encoder(connector->encoder);
 566                 } else {
 567                         const struct drm_connector_helper_funcs *connector_funcs = connector->helper_private;
 568
 569                         amdgpu_encoder = to_amdgpu_encoder(connector_funcs->best_encoder(connector));
 570                 }
 571
 572                 switch (val) {
 573                 default:
 574                 case DRM_MODE_SCALE_NONE:
 575                         rmx_type = RMX_OFF;
 576                         break;
 577                 case DRM_MODE_SCALE_CENTER:
 578                         rmx_type = RMX_CENTER;
 579                         break;
 580                 case DRM_MODE_SCALE_ASPECT:
 581                         rmx_type = RMX_ASPECT;
 582                         break;
 583                 case DRM_MODE_SCALE_FULLSCREEN:
 584                         rmx_type = RMX_FULL;
 585                         break;
 586                 }
 587
 588                 if (amdgpu_encoder->rmx_type == rmx_type)
 589                         return 0;
 590
 591                 if ((rmx_type != DRM_MODE_SCALE_NONE) &&
 592                     (amdgpu_encoder->native_mode.clock == 0))
 593                         return 0;
 594
 595                 amdgpu_encoder->rmx_type = rmx_type;
 596
 597                 amdgpu_connector_property_change_mode(&amdgpu_encoder->base);
 598         }
 599
 600         return 0;
 601 }
 602
 603 static void
 604 amdgpu_connector_fixup_lcd_native_mode(struct drm_encoder *encoder,
 605                                         struct drm_connector *connector)
 606 {
 607         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
 608         struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
 609         struct drm_display_mode *t, *mode;
 610
 611         /* If the EDID preferred mode doesn't match the native mode, use it */
 612         list_for_each_entry_safe(mode, t, &connector->probed_modes, head) {
 613                 if (mode->type & DRM_MODE_TYPE_PREFERRED) {
 614                         if (mode->hdisplay != native_mode->hdisplay ||
 615                             mode->vdisplay != native_mode->vdisplay)
 616                                 drm_mode_copy(native_mode, mode);
 617                 }
 618         }
 619
 620         /* Try to get native mode details from EDID if necessary */
 621         if (!native_mode->clock) {
 622                 list_for_each_entry_safe(mode, t, &connector->probed_modes, head) {
 623                         if (mode->hdisplay == native_mode->hdisplay &&
 624                             mode->vdisplay == native_mode->vdisplay) {
 625                                 drm_mode_copy(native_mode, mode);
 626                                 drm_mode_set_crtcinfo(native_mode, CRTC_INTERLACE_HALVE_V);
 627                                 DRM_DEBUG_KMS("Determined LVDS native mode details from EDID\n");
 628                                 break;
 629                         }
 630                 }
 631         }
 632
 633         if (!native_mode->clock) {
 634                 DRM_DEBUG_KMS("No LVDS native mode details, disabling RMX\n");
 635                 amdgpu_encoder->rmx_type = RMX_OFF;
 636         }
 637 }
 638
 639 static int amdgpu_connector_lvds_get_modes(struct drm_connector *connector)
 640 {
 641         struct drm_encoder *encoder;
 642         int ret = 0;
 643         struct drm_display_mode *mode;
 644
 645         amdgpu_connector_get_edid(connector);
 646         ret = amdgpu_connector_ddc_get_modes(connector);
 647         if (ret > 0) {
 648                 encoder = amdgpu_connector_best_single_encoder(connector);
 649                 if (encoder) {
 650                         amdgpu_connector_fixup_lcd_native_mode(encoder, connector);
 651                         /* add scaled modes */
 652                         amdgpu_connector_add_common_modes(encoder, connector);
 653                 }
 654                 return ret;
 655         }
 656
 657         encoder = amdgpu_connector_best_single_encoder(connector);
 658         if (!encoder)
 659                 return 0;
 660
 661         /* we have no EDID modes */
 662         mode = amdgpu_connector_lcd_native_mode(encoder);
 663         if (mode) {
 664                 ret = 1;
 665                 drm_mode_probed_add(connector, mode);
 666                 /* add the width/height from vbios tables if available */
 667                 connector->display_info.width_mm = mode->width_mm;
 668                 connector->display_info.height_mm = mode->height_mm;
 669                 /* add scaled modes */
 670                 amdgpu_connector_add_common_modes(encoder, connector);
 671         }
 672
 673         return ret;
 674 }
 675
 676 static enum drm_mode_status amdgpu_connector_lvds_mode_valid(struct drm_connector *connector,
 677                                              struct drm_display_mode *mode)
 678 {
 679         struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector);
 680
 681         if ((mode->hdisplay < 320) || (mode->vdisplay < 240))
 682                 return MODE_PANEL;
 683
 684         if (encoder) {
 685                 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
 686                 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
 687
 688                 /* AVIVO hardware supports downscaling modes larger than the panel
 689                  * to the panel size, but I'm not sure this is desirable.
 690                  */
 691                 if ((mode->hdisplay > native_mode->hdisplay) ||
 692                     (mode->vdisplay > native_mode->vdisplay))
 693                         return MODE_PANEL;
 694
 695                 /* if scaling is disabled, block non-native modes */
 696                 if (amdgpu_encoder->rmx_type == RMX_OFF) {
 697                         if ((mode->hdisplay != native_mode->hdisplay) ||
 698                             (mode->vdisplay != native_mode->vdisplay))
 699                                 return MODE_PANEL;
 700                 }
 701         }
 702
 703         return MODE_OK;
 704 }
 705
 706 static enum drm_connector_status
 707 amdgpu_connector_lvds_detect(struct drm_connector *connector, bool force)
 708 {
 709         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 710         struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector);
 711         enum drm_connector_status ret = connector_status_disconnected;
 712         int r;
 713
 714         if (!drm_kms_helper_is_poll_worker()) {
 715                 r = pm_runtime_get_sync(connector->dev->dev);
 716                 if (r < 0) {
 717                         pm_runtime_put_autosuspend(connector->dev->dev);
 718                         return connector_status_disconnected;
 719                 }
 720         }
 721
 722         if (encoder) {
 723                 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
 724                 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
 725
 726                 /* check if panel is valid */
 727                 if (native_mode->hdisplay >= 320 && native_mode->vdisplay >= 240)
 728                         ret = connector_status_connected;
 729
 730         }
 731
 732         /* check for edid as well */
 733         amdgpu_connector_get_edid(connector);
 734         if (amdgpu_connector->edid)
 735                 ret = connector_status_connected;
 736         /* check acpi lid status ??? */
 737
 738         amdgpu_connector_update_scratch_regs(connector, ret);
 739
 740         if (!drm_kms_helper_is_poll_worker()) {
 741                 pm_runtime_mark_last_busy(connector->dev->dev);
 742                 pm_runtime_put_autosuspend(connector->dev->dev);
 743         }
 744
 745         return ret;
 746 }
 747
 748 static void amdgpu_connector_unregister(struct drm_connector *connector)
 749 {
 750         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 751
 752         if (amdgpu_connector->ddc_bus && amdgpu_connector->ddc_bus->has_aux) {
 753                 drm_dp_aux_unregister(&amdgpu_connector->ddc_bus->aux);
 754                 amdgpu_connector->ddc_bus->has_aux = false;
 755         }
 756 }
 757
 758 static void amdgpu_connector_destroy(struct drm_connector *connector)
 759 {
 760         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 761
 762         amdgpu_connector_free_edid(connector);
 763         kfree(amdgpu_connector->con_priv);
 764         drm_connector_unregister(connector);
 765         drm_connector_cleanup(connector);
 766         kfree(connector);
 767 }
 768
 769 static int amdgpu_connector_set_lcd_property(struct drm_connector *connector,
 770                                               struct drm_property *property,
 771                                               uint64_t value)
 772 {
 773         struct drm_device *dev = connector->dev;
 774         struct amdgpu_encoder *amdgpu_encoder;
 775         enum amdgpu_rmx_type rmx_type;
 776
 777         DRM_DEBUG_KMS("\n");
 778         if (property != dev->mode_config.scaling_mode_property)
 779                 return 0;
 780
 781         if (connector->encoder)
 782                 amdgpu_encoder = to_amdgpu_encoder(connector->encoder);
 783         else {
 784                 const struct drm_connector_helper_funcs *connector_funcs = connector->helper_private;
 785
 786                 amdgpu_encoder = to_amdgpu_encoder(connector_funcs->best_encoder(connector));
 787         }
 788
 789         switch (value) {
 790         case DRM_MODE_SCALE_NONE:
 791                 rmx_type = RMX_OFF;
 792                 break;
 793         case DRM_MODE_SCALE_CENTER:
 794                 rmx_type = RMX_CENTER;
 795                 break;
 796         case DRM_MODE_SCALE_ASPECT:
 797                 rmx_type = RMX_ASPECT;
 798                 break;
 799         default:
 800         case DRM_MODE_SCALE_FULLSCREEN:
 801                 rmx_type = RMX_FULL;
 802                 break;
 803         }
 804
 805         if (amdgpu_encoder->rmx_type == rmx_type)
 806                 return 0;
 807
 808         amdgpu_encoder->rmx_type = rmx_type;
 809
 810         amdgpu_connector_property_change_mode(&amdgpu_encoder->base);
 811         return 0;
 812 }
 813
 814
 815 static const struct drm_connector_helper_funcs amdgpu_connector_lvds_helper_funcs = {
 816         .get_modes = amdgpu_connector_lvds_get_modes,
 817         .mode_valid = amdgpu_connector_lvds_mode_valid,
 818         .best_encoder = amdgpu_connector_best_single_encoder,
 819 };
 820
 821 static const struct drm_connector_funcs amdgpu_connector_lvds_funcs = {
 822         .dpms = drm_helper_connector_dpms,
 823         .detect = amdgpu_connector_lvds_detect,
 824         .fill_modes = drm_helper_probe_single_connector_modes,
 825         .early_unregister = amdgpu_connector_unregister,
 826         .destroy = amdgpu_connector_destroy,
 827         .set_property = amdgpu_connector_set_lcd_property,
 828 };
 829
 830 static int amdgpu_connector_vga_get_modes(struct drm_connector *connector)
 831 {
 832         int ret;
 833
 834         amdgpu_connector_get_edid(connector);
 835         ret = amdgpu_connector_ddc_get_modes(connector);
 836         amdgpu_get_native_mode(connector);
 837
 838         return ret;
 839 }
 840
 841 static enum drm_mode_status amdgpu_connector_vga_mode_valid(struct drm_connector *connector,
 842                                             struct drm_display_mode *mode)
 843 {
 844         struct drm_device *dev = connector->dev;
 845         struct amdgpu_device *adev = drm_to_adev(dev);
 846
 847         /* XXX check mode bandwidth */
 848
 849         if ((mode->clock / 10) > adev->clock.max_pixel_clock)
 850                 return MODE_CLOCK_HIGH;
 851
 852         return MODE_OK;
 853 }
 854
 855 static enum drm_connector_status
 856 amdgpu_connector_vga_detect(struct drm_connector *connector, bool force)
 857 {
 858         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 859         struct drm_encoder *encoder;
 860         const struct drm_encoder_helper_funcs *encoder_funcs;
 861         bool dret = false;
 862         enum drm_connector_status ret = connector_status_disconnected;
 863         int r;
 864
 865         if (!drm_kms_helper_is_poll_worker()) {
 866                 r = pm_runtime_get_sync(connector->dev->dev);
 867                 if (r < 0) {
 868                         pm_runtime_put_autosuspend(connector->dev->dev);
 869                         return connector_status_disconnected;
 870                 }
 871         }
 872
 873         encoder = amdgpu_connector_best_single_encoder(connector);
 874         if (!encoder)
 875                 ret = connector_status_disconnected;
 876
 877         if (amdgpu_connector->ddc_bus)
 878                 dret = amdgpu_display_ddc_probe(amdgpu_connector, false);
 879         if (dret) {
 880                 amdgpu_connector->detected_by_load = false;
 881                 amdgpu_connector_free_edid(connector);
 882                 amdgpu_connector_get_edid(connector);
 883
 884                 if (!amdgpu_connector->edid) {
 885                         DRM_ERROR("%s: probed a monitor but no|invalid EDID\n",
 886                                         connector->name);
 887                         ret = connector_status_connected;
 888                 } else {
 889                         amdgpu_connector->use_digital =
 890                                 !!(amdgpu_connector->edid->input & DRM_EDID_INPUT_DIGITAL);
 891
 892                         /* some oems have boards with separate digital and analog connectors
 893                          * with a shared ddc line (often vga + hdmi)
 894                          */
 895                         if (amdgpu_connector->use_digital && amdgpu_connector->shared_ddc) {
 896                                 amdgpu_connector_free_edid(connector);
 897                                 ret = connector_status_disconnected;
 898                         } else {
 899                                 ret = connector_status_connected;
 900                         }
 901                 }
 902         } else {
 903
 904                 /* if we aren't forcing don't do destructive polling */
 905                 if (!force) {
 906                         /* only return the previous status if we last
 907                          * detected a monitor via load.
 908                          */
 909                         if (amdgpu_connector->detected_by_load)
 910                                 ret = connector->status;
 911                         goto out;
 912                 }
 913
 914                 if (amdgpu_connector->dac_load_detect && encoder) {
 915                         encoder_funcs = encoder->helper_private;
 916                         ret = encoder_funcs->detect(encoder, connector);
 917                         if (ret != connector_status_disconnected)
 918                                 amdgpu_connector->detected_by_load = true;
 919                 }
 920         }
 921
 922         amdgpu_connector_update_scratch_regs(connector, ret);
 923
 924 out:
 925         if (!drm_kms_helper_is_poll_worker()) {
 926                 pm_runtime_mark_last_busy(connector->dev->dev);
 927                 pm_runtime_put_autosuspend(connector->dev->dev);
 928         }
 929
 930         return ret;
 931 }
 932
 933 static const struct drm_connector_helper_funcs amdgpu_connector_vga_helper_funcs = {
 934         .get_modes = amdgpu_connector_vga_get_modes,
 935         .mode_valid = amdgpu_connector_vga_mode_valid,
 936         .best_encoder = amdgpu_connector_best_single_encoder,
 937 };
 938
 939 static const struct drm_connector_funcs amdgpu_connector_vga_funcs = {
 940         .dpms = drm_helper_connector_dpms,
 941         .detect = amdgpu_connector_vga_detect,
 942         .fill_modes = drm_helper_probe_single_connector_modes,
 943         .early_unregister = amdgpu_connector_unregister,
 944         .destroy = amdgpu_connector_destroy,
 945         .set_property = amdgpu_connector_set_property,
 946 };
 947
 948 static bool
 949 amdgpu_connector_check_hpd_status_unchanged(struct drm_connector *connector)
 950 {
 951         struct drm_device *dev = connector->dev;
 952         struct amdgpu_device *adev = drm_to_adev(dev);
 953         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 954         enum drm_connector_status status;
 955
 956         if (amdgpu_connector->hpd.hpd != AMDGPU_HPD_NONE) {
 957                 if (amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd))
 958                         status = connector_status_connected;
 959                 else
 960                         status = connector_status_disconnected;
 961                 if (connector->status == status)
 962                         return true;
 963         }
 964
 965         return false;
 966 }
 967
 968 static void amdgpu_connector_shared_ddc(enum drm_connector_status *status,
 969                                         struct drm_connector *connector,
 970                                         struct amdgpu_connector *amdgpu_connector)
 971 {
 972         struct drm_connector *list_connector;
 973         struct drm_connector_list_iter iter;
 974         struct amdgpu_connector *list_amdgpu_connector;
 975         struct drm_device *dev = connector->dev;
 976         struct amdgpu_device *adev = drm_to_adev(dev);
 977
 978         if (amdgpu_connector->shared_ddc && *status == connector_status_connected) {
 979                 drm_connector_list_iter_begin(dev, &iter);
 980                 drm_for_each_connector_iter(list_connector,
 981                                             &iter) {
 982                         if (connector == list_connector)
 983                                 continue;
 984                         list_amdgpu_connector = to_amdgpu_connector(list_connector);
 985                         if (list_amdgpu_connector->shared_ddc &&
 986                             list_amdgpu_connector->ddc_bus->rec.i2c_id ==
 987                              amdgpu_connector->ddc_bus->rec.i2c_id) {
 988                                 /* cases where both connectors are digital */
 989                                 if (list_connector->connector_type != DRM_MODE_CONNECTOR_VGA) {
 990                                         /* hpd is our only option in this case */
 991                                         if (!amdgpu_display_hpd_sense(adev,
 992                                                                       amdgpu_connector->hpd.hpd)) {
 993                                                 amdgpu_connector_free_edid(connector);
 994                                                 *status = connector_status_disconnected;
 995                                         }
 996                                 }
 997                         }
 998                 }
 999                 drm_connector_list_iter_end(&iter);
1000         }
1001 }
1002
1003 /*
1004  * DVI is complicated
1005  * Do a DDC probe, if DDC probe passes, get the full EDID so
1006  * we can do analog/digital monitor detection at this point.
1007  * If the monitor is an analog monitor or we got no DDC,
1008  * we need to find the DAC encoder object for this connector.
1009  * If we got no DDC, we do load detection on the DAC encoder object.
1010  * If we got analog DDC or load detection passes on the DAC encoder
1011  * we have to check if this analog encoder is shared with anyone else (TV)
1012  * if its shared we have to set the other connector to disconnected.
1013  */
1014 static enum drm_connector_status
1015 amdgpu_connector_dvi_detect(struct drm_connector *connector, bool force)
1016 {
1017         struct drm_device *dev = connector->dev;
1018         struct amdgpu_device *adev = drm_to_adev(dev);
1019         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
1020         const struct drm_encoder_helper_funcs *encoder_funcs;
1021         int r;
1022         enum drm_connector_status ret = connector_status_disconnected;
1023         bool dret = false, broken_edid = false;
1024
1025         if (!drm_kms_helper_is_poll_worker()) {
1026                 r = pm_runtime_get_sync(connector->dev->dev);
1027                 if (r < 0) {
1028                         pm_runtime_put_autosuspend(connector->dev->dev);
1029                         return connector_status_disconnected;
1030                 }
1031         }
1032
1033         if (amdgpu_connector->detected_hpd_without_ddc) {
1034                 force = true;
1035                 amdgpu_connector->detected_hpd_without_ddc = false;
1036         }
1037
1038         if (!force && amdgpu_connector_check_hpd_status_unchanged(connector)) {
1039                 ret = connector->status;
1040                 goto exit;
1041         }
1042
1043         if (amdgpu_connector->ddc_bus) {
1044                 dret = amdgpu_display_ddc_probe(amdgpu_connector, false);
1045
1046                 /* Sometimes the pins required for the DDC probe on DVI
1047                  * connectors don't make contact at the same time that the ones
1048                  * for HPD do. If the DDC probe fails even though we had an HPD
1049                  * signal, try again later
1050                  */
1051                 if (!dret && !force &&
1052                     amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd)) {
1053                         DRM_DEBUG_KMS("hpd detected without ddc, retrying in 1 second\n");
1054                         amdgpu_connector->detected_hpd_without_ddc = true;
1055                         schedule_delayed_work(&adev->hotplug_work,
1056                                               msecs_to_jiffies(1000));
1057                         goto exit;
1058                 }
1059         }
1060         if (dret) {
1061                 amdgpu_connector->detected_by_load = false;
1062                 amdgpu_connector_free_edid(connector);
1063                 amdgpu_connector_get_edid(connector);
1064
1065                 if (!amdgpu_connector->edid) {
1066                         DRM_ERROR("%s: probed a monitor but no|invalid EDID\n",
1067                                         connector->name);
1068                         ret = connector_status_connected;
1069                         broken_edid = true; /* defer use_digital to later */
1070                 } else {
1071                         amdgpu_connector->use_digital =
1072                                 !!(amdgpu_connector->edid->input & DRM_EDID_INPUT_DIGITAL);
1073
1074                         /* some oems have boards with separate digital and analog connectors
1075                          * with a shared ddc line (often vga + hdmi)
1076                          */
1077                         if ((!amdgpu_connector->use_digital) && amdgpu_connector->shared_ddc) {
1078                                 amdgpu_connector_free_edid(connector);
1079                                 ret = connector_status_disconnected;
1080                         } else {
1081                                 ret = connector_status_connected;
1082                         }
1083
1084                         /* This gets complicated.  We have boards with VGA + HDMI with a
1085                          * shared DDC line and we have boards with DVI-D + HDMI with a shared
1086                          * DDC line.  The latter is more complex because with DVI<->HDMI adapters
1087                          * you don't really know what's connected to which port as both are digital.
1088                          */
1089                         amdgpu_connector_shared_ddc(&ret, connector, amdgpu_connector);
1090                 }
1091         }
1092
1093         if ((ret == connector_status_connected) && (amdgpu_connector->use_digital == true))
1094                 goto out;
1095
1096         /* DVI-D and HDMI-A are digital only */
1097         if ((connector->connector_type == DRM_MODE_CONNECTOR_DVID) ||
1098             (connector->connector_type == DRM_MODE_CONNECTOR_HDMIA))
1099                 goto out;
1100
1101         /* if we aren't forcing don't do destructive polling */
1102         if (!force) {
1103                 /* only return the previous status if we last
1104                  * detected a monitor via load.
1105                  */
1106                 if (amdgpu_connector->detected_by_load)
1107                         ret = connector->status;
1108                 goto out;
1109         }
1110
1111         /* find analog encoder */
1112         if (amdgpu_connector->dac_load_detect) {
1113                 struct drm_encoder *encoder;
1114
1115                 drm_connector_for_each_possible_encoder(connector, encoder) {
1116                         if (encoder->encoder_type != DRM_MODE_ENCODER_DAC &&
1117                             encoder->encoder_type != DRM_MODE_ENCODER_TVDAC)
1118                                 continue;
1119
1120                         encoder_funcs = encoder->helper_private;
1121                         if (encoder_funcs->detect) {
1122                                 if (!broken_edid) {
1123                                         if (ret != connector_status_connected) {
1124                                                 /* deal with analog monitors without DDC */
1125                                                 ret = encoder_funcs->detect(encoder, connector);
1126                                                 if (ret == connector_status_connected) {
1127                                                         amdgpu_connector->use_digital = false;
1128                                                 }
1129                                                 if (ret != connector_status_disconnected)
1130                                                         amdgpu_connector->detected_by_load = true;
1131                                         }
1132                                 } else {
1133                                         enum drm_connector_status lret;
1134                                         /* assume digital unless load detected otherwise */
1135                                         amdgpu_connector->use_digital = true;
1136                                         lret = encoder_funcs->detect(encoder, connector);
1137                                         DRM_DEBUG_KMS("load_detect %x returned: %x\n",
1138                                                       encoder->encoder_type, lret);
1139                                         if (lret == connector_status_connected)
1140                                                 amdgpu_connector->use_digital = false;
1141                                 }
1142                                 break;
1143                         }
1144                 }
1145         }
1146
1147 out:
1148         /* updated in get modes as well since we need to know if it's analog or digital */
1149         amdgpu_connector_update_scratch_regs(connector, ret);
1150
1151 exit:
1152         if (!drm_kms_helper_is_poll_worker()) {
1153                 pm_runtime_mark_last_busy(connector->dev->dev);
1154                 pm_runtime_put_autosuspend(connector->dev->dev);
1155         }
1156
1157         return ret;
1158 }
1159
1160 /* okay need to be smart in here about which encoder to pick */
1161 static struct drm_encoder *
1162 amdgpu_connector_dvi_encoder(struct drm_connector *connector)
1163 {
1164         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
1165         struct drm_encoder *encoder;
1166
1167         drm_connector_for_each_possible_encoder(connector, encoder) {
1168                 if (amdgpu_connector->use_digital == true) {
1169                         if (encoder->encoder_type == DRM_MODE_ENCODER_TMDS)
1170                                 return encoder;
1171                 } else {
1172                         if (encoder->encoder_type == DRM_MODE_ENCODER_DAC ||
1173                             encoder->encoder_type == DRM_MODE_ENCODER_TVDAC)
1174                                 return encoder;
1175                 }
1176         }
1177
1178         /* see if we have a default encoder  TODO */
1179
1180         /* then check use digitial */
1181         /* pick the first one */
1182         drm_connector_for_each_possible_encoder(connector, encoder)
1183                 return encoder;
1184
1185         return NULL;
1186 }
1187
1188 static void amdgpu_connector_dvi_force(struct drm_connector *connector)
1189 {
1190         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
1191
1192         if (connector->force == DRM_FORCE_ON)
1193                 amdgpu_connector->use_digital = false;
1194         if (connector->force == DRM_FORCE_ON_DIGITAL)
1195                 amdgpu_connector->use_digital = true;
1196 }
1197
1198 static enum drm_mode_status amdgpu_connector_dvi_mode_valid(struct drm_connector *connector,
1199                                             struct drm_display_mode *mode)
1200 {
1201         struct drm_device *dev = connector->dev;
1202         struct amdgpu_device *adev = drm_to_adev(dev);
1203         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
1204
1205         /* XXX check mode bandwidth */
1206
1207         if (amdgpu_connector->use_digital && (mode->clock > 165000)) {
1208                 if ((amdgpu_connector->connector_object_id == CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I) ||
1209                     (amdgpu_connector->connector_object_id == CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D) ||
1210                     (amdgpu_connector->connector_object_id == CONNECTOR_OBJECT_ID_HDMI_TYPE_B)) {
1211                         return MODE_OK;
1212                 } else if (connector->display_info.is_hdmi) {
1213                         /* HDMI 1.3+ supports max clock of 340 Mhz */
1214                         if (mode->clock > 340000)
1215                                 return MODE_CLOCK_HIGH;
1216                         else
1217                                 return MODE_OK;
1218                 } else {
1219                         return MODE_CLOCK_HIGH;
1220                 }
1221         }
1222
1223         /* check against the max pixel clock */
1224         if ((mode->clock / 10) > adev->clock.max_pixel_clock)
1225                 return MODE_CLOCK_HIGH;
1226
1227         return MODE_OK;
1228 }
1229
1230 static const struct drm_connector_helper_funcs amdgpu_connector_dvi_helper_funcs = {
1231         .get_modes = amdgpu_connector_vga_get_modes,
1232         .mode_valid = amdgpu_connector_dvi_mode_valid,
1233         .best_encoder = amdgpu_connector_dvi_encoder,
1234 };
1235
1236 static const struct drm_connector_funcs amdgpu_connector_dvi_funcs = {
1237         .dpms = drm_helper_connector_dpms,
1238         .detect = amdgpu_connector_dvi_detect,
1239         .fill_modes = drm_helper_probe_single_connector_modes,
1240         .set_property = amdgpu_connector_set_property,
1241         .early_unregister = amdgpu_connector_unregister,
1242         .destroy = amdgpu_connector_destroy,
1243         .force = amdgpu_connector_dvi_force,
1244 };
1245
1246 static int amdgpu_connector_dp_get_modes(struct drm_connector *connector)
1247 {
1248         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
1249         struct amdgpu_connector_atom_dig *amdgpu_dig_connector = amdgpu_connector->con_priv;
1250         struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector);
1251         int ret;
1252
1253         if ((connector->connector_type == DRM_MODE_CONNECTOR_eDP) ||
1254             (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)) {
1255                 struct drm_display_mode *mode;
1256
1257                 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
1258                         if (!amdgpu_dig_connector->edp_on)
1259                                 amdgpu_atombios_encoder_set_edp_panel_power(connector,
1260                                                                      ATOM_TRANSMITTER_ACTION_POWER_ON);
1261                         amdgpu_connector_get_edid(connector);
1262                         ret = amdgpu_connector_ddc_get_modes(connector);
1263                         if (!amdgpu_dig_connector->edp_on)
1264                                 amdgpu_atombios_encoder_set_edp_panel_power(connector,
1265                                                                      ATOM_TRANSMITTER_ACTION_POWER_OFF);
1266                 } else {
1267                         /* need to setup ddc on the bridge */
1268                         if (amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) !=
1269                             ENCODER_OBJECT_ID_NONE) {
1270                                 if (encoder)
1271                                         amdgpu_atombios_encoder_setup_ext_encoder_ddc(encoder);
1272                         }
1273                         amdgpu_connector_get_edid(connector);
1274                         ret = amdgpu_connector_ddc_get_modes(connector);
1275                 }
1276
1277                 if (ret > 0) {
1278                         if (encoder) {
1279                                 amdgpu_connector_fixup_lcd_native_mode(encoder, connector);
1280                                 /* add scaled modes */
1281                                 amdgpu_connector_add_common_modes(encoder, connector);
1282                         }
1283                         return ret;
1284                 }
1285
1286                 if (!encoder)
1287                         return 0;
1288
1289                 /* we have no EDID modes */
1290                 mode = amdgpu_connector_lcd_native_mode(encoder);
1291                 if (mode) {
1292                         ret = 1;
1293                         drm_mode_probed_add(connector, mode);
1294                         /* add the width/height from vbios tables if available */
1295                         connector->display_info.width_mm = mode->width_mm;
1296                         connector->display_info.height_mm = mode->height_mm;
1297                         /* add scaled modes */
1298                         amdgpu_connector_add_common_modes(encoder, connector);
1299                 }
1300         } else {
1301                 /* need to setup ddc on the bridge */
1302                 if (amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) !=
1303                         ENCODER_OBJECT_ID_NONE) {
1304                         if (encoder)
1305                                 amdgpu_atombios_encoder_setup_ext_encoder_ddc(encoder);
1306                 }
1307                 amdgpu_connector_get_edid(connector);
1308                 ret = amdgpu_connector_ddc_get_modes(connector);
1309
1310                 amdgpu_get_native_mode(connector);
1311         }
1312
1313         return ret;
1314 }
1315
1316 u16 amdgpu_connector_encoder_get_dp_bridge_encoder_id(struct drm_connector *connector)
1317 {
1318         struct drm_encoder *encoder;
1319         struct amdgpu_encoder *amdgpu_encoder;
1320
1321         drm_connector_for_each_possible_encoder(connector, encoder) {
1322                 amdgpu_encoder = to_amdgpu_encoder(encoder);
1323
1324                 switch (amdgpu_encoder->encoder_id) {
1325                 case ENCODER_OBJECT_ID_TRAVIS:
1326                 case ENCODER_OBJECT_ID_NUTMEG:
1327                         return amdgpu_encoder->encoder_id;
1328                 default:
1329                         break;
1330                 }
1331         }
1332
1333         return ENCODER_OBJECT_ID_NONE;
1334 }
1335
1336 static bool amdgpu_connector_encoder_is_hbr2(struct drm_connector *connector)
1337 {
1338         struct drm_encoder *encoder;
1339         struct amdgpu_encoder *amdgpu_encoder;
1340         bool found = false;
1341
1342         drm_connector_for_each_possible_encoder(connector, encoder) {
1343                 amdgpu_encoder = to_amdgpu_encoder(encoder);
1344                 if (amdgpu_encoder->caps & ATOM_ENCODER_CAP_RECORD_HBR2)
1345                         found = true;
1346         }
1347
1348         return found;
1349 }
1350
1351 bool amdgpu_connector_is_dp12_capable(struct drm_connector *connector)
1352 {
1353         struct drm_device *dev = connector->dev;
1354         struct amdgpu_device *adev = drm_to_adev(dev);
1355
1356         if ((adev->clock.default_dispclk >= 53900) &&
1357             amdgpu_connector_encoder_is_hbr2(connector)) {
1358                 return true;
1359         }
1360
1361         return false;
1362 }
1363
1364 static enum drm_connector_status
1365 amdgpu_connector_dp_detect(struct drm_connector *connector, bool force)
1366 {
1367         struct drm_device *dev = connector->dev;
1368         struct amdgpu_device *adev = drm_to_adev(dev);
1369         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
1370         enum drm_connector_status ret = connector_status_disconnected;
1371         struct amdgpu_connector_atom_dig *amdgpu_dig_connector = amdgpu_connector->con_priv;
1372         struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector);
1373         int r;
1374
1375         if (!drm_kms_helper_is_poll_worker()) {
1376                 r = pm_runtime_get_sync(connector->dev->dev);
1377                 if (r < 0) {
1378                         pm_runtime_put_autosuspend(connector->dev->dev);
1379                         return connector_status_disconnected;
1380                 }
1381         }
1382
1383         if (!force && amdgpu_connector_check_hpd_status_unchanged(connector)) {
1384                 ret = connector->status;
1385                 goto out;
1386         }
1387
1388         amdgpu_connector_free_edid(connector);
1389
1390         if ((connector->connector_type == DRM_MODE_CONNECTOR_eDP) ||
1391             (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)) {
1392                 if (encoder) {
1393                         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1394                         struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
1395
1396                         /* check if panel is valid */
1397                         if (native_mode->hdisplay >= 320 && native_mode->vdisplay >= 240)
1398                                 ret = connector_status_connected;
1399                 }
1400                 /* eDP is always DP */
1401                 amdgpu_dig_connector->dp_sink_type = CONNECTOR_OBJECT_ID_DISPLAYPORT;
1402                 if (!amdgpu_dig_connector->edp_on)
1403                         amdgpu_atombios_encoder_set_edp_panel_power(connector,
1404                                                              ATOM_TRANSMITTER_ACTION_POWER_ON);
1405                 if (!amdgpu_atombios_dp_get_dpcd(amdgpu_connector))
1406                         ret = connector_status_connected;
1407                 if (!amdgpu_dig_connector->edp_on)
1408                         amdgpu_atombios_encoder_set_edp_panel_power(connector,
1409                                                              ATOM_TRANSMITTER_ACTION_POWER_OFF);
1410         } else if (amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) !=
1411                    ENCODER_OBJECT_ID_NONE) {
1412                 /* DP bridges are always DP */
1413                 amdgpu_dig_connector->dp_sink_type = CONNECTOR_OBJECT_ID_DISPLAYPORT;
1414                 /* get the DPCD from the bridge */
1415                 amdgpu_atombios_dp_get_dpcd(amdgpu_connector);
1416
1417                 if (encoder) {
1418                         /* setup ddc on the bridge */
1419                         amdgpu_atombios_encoder_setup_ext_encoder_ddc(encoder);
1420                         /* bridge chips are always aux */
1421                         /* try DDC */
1422                         if (amdgpu_display_ddc_probe(amdgpu_connector, true))
1423                                 ret = connector_status_connected;
1424                         else if (amdgpu_connector->dac_load_detect) { /* try load detection */
1425                                 const struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
1426
1427                                 ret = encoder_funcs->detect(encoder, connector);
1428                         }
1429                 }
1430         } else {
1431                 amdgpu_dig_connector->dp_sink_type =
1432                         amdgpu_atombios_dp_get_sinktype(amdgpu_connector);
1433                 if (amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd)) {
1434                         ret = connector_status_connected;
1435                         if (amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT)
1436                                 amdgpu_atombios_dp_get_dpcd(amdgpu_connector);
1437                 } else {
1438                         if (amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) {
1439                                 if (!amdgpu_atombios_dp_get_dpcd(amdgpu_connector))
1440                                         ret = connector_status_connected;
1441                         } else {
1442                                 /* try non-aux ddc (DP to DVI/HDMI/etc. adapter) */
1443                                 if (amdgpu_display_ddc_probe(amdgpu_connector,
1444                                                              false))
1445                                         ret = connector_status_connected;
1446                         }
1447                 }
1448         }
1449
1450         amdgpu_connector_update_scratch_regs(connector, ret);
1451 out:
1452         if (!drm_kms_helper_is_poll_worker()) {
1453                 pm_runtime_mark_last_busy(connector->dev->dev);
1454                 pm_runtime_put_autosuspend(connector->dev->dev);
1455         }
1456
1457         if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
1458             connector->connector_type == DRM_MODE_CONNECTOR_eDP)
1459                 drm_dp_set_subconnector_property(&amdgpu_connector->base,
1460                                                  ret,
1461                                                  amdgpu_dig_connector->dpcd,
1462                                                  amdgpu_dig_connector->downstream_ports);
1463         return ret;
1464 }
1465
1466 static enum drm_mode_status amdgpu_connector_dp_mode_valid(struct drm_connector *connector,
1467                                            struct drm_display_mode *mode)
1468 {
1469         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
1470         struct amdgpu_connector_atom_dig *amdgpu_dig_connector = amdgpu_connector->con_priv;
1471
1472         /* XXX check mode bandwidth */
1473
1474         if ((connector->connector_type == DRM_MODE_CONNECTOR_eDP) ||
1475             (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)) {
1476                 struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector);
1477
1478                 if ((mode->hdisplay < 320) || (mode->vdisplay < 240))
1479                         return MODE_PANEL;
1480
1481                 if (encoder) {
1482                         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1483                         struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
1484
1485                         /* AVIVO hardware supports downscaling modes larger than the panel
1486                          * to the panel size, but I'm not sure this is desirable.
1487                          */
1488                         if ((mode->hdisplay > native_mode->hdisplay) ||
1489                             (mode->vdisplay > native_mode->vdisplay))
1490                                 return MODE_PANEL;
1491
1492                         /* if scaling is disabled, block non-native modes */
1493                         if (amdgpu_encoder->rmx_type == RMX_OFF) {
1494                                 if ((mode->hdisplay != native_mode->hdisplay) ||
1495                                     (mode->vdisplay != native_mode->vdisplay))
1496                                         return MODE_PANEL;
1497                         }
1498                 }
1499                 return MODE_OK;
1500         } else {
1501                 if ((amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
1502                     (amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) {
1503                         return amdgpu_atombios_dp_mode_valid_helper(connector, mode);
1504                 } else {
1505                         if (connector->display_info.is_hdmi) {
1506                                 /* HDMI 1.3+ supports max clock of 340 Mhz */
1507                                 if (mode->clock > 340000)
1508                                         return MODE_CLOCK_HIGH;
1509                         } else {
1510                                 if (mode->clock > 165000)
1511                                         return MODE_CLOCK_HIGH;
1512                         }
1513                 }
1514         }
1515
1516         return MODE_OK;
1517 }
1518
1519 static int
1520 amdgpu_connector_late_register(struct drm_connector *connector)
1521 {
1522         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
1523         int r = 0;
1524
1525         if (amdgpu_connector->ddc_bus->has_aux) {
1526                 amdgpu_connector->ddc_bus->aux.dev = amdgpu_connector->base.kdev;
1527                 r = drm_dp_aux_register(&amdgpu_connector->ddc_bus->aux);
1528         }
1529
1530         return r;
1531 }
1532
1533 static const struct drm_connector_helper_funcs amdgpu_connector_dp_helper_funcs = {
1534         .get_modes = amdgpu_connector_dp_get_modes,
1535         .mode_valid = amdgpu_connector_dp_mode_valid,
1536         .best_encoder = amdgpu_connector_dvi_encoder,
1537 };
1538
1539 static const struct drm_connector_funcs amdgpu_connector_dp_funcs = {
1540         .dpms = drm_helper_connector_dpms,
1541         .detect = amdgpu_connector_dp_detect,
1542         .fill_modes = drm_helper_probe_single_connector_modes,
1543         .set_property = amdgpu_connector_set_property,
1544         .early_unregister = amdgpu_connector_unregister,
1545         .destroy = amdgpu_connector_destroy,
1546         .force = amdgpu_connector_dvi_force,
1547         .late_register = amdgpu_connector_late_register,
1548 };
1549
1550 static const struct drm_connector_funcs amdgpu_connector_edp_funcs = {
1551         .dpms = drm_helper_connector_dpms,
1552         .detect = amdgpu_connector_dp_detect,
1553         .fill_modes = drm_helper_probe_single_connector_modes,
1554         .set_property = amdgpu_connector_set_lcd_property,
1555         .early_unregister = amdgpu_connector_unregister,
1556         .destroy = amdgpu_connector_destroy,
1557         .force = amdgpu_connector_dvi_force,
1558         .late_register = amdgpu_connector_late_register,
1559 };
1560
1561 void
1562 amdgpu_connector_add(struct amdgpu_device *adev,
1563                       uint32_t connector_id,
1564                       uint32_t supported_device,
1565                       int connector_type,
1566                       struct amdgpu_i2c_bus_rec *i2c_bus,
1567                       uint16_t connector_object_id,
1568                       struct amdgpu_hpd *hpd,
1569                       struct amdgpu_router *router)
1570 {
1571         struct drm_device *dev = adev_to_drm(adev);
1572         struct drm_connector *connector;
1573         struct drm_connector_list_iter iter;
1574         struct amdgpu_connector *amdgpu_connector;
1575         struct amdgpu_connector_atom_dig *amdgpu_dig_connector;
1576         struct drm_encoder *encoder;
1577         struct amdgpu_encoder *amdgpu_encoder;
1578         struct i2c_adapter *ddc = NULL;
1579         uint32_t subpixel_order = SubPixelNone;
1580         bool shared_ddc = false;
1581         bool is_dp_bridge = false;
1582         bool has_aux = false;
1583
1584         if (connector_type == DRM_MODE_CONNECTOR_Unknown)
1585                 return;
1586
1587         /* see if we already added it */
1588         drm_connector_list_iter_begin(dev, &iter);
1589         drm_for_each_connector_iter(connector, &iter) {
1590                 amdgpu_connector = to_amdgpu_connector(connector);
1591                 if (amdgpu_connector->connector_id == connector_id) {
1592                         amdgpu_connector->devices |= supported_device;
1593                         drm_connector_list_iter_end(&iter);
1594                         return;
1595                 }
1596                 if (amdgpu_connector->ddc_bus && i2c_bus->valid) {
1597                         if (amdgpu_connector->ddc_bus->rec.i2c_id == i2c_bus->i2c_id) {
1598                                 amdgpu_connector->shared_ddc = true;
1599                                 shared_ddc = true;
1600                         }
1601                         if (amdgpu_connector->router_bus && router->ddc_valid &&
1602                             (amdgpu_connector->router.router_id == router->router_id)) {
1603                                 amdgpu_connector->shared_ddc = false;
1604                                 shared_ddc = false;
1605                         }
1606                 }
1607         }
1608         drm_connector_list_iter_end(&iter);
1609
1610         /* check if it's a dp bridge */
1611         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1612                 amdgpu_encoder = to_amdgpu_encoder(encoder);
1613                 if (amdgpu_encoder->devices & supported_device) {
1614                         switch (amdgpu_encoder->encoder_id) {
1615                         case ENCODER_OBJECT_ID_TRAVIS:
1616                         case ENCODER_OBJECT_ID_NUTMEG:
1617                                 is_dp_bridge = true;
1618                                 break;
1619                         default:
1620                                 break;
1621                         }
1622                 }
1623         }
1624
1625         amdgpu_connector = kzalloc(sizeof(struct amdgpu_connector), GFP_KERNEL);
1626         if (!amdgpu_connector)
1627                 return;
1628
1629         connector = &amdgpu_connector->base;
1630
1631         amdgpu_connector->connector_id = connector_id;
1632         amdgpu_connector->devices = supported_device;
1633         amdgpu_connector->shared_ddc = shared_ddc;
1634         amdgpu_connector->connector_object_id = connector_object_id;
1635         amdgpu_connector->hpd = *hpd;
1636
1637         amdgpu_connector->router = *router;
1638         if (router->ddc_valid || router->cd_valid) {
1639                 amdgpu_connector->router_bus = amdgpu_i2c_lookup(adev, &router->i2c_info);
1640                 if (!amdgpu_connector->router_bus)
1641                         DRM_ERROR("Failed to assign router i2c bus! Check dmesg for i2c errors.\n");
1642         }
1643
1644         if (is_dp_bridge) {
1645                 amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL);
1646                 if (!amdgpu_dig_connector)
1647                         goto failed;
1648                 amdgpu_connector->con_priv = amdgpu_dig_connector;
1649                 if (i2c_bus->valid) {
1650                         amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
1651                         if (amdgpu_connector->ddc_bus) {
1652                                 has_aux = true;
1653                                 ddc = &amdgpu_connector->ddc_bus->adapter;
1654                         } else {
1655                                 DRM_ERROR("DP: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
1656                         }
1657                 }
1658                 switch (connector_type) {
1659                 case DRM_MODE_CONNECTOR_VGA:
1660                 case DRM_MODE_CONNECTOR_DVIA:
1661                 default:
1662                         drm_connector_init_with_ddc(dev, &amdgpu_connector->base,
1663                                                     &amdgpu_connector_dp_funcs,
1664                                                     connector_type,
1665                                                     ddc);
1666                         drm_connector_helper_add(&amdgpu_connector->base,
1667                                                  &amdgpu_connector_dp_helper_funcs);
1668                         connector->interlace_allowed = true;
1669                         connector->doublescan_allowed = true;
1670                         amdgpu_connector->dac_load_detect = true;
1671                         drm_object_attach_property(&amdgpu_connector->base.base,
1672                                                       adev->mode_info.load_detect_property,
1673                                                       1);
1674                         drm_object_attach_property(&amdgpu_connector->base.base,
1675                                                    dev->mode_config.scaling_mode_property,
1676                                                    DRM_MODE_SCALE_NONE);
1677                         break;
1678                 case DRM_MODE_CONNECTOR_DVII:
1679                 case DRM_MODE_CONNECTOR_DVID:
1680                 case DRM_MODE_CONNECTOR_HDMIA:
1681                 case DRM_MODE_CONNECTOR_HDMIB:
1682                 case DRM_MODE_CONNECTOR_DisplayPort:
1683                         drm_connector_init_with_ddc(dev, &amdgpu_connector->base,
1684                                                     &amdgpu_connector_dp_funcs,
1685                                                     connector_type,
1686                                                     ddc);
1687                         drm_connector_helper_add(&amdgpu_connector->base,
1688                                                  &amdgpu_connector_dp_helper_funcs);
1689                         drm_object_attach_property(&amdgpu_connector->base.base,
1690                                                       adev->mode_info.underscan_property,
1691                                                       UNDERSCAN_OFF);
1692                         drm_object_attach_property(&amdgpu_connector->base.base,
1693                                                       adev->mode_info.underscan_hborder_property,
1694                                                       0);
1695                         drm_object_attach_property(&amdgpu_connector->base.base,
1696                                                       adev->mode_info.underscan_vborder_property,
1697                                                       0);
1698
1699                         drm_object_attach_property(&amdgpu_connector->base.base,
1700                                                    dev->mode_config.scaling_mode_property,
1701                                                    DRM_MODE_SCALE_NONE);
1702
1703                         drm_object_attach_property(&amdgpu_connector->base.base,
1704                                                    adev->mode_info.dither_property,
1705                                                    AMDGPU_FMT_DITHER_DISABLE);
1706
1707                         if (amdgpu_audio != 0) {
1708                                 drm_object_attach_property(&amdgpu_connector->base.base,
1709                                                            adev->mode_info.audio_property,
1710                                                            AMDGPU_AUDIO_AUTO);
1711                                 amdgpu_connector->audio = AMDGPU_AUDIO_AUTO;
1712                         }
1713
1714                         subpixel_order = SubPixelHorizontalRGB;
1715                         connector->interlace_allowed = true;
1716                         if (connector_type == DRM_MODE_CONNECTOR_HDMIB)
1717                                 connector->doublescan_allowed = true;
1718                         else
1719                                 connector->doublescan_allowed = false;
1720                         if (connector_type == DRM_MODE_CONNECTOR_DVII) {
1721                                 amdgpu_connector->dac_load_detect = true;
1722                                 drm_object_attach_property(&amdgpu_connector->base.base,
1723                                                               adev->mode_info.load_detect_property,
1724                                                               1);
1725                         }
1726                         break;
1727                 case DRM_MODE_CONNECTOR_LVDS:
1728                 case DRM_MODE_CONNECTOR_eDP:
1729                         drm_connector_init_with_ddc(dev, &amdgpu_connector->base,
1730                                                     &amdgpu_connector_edp_funcs,
1731                                                     connector_type,
1732                                                     ddc);
1733                         drm_connector_helper_add(&amdgpu_connector->base,
1734                                                  &amdgpu_connector_dp_helper_funcs);
1735                         drm_object_attach_property(&amdgpu_connector->base.base,
1736                                                       dev->mode_config.scaling_mode_property,
1737                                                       DRM_MODE_SCALE_FULLSCREEN);
1738                         subpixel_order = SubPixelHorizontalRGB;
1739                         connector->interlace_allowed = false;
1740                         connector->doublescan_allowed = false;
1741                         break;
1742                 }
1743         } else {
1744                 switch (connector_type) {
1745                 case DRM_MODE_CONNECTOR_VGA:
1746                         if (i2c_bus->valid) {
1747                                 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
1748                                 if (!amdgpu_connector->ddc_bus)
1749                                         DRM_ERROR("VGA: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
1750                                 else
1751                                         ddc = &amdgpu_connector->ddc_bus->adapter;
1752                         }
1753                         drm_connector_init_with_ddc(dev, &amdgpu_connector->base,
1754                                                     &amdgpu_connector_vga_funcs,
1755                                                     connector_type,
1756                                                     ddc);
1757                         drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_vga_helper_funcs);
1758                         amdgpu_connector->dac_load_detect = true;
1759                         drm_object_attach_property(&amdgpu_connector->base.base,
1760                                                       adev->mode_info.load_detect_property,
1761                                                       1);
1762                         drm_object_attach_property(&amdgpu_connector->base.base,
1763                                                    dev->mode_config.scaling_mode_property,
1764                                                    DRM_MODE_SCALE_NONE);
1765                         /* no HPD on analog connectors */
1766                         amdgpu_connector->hpd.hpd = AMDGPU_HPD_NONE;
1767                         connector->interlace_allowed = true;
1768                         connector->doublescan_allowed = true;
1769                         break;
1770                 case DRM_MODE_CONNECTOR_DVIA:
1771                         if (i2c_bus->valid) {
1772                                 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
1773                                 if (!amdgpu_connector->ddc_bus)
1774                                         DRM_ERROR("DVIA: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
1775                                 else
1776                                         ddc = &amdgpu_connector->ddc_bus->adapter;
1777                         }
1778                         drm_connector_init_with_ddc(dev, &amdgpu_connector->base,
1779                                                     &amdgpu_connector_vga_funcs,
1780                                                     connector_type,
1781                                                     ddc);
1782                         drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_vga_helper_funcs);
1783                         amdgpu_connector->dac_load_detect = true;
1784                         drm_object_attach_property(&amdgpu_connector->base.base,
1785                                                       adev->mode_info.load_detect_property,
1786                                                       1);
1787                         drm_object_attach_property(&amdgpu_connector->base.base,
1788                                                    dev->mode_config.scaling_mode_property,
1789                                                    DRM_MODE_SCALE_NONE);
1790                         /* no HPD on analog connectors */
1791                         amdgpu_connector->hpd.hpd = AMDGPU_HPD_NONE;
1792                         connector->interlace_allowed = true;
1793                         connector->doublescan_allowed = true;
1794                         break;
1795                 case DRM_MODE_CONNECTOR_DVII:
1796                 case DRM_MODE_CONNECTOR_DVID:
1797                         amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL);
1798                         if (!amdgpu_dig_connector)
1799                                 goto failed;
1800                         amdgpu_connector->con_priv = amdgpu_dig_connector;
1801                         if (i2c_bus->valid) {
1802                                 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
1803                                 if (!amdgpu_connector->ddc_bus)
1804                                         DRM_ERROR("DVI: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
1805                                 else
1806                                         ddc = &amdgpu_connector->ddc_bus->adapter;
1807                         }
1808                         drm_connector_init_with_ddc(dev, &amdgpu_connector->base,
1809                                                     &amdgpu_connector_dvi_funcs,
1810                                                     connector_type,
1811                                                     ddc);
1812                         drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dvi_helper_funcs);
1813                         subpixel_order = SubPixelHorizontalRGB;
1814                         drm_object_attach_property(&amdgpu_connector->base.base,
1815                                                       adev->mode_info.coherent_mode_property,
1816                                                       1);
1817                         drm_object_attach_property(&amdgpu_connector->base.base,
1818                                                    adev->mode_info.underscan_property,
1819                                                    UNDERSCAN_OFF);
1820                         drm_object_attach_property(&amdgpu_connector->base.base,
1821                                                    adev->mode_info.underscan_hborder_property,
1822                                                    0);
1823                         drm_object_attach_property(&amdgpu_connector->base.base,
1824                                                    adev->mode_info.underscan_vborder_property,
1825                                                    0);
1826                         drm_object_attach_property(&amdgpu_connector->base.base,
1827                                                    dev->mode_config.scaling_mode_property,
1828                                                    DRM_MODE_SCALE_NONE);
1829
1830                         if (amdgpu_audio != 0) {
1831                                 drm_object_attach_property(&amdgpu_connector->base.base,
1832                                                            adev->mode_info.audio_property,
1833                                                            AMDGPU_AUDIO_AUTO);
1834                                 amdgpu_connector->audio = AMDGPU_AUDIO_AUTO;
1835                         }
1836                         drm_object_attach_property(&amdgpu_connector->base.base,
1837                                                    adev->mode_info.dither_property,
1838                                                    AMDGPU_FMT_DITHER_DISABLE);
1839                         if (connector_type == DRM_MODE_CONNECTOR_DVII) {
1840                                 amdgpu_connector->dac_load_detect = true;
1841                                 drm_object_attach_property(&amdgpu_connector->base.base,
1842                                                            adev->mode_info.load_detect_property,
1843                                                            1);
1844                         }
1845                         connector->interlace_allowed = true;
1846                         if (connector_type == DRM_MODE_CONNECTOR_DVII)
1847                                 connector->doublescan_allowed = true;
1848                         else
1849                                 connector->doublescan_allowed = false;
1850                         break;
1851                 case DRM_MODE_CONNECTOR_HDMIA:
1852                 case DRM_MODE_CONNECTOR_HDMIB:
1853                         amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL);
1854                         if (!amdgpu_dig_connector)
1855                                 goto failed;
1856                         amdgpu_connector->con_priv = amdgpu_dig_connector;
1857                         if (i2c_bus->valid) {
1858                                 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
1859                                 if (!amdgpu_connector->ddc_bus)
1860                                         DRM_ERROR("HDMI: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
1861                                 else
1862                                         ddc = &amdgpu_connector->ddc_bus->adapter;
1863                         }
1864                         drm_connector_init_with_ddc(dev, &amdgpu_connector->base,
1865                                                     &amdgpu_connector_dvi_funcs,
1866                                                     connector_type,
1867                                                     ddc);
1868                         drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dvi_helper_funcs);
1869                         drm_object_attach_property(&amdgpu_connector->base.base,
1870                                                       adev->mode_info.coherent_mode_property,
1871                                                       1);
1872                         drm_object_attach_property(&amdgpu_connector->base.base,
1873                                                    adev->mode_info.underscan_property,
1874                                                    UNDERSCAN_OFF);
1875                         drm_object_attach_property(&amdgpu_connector->base.base,
1876                                                    adev->mode_info.underscan_hborder_property,
1877                                                    0);
1878                         drm_object_attach_property(&amdgpu_connector->base.base,
1879                                                    adev->mode_info.underscan_vborder_property,
1880                                                    0);
1881                         drm_object_attach_property(&amdgpu_connector->base.base,
1882                                                    dev->mode_config.scaling_mode_property,
1883                                                    DRM_MODE_SCALE_NONE);
1884                         if (amdgpu_audio != 0) {
1885                                 drm_object_attach_property(&amdgpu_connector->base.base,
1886                                                            adev->mode_info.audio_property,
1887                                                            AMDGPU_AUDIO_AUTO);
1888                                 amdgpu_connector->audio = AMDGPU_AUDIO_AUTO;
1889                         }
1890                         drm_object_attach_property(&amdgpu_connector->base.base,
1891                                                    adev->mode_info.dither_property,
1892                                                    AMDGPU_FMT_DITHER_DISABLE);
1893                         subpixel_order = SubPixelHorizontalRGB;
1894                         connector->interlace_allowed = true;
1895                         if (connector_type == DRM_MODE_CONNECTOR_HDMIB)
1896                                 connector->doublescan_allowed = true;
1897                         else
1898                                 connector->doublescan_allowed = false;
1899                         break;
1900                 case DRM_MODE_CONNECTOR_DisplayPort:
1901                         amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL);
1902                         if (!amdgpu_dig_connector)
1903                                 goto failed;
1904                         amdgpu_connector->con_priv = amdgpu_dig_connector;
1905                         if (i2c_bus->valid) {
1906                                 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
1907                                 if (amdgpu_connector->ddc_bus) {
1908                                         has_aux = true;
1909                                         ddc = &amdgpu_connector->ddc_bus->adapter;
1910                                 } else {
1911                                         DRM_ERROR("DP: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
1912                                 }
1913                         }
1914                         drm_connector_init_with_ddc(dev, &amdgpu_connector->base,
1915                                                     &amdgpu_connector_dp_funcs,
1916                                                     connector_type,
1917                                                     ddc);
1918                         drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dp_helper_funcs);
1919                         subpixel_order = SubPixelHorizontalRGB;
1920                         drm_object_attach_property(&amdgpu_connector->base.base,
1921                                                       adev->mode_info.coherent_mode_property,
1922                                                       1);
1923                         drm_object_attach_property(&amdgpu_connector->base.base,
1924                                                    adev->mode_info.underscan_property,
1925                                                    UNDERSCAN_OFF);
1926                         drm_object_attach_property(&amdgpu_connector->base.base,
1927                                                    adev->mode_info.underscan_hborder_property,
1928                                                    0);
1929                         drm_object_attach_property(&amdgpu_connector->base.base,
1930                                                    adev->mode_info.underscan_vborder_property,
1931                                                    0);
1932                         drm_object_attach_property(&amdgpu_connector->base.base,
1933                                                    dev->mode_config.scaling_mode_property,
1934                                                    DRM_MODE_SCALE_NONE);
1935                         if (amdgpu_audio != 0) {
1936                                 drm_object_attach_property(&amdgpu_connector->base.base,
1937                                                            adev->mode_info.audio_property,
1938                                                            AMDGPU_AUDIO_AUTO);
1939                                 amdgpu_connector->audio = AMDGPU_AUDIO_AUTO;
1940                         }
1941                         drm_object_attach_property(&amdgpu_connector->base.base,
1942                                                    adev->mode_info.dither_property,
1943                                                    AMDGPU_FMT_DITHER_DISABLE);
1944                         connector->interlace_allowed = true;
1945                         /* in theory with a DP to VGA converter... */
1946                         connector->doublescan_allowed = false;
1947                         break;
1948                 case DRM_MODE_CONNECTOR_eDP:
1949                         amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL);
1950                         if (!amdgpu_dig_connector)
1951                                 goto failed;
1952                         amdgpu_connector->con_priv = amdgpu_dig_connector;
1953                         if (i2c_bus->valid) {
1954                                 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
1955                                 if (amdgpu_connector->ddc_bus) {
1956                                         has_aux = true;
1957                                         ddc = &amdgpu_connector->ddc_bus->adapter;
1958                                 } else {
1959                                         DRM_ERROR("DP: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
1960                                 }
1961                         }
1962                         drm_connector_init_with_ddc(dev, &amdgpu_connector->base,
1963                                                     &amdgpu_connector_edp_funcs,
1964                                                     connector_type,
1965                                                     ddc);
1966                         drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dp_helper_funcs);
1967                         drm_object_attach_property(&amdgpu_connector->base.base,
1968                                                       dev->mode_config.scaling_mode_property,
1969                                                       DRM_MODE_SCALE_FULLSCREEN);
1970                         subpixel_order = SubPixelHorizontalRGB;
1971                         connector->interlace_allowed = false;
1972                         connector->doublescan_allowed = false;
1973                         break;
1974                 case DRM_MODE_CONNECTOR_LVDS:
1975                         amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL);
1976                         if (!amdgpu_dig_connector)
1977                                 goto failed;
1978                         amdgpu_connector->con_priv = amdgpu_dig_connector;
1979                         if (i2c_bus->valid) {
1980                                 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
1981                                 if (!amdgpu_connector->ddc_bus)
1982                                         DRM_ERROR("LVDS: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
1983                                 else
1984                                         ddc = &amdgpu_connector->ddc_bus->adapter;
1985                         }
1986                         drm_connector_init_with_ddc(dev, &amdgpu_connector->base,
1987                                                     &amdgpu_connector_lvds_funcs,
1988                                                     connector_type,
1989                                                     ddc);
1990                         drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_lvds_helper_funcs);
1991                         drm_object_attach_property(&amdgpu_connector->base.base,
1992                                                       dev->mode_config.scaling_mode_property,
1993                                                       DRM_MODE_SCALE_FULLSCREEN);
1994                         subpixel_order = SubPixelHorizontalRGB;
1995                         connector->interlace_allowed = false;
1996                         connector->doublescan_allowed = false;
1997                         break;
1998                 }
1999         }
2000
2001         if (amdgpu_connector->hpd.hpd == AMDGPU_HPD_NONE) {
2002                 if (i2c_bus->valid) {
2003                         connector->polled = DRM_CONNECTOR_POLL_CONNECT |
2004                                                 DRM_CONNECTOR_POLL_DISCONNECT;
2005                 }
2006         } else
2007                 connector->polled = DRM_CONNECTOR_POLL_HPD;
2008
2009         connector->display_info.subpixel_order = subpixel_order;
2010
2011         if (has_aux)
2012                 amdgpu_atombios_dp_aux_init(amdgpu_connector);
2013
2014         if (connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
2015             connector_type == DRM_MODE_CONNECTOR_eDP) {
2016                 drm_connector_attach_dp_subconnector_property(&amdgpu_connector->base);
2017         }
2018
2019         return;
2020
2021 failed:
2022         drm_connector_cleanup(connector);
2023         kfree(connector);
2024 }