drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c

   1 /*
   2  * Copyright 2007-8 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: Dave Airlie
  24  *          Alex Deucher
  25  */
  26
  27 #include <drm/display/drm_dp_helper.h>
  28 #include <drm/drm_crtc_helper.h>
  29 #include <drm/drm_edid.h>
  30 #include <drm/drm_modeset_helper_vtables.h>
  31 #include <drm/drm_probe_helper.h>
  32 #include <drm/amdgpu_drm.h>
  33 #include "amdgpu.h"
  34 #include "atom.h"
  35 #include "atombios_encoders.h"
  36 #include "atombios_dp.h"
  37 #include "amdgpu_connectors.h"
  38 #include "amdgpu_i2c.h"
  39 #include "amdgpu_display.h"
  40
  41 #include <linux/pm_runtime.h>
  42
  43 void amdgpu_connector_hotplug(struct drm_connector *connector)
  44 {
  45         struct drm_device *dev = connector->dev;
  46         struct amdgpu_device *adev = drm_to_adev(dev);
  47         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
  48
  49         /* bail if the connector does not have hpd pin, e.g.,
  50          * VGA, TV, etc.
  51          */
  52         if (amdgpu_connector->hpd.hpd == AMDGPU_HPD_NONE)
  53                 return;
  54
  55         amdgpu_display_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd);
  56
  57         /* if the connector is already off, don't turn it back on */
  58         if (connector->dpms != DRM_MODE_DPMS_ON)
  59                 return;
  60
  61         /* just deal with DP (not eDP) here. */
  62         if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) {
  63                 struct amdgpu_connector_atom_dig *dig_connector =
  64                         amdgpu_connector->con_priv;
  65
  66                 /* if existing sink type was not DP no need to retrain */
  67                 if (dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_DISPLAYPORT)
  68                         return;
  69
  70                 /* first get sink type as it may be reset after (un)plug */
  71                 dig_connector->dp_sink_type = amdgpu_atombios_dp_get_sinktype(amdgpu_connector);
  72                 /* don't do anything if sink is not display port, i.e.,
  73                  * passive dp->(dvi|hdmi) adaptor
  74                  */
  75                 if (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT &&
  76                     amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd) &&
  77                     amdgpu_atombios_dp_needs_link_train(amdgpu_connector)) {
  78                         /* Don't start link training before we have the DPCD */
  79                         if (amdgpu_atombios_dp_get_dpcd(amdgpu_connector))
  80                                 return;
  81
  82                         /* Turn the connector off and back on immediately, which
  83                          * will trigger link training
  84                          */
  85                         drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF);
  86                         drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON);
  87                 }
  88         }
  89 }
  90
  91 static void amdgpu_connector_property_change_mode(struct drm_encoder *encoder)
  92 {
  93         struct drm_crtc *crtc = encoder->crtc;
  94
  95         if (crtc && crtc->enabled) {
  96                 drm_crtc_helper_set_mode(crtc, &crtc->mode,
  97                                          crtc->x, crtc->y, crtc->primary->fb);
  98         }
  99 }
 100
 101 int amdgpu_connector_get_monitor_bpc(struct drm_connector *connector)
 102 {
 103         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 104         struct amdgpu_connector_atom_dig *dig_connector;
 105         int bpc = 8;
 106         unsigned mode_clock, max_tmds_clock;
 107
 108         switch (connector->connector_type) {
 109         case DRM_MODE_CONNECTOR_DVII:
 110         case DRM_MODE_CONNECTOR_HDMIB:
 111                 if (amdgpu_connector->use_digital) {
 112                         if (connector->display_info.is_hdmi) {
 113                                 if (connector->display_info.bpc)
 114                                         bpc = connector->display_info.bpc;
 115                         }
 116                 }
 117                 break;
 118         case DRM_MODE_CONNECTOR_DVID:
 119         case DRM_MODE_CONNECTOR_HDMIA:
 120                 if (connector->display_info.is_hdmi) {
 121                         if (connector->display_info.bpc)
 122                                 bpc = connector->display_info.bpc;
 123                 }
 124                 break;
 125         case DRM_MODE_CONNECTOR_DisplayPort:
 126                 dig_connector = amdgpu_connector->con_priv;
 127                 if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
 128                     (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) ||
 129                     connector->display_info.is_hdmi) {
 130                         if (connector->display_info.bpc)
 131                                 bpc = connector->display_info.bpc;
 132                 }
 133                 break;
 134         case DRM_MODE_CONNECTOR_eDP:
 135         case DRM_MODE_CONNECTOR_LVDS:
 136                 if (connector->display_info.bpc)
 137                         bpc = connector->display_info.bpc;
 138                 else {
 139                         const struct drm_connector_helper_funcs *connector_funcs =
 140                                 connector->helper_private;
 141                         struct drm_encoder *encoder = connector_funcs->best_encoder(connector);
 142                         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
 143                         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
 144
 145                         if (dig->lcd_misc & ATOM_PANEL_MISC_V13_6BIT_PER_COLOR)
 146                                 bpc = 6;
 147                         else if (dig->lcd_misc & ATOM_PANEL_MISC_V13_8BIT_PER_COLOR)
 148                                 bpc = 8;
 149                 }
 150                 break;
 151         }
 152
 153         if (connector->display_info.is_hdmi) {
 154                 /*
 155                  * Pre DCE-8 hw can't handle > 12 bpc, and more than 12 bpc doesn't make
 156                  * much sense without support for > 12 bpc framebuffers. RGB 4:4:4 at
 157                  * 12 bpc is always supported on hdmi deep color sinks, as this is
 158                  * required by the HDMI-1.3 spec. Clamp to a safe 12 bpc maximum.
 159                  */
 160                 if (bpc > 12) {
 161                         DRM_DEBUG("%s: HDMI deep color %d bpc unsupported. Using 12 bpc.\n",
 162                                   connector->name, bpc);
 163                         bpc = 12;
 164                 }
 165
 166                 /* Any defined maximum tmds clock limit we must not exceed? */
 167                 if (connector->display_info.max_tmds_clock > 0) {
 168                         /* mode_clock is clock in kHz for mode to be modeset on this connector */
 169                         mode_clock = amdgpu_connector->pixelclock_for_modeset;
 170
 171                         /* Maximum allowable input clock in kHz */
 172                         max_tmds_clock = connector->display_info.max_tmds_clock;
 173
 174                         DRM_DEBUG("%s: hdmi mode dotclock %d kHz, max tmds input clock %d kHz.\n",
 175                                   connector->name, mode_clock, max_tmds_clock);
 176
 177                         /* Check if bpc is within clock limit. Try to degrade gracefully otherwise */
 178                         if ((bpc == 12) && (mode_clock * 3/2 > max_tmds_clock)) {
 179                                 if ((connector->display_info.edid_hdmi_rgb444_dc_modes & DRM_EDID_HDMI_DC_30) &&
 180                                     (mode_clock * 5/4 <= max_tmds_clock))
 181                                         bpc = 10;
 182                                 else
 183                                         bpc = 8;
 184
 185                                 DRM_DEBUG("%s: HDMI deep color 12 bpc exceeds max tmds clock. Using %d bpc.\n",
 186                                           connector->name, bpc);
 187                         }
 188
 189                         if ((bpc == 10) && (mode_clock * 5/4 > max_tmds_clock)) {
 190                                 bpc = 8;
 191                                 DRM_DEBUG("%s: HDMI deep color 10 bpc exceeds max tmds clock. Using %d bpc.\n",
 192                                           connector->name, bpc);
 193                         }
 194                 } else if (bpc > 8) {
 195                         /* max_tmds_clock missing, but hdmi spec mandates it for deep color. */
 196                         DRM_DEBUG("%s: Required max tmds clock for HDMI deep color missing. Using 8 bpc.\n",
 197                                   connector->name);
 198                         bpc = 8;
 199                 }
 200         }
 201
 202         if ((amdgpu_deep_color == 0) && (bpc > 8)) {
 203                 DRM_DEBUG("%s: Deep color disabled. Set amdgpu module param deep_color=1 to enable.\n",
 204                           connector->name);
 205                 bpc = 8;
 206         }
 207
 208         DRM_DEBUG("%s: Display bpc=%d, returned bpc=%d\n",
 209                   connector->name, connector->display_info.bpc, bpc);
 210
 211         return bpc;
 212 }
 213
 214 static void
 215 amdgpu_connector_update_scratch_regs(struct drm_connector *connector,
 216                                       enum drm_connector_status status)
 217 {
 218         struct drm_encoder *best_encoder;
 219         struct drm_encoder *encoder;
 220         const struct drm_connector_helper_funcs *connector_funcs = connector->helper_private;
 221         bool connected;
 222
 223         best_encoder = connector_funcs->best_encoder(connector);
 224
 225         drm_connector_for_each_possible_encoder(connector, encoder) {
 226                 if ((encoder == best_encoder) && (status == connector_status_connected))
 227                         connected = true;
 228                 else
 229                         connected = false;
 230
 231                 amdgpu_atombios_encoder_set_bios_scratch_regs(connector, encoder, connected);
 232         }
 233 }
 234
 235 static struct drm_encoder *
 236 amdgpu_connector_find_encoder(struct drm_connector *connector,
 237                                int encoder_type)
 238 {
 239         struct drm_encoder *encoder;
 240
 241         drm_connector_for_each_possible_encoder(connector, encoder) {
 242                 if (encoder->encoder_type == encoder_type)
 243                         return encoder;
 244         }
 245
 246         return NULL;
 247 }
 248
 249 struct edid *amdgpu_connector_edid(struct drm_connector *connector)
 250 {
 251         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 252         struct drm_property_blob *edid_blob = connector->edid_blob_ptr;
 253
 254         if (amdgpu_connector->edid) {
 255                 return amdgpu_connector->edid;
 256         } else if (edid_blob) {
 257                 struct edid *edid = kmemdup(edid_blob->data, edid_blob->length, GFP_KERNEL);
 258                 if (edid)
 259                         amdgpu_connector->edid = edid;
 260         }
 261         return amdgpu_connector->edid;
 262 }
 263
 264 static struct edid *
 265 amdgpu_connector_get_hardcoded_edid(struct amdgpu_device *adev)
 266 {
 267         struct edid *edid;
 268
 269         if (adev->mode_info.bios_hardcoded_edid) {
 270                 edid = kmalloc(adev->mode_info.bios_hardcoded_edid_size, GFP_KERNEL);
 271                 if (edid) {
 272                         memcpy((unsigned char *)edid,
 273                                (unsigned char *)adev->mode_info.bios_hardcoded_edid,
 274                                adev->mode_info.bios_hardcoded_edid_size);
 275                         return edid;
 276                 }
 277         }
 278         return NULL;
 279 }
 280
 281 static void amdgpu_connector_get_edid(struct drm_connector *connector)
 282 {
 283         struct drm_device *dev = connector->dev;
 284         struct amdgpu_device *adev = drm_to_adev(dev);
 285         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 286
 287         if (amdgpu_connector->edid)
 288                 return;
 289
 290         /* on hw with routers, select right port */
 291         if (amdgpu_connector->router.ddc_valid)
 292                 amdgpu_i2c_router_select_ddc_port(amdgpu_connector);
 293
 294         if ((amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) !=
 295              ENCODER_OBJECT_ID_NONE) &&
 296             amdgpu_connector->ddc_bus->has_aux) {
 297                 amdgpu_connector->edid = drm_get_edid(connector,
 298                                                       &amdgpu_connector->ddc_bus->aux.ddc);
 299         } else if ((connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) ||
 300                    (connector->connector_type == DRM_MODE_CONNECTOR_eDP)) {
 301                 struct amdgpu_connector_atom_dig *dig = amdgpu_connector->con_priv;
 302
 303                 if ((dig->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT ||
 304                      dig->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) &&
 305                     amdgpu_connector->ddc_bus->has_aux)
 306                         amdgpu_connector->edid = drm_get_edid(connector,
 307                                                               &amdgpu_connector->ddc_bus->aux.ddc);
 308                 else if (amdgpu_connector->ddc_bus)
 309                         amdgpu_connector->edid = drm_get_edid(connector,
 310                                                               &amdgpu_connector->ddc_bus->adapter);
 311         } else if (amdgpu_connector->ddc_bus) {
 312                 amdgpu_connector->edid = drm_get_edid(connector,
 313                                                       &amdgpu_connector->ddc_bus->adapter);
 314         }
 315
 316         if (!amdgpu_connector->edid) {
 317                 /* some laptops provide a hardcoded edid in rom for LCDs */
 318                 if (((connector->connector_type == DRM_MODE_CONNECTOR_LVDS) ||
 319                      (connector->connector_type == DRM_MODE_CONNECTOR_eDP))) {
 320                         amdgpu_connector->edid = amdgpu_connector_get_hardcoded_edid(adev);
 321                         drm_connector_update_edid_property(connector, amdgpu_connector->edid);
 322                 }
 323         }
 324 }
 325
 326 static void amdgpu_connector_free_edid(struct drm_connector *connector)
 327 {
 328         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 329
 330         kfree(amdgpu_connector->edid);
 331         amdgpu_connector->edid = NULL;
 332 }
 333
 334 static int amdgpu_connector_ddc_get_modes(struct drm_connector *connector)
 335 {
 336         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 337         int ret;
 338
 339         if (amdgpu_connector->edid) {
 340                 drm_connector_update_edid_property(connector, amdgpu_connector->edid);
 341                 ret = drm_add_edid_modes(connector, amdgpu_connector->edid);
 342                 return ret;
 343         }
 344         drm_connector_update_edid_property(connector, NULL);
 345         return 0;
 346 }
 347
 348 static struct drm_encoder *
 349 amdgpu_connector_best_single_encoder(struct drm_connector *connector)
 350 {
 351         struct drm_encoder *encoder;
 352
 353         /* pick the first one */
 354         drm_connector_for_each_possible_encoder(connector, encoder)
 355                 return encoder;
 356
 357         return NULL;
 358 }
 359
 360 static void amdgpu_get_native_mode(struct drm_connector *connector)
 361 {
 362         struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector);
 363         struct amdgpu_encoder *amdgpu_encoder;
 364
 365         if (encoder == NULL)
 366                 return;
 367
 368         amdgpu_encoder = to_amdgpu_encoder(encoder);
 369
 370         if (!list_empty(&connector->probed_modes)) {
 371                 struct drm_display_mode *preferred_mode =
 372                         list_first_entry(&connector->probed_modes,
 373                                          struct drm_display_mode, head);
 374
 375                 amdgpu_encoder->native_mode = *preferred_mode;
 376         } else {
 377                 amdgpu_encoder->native_mode.clock = 0;
 378         }
 379 }
 380
 381 static struct drm_display_mode *
 382 amdgpu_connector_lcd_native_mode(struct drm_encoder *encoder)
 383 {
 384         struct drm_device *dev = encoder->dev;
 385         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
 386         struct drm_display_mode *mode = NULL;
 387         struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
 388
 389         if (native_mode->hdisplay != 0 &&
 390             native_mode->vdisplay != 0 &&
 391             native_mode->clock != 0) {
 392                 mode = drm_mode_duplicate(dev, native_mode);
 393                 if (!mode)
 394                         return NULL;
 395
 396                 mode->type = DRM_MODE_TYPE_PREFERRED | DRM_MODE_TYPE_DRIVER;
 397                 drm_mode_set_name(mode);
 398
 399                 DRM_DEBUG_KMS("Adding native panel mode %s\n", mode->name);
 400         } else if (native_mode->hdisplay != 0 &&
 401                    native_mode->vdisplay != 0) {
 402                 /* mac laptops without an edid */
 403                 /* Note that this is not necessarily the exact panel mode,
 404                  * but an approximation based on the cvt formula.  For these
 405                  * systems we should ideally read the mode info out of the
 406                  * registers or add a mode table, but this works and is much
 407                  * simpler.
 408                  */
 409                 mode = drm_cvt_mode(dev, native_mode->hdisplay, native_mode->vdisplay, 60, true, false, false);
 410                 if (!mode)
 411                         return NULL;
 412
 413                 mode->type = DRM_MODE_TYPE_PREFERRED | DRM_MODE_TYPE_DRIVER;
 414                 DRM_DEBUG_KMS("Adding cvt approximation of native panel mode %s\n", mode->name);
 415         }
 416         return mode;
 417 }
 418
 419 static void amdgpu_connector_add_common_modes(struct drm_encoder *encoder,
 420                                                struct drm_connector *connector)
 421 {
 422         struct drm_device *dev = encoder->dev;
 423         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
 424         struct drm_display_mode *mode = NULL;
 425         struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
 426         int i;
 427         static const struct mode_size {
 428                 int w;
 429                 int h;
 430         } common_modes[17] = {
 431                 { 640,  480},
 432                 { 720,  480},
 433                 { 800,  600},
 434                 { 848,  480},
 435                 {1024,  768},
 436                 {1152,  768},
 437                 {1280,  720},
 438                 {1280,  800},
 439                 {1280,  854},
 440                 {1280,  960},
 441                 {1280, 1024},
 442                 {1440,  900},
 443                 {1400, 1050},
 444                 {1680, 1050},
 445                 {1600, 1200},
 446                 {1920, 1080},
 447                 {1920, 1200}
 448         };
 449
 450         for (i = 0; i < 17; i++) {
 451                 if (amdgpu_encoder->devices & (ATOM_DEVICE_TV_SUPPORT)) {
 452                         if (common_modes[i].w > 1024 ||
 453                             common_modes[i].h > 768)
 454                                 continue;
 455                 }
 456                 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
 457                         if (common_modes[i].w > native_mode->hdisplay ||
 458                             common_modes[i].h > native_mode->vdisplay ||
 459                             (common_modes[i].w == native_mode->hdisplay &&
 460                              common_modes[i].h == native_mode->vdisplay))
 461                                 continue;
 462                 }
 463                 if (common_modes[i].w < 320 || common_modes[i].h < 200)
 464                         continue;
 465
 466                 mode = drm_cvt_mode(dev, common_modes[i].w, common_modes[i].h, 60, false, false, false);
 467                 drm_mode_probed_add(connector, mode);
 468         }
 469 }
 470
 471 static int amdgpu_connector_set_property(struct drm_connector *connector,
 472                                           struct drm_property *property,
 473                                           uint64_t val)
 474 {
 475         struct drm_device *dev = connector->dev;
 476         struct amdgpu_device *adev = drm_to_adev(dev);
 477         struct drm_encoder *encoder;
 478         struct amdgpu_encoder *amdgpu_encoder;
 479
 480         if (property == adev->mode_info.coherent_mode_property) {
 481                 struct amdgpu_encoder_atom_dig *dig;
 482                 bool new_coherent_mode;
 483
 484                 /* need to find digital encoder on connector */
 485                 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS);
 486                 if (!encoder)
 487                         return 0;
 488
 489                 amdgpu_encoder = to_amdgpu_encoder(encoder);
 490
 491                 if (!amdgpu_encoder->enc_priv)
 492                         return 0;
 493
 494                 dig = amdgpu_encoder->enc_priv;
 495                 new_coherent_mode = val ? true : false;
 496                 if (dig->coherent_mode != new_coherent_mode) {
 497                         dig->coherent_mode = new_coherent_mode;
 498                         amdgpu_connector_property_change_mode(&amdgpu_encoder->base);
 499                 }
 500         }
 501
 502         if (property == adev->mode_info.audio_property) {
 503                 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 504                 /* need to find digital encoder on connector */
 505                 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS);
 506                 if (!encoder)
 507                         return 0;
 508
 509                 amdgpu_encoder = to_amdgpu_encoder(encoder);
 510
 511                 if (amdgpu_connector->audio != val) {
 512                         amdgpu_connector->audio = val;
 513                         amdgpu_connector_property_change_mode(&amdgpu_encoder->base);
 514                 }
 515         }
 516
 517         if (property == adev->mode_info.dither_property) {
 518                 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 519                 /* need to find digital encoder on connector */
 520                 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS);
 521                 if (!encoder)
 522                         return 0;
 523
 524                 amdgpu_encoder = to_amdgpu_encoder(encoder);
 525
 526                 if (amdgpu_connector->dither != val) {
 527                         amdgpu_connector->dither = val;
 528                         amdgpu_connector_property_change_mode(&amdgpu_encoder->base);
 529                 }
 530         }
 531
 532         if (property == adev->mode_info.underscan_property) {
 533                 /* need to find digital encoder on connector */
 534                 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS);
 535                 if (!encoder)
 536                         return 0;
 537
 538                 amdgpu_encoder = to_amdgpu_encoder(encoder);
 539
 540                 if (amdgpu_encoder->underscan_type != val) {
 541                         amdgpu_encoder->underscan_type = val;
 542                         amdgpu_connector_property_change_mode(&amdgpu_encoder->base);
 543                 }
 544         }
 545
 546         if (property == adev->mode_info.underscan_hborder_property) {
 547                 /* need to find digital encoder on connector */
 548                 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS);
 549                 if (!encoder)
 550                         return 0;
 551
 552                 amdgpu_encoder = to_amdgpu_encoder(encoder);
 553
 554                 if (amdgpu_encoder->underscan_hborder != val) {
 555                         amdgpu_encoder->underscan_hborder = val;
 556                         amdgpu_connector_property_change_mode(&amdgpu_encoder->base);
 557                 }
 558         }
 559
 560         if (property == adev->mode_info.underscan_vborder_property) {
 561                 /* need to find digital encoder on connector */
 562                 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS);
 563                 if (!encoder)
 564                         return 0;
 565
 566                 amdgpu_encoder = to_amdgpu_encoder(encoder);
 567
 568                 if (amdgpu_encoder->underscan_vborder != val) {
 569                         amdgpu_encoder->underscan_vborder = val;
 570                         amdgpu_connector_property_change_mode(&amdgpu_encoder->base);
 571                 }
 572         }
 573
 574         if (property == adev->mode_info.load_detect_property) {
 575                 struct amdgpu_connector *amdgpu_connector =
 576                         to_amdgpu_connector(connector);
 577
 578                 if (val == 0)
 579                         amdgpu_connector->dac_load_detect = false;
 580                 else
 581                         amdgpu_connector->dac_load_detect = true;
 582         }
 583
 584         if (property == dev->mode_config.scaling_mode_property) {
 585                 enum amdgpu_rmx_type rmx_type;
 586
 587                 if (connector->encoder) {
 588                         amdgpu_encoder = to_amdgpu_encoder(connector->encoder);
 589                 } else {
 590                         const struct drm_connector_helper_funcs *connector_funcs = connector->helper_private;
 591                         amdgpu_encoder = to_amdgpu_encoder(connector_funcs->best_encoder(connector));
 592                 }
 593
 594                 switch (val) {
 595                 default:
 596                 case DRM_MODE_SCALE_NONE: rmx_type = RMX_OFF; break;
 597                 case DRM_MODE_SCALE_CENTER: rmx_type = RMX_CENTER; break;
 598                 case DRM_MODE_SCALE_ASPECT: rmx_type = RMX_ASPECT; break;
 599                 case DRM_MODE_SCALE_FULLSCREEN: rmx_type = RMX_FULL; break;
 600                 }
 601                 if (amdgpu_encoder->rmx_type == rmx_type)
 602                         return 0;
 603
 604                 if ((rmx_type != DRM_MODE_SCALE_NONE) &&
 605                     (amdgpu_encoder->native_mode.clock == 0))
 606                         return 0;
 607
 608                 amdgpu_encoder->rmx_type = rmx_type;
 609
 610                 amdgpu_connector_property_change_mode(&amdgpu_encoder->base);
 611         }
 612
 613         return 0;
 614 }
 615
 616 static void
 617 amdgpu_connector_fixup_lcd_native_mode(struct drm_encoder *encoder,
 618                                         struct drm_connector *connector)
 619 {
 620         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
 621         struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
 622         struct drm_display_mode *t, *mode;
 623
 624         /* If the EDID preferred mode doesn't match the native mode, use it */
 625         list_for_each_entry_safe(mode, t, &connector->probed_modes, head) {
 626                 if (mode->type & DRM_MODE_TYPE_PREFERRED) {
 627                         if (mode->hdisplay != native_mode->hdisplay ||
 628                             mode->vdisplay != native_mode->vdisplay)
 629                                 drm_mode_copy(native_mode, mode);
 630                 }
 631         }
 632
 633         /* Try to get native mode details from EDID if necessary */
 634         if (!native_mode->clock) {
 635                 list_for_each_entry_safe(mode, t, &connector->probed_modes, head) {
 636                         if (mode->hdisplay == native_mode->hdisplay &&
 637                             mode->vdisplay == native_mode->vdisplay) {
 638                                 drm_mode_copy(native_mode, mode);
 639                                 drm_mode_set_crtcinfo(native_mode, CRTC_INTERLACE_HALVE_V);
 640                                 DRM_DEBUG_KMS("Determined LVDS native mode details from EDID\n");
 641                                 break;
 642                         }
 643                 }
 644         }
 645
 646         if (!native_mode->clock) {
 647                 DRM_DEBUG_KMS("No LVDS native mode details, disabling RMX\n");
 648                 amdgpu_encoder->rmx_type = RMX_OFF;
 649         }
 650 }
 651
 652 static int amdgpu_connector_lvds_get_modes(struct drm_connector *connector)
 653 {
 654         struct drm_encoder *encoder;
 655         int ret = 0;
 656         struct drm_display_mode *mode;
 657
 658         amdgpu_connector_get_edid(connector);
 659         ret = amdgpu_connector_ddc_get_modes(connector);
 660         if (ret > 0) {
 661                 encoder = amdgpu_connector_best_single_encoder(connector);
 662                 if (encoder) {
 663                         amdgpu_connector_fixup_lcd_native_mode(encoder, connector);
 664                         /* add scaled modes */
 665                         amdgpu_connector_add_common_modes(encoder, connector);
 666                 }
 667                 return ret;
 668         }
 669
 670         encoder = amdgpu_connector_best_single_encoder(connector);
 671         if (!encoder)
 672                 return 0;
 673
 674         /* we have no EDID modes */
 675         mode = amdgpu_connector_lcd_native_mode(encoder);
 676         if (mode) {
 677                 ret = 1;
 678                 drm_mode_probed_add(connector, mode);
 679                 /* add the width/height from vbios tables if available */
 680                 connector->display_info.width_mm = mode->width_mm;
 681                 connector->display_info.height_mm = mode->height_mm;
 682                 /* add scaled modes */
 683                 amdgpu_connector_add_common_modes(encoder, connector);
 684         }
 685
 686         return ret;
 687 }
 688
 689 static enum drm_mode_status amdgpu_connector_lvds_mode_valid(struct drm_connector *connector,
 690                                              struct drm_display_mode *mode)
 691 {
 692         struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector);
 693
 694         if ((mode->hdisplay < 320) || (mode->vdisplay < 240))
 695                 return MODE_PANEL;
 696
 697         if (encoder) {
 698                 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
 699                 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
 700
 701                 /* AVIVO hardware supports downscaling modes larger than the panel
 702                  * to the panel size, but I'm not sure this is desirable.
 703                  */
 704                 if ((mode->hdisplay > native_mode->hdisplay) ||
 705                     (mode->vdisplay > native_mode->vdisplay))
 706                         return MODE_PANEL;
 707
 708                 /* if scaling is disabled, block non-native modes */
 709                 if (amdgpu_encoder->rmx_type == RMX_OFF) {
 710                         if ((mode->hdisplay != native_mode->hdisplay) ||
 711                             (mode->vdisplay != native_mode->vdisplay))
 712                                 return MODE_PANEL;
 713                 }
 714         }
 715
 716         return MODE_OK;
 717 }
 718
 719 static enum drm_connector_status
 720 amdgpu_connector_lvds_detect(struct drm_connector *connector, bool force)
 721 {
 722         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 723         struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector);
 724         enum drm_connector_status ret = connector_status_disconnected;
 725         int r;
 726
 727         if (!drm_kms_helper_is_poll_worker()) {
 728                 r = pm_runtime_get_sync(connector->dev->dev);
 729                 if (r < 0) {
 730                         pm_runtime_put_autosuspend(connector->dev->dev);
 731                         return connector_status_disconnected;
 732                 }
 733         }
 734
 735         if (encoder) {
 736                 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
 737                 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
 738
 739                 /* check if panel is valid */
 740                 if (native_mode->hdisplay >= 320 && native_mode->vdisplay >= 240)
 741                         ret = connector_status_connected;
 742
 743         }
 744
 745         /* check for edid as well */
 746         amdgpu_connector_get_edid(connector);
 747         if (amdgpu_connector->edid)
 748                 ret = connector_status_connected;
 749         /* check acpi lid status ??? */
 750
 751         amdgpu_connector_update_scratch_regs(connector, ret);
 752
 753         if (!drm_kms_helper_is_poll_worker()) {
 754                 pm_runtime_mark_last_busy(connector->dev->dev);
 755                 pm_runtime_put_autosuspend(connector->dev->dev);
 756         }
 757
 758         return ret;
 759 }
 760
 761 static void amdgpu_connector_unregister(struct drm_connector *connector)
 762 {
 763         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 764
 765         if (amdgpu_connector->ddc_bus && amdgpu_connector->ddc_bus->has_aux) {
 766                 drm_dp_aux_unregister(&amdgpu_connector->ddc_bus->aux);
 767                 amdgpu_connector->ddc_bus->has_aux = false;
 768         }
 769 }
 770
 771 static void amdgpu_connector_destroy(struct drm_connector *connector)
 772 {
 773         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 774
 775         amdgpu_connector_free_edid(connector);
 776         kfree(amdgpu_connector->con_priv);
 777         drm_connector_unregister(connector);
 778         drm_connector_cleanup(connector);
 779         kfree(connector);
 780 }
 781
 782 static int amdgpu_connector_set_lcd_property(struct drm_connector *connector,
 783                                               struct drm_property *property,
 784                                               uint64_t value)
 785 {
 786         struct drm_device *dev = connector->dev;
 787         struct amdgpu_encoder *amdgpu_encoder;
 788         enum amdgpu_rmx_type rmx_type;
 789
 790         DRM_DEBUG_KMS("\n");
 791         if (property != dev->mode_config.scaling_mode_property)
 792                 return 0;
 793
 794         if (connector->encoder)
 795                 amdgpu_encoder = to_amdgpu_encoder(connector->encoder);
 796         else {
 797                 const struct drm_connector_helper_funcs *connector_funcs = connector->helper_private;
 798                 amdgpu_encoder = to_amdgpu_encoder(connector_funcs->best_encoder(connector));
 799         }
 800
 801         switch (value) {
 802         case DRM_MODE_SCALE_NONE: rmx_type = RMX_OFF; break;
 803         case DRM_MODE_SCALE_CENTER: rmx_type = RMX_CENTER; break;
 804         case DRM_MODE_SCALE_ASPECT: rmx_type = RMX_ASPECT; break;
 805         default:
 806         case DRM_MODE_SCALE_FULLSCREEN: rmx_type = RMX_FULL; break;
 807         }
 808         if (amdgpu_encoder->rmx_type == rmx_type)
 809                 return 0;
 810
 811         amdgpu_encoder->rmx_type = rmx_type;
 812
 813         amdgpu_connector_property_change_mode(&amdgpu_encoder->base);
 814         return 0;
 815 }
 816
 817
 818 static const struct drm_connector_helper_funcs amdgpu_connector_lvds_helper_funcs = {
 819         .get_modes = amdgpu_connector_lvds_get_modes,
 820         .mode_valid = amdgpu_connector_lvds_mode_valid,
 821         .best_encoder = amdgpu_connector_best_single_encoder,
 822 };
 823
 824 static const struct drm_connector_funcs amdgpu_connector_lvds_funcs = {
 825         .dpms = drm_helper_connector_dpms,
 826         .detect = amdgpu_connector_lvds_detect,
 827         .fill_modes = drm_helper_probe_single_connector_modes,
 828         .early_unregister = amdgpu_connector_unregister,
 829         .destroy = amdgpu_connector_destroy,
 830         .set_property = amdgpu_connector_set_lcd_property,
 831 };
 832
 833 static int amdgpu_connector_vga_get_modes(struct drm_connector *connector)
 834 {
 835         int ret;
 836
 837         amdgpu_connector_get_edid(connector);
 838         ret = amdgpu_connector_ddc_get_modes(connector);
 839         amdgpu_get_native_mode(connector);
 840
 841         return ret;
 842 }
 843
 844 static enum drm_mode_status amdgpu_connector_vga_mode_valid(struct drm_connector *connector,
 845                                             struct drm_display_mode *mode)
 846 {
 847         struct drm_device *dev = connector->dev;
 848         struct amdgpu_device *adev = drm_to_adev(dev);
 849
 850         /* XXX check mode bandwidth */
 851
 852         if ((mode->clock / 10) > adev->clock.max_pixel_clock)
 853                 return MODE_CLOCK_HIGH;
 854
 855         return MODE_OK;
 856 }
 857
 858 static enum drm_connector_status
 859 amdgpu_connector_vga_detect(struct drm_connector *connector, bool force)
 860 {
 861         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 862         struct drm_encoder *encoder;
 863         const struct drm_encoder_helper_funcs *encoder_funcs;
 864         bool dret = false;
 865         enum drm_connector_status ret = connector_status_disconnected;
 866         int r;
 867
 868         if (!drm_kms_helper_is_poll_worker()) {
 869                 r = pm_runtime_get_sync(connector->dev->dev);
 870                 if (r < 0) {
 871                         pm_runtime_put_autosuspend(connector->dev->dev);
 872                         return connector_status_disconnected;
 873                 }
 874         }
 875
 876         encoder = amdgpu_connector_best_single_encoder(connector);
 877         if (!encoder)
 878                 ret = connector_status_disconnected;
 879
 880         if (amdgpu_connector->ddc_bus)
 881                 dret = amdgpu_display_ddc_probe(amdgpu_connector, false);
 882         if (dret) {
 883                 amdgpu_connector->detected_by_load = false;
 884                 amdgpu_connector_free_edid(connector);
 885                 amdgpu_connector_get_edid(connector);
 886
 887                 if (!amdgpu_connector->edid) {
 888                         DRM_ERROR("%s: probed a monitor but no|invalid EDID\n",
 889                                         connector->name);
 890                         ret = connector_status_connected;
 891                 } else {
 892                         amdgpu_connector->use_digital =
 893                                 !!(amdgpu_connector->edid->input & DRM_EDID_INPUT_DIGITAL);
 894
 895                         /* some oems have boards with separate digital and analog connectors
 896                          * with a shared ddc line (often vga + hdmi)
 897                          */
 898                         if (amdgpu_connector->use_digital && amdgpu_connector->shared_ddc) {
 899                                 amdgpu_connector_free_edid(connector);
 900                                 ret = connector_status_disconnected;
 901                         } else {
 902                                 ret = connector_status_connected;
 903                         }
 904                 }
 905         } else {
 906
 907                 /* if we aren't forcing don't do destructive polling */
 908                 if (!force) {
 909                         /* only return the previous status if we last
 910                          * detected a monitor via load.
 911                          */
 912                         if (amdgpu_connector->detected_by_load)
 913                                 ret = connector->status;
 914                         goto out;
 915                 }
 916
 917                 if (amdgpu_connector->dac_load_detect && encoder) {
 918                         encoder_funcs = encoder->helper_private;
 919                         ret = encoder_funcs->detect(encoder, connector);
 920                         if (ret != connector_status_disconnected)
 921                                 amdgpu_connector->detected_by_load = true;
 922                 }
 923         }
 924
 925         amdgpu_connector_update_scratch_regs(connector, ret);
 926
 927 out:
 928         if (!drm_kms_helper_is_poll_worker()) {
 929                 pm_runtime_mark_last_busy(connector->dev->dev);
 930                 pm_runtime_put_autosuspend(connector->dev->dev);
 931         }
 932
 933         return ret;
 934 }
 935
 936 static const struct drm_connector_helper_funcs amdgpu_connector_vga_helper_funcs = {
 937         .get_modes = amdgpu_connector_vga_get_modes,
 938         .mode_valid = amdgpu_connector_vga_mode_valid,
 939         .best_encoder = amdgpu_connector_best_single_encoder,
 940 };
 941
 942 static const struct drm_connector_funcs amdgpu_connector_vga_funcs = {
 943         .dpms = drm_helper_connector_dpms,
 944         .detect = amdgpu_connector_vga_detect,
 945         .fill_modes = drm_helper_probe_single_connector_modes,
 946         .early_unregister = amdgpu_connector_unregister,
 947         .destroy = amdgpu_connector_destroy,
 948         .set_property = amdgpu_connector_set_property,
 949 };
 950
 951 static bool
 952 amdgpu_connector_check_hpd_status_unchanged(struct drm_connector *connector)
 953 {
 954         struct drm_device *dev = connector->dev;
 955         struct amdgpu_device *adev = drm_to_adev(dev);
 956         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 957         enum drm_connector_status status;
 958
 959         if (amdgpu_connector->hpd.hpd != AMDGPU_HPD_NONE) {
 960                 if (amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd))
 961                         status = connector_status_connected;
 962                 else
 963                         status = connector_status_disconnected;
 964                 if (connector->status == status)
 965                         return true;
 966         }
 967
 968         return false;
 969 }
 970
 971 /*
 972  * DVI is complicated
 973  * Do a DDC probe, if DDC probe passes, get the full EDID so
 974  * we can do analog/digital monitor detection at this point.
 975  * If the monitor is an analog monitor or we got no DDC,
 976  * we need to find the DAC encoder object for this connector.
 977  * If we got no DDC, we do load detection on the DAC encoder object.
 978  * If we got analog DDC or load detection passes on the DAC encoder
 979  * we have to check if this analog encoder is shared with anyone else (TV)
 980  * if its shared we have to set the other connector to disconnected.
 981  */
 982 static enum drm_connector_status
 983 amdgpu_connector_dvi_detect(struct drm_connector *connector, bool force)
 984 {
 985         struct drm_device *dev = connector->dev;
 986         struct amdgpu_device *adev = drm_to_adev(dev);
 987         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 988         const struct drm_encoder_helper_funcs *encoder_funcs;
 989         int r;
 990         enum drm_connector_status ret = connector_status_disconnected;
 991         bool dret = false, broken_edid = false;
 992
 993         if (!drm_kms_helper_is_poll_worker()) {
 994                 r = pm_runtime_get_sync(connector->dev->dev);
 995                 if (r < 0) {
 996                         pm_runtime_put_autosuspend(connector->dev->dev);
 997                         return connector_status_disconnected;
 998                 }
 999         }
1000
1001         if (amdgpu_connector->detected_hpd_without_ddc) {
1002                 force = true;
1003                 amdgpu_connector->detected_hpd_without_ddc = false;
1004         }
1005
1006         if (!force && amdgpu_connector_check_hpd_status_unchanged(connector)) {
1007                 ret = connector->status;
1008                 goto exit;
1009         }
1010
1011         if (amdgpu_connector->ddc_bus) {
1012                 dret = amdgpu_display_ddc_probe(amdgpu_connector, false);
1013
1014                 /* Sometimes the pins required for the DDC probe on DVI
1015                  * connectors don't make contact at the same time that the ones
1016                  * for HPD do. If the DDC probe fails even though we had an HPD
1017                  * signal, try again later
1018                  */
1019                 if (!dret && !force &&
1020                     amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd)) {
1021                         DRM_DEBUG_KMS("hpd detected without ddc, retrying in 1 second\n");
1022                         amdgpu_connector->detected_hpd_without_ddc = true;
1023                         schedule_delayed_work(&adev->hotplug_work,
1024                                               msecs_to_jiffies(1000));
1025                         goto exit;
1026                 }
1027         }
1028         if (dret) {
1029                 amdgpu_connector->detected_by_load = false;
1030                 amdgpu_connector_free_edid(connector);
1031                 amdgpu_connector_get_edid(connector);
1032
1033                 if (!amdgpu_connector->edid) {
1034                         DRM_ERROR("%s: probed a monitor but no|invalid EDID\n",
1035                                         connector->name);
1036                         ret = connector_status_connected;
1037                         broken_edid = true; /* defer use_digital to later */
1038                 } else {
1039                         amdgpu_connector->use_digital =
1040                                 !!(amdgpu_connector->edid->input & DRM_EDID_INPUT_DIGITAL);
1041
1042                         /* some oems have boards with separate digital and analog connectors
1043                          * with a shared ddc line (often vga + hdmi)
1044                          */
1045                         if ((!amdgpu_connector->use_digital) && amdgpu_connector->shared_ddc) {
1046                                 amdgpu_connector_free_edid(connector);
1047                                 ret = connector_status_disconnected;
1048                         } else {
1049                                 ret = connector_status_connected;
1050                         }
1051
1052                         /* This gets complicated.  We have boards with VGA + HDMI with a
1053                          * shared DDC line and we have boards with DVI-D + HDMI with a shared
1054                          * DDC line.  The latter is more complex because with DVI<->HDMI adapters
1055                          * you don't really know what's connected to which port as both are digital.
1056                          */
1057                         if (amdgpu_connector->shared_ddc && (ret == connector_status_connected)) {
1058                                 struct drm_connector *list_connector;
1059                                 struct drm_connector_list_iter iter;
1060                                 struct amdgpu_connector *list_amdgpu_connector;
1061
1062                                 drm_connector_list_iter_begin(dev, &iter);
1063                                 drm_for_each_connector_iter(list_connector,
1064                                                             &iter) {
1065                                         if (connector == list_connector)
1066                                                 continue;
1067                                         list_amdgpu_connector = to_amdgpu_connector(list_connector);
1068                                         if (list_amdgpu_connector->shared_ddc &&
1069                                             (list_amdgpu_connector->ddc_bus->rec.i2c_id ==
1070                                              amdgpu_connector->ddc_bus->rec.i2c_id)) {
1071                                                 /* cases where both connectors are digital */
1072                                                 if (list_connector->connector_type != DRM_MODE_CONNECTOR_VGA) {
1073                                                         /* hpd is our only option in this case */
1074                                                         if (!amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd)) {
1075                                                                 amdgpu_connector_free_edid(connector);
1076                                                                 ret = connector_status_disconnected;
1077                                                         }
1078                                                 }
1079                                         }
1080                                 }
1081                                 drm_connector_list_iter_end(&iter);
1082                         }
1083                 }
1084         }
1085
1086         if ((ret == connector_status_connected) && (amdgpu_connector->use_digital == true))
1087                 goto out;
1088
1089         /* DVI-D and HDMI-A are digital only */
1090         if ((connector->connector_type == DRM_MODE_CONNECTOR_DVID) ||
1091             (connector->connector_type == DRM_MODE_CONNECTOR_HDMIA))
1092                 goto out;
1093
1094         /* if we aren't forcing don't do destructive polling */
1095         if (!force) {
1096                 /* only return the previous status if we last
1097                  * detected a monitor via load.
1098                  */
1099                 if (amdgpu_connector->detected_by_load)
1100                         ret = connector->status;
1101                 goto out;
1102         }
1103
1104         /* find analog encoder */
1105         if (amdgpu_connector->dac_load_detect) {
1106                 struct drm_encoder *encoder;
1107
1108                 drm_connector_for_each_possible_encoder(connector, encoder) {
1109                         if (encoder->encoder_type != DRM_MODE_ENCODER_DAC &&
1110                             encoder->encoder_type != DRM_MODE_ENCODER_TVDAC)
1111                                 continue;
1112
1113                         encoder_funcs = encoder->helper_private;
1114                         if (encoder_funcs->detect) {
1115                                 if (!broken_edid) {
1116                                         if (ret != connector_status_connected) {
1117                                                 /* deal with analog monitors without DDC */
1118                                                 ret = encoder_funcs->detect(encoder, connector);
1119                                                 if (ret == connector_status_connected) {
1120                                                         amdgpu_connector->use_digital = false;
1121                                                 }
1122                                                 if (ret != connector_status_disconnected)
1123                                                         amdgpu_connector->detected_by_load = true;
1124                                         }
1125                                 } else {
1126                                         enum drm_connector_status lret;
1127                                         /* assume digital unless load detected otherwise */
1128                                         amdgpu_connector->use_digital = true;
1129                                         lret = encoder_funcs->detect(encoder, connector);
1130                                         DRM_DEBUG_KMS("load_detect %x returned: %x\n",encoder->encoder_type,lret);
1131                                         if (lret == connector_status_connected)
1132                                                 amdgpu_connector->use_digital = false;
1133                                 }
1134                                 break;
1135                         }
1136                 }
1137         }
1138
1139 out:
1140         /* updated in get modes as well since we need to know if it's analog or digital */
1141         amdgpu_connector_update_scratch_regs(connector, ret);
1142
1143 exit:
1144         if (!drm_kms_helper_is_poll_worker()) {
1145                 pm_runtime_mark_last_busy(connector->dev->dev);
1146                 pm_runtime_put_autosuspend(connector->dev->dev);
1147         }
1148
1149         return ret;
1150 }
1151
1152 /* okay need to be smart in here about which encoder to pick */
1153 static struct drm_encoder *
1154 amdgpu_connector_dvi_encoder(struct drm_connector *connector)
1155 {
1156         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
1157         struct drm_encoder *encoder;
1158
1159         drm_connector_for_each_possible_encoder(connector, encoder) {
1160                 if (amdgpu_connector->use_digital == true) {
1161                         if (encoder->encoder_type == DRM_MODE_ENCODER_TMDS)
1162                                 return encoder;
1163                 } else {
1164                         if (encoder->encoder_type == DRM_MODE_ENCODER_DAC ||
1165                             encoder->encoder_type == DRM_MODE_ENCODER_TVDAC)
1166                                 return encoder;
1167                 }
1168         }
1169
1170         /* see if we have a default encoder  TODO */
1171
1172         /* then check use digitial */
1173         /* pick the first one */
1174         drm_connector_for_each_possible_encoder(connector, encoder)
1175                 return encoder;
1176
1177         return NULL;
1178 }
1179
1180 static void amdgpu_connector_dvi_force(struct drm_connector *connector)
1181 {
1182         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
1183         if (connector->force == DRM_FORCE_ON)
1184                 amdgpu_connector->use_digital = false;
1185         if (connector->force == DRM_FORCE_ON_DIGITAL)
1186                 amdgpu_connector->use_digital = true;
1187 }
1188
1189 static enum drm_mode_status amdgpu_connector_dvi_mode_valid(struct drm_connector *connector,
1190                                             struct drm_display_mode *mode)
1191 {
1192         struct drm_device *dev = connector->dev;
1193         struct amdgpu_device *adev = drm_to_adev(dev);
1194         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
1195
1196         /* XXX check mode bandwidth */
1197
1198         if (amdgpu_connector->use_digital && (mode->clock > 165000)) {
1199                 if ((amdgpu_connector->connector_object_id == CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I) ||
1200                     (amdgpu_connector->connector_object_id == CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D) ||
1201                     (amdgpu_connector->connector_object_id == CONNECTOR_OBJECT_ID_HDMI_TYPE_B)) {
1202                         return MODE_OK;
1203                 } else if (connector->display_info.is_hdmi) {
1204                         /* HDMI 1.3+ supports max clock of 340 Mhz */
1205                         if (mode->clock > 340000)
1206                                 return MODE_CLOCK_HIGH;
1207                         else
1208                                 return MODE_OK;
1209                 } else {
1210                         return MODE_CLOCK_HIGH;
1211                 }
1212         }
1213
1214         /* check against the max pixel clock */
1215         if ((mode->clock / 10) > adev->clock.max_pixel_clock)
1216                 return MODE_CLOCK_HIGH;
1217
1218         return MODE_OK;
1219 }
1220
1221 static const struct drm_connector_helper_funcs amdgpu_connector_dvi_helper_funcs = {
1222         .get_modes = amdgpu_connector_vga_get_modes,
1223         .mode_valid = amdgpu_connector_dvi_mode_valid,
1224         .best_encoder = amdgpu_connector_dvi_encoder,
1225 };
1226
1227 static const struct drm_connector_funcs amdgpu_connector_dvi_funcs = {
1228         .dpms = drm_helper_connector_dpms,
1229         .detect = amdgpu_connector_dvi_detect,
1230         .fill_modes = drm_helper_probe_single_connector_modes,
1231         .set_property = amdgpu_connector_set_property,
1232         .early_unregister = amdgpu_connector_unregister,
1233         .destroy = amdgpu_connector_destroy,
1234         .force = amdgpu_connector_dvi_force,
1235 };
1236
1237 static int amdgpu_connector_dp_get_modes(struct drm_connector *connector)
1238 {
1239         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
1240         struct amdgpu_connector_atom_dig *amdgpu_dig_connector = amdgpu_connector->con_priv;
1241         struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector);
1242         int ret;
1243
1244         if ((connector->connector_type == DRM_MODE_CONNECTOR_eDP) ||
1245             (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)) {
1246                 struct drm_display_mode *mode;
1247
1248                 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
1249                         if (!amdgpu_dig_connector->edp_on)
1250                                 amdgpu_atombios_encoder_set_edp_panel_power(connector,
1251                                                                      ATOM_TRANSMITTER_ACTION_POWER_ON);
1252                         amdgpu_connector_get_edid(connector);
1253                         ret = amdgpu_connector_ddc_get_modes(connector);
1254                         if (!amdgpu_dig_connector->edp_on)
1255                                 amdgpu_atombios_encoder_set_edp_panel_power(connector,
1256                                                                      ATOM_TRANSMITTER_ACTION_POWER_OFF);
1257                 } else {
1258                         /* need to setup ddc on the bridge */
1259                         if (amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) !=
1260                             ENCODER_OBJECT_ID_NONE) {
1261                                 if (encoder)
1262                                         amdgpu_atombios_encoder_setup_ext_encoder_ddc(encoder);
1263                         }
1264                         amdgpu_connector_get_edid(connector);
1265                         ret = amdgpu_connector_ddc_get_modes(connector);
1266                 }
1267
1268                 if (ret > 0) {
1269                         if (encoder) {
1270                                 amdgpu_connector_fixup_lcd_native_mode(encoder, connector);
1271                                 /* add scaled modes */
1272                                 amdgpu_connector_add_common_modes(encoder, connector);
1273                         }
1274                         return ret;
1275                 }
1276
1277                 if (!encoder)
1278                         return 0;
1279
1280                 /* we have no EDID modes */
1281                 mode = amdgpu_connector_lcd_native_mode(encoder);
1282                 if (mode) {
1283                         ret = 1;
1284                         drm_mode_probed_add(connector, mode);
1285                         /* add the width/height from vbios tables if available */
1286                         connector->display_info.width_mm = mode->width_mm;
1287                         connector->display_info.height_mm = mode->height_mm;
1288                         /* add scaled modes */
1289                         amdgpu_connector_add_common_modes(encoder, connector);
1290                 }
1291         } else {
1292                 /* need to setup ddc on the bridge */
1293                 if (amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) !=
1294                         ENCODER_OBJECT_ID_NONE) {
1295                         if (encoder)
1296                                 amdgpu_atombios_encoder_setup_ext_encoder_ddc(encoder);
1297                 }
1298                 amdgpu_connector_get_edid(connector);
1299                 ret = amdgpu_connector_ddc_get_modes(connector);
1300
1301                 amdgpu_get_native_mode(connector);
1302         }
1303
1304         return ret;
1305 }
1306
1307 u16 amdgpu_connector_encoder_get_dp_bridge_encoder_id(struct drm_connector *connector)
1308 {
1309         struct drm_encoder *encoder;
1310         struct amdgpu_encoder *amdgpu_encoder;
1311
1312         drm_connector_for_each_possible_encoder(connector, encoder) {
1313                 amdgpu_encoder = to_amdgpu_encoder(encoder);
1314
1315                 switch (amdgpu_encoder->encoder_id) {
1316                 case ENCODER_OBJECT_ID_TRAVIS:
1317                 case ENCODER_OBJECT_ID_NUTMEG:
1318                         return amdgpu_encoder->encoder_id;
1319                 default:
1320                         break;
1321                 }
1322         }
1323
1324         return ENCODER_OBJECT_ID_NONE;
1325 }
1326
1327 static bool amdgpu_connector_encoder_is_hbr2(struct drm_connector *connector)
1328 {
1329         struct drm_encoder *encoder;
1330         struct amdgpu_encoder *amdgpu_encoder;
1331         bool found = false;
1332
1333         drm_connector_for_each_possible_encoder(connector, encoder) {
1334                 amdgpu_encoder = to_amdgpu_encoder(encoder);
1335                 if (amdgpu_encoder->caps & ATOM_ENCODER_CAP_RECORD_HBR2)
1336                         found = true;
1337         }
1338
1339         return found;
1340 }
1341
1342 bool amdgpu_connector_is_dp12_capable(struct drm_connector *connector)
1343 {
1344         struct drm_device *dev = connector->dev;
1345         struct amdgpu_device *adev = drm_to_adev(dev);
1346
1347         if ((adev->clock.default_dispclk >= 53900) &&
1348             amdgpu_connector_encoder_is_hbr2(connector)) {
1349                 return true;
1350         }
1351
1352         return false;
1353 }
1354
1355 static enum drm_connector_status
1356 amdgpu_connector_dp_detect(struct drm_connector *connector, bool force)
1357 {
1358         struct drm_device *dev = connector->dev;
1359         struct amdgpu_device *adev = drm_to_adev(dev);
1360         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
1361         enum drm_connector_status ret = connector_status_disconnected;
1362         struct amdgpu_connector_atom_dig *amdgpu_dig_connector = amdgpu_connector->con_priv;
1363         struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector);
1364         int r;
1365
1366         if (!drm_kms_helper_is_poll_worker()) {
1367                 r = pm_runtime_get_sync(connector->dev->dev);
1368                 if (r < 0) {
1369                         pm_runtime_put_autosuspend(connector->dev->dev);
1370                         return connector_status_disconnected;
1371                 }
1372         }
1373
1374         if (!force && amdgpu_connector_check_hpd_status_unchanged(connector)) {
1375                 ret = connector->status;
1376                 goto out;
1377         }
1378
1379         amdgpu_connector_free_edid(connector);
1380
1381         if ((connector->connector_type == DRM_MODE_CONNECTOR_eDP) ||
1382             (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)) {
1383                 if (encoder) {
1384                         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1385                         struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
1386
1387                         /* check if panel is valid */
1388                         if (native_mode->hdisplay >= 320 && native_mode->vdisplay >= 240)
1389                                 ret = connector_status_connected;
1390                 }
1391                 /* eDP is always DP */
1392                 amdgpu_dig_connector->dp_sink_type = CONNECTOR_OBJECT_ID_DISPLAYPORT;
1393                 if (!amdgpu_dig_connector->edp_on)
1394                         amdgpu_atombios_encoder_set_edp_panel_power(connector,
1395                                                              ATOM_TRANSMITTER_ACTION_POWER_ON);
1396                 if (!amdgpu_atombios_dp_get_dpcd(amdgpu_connector))
1397                         ret = connector_status_connected;
1398                 if (!amdgpu_dig_connector->edp_on)
1399                         amdgpu_atombios_encoder_set_edp_panel_power(connector,
1400                                                              ATOM_TRANSMITTER_ACTION_POWER_OFF);
1401         } else if (amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) !=
1402                    ENCODER_OBJECT_ID_NONE) {
1403                 /* DP bridges are always DP */
1404                 amdgpu_dig_connector->dp_sink_type = CONNECTOR_OBJECT_ID_DISPLAYPORT;
1405                 /* get the DPCD from the bridge */
1406                 amdgpu_atombios_dp_get_dpcd(amdgpu_connector);
1407
1408                 if (encoder) {
1409                         /* setup ddc on the bridge */
1410                         amdgpu_atombios_encoder_setup_ext_encoder_ddc(encoder);
1411                         /* bridge chips are always aux */
1412                         /* try DDC */
1413                         if (amdgpu_display_ddc_probe(amdgpu_connector, true))
1414                                 ret = connector_status_connected;
1415                         else if (amdgpu_connector->dac_load_detect) { /* try load detection */
1416                                 const struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
1417                                 ret = encoder_funcs->detect(encoder, connector);
1418                         }
1419                 }
1420         } else {
1421                 amdgpu_dig_connector->dp_sink_type =
1422                         amdgpu_atombios_dp_get_sinktype(amdgpu_connector);
1423                 if (amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd)) {
1424                         ret = connector_status_connected;
1425                         if (amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT)
1426                                 amdgpu_atombios_dp_get_dpcd(amdgpu_connector);
1427                 } else {
1428                         if (amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) {
1429                                 if (!amdgpu_atombios_dp_get_dpcd(amdgpu_connector))
1430                                         ret = connector_status_connected;
1431                         } else {
1432                                 /* try non-aux ddc (DP to DVI/HDMI/etc. adapter) */
1433                                 if (amdgpu_display_ddc_probe(amdgpu_connector,
1434                                                              false))
1435                                         ret = connector_status_connected;
1436                         }
1437                 }
1438         }
1439
1440         amdgpu_connector_update_scratch_regs(connector, ret);
1441 out:
1442         if (!drm_kms_helper_is_poll_worker()) {
1443                 pm_runtime_mark_last_busy(connector->dev->dev);
1444                 pm_runtime_put_autosuspend(connector->dev->dev);
1445         }
1446
1447         if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
1448             connector->connector_type == DRM_MODE_CONNECTOR_eDP)
1449                 drm_dp_set_subconnector_property(&amdgpu_connector->base,
1450                                                  ret,
1451                                                  amdgpu_dig_connector->dpcd,
1452                                                  amdgpu_dig_connector->downstream_ports);
1453         return ret;
1454 }
1455
1456 static enum drm_mode_status amdgpu_connector_dp_mode_valid(struct drm_connector *connector,
1457                                            struct drm_display_mode *mode)
1458 {
1459         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
1460         struct amdgpu_connector_atom_dig *amdgpu_dig_connector = amdgpu_connector->con_priv;
1461
1462         /* XXX check mode bandwidth */
1463
1464         if ((connector->connector_type == DRM_MODE_CONNECTOR_eDP) ||
1465             (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)) {
1466                 struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector);
1467
1468                 if ((mode->hdisplay < 320) || (mode->vdisplay < 240))
1469                         return MODE_PANEL;
1470
1471                 if (encoder) {
1472                         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1473                         struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
1474
1475                         /* AVIVO hardware supports downscaling modes larger than the panel
1476                          * to the panel size, but I'm not sure this is desirable.
1477                          */
1478                         if ((mode->hdisplay > native_mode->hdisplay) ||
1479                             (mode->vdisplay > native_mode->vdisplay))
1480                                 return MODE_PANEL;
1481
1482                         /* if scaling is disabled, block non-native modes */
1483                         if (amdgpu_encoder->rmx_type == RMX_OFF) {
1484                                 if ((mode->hdisplay != native_mode->hdisplay) ||
1485                                     (mode->vdisplay != native_mode->vdisplay))
1486                                         return MODE_PANEL;
1487                         }
1488                 }
1489                 return MODE_OK;
1490         } else {
1491                 if ((amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
1492                     (amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) {
1493                         return amdgpu_atombios_dp_mode_valid_helper(connector, mode);
1494                 } else {
1495                         if (connector->display_info.is_hdmi) {
1496                                 /* HDMI 1.3+ supports max clock of 340 Mhz */
1497                                 if (mode->clock > 340000)
1498                                         return MODE_CLOCK_HIGH;
1499                         } else {
1500                                 if (mode->clock > 165000)
1501                                         return MODE_CLOCK_HIGH;
1502                         }
1503                 }
1504         }
1505
1506         return MODE_OK;
1507 }
1508
1509 static int
1510 amdgpu_connector_late_register(struct drm_connector *connector)
1511 {
1512         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
1513         int r = 0;
1514
1515         if (amdgpu_connector->ddc_bus->has_aux) {
1516                 amdgpu_connector->ddc_bus->aux.dev = amdgpu_connector->base.kdev;
1517                 r = drm_dp_aux_register(&amdgpu_connector->ddc_bus->aux);
1518         }
1519
1520         return r;
1521 }
1522
1523 static const struct drm_connector_helper_funcs amdgpu_connector_dp_helper_funcs = {
1524         .get_modes = amdgpu_connector_dp_get_modes,
1525         .mode_valid = amdgpu_connector_dp_mode_valid,
1526         .best_encoder = amdgpu_connector_dvi_encoder,
1527 };
1528
1529 static const struct drm_connector_funcs amdgpu_connector_dp_funcs = {
1530         .dpms = drm_helper_connector_dpms,
1531         .detect = amdgpu_connector_dp_detect,
1532         .fill_modes = drm_helper_probe_single_connector_modes,
1533         .set_property = amdgpu_connector_set_property,
1534         .early_unregister = amdgpu_connector_unregister,
1535         .destroy = amdgpu_connector_destroy,
1536         .force = amdgpu_connector_dvi_force,
1537         .late_register = amdgpu_connector_late_register,
1538 };
1539
1540 static const struct drm_connector_funcs amdgpu_connector_edp_funcs = {
1541         .dpms = drm_helper_connector_dpms,
1542         .detect = amdgpu_connector_dp_detect,
1543         .fill_modes = drm_helper_probe_single_connector_modes,
1544         .set_property = amdgpu_connector_set_lcd_property,
1545         .early_unregister = amdgpu_connector_unregister,
1546         .destroy = amdgpu_connector_destroy,
1547         .force = amdgpu_connector_dvi_force,
1548         .late_register = amdgpu_connector_late_register,
1549 };
1550
1551 void
1552 amdgpu_connector_add(struct amdgpu_device *adev,
1553                       uint32_t connector_id,
1554                       uint32_t supported_device,
1555                       int connector_type,
1556                       struct amdgpu_i2c_bus_rec *i2c_bus,
1557                       uint16_t connector_object_id,
1558                       struct amdgpu_hpd *hpd,
1559                       struct amdgpu_router *router)
1560 {
1561         struct drm_device *dev = adev_to_drm(adev);
1562         struct drm_connector *connector;
1563         struct drm_connector_list_iter iter;
1564         struct amdgpu_connector *amdgpu_connector;
1565         struct amdgpu_connector_atom_dig *amdgpu_dig_connector;
1566         struct drm_encoder *encoder;
1567         struct amdgpu_encoder *amdgpu_encoder;
1568         struct i2c_adapter *ddc = NULL;
1569         uint32_t subpixel_order = SubPixelNone;
1570         bool shared_ddc = false;
1571         bool is_dp_bridge = false;
1572         bool has_aux = false;
1573
1574         if (connector_type == DRM_MODE_CONNECTOR_Unknown)
1575                 return;
1576
1577         /* see if we already added it */
1578         drm_connector_list_iter_begin(dev, &iter);
1579         drm_for_each_connector_iter(connector, &iter) {
1580                 amdgpu_connector = to_amdgpu_connector(connector);
1581                 if (amdgpu_connector->connector_id == connector_id) {
1582                         amdgpu_connector->devices |= supported_device;
1583                         drm_connector_list_iter_end(&iter);
1584                         return;
1585                 }
1586                 if (amdgpu_connector->ddc_bus && i2c_bus->valid) {
1587                         if (amdgpu_connector->ddc_bus->rec.i2c_id == i2c_bus->i2c_id) {
1588                                 amdgpu_connector->shared_ddc = true;
1589                                 shared_ddc = true;
1590                         }
1591                         if (amdgpu_connector->router_bus && router->ddc_valid &&
1592                             (amdgpu_connector->router.router_id == router->router_id)) {
1593                                 amdgpu_connector->shared_ddc = false;
1594                                 shared_ddc = false;
1595                         }
1596                 }
1597         }
1598         drm_connector_list_iter_end(&iter);
1599
1600         /* check if it's a dp bridge */
1601         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1602                 amdgpu_encoder = to_amdgpu_encoder(encoder);
1603                 if (amdgpu_encoder->devices & supported_device) {
1604                         switch (amdgpu_encoder->encoder_id) {
1605                         case ENCODER_OBJECT_ID_TRAVIS:
1606                         case ENCODER_OBJECT_ID_NUTMEG:
1607                                 is_dp_bridge = true;
1608                                 break;
1609                         default:
1610                                 break;
1611                         }
1612                 }
1613         }
1614
1615         amdgpu_connector = kzalloc(sizeof(struct amdgpu_connector), GFP_KERNEL);
1616         if (!amdgpu_connector)
1617                 return;
1618
1619         connector = &amdgpu_connector->base;
1620
1621         amdgpu_connector->connector_id = connector_id;
1622         amdgpu_connector->devices = supported_device;
1623         amdgpu_connector->shared_ddc = shared_ddc;
1624         amdgpu_connector->connector_object_id = connector_object_id;
1625         amdgpu_connector->hpd = *hpd;
1626
1627         amdgpu_connector->router = *router;
1628         if (router->ddc_valid || router->cd_valid) {
1629                 amdgpu_connector->router_bus = amdgpu_i2c_lookup(adev, &router->i2c_info);
1630                 if (!amdgpu_connector->router_bus)
1631                         DRM_ERROR("Failed to assign router i2c bus! Check dmesg for i2c errors.\n");
1632         }
1633
1634         if (is_dp_bridge) {
1635                 amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL);
1636                 if (!amdgpu_dig_connector)
1637                         goto failed;
1638                 amdgpu_connector->con_priv = amdgpu_dig_connector;
1639                 if (i2c_bus->valid) {
1640                         amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
1641                         if (amdgpu_connector->ddc_bus) {
1642                                 has_aux = true;
1643                                 ddc = &amdgpu_connector->ddc_bus->adapter;
1644                         } else {
1645                                 DRM_ERROR("DP: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
1646                         }
1647                 }
1648                 switch (connector_type) {
1649                 case DRM_MODE_CONNECTOR_VGA:
1650                 case DRM_MODE_CONNECTOR_DVIA:
1651                 default:
1652                         drm_connector_init_with_ddc(dev, &amdgpu_connector->base,
1653                                                     &amdgpu_connector_dp_funcs,
1654                                                     connector_type,
1655                                                     ddc);
1656                         drm_connector_helper_add(&amdgpu_connector->base,
1657                                                  &amdgpu_connector_dp_helper_funcs);
1658                         connector->interlace_allowed = true;
1659                         connector->doublescan_allowed = true;
1660                         amdgpu_connector->dac_load_detect = true;
1661                         drm_object_attach_property(&amdgpu_connector->base.base,
1662                                                       adev->mode_info.load_detect_property,
1663                                                       1);
1664                         drm_object_attach_property(&amdgpu_connector->base.base,
1665                                                    dev->mode_config.scaling_mode_property,
1666                                                    DRM_MODE_SCALE_NONE);
1667                         break;
1668                 case DRM_MODE_CONNECTOR_DVII:
1669                 case DRM_MODE_CONNECTOR_DVID:
1670                 case DRM_MODE_CONNECTOR_HDMIA:
1671                 case DRM_MODE_CONNECTOR_HDMIB:
1672                 case DRM_MODE_CONNECTOR_DisplayPort:
1673                         drm_connector_init_with_ddc(dev, &amdgpu_connector->base,
1674                                                     &amdgpu_connector_dp_funcs,
1675                                                     connector_type,
1676                                                     ddc);
1677                         drm_connector_helper_add(&amdgpu_connector->base,
1678                                                  &amdgpu_connector_dp_helper_funcs);
1679                         drm_object_attach_property(&amdgpu_connector->base.base,
1680                                                       adev->mode_info.underscan_property,
1681                                                       UNDERSCAN_OFF);
1682                         drm_object_attach_property(&amdgpu_connector->base.base,
1683                                                       adev->mode_info.underscan_hborder_property,
1684                                                       0);
1685                         drm_object_attach_property(&amdgpu_connector->base.base,
1686                                                       adev->mode_info.underscan_vborder_property,
1687                                                       0);
1688
1689                         drm_object_attach_property(&amdgpu_connector->base.base,
1690                                                    dev->mode_config.scaling_mode_property,
1691                                                    DRM_MODE_SCALE_NONE);
1692
1693                         drm_object_attach_property(&amdgpu_connector->base.base,
1694                                                    adev->mode_info.dither_property,
1695                                                    AMDGPU_FMT_DITHER_DISABLE);
1696
1697                         if (amdgpu_audio != 0) {
1698                                 drm_object_attach_property(&amdgpu_connector->base.base,
1699                                                            adev->mode_info.audio_property,
1700                                                            AMDGPU_AUDIO_AUTO);
1701                                 amdgpu_connector->audio = AMDGPU_AUDIO_AUTO;
1702                         }
1703
1704                         subpixel_order = SubPixelHorizontalRGB;
1705                         connector->interlace_allowed = true;
1706                         if (connector_type == DRM_MODE_CONNECTOR_HDMIB)
1707                                 connector->doublescan_allowed = true;
1708                         else
1709                                 connector->doublescan_allowed = false;
1710                         if (connector_type == DRM_MODE_CONNECTOR_DVII) {
1711                                 amdgpu_connector->dac_load_detect = true;
1712                                 drm_object_attach_property(&amdgpu_connector->base.base,
1713                                                               adev->mode_info.load_detect_property,
1714                                                               1);
1715                         }
1716                         break;
1717                 case DRM_MODE_CONNECTOR_LVDS:
1718                 case DRM_MODE_CONNECTOR_eDP:
1719                         drm_connector_init_with_ddc(dev, &amdgpu_connector->base,
1720                                                     &amdgpu_connector_edp_funcs,
1721                                                     connector_type,
1722                                                     ddc);
1723                         drm_connector_helper_add(&amdgpu_connector->base,
1724                                                  &amdgpu_connector_dp_helper_funcs);
1725                         drm_object_attach_property(&amdgpu_connector->base.base,
1726                                                       dev->mode_config.scaling_mode_property,
1727                                                       DRM_MODE_SCALE_FULLSCREEN);
1728                         subpixel_order = SubPixelHorizontalRGB;
1729                         connector->interlace_allowed = false;
1730                         connector->doublescan_allowed = false;
1731                         break;
1732                 }
1733         } else {
1734                 switch (connector_type) {
1735                 case DRM_MODE_CONNECTOR_VGA:
1736                         if (i2c_bus->valid) {
1737                                 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
1738                                 if (!amdgpu_connector->ddc_bus)
1739                                         DRM_ERROR("VGA: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
1740                                 else
1741                                         ddc = &amdgpu_connector->ddc_bus->adapter;
1742                         }
1743                         drm_connector_init_with_ddc(dev, &amdgpu_connector->base,
1744                                                     &amdgpu_connector_vga_funcs,
1745                                                     connector_type,
1746                                                     ddc);
1747                         drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_vga_helper_funcs);
1748                         amdgpu_connector->dac_load_detect = true;
1749                         drm_object_attach_property(&amdgpu_connector->base.base,
1750                                                       adev->mode_info.load_detect_property,
1751                                                       1);
1752                         drm_object_attach_property(&amdgpu_connector->base.base,
1753                                                    dev->mode_config.scaling_mode_property,
1754                                                    DRM_MODE_SCALE_NONE);
1755                         /* no HPD on analog connectors */
1756                         amdgpu_connector->hpd.hpd = AMDGPU_HPD_NONE;
1757                         connector->interlace_allowed = true;
1758                         connector->doublescan_allowed = true;
1759                         break;
1760                 case DRM_MODE_CONNECTOR_DVIA:
1761                         if (i2c_bus->valid) {
1762                                 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
1763                                 if (!amdgpu_connector->ddc_bus)
1764                                         DRM_ERROR("DVIA: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
1765                                 else
1766                                         ddc = &amdgpu_connector->ddc_bus->adapter;
1767                         }
1768                         drm_connector_init_with_ddc(dev, &amdgpu_connector->base,
1769                                                     &amdgpu_connector_vga_funcs,
1770                                                     connector_type,
1771                                                     ddc);
1772                         drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_vga_helper_funcs);
1773                         amdgpu_connector->dac_load_detect = true;
1774                         drm_object_attach_property(&amdgpu_connector->base.base,
1775                                                       adev->mode_info.load_detect_property,
1776                                                       1);
1777                         drm_object_attach_property(&amdgpu_connector->base.base,
1778                                                    dev->mode_config.scaling_mode_property,
1779                                                    DRM_MODE_SCALE_NONE);
1780                         /* no HPD on analog connectors */
1781                         amdgpu_connector->hpd.hpd = AMDGPU_HPD_NONE;
1782                         connector->interlace_allowed = true;
1783                         connector->doublescan_allowed = true;
1784                         break;
1785                 case DRM_MODE_CONNECTOR_DVII:
1786                 case DRM_MODE_CONNECTOR_DVID:
1787                         amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL);
1788                         if (!amdgpu_dig_connector)
1789                                 goto failed;
1790                         amdgpu_connector->con_priv = amdgpu_dig_connector;
1791                         if (i2c_bus->valid) {
1792                                 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
1793                                 if (!amdgpu_connector->ddc_bus)
1794                                         DRM_ERROR("DVI: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
1795                                 else
1796                                         ddc = &amdgpu_connector->ddc_bus->adapter;
1797                         }
1798                         drm_connector_init_with_ddc(dev, &amdgpu_connector->base,
1799                                                     &amdgpu_connector_dvi_funcs,
1800                                                     connector_type,
1801                                                     ddc);
1802                         drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dvi_helper_funcs);
1803                         subpixel_order = SubPixelHorizontalRGB;
1804                         drm_object_attach_property(&amdgpu_connector->base.base,
1805                                                       adev->mode_info.coherent_mode_property,
1806                                                       1);
1807                         drm_object_attach_property(&amdgpu_connector->base.base,
1808                                                    adev->mode_info.underscan_property,
1809                                                    UNDERSCAN_OFF);
1810                         drm_object_attach_property(&amdgpu_connector->base.base,
1811                                                    adev->mode_info.underscan_hborder_property,
1812                                                    0);
1813                         drm_object_attach_property(&amdgpu_connector->base.base,
1814                                                    adev->mode_info.underscan_vborder_property,
1815                                                    0);
1816                         drm_object_attach_property(&amdgpu_connector->base.base,
1817                                                    dev->mode_config.scaling_mode_property,
1818                                                    DRM_MODE_SCALE_NONE);
1819
1820                         if (amdgpu_audio != 0) {
1821                                 drm_object_attach_property(&amdgpu_connector->base.base,
1822                                                            adev->mode_info.audio_property,
1823                                                            AMDGPU_AUDIO_AUTO);
1824                                 amdgpu_connector->audio = AMDGPU_AUDIO_AUTO;
1825                         }
1826                         drm_object_attach_property(&amdgpu_connector->base.base,
1827                                                    adev->mode_info.dither_property,
1828                                                    AMDGPU_FMT_DITHER_DISABLE);
1829                         if (connector_type == DRM_MODE_CONNECTOR_DVII) {
1830                                 amdgpu_connector->dac_load_detect = true;
1831                                 drm_object_attach_property(&amdgpu_connector->base.base,
1832                                                            adev->mode_info.load_detect_property,
1833                                                            1);
1834                         }
1835                         connector->interlace_allowed = true;
1836                         if (connector_type == DRM_MODE_CONNECTOR_DVII)
1837                                 connector->doublescan_allowed = true;
1838                         else
1839                                 connector->doublescan_allowed = false;
1840                         break;
1841                 case DRM_MODE_CONNECTOR_HDMIA:
1842                 case DRM_MODE_CONNECTOR_HDMIB:
1843                         amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL);
1844                         if (!amdgpu_dig_connector)
1845                                 goto failed;
1846                         amdgpu_connector->con_priv = amdgpu_dig_connector;
1847                         if (i2c_bus->valid) {
1848                                 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
1849                                 if (!amdgpu_connector->ddc_bus)
1850                                         DRM_ERROR("HDMI: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
1851                                 else
1852                                         ddc = &amdgpu_connector->ddc_bus->adapter;
1853                         }
1854                         drm_connector_init_with_ddc(dev, &amdgpu_connector->base,
1855                                                     &amdgpu_connector_dvi_funcs,
1856                                                     connector_type,
1857                                                     ddc);
1858                         drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dvi_helper_funcs);
1859                         drm_object_attach_property(&amdgpu_connector->base.base,
1860                                                       adev->mode_info.coherent_mode_property,
1861                                                       1);
1862                         drm_object_attach_property(&amdgpu_connector->base.base,
1863                                                    adev->mode_info.underscan_property,
1864                                                    UNDERSCAN_OFF);
1865                         drm_object_attach_property(&amdgpu_connector->base.base,
1866                                                    adev->mode_info.underscan_hborder_property,
1867                                                    0);
1868                         drm_object_attach_property(&amdgpu_connector->base.base,
1869                                                    adev->mode_info.underscan_vborder_property,
1870                                                    0);
1871                         drm_object_attach_property(&amdgpu_connector->base.base,
1872                                                    dev->mode_config.scaling_mode_property,
1873                                                    DRM_MODE_SCALE_NONE);
1874                         if (amdgpu_audio != 0) {
1875                                 drm_object_attach_property(&amdgpu_connector->base.base,
1876                                                            adev->mode_info.audio_property,
1877                                                            AMDGPU_AUDIO_AUTO);
1878                                 amdgpu_connector->audio = AMDGPU_AUDIO_AUTO;
1879                         }
1880                         drm_object_attach_property(&amdgpu_connector->base.base,
1881                                                    adev->mode_info.dither_property,
1882                                                    AMDGPU_FMT_DITHER_DISABLE);
1883                         subpixel_order = SubPixelHorizontalRGB;
1884                         connector->interlace_allowed = true;
1885                         if (connector_type == DRM_MODE_CONNECTOR_HDMIB)
1886                                 connector->doublescan_allowed = true;
1887                         else
1888                                 connector->doublescan_allowed = false;
1889                         break;
1890                 case DRM_MODE_CONNECTOR_DisplayPort:
1891                         amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL);
1892                         if (!amdgpu_dig_connector)
1893                                 goto failed;
1894                         amdgpu_connector->con_priv = amdgpu_dig_connector;
1895                         if (i2c_bus->valid) {
1896                                 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
1897                                 if (amdgpu_connector->ddc_bus) {
1898                                         has_aux = true;
1899                                         ddc = &amdgpu_connector->ddc_bus->adapter;
1900                                 } else {
1901                                         DRM_ERROR("DP: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
1902                                 }
1903                         }
1904                         drm_connector_init_with_ddc(dev, &amdgpu_connector->base,
1905                                                     &amdgpu_connector_dp_funcs,
1906                                                     connector_type,
1907                                                     ddc);
1908                         drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dp_helper_funcs);
1909                         subpixel_order = SubPixelHorizontalRGB;
1910                         drm_object_attach_property(&amdgpu_connector->base.base,
1911                                                       adev->mode_info.coherent_mode_property,
1912                                                       1);
1913                         drm_object_attach_property(&amdgpu_connector->base.base,
1914                                                    adev->mode_info.underscan_property,
1915                                                    UNDERSCAN_OFF);
1916                         drm_object_attach_property(&amdgpu_connector->base.base,
1917                                                    adev->mode_info.underscan_hborder_property,
1918                                                    0);
1919                         drm_object_attach_property(&amdgpu_connector->base.base,
1920                                                    adev->mode_info.underscan_vborder_property,
1921                                                    0);
1922                         drm_object_attach_property(&amdgpu_connector->base.base,
1923                                                    dev->mode_config.scaling_mode_property,
1924                                                    DRM_MODE_SCALE_NONE);
1925                         if (amdgpu_audio != 0) {
1926                                 drm_object_attach_property(&amdgpu_connector->base.base,
1927                                                            adev->mode_info.audio_property,
1928                                                            AMDGPU_AUDIO_AUTO);
1929                                 amdgpu_connector->audio = AMDGPU_AUDIO_AUTO;
1930                         }
1931                         drm_object_attach_property(&amdgpu_connector->base.base,
1932                                                    adev->mode_info.dither_property,
1933                                                    AMDGPU_FMT_DITHER_DISABLE);
1934                         connector->interlace_allowed = true;
1935                         /* in theory with a DP to VGA converter... */
1936                         connector->doublescan_allowed = false;
1937                         break;
1938                 case DRM_MODE_CONNECTOR_eDP:
1939                         amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL);
1940                         if (!amdgpu_dig_connector)
1941                                 goto failed;
1942                         amdgpu_connector->con_priv = amdgpu_dig_connector;
1943                         if (i2c_bus->valid) {
1944                                 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
1945                                 if (amdgpu_connector->ddc_bus) {
1946                                         has_aux = true;
1947                                         ddc = &amdgpu_connector->ddc_bus->adapter;
1948                                 } else {
1949                                         DRM_ERROR("DP: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
1950                                 }
1951                         }
1952                         drm_connector_init_with_ddc(dev, &amdgpu_connector->base,
1953                                                     &amdgpu_connector_edp_funcs,
1954                                                     connector_type,
1955                                                     ddc);
1956                         drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dp_helper_funcs);
1957                         drm_object_attach_property(&amdgpu_connector->base.base,
1958                                                       dev->mode_config.scaling_mode_property,
1959                                                       DRM_MODE_SCALE_FULLSCREEN);
1960                         subpixel_order = SubPixelHorizontalRGB;
1961                         connector->interlace_allowed = false;
1962                         connector->doublescan_allowed = false;
1963                         break;
1964                 case DRM_MODE_CONNECTOR_LVDS:
1965                         amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL);
1966                         if (!amdgpu_dig_connector)
1967                                 goto failed;
1968                         amdgpu_connector->con_priv = amdgpu_dig_connector;
1969                         if (i2c_bus->valid) {
1970                                 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
1971                                 if (!amdgpu_connector->ddc_bus)
1972                                         DRM_ERROR("LVDS: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
1973                                 else
1974                                         ddc = &amdgpu_connector->ddc_bus->adapter;
1975                         }
1976                         drm_connector_init_with_ddc(dev, &amdgpu_connector->base,
1977                                                     &amdgpu_connector_lvds_funcs,
1978                                                     connector_type,
1979                                                     ddc);
1980                         drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_lvds_helper_funcs);
1981                         drm_object_attach_property(&amdgpu_connector->base.base,
1982                                                       dev->mode_config.scaling_mode_property,
1983                                                       DRM_MODE_SCALE_FULLSCREEN);
1984                         subpixel_order = SubPixelHorizontalRGB;
1985                         connector->interlace_allowed = false;
1986                         connector->doublescan_allowed = false;
1987                         break;
1988                 }
1989         }
1990
1991         if (amdgpu_connector->hpd.hpd == AMDGPU_HPD_NONE) {
1992                 if (i2c_bus->valid) {
1993                         connector->polled = DRM_CONNECTOR_POLL_CONNECT |
1994                                             DRM_CONNECTOR_POLL_DISCONNECT;
1995                 }
1996         } else
1997                 connector->polled = DRM_CONNECTOR_POLL_HPD;
1998
1999         connector->display_info.subpixel_order = subpixel_order;
2000
2001         if (has_aux)
2002                 amdgpu_atombios_dp_aux_init(amdgpu_connector);
2003
2004         if (connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
2005             connector_type == DRM_MODE_CONNECTOR_eDP) {
2006                 drm_connector_attach_dp_subconnector_property(&amdgpu_connector->base);
2007         }
2008
2009         return;
2010
2011 failed:
2012         drm_connector_cleanup(connector);
2013         kfree(connector);
2014 }