drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c

   1 /*
   2  * Copyright 2007-8 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: Dave Airlie
  24  *          Alex Deucher
  25  */
  26 #include <drm/drmP.h>
  27 #include <drm/amdgpu_drm.h>
  28 #include "amdgpu.h"
  29 #include "amdgpu_atombios.h"
  30 #include "amdgpu_atomfirmware.h"
  31 #include "amdgpu_i2c.h"
  32
  33 #include "atom.h"
  34 #include "atom-bits.h"
  35 #include "atombios_encoders.h"
  36 #include "bif/bif_4_1_d.h"
  37
  38 static void amdgpu_atombios_lookup_i2c_gpio_quirks(struct amdgpu_device *adev,
  39                                           ATOM_GPIO_I2C_ASSIGMENT *gpio,
  40                                           u8 index)
  41 {
  42
  43 }
  44
  45 static struct amdgpu_i2c_bus_rec amdgpu_atombios_get_bus_rec_for_i2c_gpio(ATOM_GPIO_I2C_ASSIGMENT *gpio)
  46 {
  47         struct amdgpu_i2c_bus_rec i2c;
  48
  49         memset(&i2c, 0, sizeof(struct amdgpu_i2c_bus_rec));
  50
  51         i2c.mask_clk_reg = le16_to_cpu(gpio->usClkMaskRegisterIndex);
  52         i2c.mask_data_reg = le16_to_cpu(gpio->usDataMaskRegisterIndex);
  53         i2c.en_clk_reg = le16_to_cpu(gpio->usClkEnRegisterIndex);
  54         i2c.en_data_reg = le16_to_cpu(gpio->usDataEnRegisterIndex);
  55         i2c.y_clk_reg = le16_to_cpu(gpio->usClkY_RegisterIndex);
  56         i2c.y_data_reg = le16_to_cpu(gpio->usDataY_RegisterIndex);
  57         i2c.a_clk_reg = le16_to_cpu(gpio->usClkA_RegisterIndex);
  58         i2c.a_data_reg = le16_to_cpu(gpio->usDataA_RegisterIndex);
  59         i2c.mask_clk_mask = (1 << gpio->ucClkMaskShift);
  60         i2c.mask_data_mask = (1 << gpio->ucDataMaskShift);
  61         i2c.en_clk_mask = (1 << gpio->ucClkEnShift);
  62         i2c.en_data_mask = (1 << gpio->ucDataEnShift);
  63         i2c.y_clk_mask = (1 << gpio->ucClkY_Shift);
  64         i2c.y_data_mask = (1 << gpio->ucDataY_Shift);
  65         i2c.a_clk_mask = (1 << gpio->ucClkA_Shift);
  66         i2c.a_data_mask = (1 << gpio->ucDataA_Shift);
  67
  68         if (gpio->sucI2cId.sbfAccess.bfHW_Capable)
  69                 i2c.hw_capable = true;
  70         else
  71                 i2c.hw_capable = false;
  72
  73         if (gpio->sucI2cId.ucAccess == 0xa0)
  74                 i2c.mm_i2c = true;
  75         else
  76                 i2c.mm_i2c = false;
  77
  78         i2c.i2c_id = gpio->sucI2cId.ucAccess;
  79
  80         if (i2c.mask_clk_reg)
  81                 i2c.valid = true;
  82         else
  83                 i2c.valid = false;
  84
  85         return i2c;
  86 }
  87
  88 struct amdgpu_i2c_bus_rec amdgpu_atombios_lookup_i2c_gpio(struct amdgpu_device *adev,
  89                                                           uint8_t id)
  90 {
  91         struct atom_context *ctx = adev->mode_info.atom_context;
  92         ATOM_GPIO_I2C_ASSIGMENT *gpio;
  93         struct amdgpu_i2c_bus_rec i2c;
  94         int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
  95         struct _ATOM_GPIO_I2C_INFO *i2c_info;
  96         uint16_t data_offset, size;
  97         int i, num_indices;
  98
  99         memset(&i2c, 0, sizeof(struct amdgpu_i2c_bus_rec));
 100         i2c.valid = false;
 101
 102         if (amdgpu_atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
 103                 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
 104
 105                 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
 106                         sizeof(ATOM_GPIO_I2C_ASSIGMENT);
 107
 108                 gpio = &i2c_info->asGPIO_Info[0];
 109                 for (i = 0; i < num_indices; i++) {
 110
 111                         amdgpu_atombios_lookup_i2c_gpio_quirks(adev, gpio, i);
 112
 113                         if (gpio->sucI2cId.ucAccess == id) {
 114                                 i2c = amdgpu_atombios_get_bus_rec_for_i2c_gpio(gpio);
 115                                 break;
 116                         }
 117                         gpio = (ATOM_GPIO_I2C_ASSIGMENT *)
 118                                 ((u8 *)gpio + sizeof(ATOM_GPIO_I2C_ASSIGMENT));
 119                 }
 120         }
 121
 122         return i2c;
 123 }
 124
 125 void amdgpu_atombios_i2c_init(struct amdgpu_device *adev)
 126 {
 127         struct atom_context *ctx = adev->mode_info.atom_context;
 128         ATOM_GPIO_I2C_ASSIGMENT *gpio;
 129         struct amdgpu_i2c_bus_rec i2c;
 130         int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
 131         struct _ATOM_GPIO_I2C_INFO *i2c_info;
 132         uint16_t data_offset, size;
 133         int i, num_indices;
 134         char stmp[32];
 135
 136         if (amdgpu_atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
 137                 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
 138
 139                 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
 140                         sizeof(ATOM_GPIO_I2C_ASSIGMENT);
 141
 142                 gpio = &i2c_info->asGPIO_Info[0];
 143                 for (i = 0; i < num_indices; i++) {
 144                         amdgpu_atombios_lookup_i2c_gpio_quirks(adev, gpio, i);
 145
 146                         i2c = amdgpu_atombios_get_bus_rec_for_i2c_gpio(gpio);
 147
 148                         if (i2c.valid) {
 149                                 sprintf(stmp, "0x%x", i2c.i2c_id);
 150                                 adev->i2c_bus[i] = amdgpu_i2c_create(adev->ddev, &i2c, stmp);
 151                         }
 152                         gpio = (ATOM_GPIO_I2C_ASSIGMENT *)
 153                                 ((u8 *)gpio + sizeof(ATOM_GPIO_I2C_ASSIGMENT));
 154                 }
 155         }
 156 }
 157
 158 struct amdgpu_gpio_rec
 159 amdgpu_atombios_lookup_gpio(struct amdgpu_device *adev,
 160                             u8 id)
 161 {
 162         struct atom_context *ctx = adev->mode_info.atom_context;
 163         struct amdgpu_gpio_rec gpio;
 164         int index = GetIndexIntoMasterTable(DATA, GPIO_Pin_LUT);
 165         struct _ATOM_GPIO_PIN_LUT *gpio_info;
 166         ATOM_GPIO_PIN_ASSIGNMENT *pin;
 167         u16 data_offset, size;
 168         int i, num_indices;
 169
 170         memset(&gpio, 0, sizeof(struct amdgpu_gpio_rec));
 171         gpio.valid = false;
 172
 173         if (amdgpu_atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
 174                 gpio_info = (struct _ATOM_GPIO_PIN_LUT *)(ctx->bios + data_offset);
 175
 176                 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
 177                         sizeof(ATOM_GPIO_PIN_ASSIGNMENT);
 178
 179                 pin = gpio_info->asGPIO_Pin;
 180                 for (i = 0; i < num_indices; i++) {
 181                         if (id == pin->ucGPIO_ID) {
 182                                 gpio.id = pin->ucGPIO_ID;
 183                                 gpio.reg = le16_to_cpu(pin->usGpioPin_AIndex);
 184                                 gpio.shift = pin->ucGpioPinBitShift;
 185                                 gpio.mask = (1 << pin->ucGpioPinBitShift);
 186                                 gpio.valid = true;
 187                                 break;
 188                         }
 189                         pin = (ATOM_GPIO_PIN_ASSIGNMENT *)
 190                                 ((u8 *)pin + sizeof(ATOM_GPIO_PIN_ASSIGNMENT));
 191                 }
 192         }
 193
 194         return gpio;
 195 }
 196
 197 static struct amdgpu_hpd
 198 amdgpu_atombios_get_hpd_info_from_gpio(struct amdgpu_device *adev,
 199                                        struct amdgpu_gpio_rec *gpio)
 200 {
 201         struct amdgpu_hpd hpd;
 202         u32 reg;
 203
 204         memset(&hpd, 0, sizeof(struct amdgpu_hpd));
 205
 206         reg = amdgpu_display_hpd_get_gpio_reg(adev);
 207
 208         hpd.gpio = *gpio;
 209         if (gpio->reg == reg) {
 210                 switch(gpio->mask) {
 211                 case (1 << 0):
 212                         hpd.hpd = AMDGPU_HPD_1;
 213                         break;
 214                 case (1 << 8):
 215                         hpd.hpd = AMDGPU_HPD_2;
 216                         break;
 217                 case (1 << 16):
 218                         hpd.hpd = AMDGPU_HPD_3;
 219                         break;
 220                 case (1 << 24):
 221                         hpd.hpd = AMDGPU_HPD_4;
 222                         break;
 223                 case (1 << 26):
 224                         hpd.hpd = AMDGPU_HPD_5;
 225                         break;
 226                 case (1 << 28):
 227                         hpd.hpd = AMDGPU_HPD_6;
 228                         break;
 229                 default:
 230                         hpd.hpd = AMDGPU_HPD_NONE;
 231                         break;
 232                 }
 233         } else
 234                 hpd.hpd = AMDGPU_HPD_NONE;
 235         return hpd;
 236 }
 237
 238 static const int object_connector_convert[] = {
 239         DRM_MODE_CONNECTOR_Unknown,
 240         DRM_MODE_CONNECTOR_DVII,
 241         DRM_MODE_CONNECTOR_DVII,
 242         DRM_MODE_CONNECTOR_DVID,
 243         DRM_MODE_CONNECTOR_DVID,
 244         DRM_MODE_CONNECTOR_VGA,
 245         DRM_MODE_CONNECTOR_Composite,
 246         DRM_MODE_CONNECTOR_SVIDEO,
 247         DRM_MODE_CONNECTOR_Unknown,
 248         DRM_MODE_CONNECTOR_Unknown,
 249         DRM_MODE_CONNECTOR_9PinDIN,
 250         DRM_MODE_CONNECTOR_Unknown,
 251         DRM_MODE_CONNECTOR_HDMIA,
 252         DRM_MODE_CONNECTOR_HDMIB,
 253         DRM_MODE_CONNECTOR_LVDS,
 254         DRM_MODE_CONNECTOR_9PinDIN,
 255         DRM_MODE_CONNECTOR_Unknown,
 256         DRM_MODE_CONNECTOR_Unknown,
 257         DRM_MODE_CONNECTOR_Unknown,
 258         DRM_MODE_CONNECTOR_DisplayPort,
 259         DRM_MODE_CONNECTOR_eDP,
 260         DRM_MODE_CONNECTOR_Unknown
 261 };
 262
 263 bool amdgpu_atombios_has_dce_engine_info(struct amdgpu_device *adev)
 264 {
 265         struct amdgpu_mode_info *mode_info = &adev->mode_info;
 266         struct atom_context *ctx = mode_info->atom_context;
 267         int index = GetIndexIntoMasterTable(DATA, Object_Header);
 268         u16 size, data_offset;
 269         u8 frev, crev;
 270         ATOM_DISPLAY_OBJECT_PATH_TABLE *path_obj;
 271         ATOM_OBJECT_HEADER *obj_header;
 272
 273         if (!amdgpu_atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset))
 274                 return false;
 275
 276         if (crev < 2)
 277                 return false;
 278
 279         obj_header = (ATOM_OBJECT_HEADER *) (ctx->bios + data_offset);
 280         path_obj = (ATOM_DISPLAY_OBJECT_PATH_TABLE *)
 281             (ctx->bios + data_offset +
 282              le16_to_cpu(obj_header->usDisplayPathTableOffset));
 283
 284         if (path_obj->ucNumOfDispPath)
 285                 return true;
 286         else
 287                 return false;
 288 }
 289
 290 bool amdgpu_atombios_get_connector_info_from_object_table(struct amdgpu_device *adev)
 291 {
 292         struct amdgpu_mode_info *mode_info = &adev->mode_info;
 293         struct atom_context *ctx = mode_info->atom_context;
 294         int index = GetIndexIntoMasterTable(DATA, Object_Header);
 295         u16 size, data_offset;
 296         u8 frev, crev;
 297         ATOM_CONNECTOR_OBJECT_TABLE *con_obj;
 298         ATOM_ENCODER_OBJECT_TABLE *enc_obj;
 299         ATOM_OBJECT_TABLE *router_obj;
 300         ATOM_DISPLAY_OBJECT_PATH_TABLE *path_obj;
 301         ATOM_OBJECT_HEADER *obj_header;
 302         int i, j, k, path_size, device_support;
 303         int connector_type;
 304         u16 conn_id, connector_object_id;
 305         struct amdgpu_i2c_bus_rec ddc_bus;
 306         struct amdgpu_router router;
 307         struct amdgpu_gpio_rec gpio;
 308         struct amdgpu_hpd hpd;
 309
 310         if (!amdgpu_atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset))
 311                 return false;
 312
 313         if (crev < 2)
 314                 return false;
 315
 316         obj_header = (ATOM_OBJECT_HEADER *) (ctx->bios + data_offset);
 317         path_obj = (ATOM_DISPLAY_OBJECT_PATH_TABLE *)
 318             (ctx->bios + data_offset +
 319              le16_to_cpu(obj_header->usDisplayPathTableOffset));
 320         con_obj = (ATOM_CONNECTOR_OBJECT_TABLE *)
 321             (ctx->bios + data_offset +
 322              le16_to_cpu(obj_header->usConnectorObjectTableOffset));
 323         enc_obj = (ATOM_ENCODER_OBJECT_TABLE *)
 324             (ctx->bios + data_offset +
 325              le16_to_cpu(obj_header->usEncoderObjectTableOffset));
 326         router_obj = (ATOM_OBJECT_TABLE *)
 327                 (ctx->bios + data_offset +
 328                  le16_to_cpu(obj_header->usRouterObjectTableOffset));
 329         device_support = le16_to_cpu(obj_header->usDeviceSupport);
 330
 331         path_size = 0;
 332         for (i = 0; i < path_obj->ucNumOfDispPath; i++) {
 333                 uint8_t *addr = (uint8_t *) path_obj->asDispPath;
 334                 ATOM_DISPLAY_OBJECT_PATH *path;
 335                 addr += path_size;
 336                 path = (ATOM_DISPLAY_OBJECT_PATH *) addr;
 337                 path_size += le16_to_cpu(path->usSize);
 338
 339                 if (device_support & le16_to_cpu(path->usDeviceTag)) {
 340                         uint8_t con_obj_id, con_obj_num, con_obj_type;
 341
 342                         con_obj_id =
 343                             (le16_to_cpu(path->usConnObjectId) & OBJECT_ID_MASK)
 344                             >> OBJECT_ID_SHIFT;
 345                         con_obj_num =
 346                             (le16_to_cpu(path->usConnObjectId) & ENUM_ID_MASK)
 347                             >> ENUM_ID_SHIFT;
 348                         con_obj_type =
 349                             (le16_to_cpu(path->usConnObjectId) &
 350                              OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
 351
 352                         /* Skip TV/CV support */
 353                         if ((le16_to_cpu(path->usDeviceTag) ==
 354                              ATOM_DEVICE_TV1_SUPPORT) ||
 355                             (le16_to_cpu(path->usDeviceTag) ==
 356                              ATOM_DEVICE_CV_SUPPORT))
 357                                 continue;
 358
 359                         if (con_obj_id >= ARRAY_SIZE(object_connector_convert)) {
 360                                 DRM_ERROR("invalid con_obj_id %d for device tag 0x%04x\n",
 361                                           con_obj_id, le16_to_cpu(path->usDeviceTag));
 362                                 continue;
 363                         }
 364
 365                         connector_type =
 366                                 object_connector_convert[con_obj_id];
 367                         connector_object_id = con_obj_id;
 368
 369                         if (connector_type == DRM_MODE_CONNECTOR_Unknown)
 370                                 continue;
 371
 372                         router.ddc_valid = false;
 373                         router.cd_valid = false;
 374                         for (j = 0; j < ((le16_to_cpu(path->usSize) - 8) / 2); j++) {
 375                                 uint8_t grph_obj_id, grph_obj_num, grph_obj_type;
 376
 377                                 grph_obj_id =
 378                                     (le16_to_cpu(path->usGraphicObjIds[j]) &
 379                                      OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
 380                                 grph_obj_num =
 381                                     (le16_to_cpu(path->usGraphicObjIds[j]) &
 382                                      ENUM_ID_MASK) >> ENUM_ID_SHIFT;
 383                                 grph_obj_type =
 384                                     (le16_to_cpu(path->usGraphicObjIds[j]) &
 385                                      OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
 386
 387                                 if (grph_obj_type == GRAPH_OBJECT_TYPE_ENCODER) {
 388                                         for (k = 0; k < enc_obj->ucNumberOfObjects; k++) {
 389                                                 u16 encoder_obj = le16_to_cpu(enc_obj->asObjects[k].usObjectID);
 390                                                 if (le16_to_cpu(path->usGraphicObjIds[j]) == encoder_obj) {
 391                                                         ATOM_COMMON_RECORD_HEADER *record = (ATOM_COMMON_RECORD_HEADER *)
 392                                                                 (ctx->bios + data_offset +
 393                                                                  le16_to_cpu(enc_obj->asObjects[k].usRecordOffset));
 394                                                         ATOM_ENCODER_CAP_RECORD *cap_record;
 395                                                         u16 caps = 0;
 396
 397                                                         while (record->ucRecordSize > 0 &&
 398                                                                record->ucRecordType > 0 &&
 399                                                                record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
 400                                                                 switch (record->ucRecordType) {
 401                                                                 case ATOM_ENCODER_CAP_RECORD_TYPE:
 402                                                                         cap_record =(ATOM_ENCODER_CAP_RECORD *)
 403                                                                                 record;
 404                                                                         caps = le16_to_cpu(cap_record->usEncoderCap);
 405                                                                         break;
 406                                                                 }
 407                                                                 record = (ATOM_COMMON_RECORD_HEADER *)
 408                                                                         ((char *)record + record->ucRecordSize);
 409                                                         }
 410                                                         amdgpu_display_add_encoder(adev, encoder_obj,
 411                                                                                     le16_to_cpu(path->usDeviceTag),
 412                                                                                     caps);
 413                                                 }
 414                                         }
 415                                 } else if (grph_obj_type == GRAPH_OBJECT_TYPE_ROUTER) {
 416                                         for (k = 0; k < router_obj->ucNumberOfObjects; k++) {
 417                                                 u16 router_obj_id = le16_to_cpu(router_obj->asObjects[k].usObjectID);
 418                                                 if (le16_to_cpu(path->usGraphicObjIds[j]) == router_obj_id) {
 419                                                         ATOM_COMMON_RECORD_HEADER *record = (ATOM_COMMON_RECORD_HEADER *)
 420                                                                 (ctx->bios + data_offset +
 421                                                                  le16_to_cpu(router_obj->asObjects[k].usRecordOffset));
 422                                                         ATOM_I2C_RECORD *i2c_record;
 423                                                         ATOM_I2C_ID_CONFIG_ACCESS *i2c_config;
 424                                                         ATOM_ROUTER_DDC_PATH_SELECT_RECORD *ddc_path;
 425                                                         ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD *cd_path;
 426                                                         ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *router_src_dst_table =
 427                                                                 (ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *)
 428                                                                 (ctx->bios + data_offset +
 429                                                                  le16_to_cpu(router_obj->asObjects[k].usSrcDstTableOffset));
 430                                                         u8 *num_dst_objs = (u8 *)
 431                                                                 ((u8 *)router_src_dst_table + 1 +
 432                                                                  (router_src_dst_table->ucNumberOfSrc * 2));
 433                                                         u16 *dst_objs = (u16 *)(num_dst_objs + 1);
 434                                                         int enum_id;
 435
 436                                                         router.router_id = router_obj_id;
 437                                                         for (enum_id = 0; enum_id < (*num_dst_objs); enum_id++) {
 438                                                                 if (le16_to_cpu(path->usConnObjectId) ==
 439                                                                     le16_to_cpu(dst_objs[enum_id]))
 440                                                                         break;
 441                                                         }
 442
 443                                                         while (record->ucRecordSize > 0 &&
 444                                                                record->ucRecordType > 0 &&
 445                                                                record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
 446                                                                 switch (record->ucRecordType) {
 447                                                                 case ATOM_I2C_RECORD_TYPE:
 448                                                                         i2c_record =
 449                                                                                 (ATOM_I2C_RECORD *)
 450                                                                                 record;
 451                                                                         i2c_config =
 452                                                                                 (ATOM_I2C_ID_CONFIG_ACCESS *)
 453                                                                                 &i2c_record->sucI2cId;
 454                                                                         router.i2c_info =
 455                                                                                 amdgpu_atombios_lookup_i2c_gpio(adev,
 456                                                                                                        i2c_config->
 457                                                                                                        ucAccess);
 458                                                                         router.i2c_addr = i2c_record->ucI2CAddr >> 1;
 459                                                                         break;
 460                                                                 case ATOM_ROUTER_DDC_PATH_SELECT_RECORD_TYPE:
 461                                                                         ddc_path = (ATOM_ROUTER_DDC_PATH_SELECT_RECORD *)
 462                                                                                 record;
 463                                                                         router.ddc_valid = true;
 464                                                                         router.ddc_mux_type = ddc_path->ucMuxType;
 465                                                                         router.ddc_mux_control_pin = ddc_path->ucMuxControlPin;
 466                                                                         router.ddc_mux_state = ddc_path->ucMuxState[enum_id];
 467                                                                         break;
 468                                                                 case ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD_TYPE:
 469                                                                         cd_path = (ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD *)
 470                                                                                 record;
 471                                                                         router.cd_valid = true;
 472                                                                         router.cd_mux_type = cd_path->ucMuxType;
 473                                                                         router.cd_mux_control_pin = cd_path->ucMuxControlPin;
 474                                                                         router.cd_mux_state = cd_path->ucMuxState[enum_id];
 475                                                                         break;
 476                                                                 }
 477                                                                 record = (ATOM_COMMON_RECORD_HEADER *)
 478                                                                         ((char *)record + record->ucRecordSize);
 479                                                         }
 480                                                 }
 481                                         }
 482                                 }
 483                         }
 484
 485                         /* look up gpio for ddc, hpd */
 486                         ddc_bus.valid = false;
 487                         hpd.hpd = AMDGPU_HPD_NONE;
 488                         if ((le16_to_cpu(path->usDeviceTag) &
 489                              (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) == 0) {
 490                                 for (j = 0; j < con_obj->ucNumberOfObjects; j++) {
 491                                         if (le16_to_cpu(path->usConnObjectId) ==
 492                                             le16_to_cpu(con_obj->asObjects[j].
 493                                                         usObjectID)) {
 494                                                 ATOM_COMMON_RECORD_HEADER
 495                                                     *record =
 496                                                     (ATOM_COMMON_RECORD_HEADER
 497                                                      *)
 498                                                     (ctx->bios + data_offset +
 499                                                      le16_to_cpu(con_obj->
 500                                                                  asObjects[j].
 501                                                                  usRecordOffset));
 502                                                 ATOM_I2C_RECORD *i2c_record;
 503                                                 ATOM_HPD_INT_RECORD *hpd_record;
 504                                                 ATOM_I2C_ID_CONFIG_ACCESS *i2c_config;
 505
 506                                                 while (record->ucRecordSize > 0 &&
 507                                                        record->ucRecordType > 0 &&
 508                                                        record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
 509                                                         switch (record->ucRecordType) {
 510                                                         case ATOM_I2C_RECORD_TYPE:
 511                                                                 i2c_record =
 512                                                                     (ATOM_I2C_RECORD *)
 513                                                                         record;
 514                                                                 i2c_config =
 515                                                                         (ATOM_I2C_ID_CONFIG_ACCESS *)
 516                                                                         &i2c_record->sucI2cId;
 517                                                                 ddc_bus = amdgpu_atombios_lookup_i2c_gpio(adev,
 518                                                                                                  i2c_config->
 519                                                                                                  ucAccess);
 520                                                                 break;
 521                                                         case ATOM_HPD_INT_RECORD_TYPE:
 522                                                                 hpd_record =
 523                                                                         (ATOM_HPD_INT_RECORD *)
 524                                                                         record;
 525                                                                 gpio = amdgpu_atombios_lookup_gpio(adev,
 526                                                                                           hpd_record->ucHPDIntGPIOID);
 527                                                                 hpd = amdgpu_atombios_get_hpd_info_from_gpio(adev, &gpio);
 528                                                                 hpd.plugged_state = hpd_record->ucPlugged_PinState;
 529                                                                 break;
 530                                                         }
 531                                                         record =
 532                                                             (ATOM_COMMON_RECORD_HEADER
 533                                                              *) ((char *)record
 534                                                                  +
 535                                                                  record->
 536                                                                  ucRecordSize);
 537                                                 }
 538                                                 break;
 539                                         }
 540                                 }
 541                         }
 542
 543                         /* needed for aux chan transactions */
 544                         ddc_bus.hpd = hpd.hpd;
 545
 546                         conn_id = le16_to_cpu(path->usConnObjectId);
 547
 548                         amdgpu_display_add_connector(adev,
 549                                                       conn_id,
 550                                                       le16_to_cpu(path->usDeviceTag),
 551                                                       connector_type, &ddc_bus,
 552                                                       connector_object_id,
 553                                                       &hpd,
 554                                                       &router);
 555
 556                 }
 557         }
 558
 559         amdgpu_link_encoder_connector(adev->ddev);
 560
 561         return true;
 562 }
 563
 564 union firmware_info {
 565         ATOM_FIRMWARE_INFO info;
 566         ATOM_FIRMWARE_INFO_V1_2 info_12;
 567         ATOM_FIRMWARE_INFO_V1_3 info_13;
 568         ATOM_FIRMWARE_INFO_V1_4 info_14;
 569         ATOM_FIRMWARE_INFO_V2_1 info_21;
 570         ATOM_FIRMWARE_INFO_V2_2 info_22;
 571 };
 572
 573 int amdgpu_atombios_get_clock_info(struct amdgpu_device *adev)
 574 {
 575         struct amdgpu_mode_info *mode_info = &adev->mode_info;
 576         int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
 577         uint8_t frev, crev;
 578         uint16_t data_offset;
 579         int ret = -EINVAL;
 580
 581         if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,
 582                                    &frev, &crev, &data_offset)) {
 583                 int i;
 584                 struct amdgpu_pll *ppll = &adev->clock.ppll[0];
 585                 struct amdgpu_pll *spll = &adev->clock.spll;
 586                 struct amdgpu_pll *mpll = &adev->clock.mpll;
 587                 union firmware_info *firmware_info =
 588                         (union firmware_info *)(mode_info->atom_context->bios +
 589                                                 data_offset);
 590                 /* pixel clocks */
 591                 ppll->reference_freq =
 592                     le16_to_cpu(firmware_info->info.usReferenceClock);
 593                 ppll->reference_div = 0;
 594
 595                 ppll->pll_out_min =
 596                         le32_to_cpu(firmware_info->info_12.ulMinPixelClockPLL_Output);
 597                 ppll->pll_out_max =
 598                     le32_to_cpu(firmware_info->info.ulMaxPixelClockPLL_Output);
 599
 600                 ppll->lcd_pll_out_min =
 601                         le16_to_cpu(firmware_info->info_14.usLcdMinPixelClockPLL_Output) * 100;
 602                 if (ppll->lcd_pll_out_min == 0)
 603                         ppll->lcd_pll_out_min = ppll->pll_out_min;
 604                 ppll->lcd_pll_out_max =
 605                         le16_to_cpu(firmware_info->info_14.usLcdMaxPixelClockPLL_Output) * 100;
 606                 if (ppll->lcd_pll_out_max == 0)
 607                         ppll->lcd_pll_out_max = ppll->pll_out_max;
 608
 609                 if (ppll->pll_out_min == 0)
 610                         ppll->pll_out_min = 64800;
 611
 612                 ppll->pll_in_min =
 613                     le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Input);
 614                 ppll->pll_in_max =
 615                     le16_to_cpu(firmware_info->info.usMaxPixelClockPLL_Input);
 616
 617                 ppll->min_post_div = 2;
 618                 ppll->max_post_div = 0x7f;
 619                 ppll->min_frac_feedback_div = 0;
 620                 ppll->max_frac_feedback_div = 9;
 621                 ppll->min_ref_div = 2;
 622                 ppll->max_ref_div = 0x3ff;
 623                 ppll->min_feedback_div = 4;
 624                 ppll->max_feedback_div = 0xfff;
 625                 ppll->best_vco = 0;
 626
 627                 for (i = 1; i < AMDGPU_MAX_PPLL; i++)
 628                         adev->clock.ppll[i] = *ppll;
 629
 630                 /* system clock */
 631                 spll->reference_freq =
 632                         le16_to_cpu(firmware_info->info_21.usCoreReferenceClock);
 633                 spll->reference_div = 0;
 634
 635                 spll->pll_out_min =
 636                     le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Output);
 637                 spll->pll_out_max =
 638                     le32_to_cpu(firmware_info->info.ulMaxEngineClockPLL_Output);
 639
 640                 /* ??? */
 641                 if (spll->pll_out_min == 0)
 642                         spll->pll_out_min = 64800;
 643
 644                 spll->pll_in_min =
 645                     le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Input);
 646                 spll->pll_in_max =
 647                     le16_to_cpu(firmware_info->info.usMaxEngineClockPLL_Input);
 648
 649                 spll->min_post_div = 1;
 650                 spll->max_post_div = 1;
 651                 spll->min_ref_div = 2;
 652                 spll->max_ref_div = 0xff;
 653                 spll->min_feedback_div = 4;
 654                 spll->max_feedback_div = 0xff;
 655                 spll->best_vco = 0;
 656
 657                 /* memory clock */
 658                 mpll->reference_freq =
 659                         le16_to_cpu(firmware_info->info_21.usMemoryReferenceClock);
 660                 mpll->reference_div = 0;
 661
 662                 mpll->pll_out_min =
 663                     le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Output);
 664                 mpll->pll_out_max =
 665                     le32_to_cpu(firmware_info->info.ulMaxMemoryClockPLL_Output);
 666
 667                 /* ??? */
 668                 if (mpll->pll_out_min == 0)
 669                         mpll->pll_out_min = 64800;
 670
 671                 mpll->pll_in_min =
 672                     le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Input);
 673                 mpll->pll_in_max =
 674                     le16_to_cpu(firmware_info->info.usMaxMemoryClockPLL_Input);
 675
 676                 adev->clock.default_sclk =
 677                     le32_to_cpu(firmware_info->info.ulDefaultEngineClock);
 678                 adev->clock.default_mclk =
 679                     le32_to_cpu(firmware_info->info.ulDefaultMemoryClock);
 680
 681                 mpll->min_post_div = 1;
 682                 mpll->max_post_div = 1;
 683                 mpll->min_ref_div = 2;
 684                 mpll->max_ref_div = 0xff;
 685                 mpll->min_feedback_div = 4;
 686                 mpll->max_feedback_div = 0xff;
 687                 mpll->best_vco = 0;
 688
 689                 /* disp clock */
 690                 adev->clock.default_dispclk =
 691                         le32_to_cpu(firmware_info->info_21.ulDefaultDispEngineClkFreq);
 692                 /* set a reasonable default for DP */
 693                 if (adev->clock.default_dispclk < 53900) {
 694                         DRM_DEBUG("Changing default dispclk from %dMhz to 600Mhz\n",
 695                                   adev->clock.default_dispclk / 100);
 696                         adev->clock.default_dispclk = 60000;
 697                 } else if (adev->clock.default_dispclk <= 60000) {
 698                         DRM_DEBUG("Changing default dispclk from %dMhz to 625Mhz\n",
 699                                   adev->clock.default_dispclk / 100);
 700                         adev->clock.default_dispclk = 62500;
 701                 }
 702                 adev->clock.dp_extclk =
 703                         le16_to_cpu(firmware_info->info_21.usUniphyDPModeExtClkFreq);
 704                 adev->clock.current_dispclk = adev->clock.default_dispclk;
 705
 706                 adev->clock.max_pixel_clock = le16_to_cpu(firmware_info->info.usMaxPixelClock);
 707                 if (adev->clock.max_pixel_clock == 0)
 708                         adev->clock.max_pixel_clock = 40000;
 709
 710                 /* not technically a clock, but... */
 711                 adev->mode_info.firmware_flags =
 712                         le16_to_cpu(firmware_info->info.usFirmwareCapability.susAccess);
 713
 714                 ret = 0;
 715         }
 716
 717         adev->pm.current_sclk = adev->clock.default_sclk;
 718         adev->pm.current_mclk = adev->clock.default_mclk;
 719
 720         return ret;
 721 }
 722
 723 union gfx_info {
 724         ATOM_GFX_INFO_V2_1 info;
 725 };
 726
 727 int amdgpu_atombios_get_gfx_info(struct amdgpu_device *adev)
 728 {
 729         struct amdgpu_mode_info *mode_info = &adev->mode_info;
 730         int index = GetIndexIntoMasterTable(DATA, GFX_Info);
 731         uint8_t frev, crev;
 732         uint16_t data_offset;
 733         int ret = -EINVAL;
 734
 735         if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,
 736                                    &frev, &crev, &data_offset)) {
 737                 union gfx_info *gfx_info = (union gfx_info *)
 738                         (mode_info->atom_context->bios + data_offset);
 739
 740                 adev->gfx.config.max_shader_engines = gfx_info->info.max_shader_engines;
 741                 adev->gfx.config.max_tile_pipes = gfx_info->info.max_tile_pipes;
 742                 adev->gfx.config.max_cu_per_sh = gfx_info->info.max_cu_per_sh;
 743                 adev->gfx.config.max_sh_per_se = gfx_info->info.max_sh_per_se;
 744                 adev->gfx.config.max_backends_per_se = gfx_info->info.max_backends_per_se;
 745                 adev->gfx.config.max_texture_channel_caches =
 746                         gfx_info->info.max_texture_channel_caches;
 747
 748                 ret = 0;
 749         }
 750         return ret;
 751 }
 752
 753 union igp_info {
 754         struct _ATOM_INTEGRATED_SYSTEM_INFO info;
 755         struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_2;
 756         struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 info_6;
 757         struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_7 info_7;
 758         struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_8 info_8;
 759         struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_9 info_9;
 760 };
 761
 762 /*
 763  * Return vram width from integrated system info table, if available,
 764  * or 0 if not.
 765  */
 766 int amdgpu_atombios_get_vram_width(struct amdgpu_device *adev)
 767 {
 768         struct amdgpu_mode_info *mode_info = &adev->mode_info;
 769         int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
 770         u16 data_offset, size;
 771         union igp_info *igp_info;
 772         u8 frev, crev;
 773
 774         /* get any igp specific overrides */
 775         if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, &size,
 776                                    &frev, &crev, &data_offset)) {
 777                 igp_info = (union igp_info *)
 778                         (mode_info->atom_context->bios + data_offset);
 779                 switch (crev) {
 780                 case 8:
 781                 case 9:
 782                         return igp_info->info_8.ucUMAChannelNumber * 64;
 783                 default:
 784                         return 0;
 785                 }
 786         }
 787
 788         return 0;
 789 }
 790
 791 static void amdgpu_atombios_get_igp_ss_overrides(struct amdgpu_device *adev,
 792                                                  struct amdgpu_atom_ss *ss,
 793                                                  int id)
 794 {
 795         struct amdgpu_mode_info *mode_info = &adev->mode_info;
 796         int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
 797         u16 data_offset, size;
 798         union igp_info *igp_info;
 799         u8 frev, crev;
 800         u16 percentage = 0, rate = 0;
 801
 802         /* get any igp specific overrides */
 803         if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, &size,
 804                                    &frev, &crev, &data_offset)) {
 805                 igp_info = (union igp_info *)
 806                         (mode_info->atom_context->bios + data_offset);
 807                 switch (crev) {
 808                 case 6:
 809                         switch (id) {
 810                         case ASIC_INTERNAL_SS_ON_TMDS:
 811                                 percentage = le16_to_cpu(igp_info->info_6.usDVISSPercentage);
 812                                 rate = le16_to_cpu(igp_info->info_6.usDVISSpreadRateIn10Hz);
 813                                 break;
 814                         case ASIC_INTERNAL_SS_ON_HDMI:
 815                                 percentage = le16_to_cpu(igp_info->info_6.usHDMISSPercentage);
 816                                 rate = le16_to_cpu(igp_info->info_6.usHDMISSpreadRateIn10Hz);
 817                                 break;
 818                         case ASIC_INTERNAL_SS_ON_LVDS:
 819                                 percentage = le16_to_cpu(igp_info->info_6.usLvdsSSPercentage);
 820                                 rate = le16_to_cpu(igp_info->info_6.usLvdsSSpreadRateIn10Hz);
 821                                 break;
 822                         }
 823                         break;
 824                 case 7:
 825                         switch (id) {
 826                         case ASIC_INTERNAL_SS_ON_TMDS:
 827                                 percentage = le16_to_cpu(igp_info->info_7.usDVISSPercentage);
 828                                 rate = le16_to_cpu(igp_info->info_7.usDVISSpreadRateIn10Hz);
 829                                 break;
 830                         case ASIC_INTERNAL_SS_ON_HDMI:
 831                                 percentage = le16_to_cpu(igp_info->info_7.usHDMISSPercentage);
 832                                 rate = le16_to_cpu(igp_info->info_7.usHDMISSpreadRateIn10Hz);
 833                                 break;
 834                         case ASIC_INTERNAL_SS_ON_LVDS:
 835                                 percentage = le16_to_cpu(igp_info->info_7.usLvdsSSPercentage);
 836                                 rate = le16_to_cpu(igp_info->info_7.usLvdsSSpreadRateIn10Hz);
 837                                 break;
 838                         }
 839                         break;
 840                 case 8:
 841                         switch (id) {
 842                         case ASIC_INTERNAL_SS_ON_TMDS:
 843                                 percentage = le16_to_cpu(igp_info->info_8.usDVISSPercentage);
 844                                 rate = le16_to_cpu(igp_info->info_8.usDVISSpreadRateIn10Hz);
 845                                 break;
 846                         case ASIC_INTERNAL_SS_ON_HDMI:
 847                                 percentage = le16_to_cpu(igp_info->info_8.usHDMISSPercentage);
 848                                 rate = le16_to_cpu(igp_info->info_8.usHDMISSpreadRateIn10Hz);
 849                                 break;
 850                         case ASIC_INTERNAL_SS_ON_LVDS:
 851                                 percentage = le16_to_cpu(igp_info->info_8.usLvdsSSPercentage);
 852                                 rate = le16_to_cpu(igp_info->info_8.usLvdsSSpreadRateIn10Hz);
 853                                 break;
 854                         }
 855                         break;
 856                 case 9:
 857                         switch (id) {
 858                         case ASIC_INTERNAL_SS_ON_TMDS:
 859                                 percentage = le16_to_cpu(igp_info->info_9.usDVISSPercentage);
 860                                 rate = le16_to_cpu(igp_info->info_9.usDVISSpreadRateIn10Hz);
 861                                 break;
 862                         case ASIC_INTERNAL_SS_ON_HDMI:
 863                                 percentage = le16_to_cpu(igp_info->info_9.usHDMISSPercentage);
 864                                 rate = le16_to_cpu(igp_info->info_9.usHDMISSpreadRateIn10Hz);
 865                                 break;
 866                         case ASIC_INTERNAL_SS_ON_LVDS:
 867                                 percentage = le16_to_cpu(igp_info->info_9.usLvdsSSPercentage);
 868                                 rate = le16_to_cpu(igp_info->info_9.usLvdsSSpreadRateIn10Hz);
 869                                 break;
 870                         }
 871                         break;
 872                 default:
 873                         DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev);
 874                         break;
 875                 }
 876                 if (percentage)
 877                         ss->percentage = percentage;
 878                 if (rate)
 879                         ss->rate = rate;
 880         }
 881 }
 882
 883 union asic_ss_info {
 884         struct _ATOM_ASIC_INTERNAL_SS_INFO info;
 885         struct _ATOM_ASIC_INTERNAL_SS_INFO_V2 info_2;
 886         struct _ATOM_ASIC_INTERNAL_SS_INFO_V3 info_3;
 887 };
 888
 889 union asic_ss_assignment {
 890         struct _ATOM_ASIC_SS_ASSIGNMENT v1;
 891         struct _ATOM_ASIC_SS_ASSIGNMENT_V2 v2;
 892         struct _ATOM_ASIC_SS_ASSIGNMENT_V3 v3;
 893 };
 894
 895 bool amdgpu_atombios_get_asic_ss_info(struct amdgpu_device *adev,
 896                                       struct amdgpu_atom_ss *ss,
 897                                       int id, u32 clock)
 898 {
 899         struct amdgpu_mode_info *mode_info = &adev->mode_info;
 900         int index = GetIndexIntoMasterTable(DATA, ASIC_InternalSS_Info);
 901         uint16_t data_offset, size;
 902         union asic_ss_info *ss_info;
 903         union asic_ss_assignment *ss_assign;
 904         uint8_t frev, crev;
 905         int i, num_indices;
 906
 907         if (id == ASIC_INTERNAL_MEMORY_SS) {
 908                 if (!(adev->mode_info.firmware_flags & ATOM_BIOS_INFO_MEMORY_CLOCK_SS_SUPPORT))
 909                         return false;
 910         }
 911         if (id == ASIC_INTERNAL_ENGINE_SS) {
 912                 if (!(adev->mode_info.firmware_flags & ATOM_BIOS_INFO_ENGINE_CLOCK_SS_SUPPORT))
 913                         return false;
 914         }
 915
 916         memset(ss, 0, sizeof(struct amdgpu_atom_ss));
 917         if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, &size,
 918                                    &frev, &crev, &data_offset)) {
 919
 920                 ss_info =
 921                         (union asic_ss_info *)(mode_info->atom_context->bios + data_offset);
 922
 923                 switch (frev) {
 924                 case 1:
 925                         num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
 926                                 sizeof(ATOM_ASIC_SS_ASSIGNMENT);
 927
 928                         ss_assign = (union asic_ss_assignment *)((u8 *)&ss_info->info.asSpreadSpectrum[0]);
 929                         for (i = 0; i < num_indices; i++) {
 930                                 if ((ss_assign->v1.ucClockIndication == id) &&
 931                                     (clock <= le32_to_cpu(ss_assign->v1.ulTargetClockRange))) {
 932                                         ss->percentage =
 933                                                 le16_to_cpu(ss_assign->v1.usSpreadSpectrumPercentage);
 934                                         ss->type = ss_assign->v1.ucSpreadSpectrumMode;
 935                                         ss->rate = le16_to_cpu(ss_assign->v1.usSpreadRateInKhz);
 936                                         ss->percentage_divider = 100;
 937                                         return true;
 938                                 }
 939                                 ss_assign = (union asic_ss_assignment *)
 940                                         ((u8 *)ss_assign + sizeof(ATOM_ASIC_SS_ASSIGNMENT));
 941                         }
 942                         break;
 943                 case 2:
 944                         num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
 945                                 sizeof(ATOM_ASIC_SS_ASSIGNMENT_V2);
 946                         ss_assign = (union asic_ss_assignment *)((u8 *)&ss_info->info_2.asSpreadSpectrum[0]);
 947                         for (i = 0; i < num_indices; i++) {
 948                                 if ((ss_assign->v2.ucClockIndication == id) &&
 949                                     (clock <= le32_to_cpu(ss_assign->v2.ulTargetClockRange))) {
 950                                         ss->percentage =
 951                                                 le16_to_cpu(ss_assign->v2.usSpreadSpectrumPercentage);
 952                                         ss->type = ss_assign->v2.ucSpreadSpectrumMode;
 953                                         ss->rate = le16_to_cpu(ss_assign->v2.usSpreadRateIn10Hz);
 954                                         ss->percentage_divider = 100;
 955                                         if ((crev == 2) &&
 956                                             ((id == ASIC_INTERNAL_ENGINE_SS) ||
 957                                              (id == ASIC_INTERNAL_MEMORY_SS)))
 958                                                 ss->rate /= 100;
 959                                         return true;
 960                                 }
 961                                 ss_assign = (union asic_ss_assignment *)
 962                                         ((u8 *)ss_assign + sizeof(ATOM_ASIC_SS_ASSIGNMENT_V2));
 963                         }
 964                         break;
 965                 case 3:
 966                         num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
 967                                 sizeof(ATOM_ASIC_SS_ASSIGNMENT_V3);
 968                         ss_assign = (union asic_ss_assignment *)((u8 *)&ss_info->info_3.asSpreadSpectrum[0]);
 969                         for (i = 0; i < num_indices; i++) {
 970                                 if ((ss_assign->v3.ucClockIndication == id) &&
 971                                     (clock <= le32_to_cpu(ss_assign->v3.ulTargetClockRange))) {
 972                                         ss->percentage =
 973                                                 le16_to_cpu(ss_assign->v3.usSpreadSpectrumPercentage);
 974                                         ss->type = ss_assign->v3.ucSpreadSpectrumMode;
 975                                         ss->rate = le16_to_cpu(ss_assign->v3.usSpreadRateIn10Hz);
 976                                         if (ss_assign->v3.ucSpreadSpectrumMode &
 977                                             SS_MODE_V3_PERCENTAGE_DIV_BY_1000_MASK)
 978                                                 ss->percentage_divider = 1000;
 979                                         else
 980                                                 ss->percentage_divider = 100;
 981                                         if ((id == ASIC_INTERNAL_ENGINE_SS) ||
 982                                             (id == ASIC_INTERNAL_MEMORY_SS))
 983                                                 ss->rate /= 100;
 984                                         if (adev->flags & AMD_IS_APU)
 985                                                 amdgpu_atombios_get_igp_ss_overrides(adev, ss, id);
 986                                         return true;
 987                                 }
 988                                 ss_assign = (union asic_ss_assignment *)
 989                                         ((u8 *)ss_assign + sizeof(ATOM_ASIC_SS_ASSIGNMENT_V3));
 990                         }
 991                         break;
 992                 default:
 993                         DRM_ERROR("Unsupported ASIC_InternalSS_Info table: %d %d\n", frev, crev);
 994                         break;
 995                 }
 996
 997         }
 998         return false;
 999 }
1000
1001 union get_clock_dividers {
1002         struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS v1;
1003         struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V2 v2;
1004         struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V3 v3;
1005         struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4 v4;
1006         struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V5 v5;
1007         struct _COMPUTE_GPU_CLOCK_INPUT_PARAMETERS_V1_6 v6_in;
1008         struct _COMPUTE_GPU_CLOCK_OUTPUT_PARAMETERS_V1_6 v6_out;
1009 };
1010
1011 int amdgpu_atombios_get_clock_dividers(struct amdgpu_device *adev,
1012                                        u8 clock_type,
1013                                        u32 clock,
1014                                        bool strobe_mode,
1015                                        struct atom_clock_dividers *dividers)
1016 {
1017         union get_clock_dividers args;
1018         int index = GetIndexIntoMasterTable(COMMAND, ComputeMemoryEnginePLL);
1019         u8 frev, crev;
1020
1021         memset(&args, 0, sizeof(args));
1022         memset(dividers, 0, sizeof(struct atom_clock_dividers));
1023
1024         if (!amdgpu_atom_parse_cmd_header(adev->mode_info.atom_context, index, &frev, &crev))
1025                 return -EINVAL;
1026
1027         switch (crev) {
1028         case 2:
1029         case 3:
1030         case 5:
1031                 /* r6xx, r7xx, evergreen, ni, si.
1032                  * TODO: add support for asic_type <= CHIP_RV770*/
1033                 if (clock_type == COMPUTE_ENGINE_PLL_PARAM) {
1034                         args.v3.ulClockParams = cpu_to_le32((clock_type << 24) | clock);
1035
1036                         amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
1037
1038                         dividers->post_div = args.v3.ucPostDiv;
1039                         dividers->enable_post_div = (args.v3.ucCntlFlag &
1040                                                      ATOM_PLL_CNTL_FLAG_PLL_POST_DIV_EN) ? true : false;
1041                         dividers->enable_dithen = (args.v3.ucCntlFlag &
1042                                                    ATOM_PLL_CNTL_FLAG_FRACTION_DISABLE) ? false : true;
1043                         dividers->whole_fb_div = le16_to_cpu(args.v3.ulFbDiv.usFbDiv);
1044                         dividers->frac_fb_div = le16_to_cpu(args.v3.ulFbDiv.usFbDivFrac);
1045                         dividers->ref_div = args.v3.ucRefDiv;
1046                         dividers->vco_mode = (args.v3.ucCntlFlag &
1047                                               ATOM_PLL_CNTL_FLAG_MPLL_VCO_MODE) ? 1 : 0;
1048                 } else {
1049                         /* for SI we use ComputeMemoryClockParam for memory plls */
1050                         if (adev->asic_type >= CHIP_TAHITI)
1051                                 return -EINVAL;
1052                         args.v5.ulClockParams = cpu_to_le32((clock_type << 24) | clock);
1053                         if (strobe_mode)
1054                                 args.v5.ucInputFlag = ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN;
1055
1056                         amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
1057
1058                         dividers->post_div = args.v5.ucPostDiv;
1059                         dividers->enable_post_div = (args.v5.ucCntlFlag &
1060                                                      ATOM_PLL_CNTL_FLAG_PLL_POST_DIV_EN) ? true : false;
1061                         dividers->enable_dithen = (args.v5.ucCntlFlag &
1062                                                    ATOM_PLL_CNTL_FLAG_FRACTION_DISABLE) ? false : true;
1063                         dividers->whole_fb_div = le16_to_cpu(args.v5.ulFbDiv.usFbDiv);
1064                         dividers->frac_fb_div = le16_to_cpu(args.v5.ulFbDiv.usFbDivFrac);
1065                         dividers->ref_div = args.v5.ucRefDiv;
1066                         dividers->vco_mode = (args.v5.ucCntlFlag &
1067                                               ATOM_PLL_CNTL_FLAG_MPLL_VCO_MODE) ? 1 : 0;
1068                 }
1069                 break;
1070         case 4:
1071                 /* fusion */
1072                 args.v4.ulClock = cpu_to_le32(clock);   /* 10 khz */
1073
1074                 amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
1075
1076                 dividers->post_divider = dividers->post_div = args.v4.ucPostDiv;
1077                 dividers->real_clock = le32_to_cpu(args.v4.ulClock);
1078                 break;
1079         case 6:
1080                 /* CI */
1081                 /* COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK, COMPUTE_GPUCLK_INPUT_FLAG_SCLK */
1082                 args.v6_in.ulClock.ulComputeClockFlag = clock_type;
1083                 args.v6_in.ulClock.ulClockFreq = cpu_to_le32(clock);    /* 10 khz */
1084
1085                 amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
1086
1087                 dividers->whole_fb_div = le16_to_cpu(args.v6_out.ulFbDiv.usFbDiv);
1088                 dividers->frac_fb_div = le16_to_cpu(args.v6_out.ulFbDiv.usFbDivFrac);
1089                 dividers->ref_div = args.v6_out.ucPllRefDiv;
1090                 dividers->post_div = args.v6_out.ucPllPostDiv;
1091                 dividers->flags = args.v6_out.ucPllCntlFlag;
1092                 dividers->real_clock = le32_to_cpu(args.v6_out.ulClock.ulClock);
1093                 dividers->post_divider = args.v6_out.ulClock.ucPostDiv;
1094                 break;
1095         default:
1096                 return -EINVAL;
1097         }
1098         return 0;
1099 }
1100
1101 int amdgpu_atombios_get_memory_pll_dividers(struct amdgpu_device *adev,
1102                                             u32 clock,
1103                                             bool strobe_mode,
1104                                             struct atom_mpll_param *mpll_param)
1105 {
1106         COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_1 args;
1107         int index = GetIndexIntoMasterTable(COMMAND, ComputeMemoryClockParam);
1108         u8 frev, crev;
1109
1110         memset(&args, 0, sizeof(args));
1111         memset(mpll_param, 0, sizeof(struct atom_mpll_param));
1112
1113         if (!amdgpu_atom_parse_cmd_header(adev->mode_info.atom_context, index, &frev, &crev))
1114                 return -EINVAL;
1115
1116         switch (frev) {
1117         case 2:
1118                 switch (crev) {
1119                 case 1:
1120                         /* SI */
1121                         args.ulClock = cpu_to_le32(clock);      /* 10 khz */
1122                         args.ucInputFlag = 0;
1123                         if (strobe_mode)
1124                                 args.ucInputFlag |= MPLL_INPUT_FLAG_STROBE_MODE_EN;
1125
1126                         amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
1127
1128                         mpll_param->clkfrac = le16_to_cpu(args.ulFbDiv.usFbDivFrac);
1129                         mpll_param->clkf = le16_to_cpu(args.ulFbDiv.usFbDiv);
1130                         mpll_param->post_div = args.ucPostDiv;
1131                         mpll_param->dll_speed = args.ucDllSpeed;
1132                         mpll_param->bwcntl = args.ucBWCntl;
1133                         mpll_param->vco_mode =
1134                                 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_VCO_MODE_MASK);
1135                         mpll_param->yclk_sel =
1136                                 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_BYPASS_DQ_PLL) ? 1 : 0;
1137                         mpll_param->qdr =
1138                                 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_QDR_ENABLE) ? 1 : 0;
1139                         mpll_param->half_rate =
1140                                 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_AD_HALF_RATE) ? 1 : 0;
1141                         break;
1142                 default:
1143                         return -EINVAL;
1144                 }
1145                 break;
1146         default:
1147                 return -EINVAL;
1148         }
1149         return 0;
1150 }
1151
1152 void amdgpu_atombios_set_engine_dram_timings(struct amdgpu_device *adev,
1153                                              u32 eng_clock, u32 mem_clock)
1154 {
1155         SET_ENGINE_CLOCK_PS_ALLOCATION args;
1156         int index = GetIndexIntoMasterTable(COMMAND, DynamicMemorySettings);
1157         u32 tmp;
1158
1159         memset(&args, 0, sizeof(args));
1160
1161         tmp = eng_clock & SET_CLOCK_FREQ_MASK;
1162         tmp |= (COMPUTE_ENGINE_PLL_PARAM << 24);
1163
1164         args.ulTargetEngineClock = cpu_to_le32(tmp);
1165         if (mem_clock)
1166                 args.sReserved.ulClock = cpu_to_le32(mem_clock & SET_CLOCK_FREQ_MASK);
1167
1168         amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
1169 }
1170
1171 void amdgpu_atombios_get_default_voltages(struct amdgpu_device *adev,
1172                                           u16 *vddc, u16 *vddci, u16 *mvdd)
1173 {
1174         struct amdgpu_mode_info *mode_info = &adev->mode_info;
1175         int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
1176         u8 frev, crev;
1177         u16 data_offset;
1178         union firmware_info *firmware_info;
1179
1180         *vddc = 0;
1181         *vddci = 0;
1182         *mvdd = 0;
1183
1184         if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,
1185                                    &frev, &crev, &data_offset)) {
1186                 firmware_info =
1187                         (union firmware_info *)(mode_info->atom_context->bios +
1188                                                 data_offset);
1189                 *vddc = le16_to_cpu(firmware_info->info_14.usBootUpVDDCVoltage);
1190                 if ((frev == 2) && (crev >= 2)) {
1191                         *vddci = le16_to_cpu(firmware_info->info_22.usBootUpVDDCIVoltage);
1192                         *mvdd = le16_to_cpu(firmware_info->info_22.usBootUpMVDDCVoltage);
1193                 }
1194         }
1195 }
1196
1197 union set_voltage {
1198         struct _SET_VOLTAGE_PS_ALLOCATION alloc;
1199         struct _SET_VOLTAGE_PARAMETERS v1;
1200         struct _SET_VOLTAGE_PARAMETERS_V2 v2;
1201         struct _SET_VOLTAGE_PARAMETERS_V1_3 v3;
1202 };
1203
1204 int amdgpu_atombios_get_max_vddc(struct amdgpu_device *adev, u8 voltage_type,
1205                              u16 voltage_id, u16 *voltage)
1206 {
1207         union set_voltage args;
1208         int index = GetIndexIntoMasterTable(COMMAND, SetVoltage);
1209         u8 frev, crev;
1210
1211         if (!amdgpu_atom_parse_cmd_header(adev->mode_info.atom_context, index, &frev, &crev))
1212                 return -EINVAL;
1213
1214         switch (crev) {
1215         case 1:
1216                 return -EINVAL;
1217         case 2:
1218                 args.v2.ucVoltageType = SET_VOLTAGE_GET_MAX_VOLTAGE;
1219                 args.v2.ucVoltageMode = 0;
1220                 args.v2.usVoltageLevel = 0;
1221
1222                 amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
1223
1224                 *voltage = le16_to_cpu(args.v2.usVoltageLevel);
1225                 break;
1226         case 3:
1227                 args.v3.ucVoltageType = voltage_type;
1228                 args.v3.ucVoltageMode = ATOM_GET_VOLTAGE_LEVEL;
1229                 args.v3.usVoltageLevel = cpu_to_le16(voltage_id);
1230
1231                 amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
1232
1233                 *voltage = le16_to_cpu(args.v3.usVoltageLevel);
1234                 break;
1235         default:
1236                 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
1237                 return -EINVAL;
1238         }
1239
1240         return 0;
1241 }
1242
1243 int amdgpu_atombios_get_leakage_vddc_based_on_leakage_idx(struct amdgpu_device *adev,
1244                                                       u16 *voltage,
1245                                                       u16 leakage_idx)
1246 {
1247         return amdgpu_atombios_get_max_vddc(adev, VOLTAGE_TYPE_VDDC, leakage_idx, voltage);
1248 }
1249
1250 int amdgpu_atombios_get_leakage_id_from_vbios(struct amdgpu_device *adev,
1251                                               u16 *leakage_id)
1252 {
1253         union set_voltage args;
1254         int index = GetIndexIntoMasterTable(COMMAND, SetVoltage);
1255         u8 frev, crev;
1256
1257         if (!amdgpu_atom_parse_cmd_header(adev->mode_info.atom_context, index, &frev, &crev))
1258                 return -EINVAL;
1259
1260         switch (crev) {
1261         case 3:
1262         case 4:
1263                 args.v3.ucVoltageType = 0;
1264                 args.v3.ucVoltageMode = ATOM_GET_LEAKAGE_ID;
1265                 args.v3.usVoltageLevel = 0;
1266
1267                 amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
1268
1269                 *leakage_id = le16_to_cpu(args.v3.usVoltageLevel);
1270                 break;
1271         default:
1272                 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
1273                 return -EINVAL;
1274         }
1275
1276         return 0;
1277 }
1278
1279 int amdgpu_atombios_get_leakage_vddc_based_on_leakage_params(struct amdgpu_device *adev,
1280                                                              u16 *vddc, u16 *vddci,
1281                                                              u16 virtual_voltage_id,
1282                                                              u16 vbios_voltage_id)
1283 {
1284         int index = GetIndexIntoMasterTable(DATA, ASIC_ProfilingInfo);
1285         u8 frev, crev;
1286         u16 data_offset, size;
1287         int i, j;
1288         ATOM_ASIC_PROFILING_INFO_V2_1 *profile;
1289         u16 *leakage_bin, *vddc_id_buf, *vddc_buf, *vddci_id_buf, *vddci_buf;
1290
1291         *vddc = 0;
1292         *vddci = 0;
1293
1294         if (!amdgpu_atom_parse_data_header(adev->mode_info.atom_context, index, &size,
1295                                     &frev, &crev, &data_offset))
1296                 return -EINVAL;
1297
1298         profile = (ATOM_ASIC_PROFILING_INFO_V2_1 *)
1299                 (adev->mode_info.atom_context->bios + data_offset);
1300
1301         switch (frev) {
1302         case 1:
1303                 return -EINVAL;
1304         case 2:
1305                 switch (crev) {
1306                 case 1:
1307                         if (size < sizeof(ATOM_ASIC_PROFILING_INFO_V2_1))
1308                                 return -EINVAL;
1309                         leakage_bin = (u16 *)
1310                                 (adev->mode_info.atom_context->bios + data_offset +
1311                                  le16_to_cpu(profile->usLeakageBinArrayOffset));
1312                         vddc_id_buf = (u16 *)
1313                                 (adev->mode_info.atom_context->bios + data_offset +
1314                                  le16_to_cpu(profile->usElbVDDC_IdArrayOffset));
1315                         vddc_buf = (u16 *)
1316                                 (adev->mode_info.atom_context->bios + data_offset +
1317                                  le16_to_cpu(profile->usElbVDDC_LevelArrayOffset));
1318                         vddci_id_buf = (u16 *)
1319                                 (adev->mode_info.atom_context->bios + data_offset +
1320                                  le16_to_cpu(profile->usElbVDDCI_IdArrayOffset));
1321                         vddci_buf = (u16 *)
1322                                 (adev->mode_info.atom_context->bios + data_offset +
1323                                  le16_to_cpu(profile->usElbVDDCI_LevelArrayOffset));
1324
1325                         if (profile->ucElbVDDC_Num > 0) {
1326                                 for (i = 0; i < profile->ucElbVDDC_Num; i++) {
1327                                         if (vddc_id_buf[i] == virtual_voltage_id) {
1328                                                 for (j = 0; j < profile->ucLeakageBinNum; j++) {
1329                                                         if (vbios_voltage_id <= leakage_bin[j]) {
1330                                                                 *vddc = vddc_buf[j * profile->ucElbVDDC_Num + i];
1331                                                                 break;
1332                                                         }
1333                                                 }
1334                                                 break;
1335                                         }
1336                                 }
1337                         }
1338                         if (profile->ucElbVDDCI_Num > 0) {
1339                                 for (i = 0; i < profile->ucElbVDDCI_Num; i++) {
1340                                         if (vddci_id_buf[i] == virtual_voltage_id) {
1341                                                 for (j = 0; j < profile->ucLeakageBinNum; j++) {
1342                                                         if (vbios_voltage_id <= leakage_bin[j]) {
1343                                                                 *vddci = vddci_buf[j * profile->ucElbVDDCI_Num + i];
1344                                                                 break;
1345                                                         }
1346                                                 }
1347                                                 break;
1348                                         }
1349                                 }
1350                         }
1351                         break;
1352                 default:
1353                         DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
1354                         return -EINVAL;
1355                 }
1356                 break;
1357         default:
1358                 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
1359                 return -EINVAL;
1360         }
1361
1362         return 0;
1363 }
1364
1365 union get_voltage_info {
1366         struct _GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_2 in;
1367         struct _GET_EVV_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_2 evv_out;
1368 };
1369
1370 int amdgpu_atombios_get_voltage_evv(struct amdgpu_device *adev,
1371                                     u16 virtual_voltage_id,
1372                                     u16 *voltage)
1373 {
1374         int index = GetIndexIntoMasterTable(COMMAND, GetVoltageInfo);
1375         u32 entry_id;
1376         u32 count = adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count;
1377         union get_voltage_info args;
1378
1379         for (entry_id = 0; entry_id < count; entry_id++) {
1380                 if (adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[entry_id].v ==
1381                     virtual_voltage_id)
1382                         break;
1383         }
1384
1385         if (entry_id >= count)
1386                 return -EINVAL;
1387
1388         args.in.ucVoltageType = VOLTAGE_TYPE_VDDC;
1389         args.in.ucVoltageMode = ATOM_GET_VOLTAGE_EVV_VOLTAGE;
1390         args.in.usVoltageLevel = cpu_to_le16(virtual_voltage_id);
1391         args.in.ulSCLKFreq =
1392                 cpu_to_le32(adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[entry_id].clk);
1393
1394         amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
1395
1396         *voltage = le16_to_cpu(args.evv_out.usVoltageLevel);
1397
1398         return 0;
1399 }
1400
1401 union voltage_object_info {
1402         struct _ATOM_VOLTAGE_OBJECT_INFO v1;
1403         struct _ATOM_VOLTAGE_OBJECT_INFO_V2 v2;
1404         struct _ATOM_VOLTAGE_OBJECT_INFO_V3_1 v3;
1405 };
1406
1407 union voltage_object {
1408         struct _ATOM_VOLTAGE_OBJECT v1;
1409         struct _ATOM_VOLTAGE_OBJECT_V2 v2;
1410         union _ATOM_VOLTAGE_OBJECT_V3 v3;
1411 };
1412
1413
1414 static ATOM_VOLTAGE_OBJECT_V3 *amdgpu_atombios_lookup_voltage_object_v3(ATOM_VOLTAGE_OBJECT_INFO_V3_1 *v3,
1415                                                                         u8 voltage_type, u8 voltage_mode)
1416 {
1417         u32 size = le16_to_cpu(v3->sHeader.usStructureSize);
1418         u32 offset = offsetof(ATOM_VOLTAGE_OBJECT_INFO_V3_1, asVoltageObj[0]);
1419         u8 *start = (u8*)v3;
1420
1421         while (offset < size) {
1422                 ATOM_VOLTAGE_OBJECT_V3 *vo = (ATOM_VOLTAGE_OBJECT_V3 *)(start + offset);
1423                 if ((vo->asGpioVoltageObj.sHeader.ucVoltageType == voltage_type) &&
1424                     (vo->asGpioVoltageObj.sHeader.ucVoltageMode == voltage_mode))
1425                         return vo;
1426                 offset += le16_to_cpu(vo->asGpioVoltageObj.sHeader.usSize);
1427         }
1428         return NULL;
1429 }
1430
1431 int amdgpu_atombios_get_svi2_info(struct amdgpu_device *adev,
1432                               u8 voltage_type,
1433                               u8 *svd_gpio_id, u8 *svc_gpio_id)
1434 {
1435         int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo);
1436         u8 frev, crev;
1437         u16 data_offset, size;
1438         union voltage_object_info *voltage_info;
1439         union voltage_object *voltage_object = NULL;
1440
1441         if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context, index, &size,
1442                                    &frev, &crev, &data_offset)) {
1443                 voltage_info = (union voltage_object_info *)
1444                         (adev->mode_info.atom_context->bios + data_offset);
1445
1446                 switch (frev) {
1447                 case 3:
1448                         switch (crev) {
1449                         case 1:
1450                                 voltage_object = (union voltage_object *)
1451                                         amdgpu_atombios_lookup_voltage_object_v3(&voltage_info->v3,
1452                                                                       voltage_type,
1453                                                                       VOLTAGE_OBJ_SVID2);
1454                                 if (voltage_object) {
1455                                         *svd_gpio_id = voltage_object->v3.asSVID2Obj.ucSVDGpioId;
1456                                         *svc_gpio_id = voltage_object->v3.asSVID2Obj.ucSVCGpioId;
1457                                 } else {
1458                                         return -EINVAL;
1459                                 }
1460                                 break;
1461                         default:
1462                                 DRM_ERROR("unknown voltage object table\n");
1463                                 return -EINVAL;
1464                         }
1465                         break;
1466                 default:
1467                         DRM_ERROR("unknown voltage object table\n");
1468                         return -EINVAL;
1469                 }
1470
1471         }
1472         return 0;
1473 }
1474
1475 bool
1476 amdgpu_atombios_is_voltage_gpio(struct amdgpu_device *adev,
1477                                 u8 voltage_type, u8 voltage_mode)
1478 {
1479         int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo);
1480         u8 frev, crev;
1481         u16 data_offset, size;
1482         union voltage_object_info *voltage_info;
1483
1484         if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context, index, &size,
1485                                    &frev, &crev, &data_offset)) {
1486                 voltage_info = (union voltage_object_info *)
1487                         (adev->mode_info.atom_context->bios + data_offset);
1488
1489                 switch (frev) {
1490                 case 3:
1491                         switch (crev) {
1492                         case 1:
1493                                 if (amdgpu_atombios_lookup_voltage_object_v3(&voltage_info->v3,
1494                                                                   voltage_type, voltage_mode))
1495                                         return true;
1496                                 break;
1497                         default:
1498                                 DRM_ERROR("unknown voltage object table\n");
1499                                 return false;
1500                         }
1501                         break;
1502                 default:
1503                         DRM_ERROR("unknown voltage object table\n");
1504                         return false;
1505                 }
1506
1507         }
1508         return false;
1509 }
1510
1511 int amdgpu_atombios_get_voltage_table(struct amdgpu_device *adev,
1512                                       u8 voltage_type, u8 voltage_mode,
1513                                       struct atom_voltage_table *voltage_table)
1514 {
1515         int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo);
1516         u8 frev, crev;
1517         u16 data_offset, size;
1518         int i;
1519         union voltage_object_info *voltage_info;
1520         union voltage_object *voltage_object = NULL;
1521
1522         if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context, index, &size,
1523                                    &frev, &crev, &data_offset)) {
1524                 voltage_info = (union voltage_object_info *)
1525                         (adev->mode_info.atom_context->bios + data_offset);
1526
1527                 switch (frev) {
1528                 case 3:
1529                         switch (crev) {
1530                         case 1:
1531                                 voltage_object = (union voltage_object *)
1532                                         amdgpu_atombios_lookup_voltage_object_v3(&voltage_info->v3,
1533                                                                       voltage_type, voltage_mode);
1534                                 if (voltage_object) {
1535                                         ATOM_GPIO_VOLTAGE_OBJECT_V3 *gpio =
1536                                                 &voltage_object->v3.asGpioVoltageObj;
1537                                         VOLTAGE_LUT_ENTRY_V2 *lut;
1538                                         if (gpio->ucGpioEntryNum > MAX_VOLTAGE_ENTRIES)
1539                                                 return -EINVAL;
1540                                         lut = &gpio->asVolGpioLut[0];
1541                                         for (i = 0; i < gpio->ucGpioEntryNum; i++) {
1542                                                 voltage_table->entries[i].value =
1543                                                         le16_to_cpu(lut->usVoltageValue);
1544                                                 voltage_table->entries[i].smio_low =
1545                                                         le32_to_cpu(lut->ulVoltageId);
1546                                                 lut = (VOLTAGE_LUT_ENTRY_V2 *)
1547                                                         ((u8 *)lut + sizeof(VOLTAGE_LUT_ENTRY_V2));
1548                                         }
1549                                         voltage_table->mask_low = le32_to_cpu(gpio->ulGpioMaskVal);
1550                                         voltage_table->count = gpio->ucGpioEntryNum;
1551                                         voltage_table->phase_delay = gpio->ucPhaseDelay;
1552                                         return 0;
1553                                 }
1554                                 break;
1555                         default:
1556                                 DRM_ERROR("unknown voltage object table\n");
1557                                 return -EINVAL;
1558                         }
1559                         break;
1560                 default:
1561                         DRM_ERROR("unknown voltage object table\n");
1562                         return -EINVAL;
1563                 }
1564         }
1565         return -EINVAL;
1566 }
1567
1568 union vram_info {
1569         struct _ATOM_VRAM_INFO_V3 v1_3;
1570         struct _ATOM_VRAM_INFO_V4 v1_4;
1571         struct _ATOM_VRAM_INFO_HEADER_V2_1 v2_1;
1572 };
1573
1574 #define MEM_ID_MASK           0xff000000
1575 #define MEM_ID_SHIFT          24
1576 #define CLOCK_RANGE_MASK      0x00ffffff
1577 #define CLOCK_RANGE_SHIFT     0
1578 #define LOW_NIBBLE_MASK       0xf
1579 #define DATA_EQU_PREV         0
1580 #define DATA_FROM_TABLE       4
1581
1582 int amdgpu_atombios_init_mc_reg_table(struct amdgpu_device *adev,
1583                                       u8 module_index,
1584                                       struct atom_mc_reg_table *reg_table)
1585 {
1586         int index = GetIndexIntoMasterTable(DATA, VRAM_Info);
1587         u8 frev, crev, num_entries, t_mem_id, num_ranges = 0;
1588         u32 i = 0, j;
1589         u16 data_offset, size;
1590         union vram_info *vram_info;
1591
1592         memset(reg_table, 0, sizeof(struct atom_mc_reg_table));
1593
1594         if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context, index, &size,
1595                                    &frev, &crev, &data_offset)) {
1596                 vram_info = (union vram_info *)
1597                         (adev->mode_info.atom_context->bios + data_offset);
1598                 switch (frev) {
1599                 case 1:
1600                         DRM_ERROR("old table version %d, %d\n", frev, crev);
1601                         return -EINVAL;
1602                 case 2:
1603                         switch (crev) {
1604                         case 1:
1605                                 if (module_index < vram_info->v2_1.ucNumOfVRAMModule) {
1606                                         ATOM_INIT_REG_BLOCK *reg_block =
1607                                                 (ATOM_INIT_REG_BLOCK *)
1608                                                 ((u8 *)vram_info + le16_to_cpu(vram_info->v2_1.usMemClkPatchTblOffset));
1609                                         ATOM_MEMORY_SETTING_DATA_BLOCK *reg_data =
1610                                                 (ATOM_MEMORY_SETTING_DATA_BLOCK *)
1611                                                 ((u8 *)reg_block + (2 * sizeof(u16)) +
1612                                                  le16_to_cpu(reg_block->usRegIndexTblSize));
1613                                         ATOM_INIT_REG_INDEX_FORMAT *format = &reg_block->asRegIndexBuf[0];
1614                                         num_entries = (u8)((le16_to_cpu(reg_block->usRegIndexTblSize)) /
1615                                                            sizeof(ATOM_INIT_REG_INDEX_FORMAT)) - 1;
1616                                         if (num_entries > VBIOS_MC_REGISTER_ARRAY_SIZE)
1617                                                 return -EINVAL;
1618                                         while (i < num_entries) {
1619                                                 if (format->ucPreRegDataLength & ACCESS_PLACEHOLDER)
1620                                                         break;
1621                                                 reg_table->mc_reg_address[i].s1 =
1622                                                         (u16)(le16_to_cpu(format->usRegIndex));
1623                                                 reg_table->mc_reg_address[i].pre_reg_data =
1624                                                         (u8)(format->ucPreRegDataLength);
1625                                                 i++;
1626                                                 format = (ATOM_INIT_REG_INDEX_FORMAT *)
1627                                                         ((u8 *)format + sizeof(ATOM_INIT_REG_INDEX_FORMAT));
1628                                         }
1629                                         reg_table->last = i;
1630                                         while ((le32_to_cpu(*(u32 *)reg_data) != END_OF_REG_DATA_BLOCK) &&
1631                                                (num_ranges < VBIOS_MAX_AC_TIMING_ENTRIES)) {
1632                                                 t_mem_id = (u8)((le32_to_cpu(*(u32 *)reg_data) & MEM_ID_MASK)
1633                                                                 >> MEM_ID_SHIFT);
1634                                                 if (module_index == t_mem_id) {
1635                                                         reg_table->mc_reg_table_entry[num_ranges].mclk_max =
1636                                                                 (u32)((le32_to_cpu(*(u32 *)reg_data) & CLOCK_RANGE_MASK)
1637                                                                       >> CLOCK_RANGE_SHIFT);
1638                                                         for (i = 0, j = 1; i < reg_table->last; i++) {
1639                                                                 if ((reg_table->mc_reg_address[i].pre_reg_data & LOW_NIBBLE_MASK) == DATA_FROM_TABLE) {
1640                                                                         reg_table->mc_reg_table_entry[num_ranges].mc_data[i] =
1641                                                                                 (u32)le32_to_cpu(*((u32 *)reg_data + j));
1642                                                                         j++;
1643                                                                 } else if ((reg_table->mc_reg_address[i].pre_reg_data & LOW_NIBBLE_MASK) == DATA_EQU_PREV) {
1644                                                                         reg_table->mc_reg_table_entry[num_ranges].mc_data[i] =
1645                                                                                 reg_table->mc_reg_table_entry[num_ranges].mc_data[i - 1];
1646                                                                 }
1647                                                         }
1648                                                         num_ranges++;
1649                                                 }
1650                                                 reg_data = (ATOM_MEMORY_SETTING_DATA_BLOCK *)
1651                                                         ((u8 *)reg_data + le16_to_cpu(reg_block->usRegDataBlkSize));
1652                                         }
1653                                         if (le32_to_cpu(*(u32 *)reg_data) != END_OF_REG_DATA_BLOCK)
1654                                                 return -EINVAL;
1655                                         reg_table->num_entries = num_ranges;
1656                                 } else
1657                                         return -EINVAL;
1658                                 break;
1659                         default:
1660                                 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
1661                                 return -EINVAL;
1662                         }
1663                         break;
1664                 default:
1665                         DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
1666                         return -EINVAL;
1667                 }
1668                 return 0;
1669         }
1670         return -EINVAL;
1671 }
1672
1673 bool amdgpu_atombios_has_gpu_virtualization_table(struct amdgpu_device *adev)
1674 {
1675         int index = GetIndexIntoMasterTable(DATA, GPUVirtualizationInfo);
1676         u8 frev, crev;
1677         u16 data_offset, size;
1678
1679         if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context, index, &size,
1680                                           &frev, &crev, &data_offset))
1681                 return true;
1682
1683         return false;
1684 }
1685
1686 void amdgpu_atombios_scratch_regs_lock(struct amdgpu_device *adev, bool lock)
1687 {
1688         uint32_t bios_6_scratch;
1689
1690         bios_6_scratch = RREG32(adev->bios_scratch_reg_offset + 6);
1691
1692         if (lock) {
1693                 bios_6_scratch |= ATOM_S6_CRITICAL_STATE;
1694                 bios_6_scratch &= ~ATOM_S6_ACC_MODE;
1695         } else {
1696                 bios_6_scratch &= ~ATOM_S6_CRITICAL_STATE;
1697                 bios_6_scratch |= ATOM_S6_ACC_MODE;
1698         }
1699
1700         WREG32(adev->bios_scratch_reg_offset + 6, bios_6_scratch);
1701 }
1702
1703 static void amdgpu_atombios_scratch_regs_init(struct amdgpu_device *adev)
1704 {
1705         uint32_t bios_2_scratch, bios_6_scratch;
1706
1707         adev->bios_scratch_reg_offset = mmBIOS_SCRATCH_0;
1708
1709         bios_2_scratch = RREG32(adev->bios_scratch_reg_offset + 2);
1710         bios_6_scratch = RREG32(adev->bios_scratch_reg_offset + 6);
1711
1712         /* let the bios control the backlight */
1713         bios_2_scratch &= ~ATOM_S2_VRI_BRIGHT_ENABLE;
1714
1715         /* tell the bios not to handle mode switching */
1716         bios_6_scratch |= ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH;
1717
1718         /* clear the vbios dpms state */
1719         bios_2_scratch &= ~ATOM_S2_DEVICE_DPMS_STATE;
1720
1721         WREG32(adev->bios_scratch_reg_offset + 2, bios_2_scratch);
1722         WREG32(adev->bios_scratch_reg_offset + 6, bios_6_scratch);
1723 }
1724
1725 void amdgpu_atombios_scratch_regs_engine_hung(struct amdgpu_device *adev,
1726                                               bool hung)
1727 {
1728         u32 tmp = RREG32(adev->bios_scratch_reg_offset + 3);
1729
1730         if (hung)
1731                 tmp |= ATOM_S3_ASIC_GUI_ENGINE_HUNG;
1732         else
1733                 tmp &= ~ATOM_S3_ASIC_GUI_ENGINE_HUNG;
1734
1735         WREG32(adev->bios_scratch_reg_offset + 3, tmp);
1736 }
1737
1738 bool amdgpu_atombios_scratch_need_asic_init(struct amdgpu_device *adev)
1739 {
1740         u32 tmp = RREG32(adev->bios_scratch_reg_offset + 7);
1741
1742         if (tmp & ATOM_S7_ASIC_INIT_COMPLETE_MASK)
1743                 return false;
1744         else
1745                 return true;
1746 }
1747
1748 /* Atom needs data in little endian format so swap as appropriate when copying
1749  * data to or from atom. Note that atom operates on dw units.
1750  *
1751  * Use to_le=true when sending data to atom and provide at least
1752  * ALIGN(num_bytes,4) bytes in the dst buffer.
1753  *
1754  * Use to_le=false when receiving data from atom and provide ALIGN(num_bytes,4)
1755  * byes in the src buffer.
1756  */
1757 void amdgpu_atombios_copy_swap(u8 *dst, u8 *src, u8 num_bytes, bool to_le)
1758 {
1759 #ifdef __BIG_ENDIAN
1760         u32 src_tmp[5], dst_tmp[5];
1761         int i;
1762         u8 align_num_bytes = ALIGN(num_bytes, 4);
1763
1764         if (to_le) {
1765                 memcpy(src_tmp, src, num_bytes);
1766                 for (i = 0; i < align_num_bytes / 4; i++)
1767                         dst_tmp[i] = cpu_to_le32(src_tmp[i]);
1768                 memcpy(dst, dst_tmp, align_num_bytes);
1769         } else {
1770                 memcpy(src_tmp, src, align_num_bytes);
1771                 for (i = 0; i < align_num_bytes / 4; i++)
1772                         dst_tmp[i] = le32_to_cpu(src_tmp[i]);
1773                 memcpy(dst, dst_tmp, num_bytes);
1774         }
1775 #else
1776         memcpy(dst, src, num_bytes);
1777 #endif
1778 }
1779
1780 static int amdgpu_atombios_allocate_fb_scratch(struct amdgpu_device *adev)
1781 {
1782         struct atom_context *ctx = adev->mode_info.atom_context;
1783         int index = GetIndexIntoMasterTable(DATA, VRAM_UsageByFirmware);
1784         uint16_t data_offset;
1785         int usage_bytes = 0;
1786         struct _ATOM_VRAM_USAGE_BY_FIRMWARE *firmware_usage;
1787         u64 start_addr;
1788         u64 size;
1789
1790         if (amdgpu_atom_parse_data_header(ctx, index, NULL, NULL, NULL, &data_offset)) {
1791                 firmware_usage = (struct _ATOM_VRAM_USAGE_BY_FIRMWARE *)(ctx->bios + data_offset);
1792
1793                 DRM_DEBUG("atom firmware requested %08x %dkb\n",
1794                           le32_to_cpu(firmware_usage->asFirmwareVramReserveInfo[0].ulStartAddrUsedByFirmware),
1795                           le16_to_cpu(firmware_usage->asFirmwareVramReserveInfo[0].usFirmwareUseInKb));
1796
1797                 start_addr = firmware_usage->asFirmwareVramReserveInfo[0].ulStartAddrUsedByFirmware;
1798                 size = firmware_usage->asFirmwareVramReserveInfo[0].usFirmwareUseInKb;
1799
1800                 if ((uint32_t)(start_addr & ATOM_VRAM_OPERATION_FLAGS_MASK) ==
1801                         (uint32_t)(ATOM_VRAM_BLOCK_SRIOV_MSG_SHARE_RESERVATION <<
1802                         ATOM_VRAM_OPERATION_FLAGS_SHIFT)) {
1803                         /* Firmware request VRAM reservation for SR-IOV */
1804                         adev->fw_vram_usage.start_offset = (start_addr &
1805                                 (~ATOM_VRAM_OPERATION_FLAGS_MASK)) << 10;
1806                         adev->fw_vram_usage.size = size << 10;
1807                         /* Use the default scratch size */
1808                         usage_bytes = 0;
1809                 } else {
1810                         usage_bytes = le16_to_cpu(firmware_usage->asFirmwareVramReserveInfo[0].usFirmwareUseInKb) * 1024;
1811                 }
1812         }
1813         ctx->scratch_size_bytes = 0;
1814         if (usage_bytes == 0)
1815                 usage_bytes = 20 * 1024;
1816         /* allocate some scratch memory */
1817         ctx->scratch = kzalloc(usage_bytes, GFP_KERNEL);
1818         if (!ctx->scratch)
1819                 return -ENOMEM;
1820         ctx->scratch_size_bytes = usage_bytes;
1821         return 0;
1822 }
1823
1824 /* ATOM accessor methods */
1825 /*
1826  * ATOM is an interpreted byte code stored in tables in the vbios.  The
1827  * driver registers callbacks to access registers and the interpreter
1828  * in the driver parses the tables and executes then to program specific
1829  * actions (set display modes, asic init, etc.).  See amdgpu_atombios.c,
1830  * atombios.h, and atom.c
1831  */
1832
1833 /**
1834  * cail_pll_read - read PLL register
1835  *
1836  * @info: atom card_info pointer
1837  * @reg: PLL register offset
1838  *
1839  * Provides a PLL register accessor for the atom interpreter (r4xx+).
1840  * Returns the value of the PLL register.
1841  */
1842 static uint32_t cail_pll_read(struct card_info *info, uint32_t reg)
1843 {
1844         return 0;
1845 }
1846
1847 /**
1848  * cail_pll_write - write PLL register
1849  *
1850  * @info: atom card_info pointer
1851  * @reg: PLL register offset
1852  * @val: value to write to the pll register
1853  *
1854  * Provides a PLL register accessor for the atom interpreter (r4xx+).
1855  */
1856 static void cail_pll_write(struct card_info *info, uint32_t reg, uint32_t val)
1857 {
1858
1859 }
1860
1861 /**
1862  * cail_mc_read - read MC (Memory Controller) register
1863  *
1864  * @info: atom card_info pointer
1865  * @reg: MC register offset
1866  *
1867  * Provides an MC register accessor for the atom interpreter (r4xx+).
1868  * Returns the value of the MC register.
1869  */
1870 static uint32_t cail_mc_read(struct card_info *info, uint32_t reg)
1871 {
1872         return 0;
1873 }
1874
1875 /**
1876  * cail_mc_write - write MC (Memory Controller) register
1877  *
1878  * @info: atom card_info pointer
1879  * @reg: MC register offset
1880  * @val: value to write to the pll register
1881  *
1882  * Provides a MC register accessor for the atom interpreter (r4xx+).
1883  */
1884 static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val)
1885 {
1886
1887 }
1888
1889 /**
1890  * cail_reg_write - write MMIO register
1891  *
1892  * @info: atom card_info pointer
1893  * @reg: MMIO register offset
1894  * @val: value to write to the pll register
1895  *
1896  * Provides a MMIO register accessor for the atom interpreter (r4xx+).
1897  */
1898 static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val)
1899 {
1900         struct amdgpu_device *adev = info->dev->dev_private;
1901
1902         WREG32(reg, val);
1903 }
1904
1905 /**
1906  * cail_reg_read - read MMIO register
1907  *
1908  * @info: atom card_info pointer
1909  * @reg: MMIO register offset
1910  *
1911  * Provides an MMIO register accessor for the atom interpreter (r4xx+).
1912  * Returns the value of the MMIO register.
1913  */
1914 static uint32_t cail_reg_read(struct card_info *info, uint32_t reg)
1915 {
1916         struct amdgpu_device *adev = info->dev->dev_private;
1917         uint32_t r;
1918
1919         r = RREG32(reg);
1920         return r;
1921 }
1922
1923 /**
1924  * cail_ioreg_write - write IO register
1925  *
1926  * @info: atom card_info pointer
1927  * @reg: IO register offset
1928  * @val: value to write to the pll register
1929  *
1930  * Provides a IO register accessor for the atom interpreter (r4xx+).
1931  */
1932 static void cail_ioreg_write(struct card_info *info, uint32_t reg, uint32_t val)
1933 {
1934         struct amdgpu_device *adev = info->dev->dev_private;
1935
1936         WREG32_IO(reg, val);
1937 }
1938
1939 /**
1940  * cail_ioreg_read - read IO register
1941  *
1942  * @info: atom card_info pointer
1943  * @reg: IO register offset
1944  *
1945  * Provides an IO register accessor for the atom interpreter (r4xx+).
1946  * Returns the value of the IO register.
1947  */
1948 static uint32_t cail_ioreg_read(struct card_info *info, uint32_t reg)
1949 {
1950         struct amdgpu_device *adev = info->dev->dev_private;
1951         uint32_t r;
1952
1953         r = RREG32_IO(reg);
1954         return r;
1955 }
1956
1957 static ssize_t amdgpu_atombios_get_vbios_version(struct device *dev,
1958                                                  struct device_attribute *attr,
1959                                                  char *buf)
1960 {
1961         struct drm_device *ddev = dev_get_drvdata(dev);
1962         struct amdgpu_device *adev = ddev->dev_private;
1963         struct atom_context *ctx = adev->mode_info.atom_context;
1964
1965         return snprintf(buf, PAGE_SIZE, "%s\n", ctx->vbios_version);
1966 }
1967
1968 static DEVICE_ATTR(vbios_version, 0444, amdgpu_atombios_get_vbios_version,
1969                    NULL);
1970
1971 /**
1972  * amdgpu_atombios_fini - free the driver info and callbacks for atombios
1973  *
1974  * @adev: amdgpu_device pointer
1975  *
1976  * Frees the driver info and register access callbacks for the ATOM
1977  * interpreter (r4xx+).
1978  * Called at driver shutdown.
1979  */
1980 void amdgpu_atombios_fini(struct amdgpu_device *adev)
1981 {
1982         if (adev->mode_info.atom_context) {
1983                 kfree(adev->mode_info.atom_context->scratch);
1984                 kfree(adev->mode_info.atom_context->iio);
1985         }
1986         kfree(adev->mode_info.atom_context);
1987         adev->mode_info.atom_context = NULL;
1988         kfree(adev->mode_info.atom_card_info);
1989         adev->mode_info.atom_card_info = NULL;
1990         device_remove_file(adev->dev, &dev_attr_vbios_version);
1991 }
1992
1993 /**
1994  * amdgpu_atombios_init - init the driver info and callbacks for atombios
1995  *
1996  * @adev: amdgpu_device pointer
1997  *
1998  * Initializes the driver info and register access callbacks for the
1999  * ATOM interpreter (r4xx+).
2000  * Returns 0 on sucess, -ENOMEM on failure.
2001  * Called at driver startup.
2002  */
2003 int amdgpu_atombios_init(struct amdgpu_device *adev)
2004 {
2005         struct card_info *atom_card_info =
2006             kzalloc(sizeof(struct card_info), GFP_KERNEL);
2007         int ret;
2008
2009         if (!atom_card_info)
2010                 return -ENOMEM;
2011
2012         adev->mode_info.atom_card_info = atom_card_info;
2013         atom_card_info->dev = adev->ddev;
2014         atom_card_info->reg_read = cail_reg_read;
2015         atom_card_info->reg_write = cail_reg_write;
2016         /* needed for iio ops */
2017         if (adev->rio_mem) {
2018                 atom_card_info->ioreg_read = cail_ioreg_read;
2019                 atom_card_info->ioreg_write = cail_ioreg_write;
2020         } else {
2021                 DRM_DEBUG("PCI I/O BAR is not found. Using MMIO to access ATOM BIOS\n");
2022                 atom_card_info->ioreg_read = cail_reg_read;
2023                 atom_card_info->ioreg_write = cail_reg_write;
2024         }
2025         atom_card_info->mc_read = cail_mc_read;
2026         atom_card_info->mc_write = cail_mc_write;
2027         atom_card_info->pll_read = cail_pll_read;
2028         atom_card_info->pll_write = cail_pll_write;
2029
2030         adev->mode_info.atom_context = amdgpu_atom_parse(atom_card_info, adev->bios);
2031         if (!adev->mode_info.atom_context) {
2032                 amdgpu_atombios_fini(adev);
2033                 return -ENOMEM;
2034         }
2035
2036         mutex_init(&adev->mode_info.atom_context->mutex);
2037         if (adev->is_atom_fw) {
2038                 amdgpu_atomfirmware_scratch_regs_init(adev);
2039                 amdgpu_atomfirmware_allocate_fb_scratch(adev);
2040         } else {
2041                 amdgpu_atombios_scratch_regs_init(adev);
2042                 amdgpu_atombios_allocate_fb_scratch(adev);
2043         }
2044
2045         ret = device_create_file(adev->dev, &dev_attr_vbios_version);
2046         if (ret) {
2047                 DRM_ERROR("Failed to create device file for VBIOS version\n");
2048                 return ret;
2049         }
2050
2051         return 0;
2052 }
2053