2 * Copyright 2014 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
23 #include "amdgpu_amdkfd.h"
24 #include "amd_shared.h"
27 #include "amdgpu_gfx.h"
28 #include "amdgpu_dma_buf.h"
29 #include <linux/module.h>
30 #include <linux/dma-buf.h>
31 #include "amdgpu_xgmi.h"
32 #include <uapi/linux/kfd_ioctl.h>
34 /* Total memory size in system memory and all GPU VRAM. Used to
35 * estimate worst case amount of memory to reserve for page tables
37 uint64_t amdgpu_amdkfd_total_mem_size;
39 static bool kfd_initialized;
41 int amdgpu_amdkfd_init(void)
47 amdgpu_amdkfd_total_mem_size = si.freeram - si.freehigh;
48 amdgpu_amdkfd_total_mem_size *= si.mem_unit;
51 amdgpu_amdkfd_gpuvm_init_mem_limits();
52 kfd_initialized = !ret;
57 void amdgpu_amdkfd_fini(void)
59 if (kfd_initialized) {
61 kfd_initialized = false;
65 void amdgpu_amdkfd_device_probe(struct amdgpu_device *adev)
67 bool vf = amdgpu_sriov_vf(adev);
72 adev->kfd.dev = kgd2kfd_probe((struct kgd_dev *)adev,
73 adev->pdev, adev->asic_type, vf);
76 amdgpu_amdkfd_total_mem_size += adev->gmc.real_vram_size;
80 * amdgpu_doorbell_get_kfd_info - Report doorbell configuration required to
83 * @adev: amdgpu_device pointer
84 * @aperture_base: output returning doorbell aperture base physical address
85 * @aperture_size: output returning doorbell aperture size in bytes
86 * @start_offset: output returning # of doorbell bytes reserved for amdgpu.
88 * amdgpu and amdkfd share the doorbell aperture. amdgpu sets it up,
89 * takes doorbells required for its own rings and reports the setup to amdkfd.
90 * amdgpu reserved doorbells are at the start of the doorbell aperture.
92 static void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev,
93 phys_addr_t *aperture_base,
94 size_t *aperture_size,
98 * The first num_doorbells are used by amdgpu.
99 * amdkfd takes whatever's left in the aperture.
101 if (adev->doorbell.size > adev->doorbell.num_doorbells * sizeof(u32)) {
102 *aperture_base = adev->doorbell.base;
103 *aperture_size = adev->doorbell.size;
104 *start_offset = adev->doorbell.num_doorbells * sizeof(u32);
112 void amdgpu_amdkfd_device_init(struct amdgpu_device *adev)
118 struct kgd2kfd_shared_resources gpu_resources = {
119 .compute_vmid_bitmap =
120 ((1 << AMDGPU_NUM_VMID) - 1) -
121 ((1 << adev->vm_manager.first_kfd_vmid) - 1),
122 .num_pipe_per_mec = adev->gfx.mec.num_pipe_per_mec,
123 .num_queue_per_pipe = adev->gfx.mec.num_queue_per_pipe,
124 .gpuvm_size = min(adev->vm_manager.max_pfn
125 << AMDGPU_GPU_PAGE_SHIFT,
126 AMDGPU_GMC_HOLE_START),
127 .drm_render_minor = adev_to_drm(adev)->render->index,
128 .sdma_doorbell_idx = adev->doorbell_index.sdma_engine,
132 /* this is going to have a few of the MSBs set that we need to
135 bitmap_complement(gpu_resources.cp_queue_bitmap,
136 adev->gfx.mec.queue_bitmap,
139 /* According to linux/bitmap.h we shouldn't use bitmap_clear if
140 * nbits is not compile time constant
142 last_valid_bit = 1 /* only first MEC can have compute queues */
143 * adev->gfx.mec.num_pipe_per_mec
144 * adev->gfx.mec.num_queue_per_pipe;
145 for (i = last_valid_bit; i < KGD_MAX_QUEUES; ++i)
146 clear_bit(i, gpu_resources.cp_queue_bitmap);
148 amdgpu_doorbell_get_kfd_info(adev,
149 &gpu_resources.doorbell_physical_address,
150 &gpu_resources.doorbell_aperture_size,
151 &gpu_resources.doorbell_start_offset);
153 /* Since SOC15, BIF starts to statically use the
154 * lower 12 bits of doorbell addresses for routing
155 * based on settings in registers like
156 * SDMA0_DOORBELL_RANGE etc..
157 * In order to route a doorbell to CP engine, the lower
158 * 12 bits of its address has to be outside the range
159 * set for SDMA, VCN, and IH blocks.
161 if (adev->asic_type >= CHIP_VEGA10) {
162 gpu_resources.non_cp_doorbells_start =
163 adev->doorbell_index.first_non_cp;
164 gpu_resources.non_cp_doorbells_end =
165 adev->doorbell_index.last_non_cp;
168 adev->kfd.init_complete = kgd2kfd_device_init(adev->kfd.dev,
169 adev_to_drm(adev), &gpu_resources);
173 void amdgpu_amdkfd_device_fini(struct amdgpu_device *adev)
176 kgd2kfd_device_exit(adev->kfd.dev);
177 adev->kfd.dev = NULL;
181 void amdgpu_amdkfd_interrupt(struct amdgpu_device *adev,
182 const void *ih_ring_entry)
185 kgd2kfd_interrupt(adev->kfd.dev, ih_ring_entry);
188 void amdgpu_amdkfd_suspend(struct amdgpu_device *adev, bool run_pm)
191 kgd2kfd_suspend(adev->kfd.dev, run_pm);
194 int amdgpu_amdkfd_resume(struct amdgpu_device *adev, bool run_pm)
199 r = kgd2kfd_resume(adev->kfd.dev, run_pm);
204 int amdgpu_amdkfd_pre_reset(struct amdgpu_device *adev)
209 r = kgd2kfd_pre_reset(adev->kfd.dev);
214 int amdgpu_amdkfd_post_reset(struct amdgpu_device *adev)
219 r = kgd2kfd_post_reset(adev->kfd.dev);
224 void amdgpu_amdkfd_gpu_reset(struct kgd_dev *kgd)
226 struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
228 if (amdgpu_device_should_recover_gpu(adev))
229 amdgpu_device_gpu_recover(adev, NULL);
232 int amdgpu_amdkfd_alloc_gtt_mem(struct kgd_dev *kgd, size_t size,
233 void **mem_obj, uint64_t *gpu_addr,
234 void **cpu_ptr, bool cp_mqd_gfx9)
236 struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
237 struct amdgpu_bo *bo = NULL;
238 struct amdgpu_bo_param bp;
240 void *cpu_ptr_tmp = NULL;
242 memset(&bp, 0, sizeof(bp));
244 bp.byte_align = PAGE_SIZE;
245 bp.domain = AMDGPU_GEM_DOMAIN_GTT;
246 bp.flags = AMDGPU_GEM_CREATE_CPU_GTT_USWC;
247 bp.type = ttm_bo_type_kernel;
251 bp.flags |= AMDGPU_GEM_CREATE_CP_MQD_GFX9;
253 r = amdgpu_bo_create(adev, &bp, &bo);
256 "failed to allocate BO for amdkfd (%d)\n", r);
261 r = amdgpu_bo_reserve(bo, true);
263 dev_err(adev->dev, "(%d) failed to reserve bo for amdkfd\n", r);
264 goto allocate_mem_reserve_bo_failed;
267 r = amdgpu_bo_pin(bo, AMDGPU_GEM_DOMAIN_GTT);
269 dev_err(adev->dev, "(%d) failed to pin bo for amdkfd\n", r);
270 goto allocate_mem_pin_bo_failed;
273 r = amdgpu_ttm_alloc_gart(&bo->tbo);
275 dev_err(adev->dev, "%p bind failed\n", bo);
276 goto allocate_mem_kmap_bo_failed;
279 r = amdgpu_bo_kmap(bo, &cpu_ptr_tmp);
282 "(%d) failed to map bo to kernel for amdkfd\n", r);
283 goto allocate_mem_kmap_bo_failed;
287 *gpu_addr = amdgpu_bo_gpu_offset(bo);
288 *cpu_ptr = cpu_ptr_tmp;
290 amdgpu_bo_unreserve(bo);
294 allocate_mem_kmap_bo_failed:
296 allocate_mem_pin_bo_failed:
297 amdgpu_bo_unreserve(bo);
298 allocate_mem_reserve_bo_failed:
299 amdgpu_bo_unref(&bo);
304 void amdgpu_amdkfd_free_gtt_mem(struct kgd_dev *kgd, void *mem_obj)
306 struct amdgpu_bo *bo = (struct amdgpu_bo *) mem_obj;
308 amdgpu_bo_reserve(bo, true);
309 amdgpu_bo_kunmap(bo);
311 amdgpu_bo_unreserve(bo);
312 amdgpu_bo_unref(&(bo));
315 int amdgpu_amdkfd_alloc_gws(struct kgd_dev *kgd, size_t size,
318 struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
319 struct amdgpu_bo *bo = NULL;
320 struct amdgpu_bo_param bp;
323 memset(&bp, 0, sizeof(bp));
326 bp.domain = AMDGPU_GEM_DOMAIN_GWS;
327 bp.flags = AMDGPU_GEM_CREATE_NO_CPU_ACCESS;
328 bp.type = ttm_bo_type_device;
331 r = amdgpu_bo_create(adev, &bp, &bo);
334 "failed to allocate gws BO for amdkfd (%d)\n", r);
342 void amdgpu_amdkfd_free_gws(struct kgd_dev *kgd, void *mem_obj)
344 struct amdgpu_bo *bo = (struct amdgpu_bo *)mem_obj;
346 amdgpu_bo_unref(&bo);
349 uint32_t amdgpu_amdkfd_get_fw_version(struct kgd_dev *kgd,
350 enum kgd_engine_type type)
352 struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
356 return adev->gfx.pfp_fw_version;
359 return adev->gfx.me_fw_version;
362 return adev->gfx.ce_fw_version;
364 case KGD_ENGINE_MEC1:
365 return adev->gfx.mec_fw_version;
367 case KGD_ENGINE_MEC2:
368 return adev->gfx.mec2_fw_version;
371 return adev->gfx.rlc_fw_version;
373 case KGD_ENGINE_SDMA1:
374 return adev->sdma.instance[0].fw_version;
376 case KGD_ENGINE_SDMA2:
377 return adev->sdma.instance[1].fw_version;
386 void amdgpu_amdkfd_get_local_mem_info(struct kgd_dev *kgd,
387 struct kfd_local_mem_info *mem_info)
389 struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
391 memset(mem_info, 0, sizeof(*mem_info));
393 mem_info->local_mem_size_public = adev->gmc.visible_vram_size;
394 mem_info->local_mem_size_private = adev->gmc.real_vram_size -
395 adev->gmc.visible_vram_size;
397 mem_info->vram_width = adev->gmc.vram_width;
399 pr_debug("Address base: %pap public 0x%llx private 0x%llx\n",
400 &adev->gmc.aper_base,
401 mem_info->local_mem_size_public,
402 mem_info->local_mem_size_private);
404 if (amdgpu_sriov_vf(adev))
405 mem_info->mem_clk_max = adev->clock.default_mclk / 100;
406 else if (adev->pm.dpm_enabled) {
407 if (amdgpu_emu_mode == 1)
408 mem_info->mem_clk_max = 0;
410 mem_info->mem_clk_max = amdgpu_dpm_get_mclk(adev, false) / 100;
412 mem_info->mem_clk_max = 100;
415 uint64_t amdgpu_amdkfd_get_gpu_clock_counter(struct kgd_dev *kgd)
417 struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
419 if (adev->gfx.funcs->get_gpu_clock_counter)
420 return adev->gfx.funcs->get_gpu_clock_counter(adev);
424 uint32_t amdgpu_amdkfd_get_max_engine_clock_in_mhz(struct kgd_dev *kgd)
426 struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
428 /* the sclk is in quantas of 10kHz */
429 if (amdgpu_sriov_vf(adev))
430 return adev->clock.default_sclk / 100;
431 else if (adev->pm.dpm_enabled)
432 return amdgpu_dpm_get_sclk(adev, false) / 100;
437 void amdgpu_amdkfd_get_cu_info(struct kgd_dev *kgd, struct kfd_cu_info *cu_info)
439 struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
440 struct amdgpu_cu_info acu_info = adev->gfx.cu_info;
442 memset(cu_info, 0, sizeof(*cu_info));
443 if (sizeof(cu_info->cu_bitmap) != sizeof(acu_info.bitmap))
446 cu_info->cu_active_number = acu_info.number;
447 cu_info->cu_ao_mask = acu_info.ao_cu_mask;
448 memcpy(&cu_info->cu_bitmap[0], &acu_info.bitmap[0],
449 sizeof(acu_info.bitmap));
450 cu_info->num_shader_engines = adev->gfx.config.max_shader_engines;
451 cu_info->num_shader_arrays_per_engine = adev->gfx.config.max_sh_per_se;
452 cu_info->num_cu_per_sh = adev->gfx.config.max_cu_per_sh;
453 cu_info->simd_per_cu = acu_info.simd_per_cu;
454 cu_info->max_waves_per_simd = acu_info.max_waves_per_simd;
455 cu_info->wave_front_size = acu_info.wave_front_size;
456 cu_info->max_scratch_slots_per_cu = acu_info.max_scratch_slots_per_cu;
457 cu_info->lds_size = acu_info.lds_size;
460 int amdgpu_amdkfd_get_dmabuf_info(struct kgd_dev *kgd, int dma_buf_fd,
461 struct kgd_dev **dma_buf_kgd,
462 uint64_t *bo_size, void *metadata_buffer,
463 size_t buffer_size, uint32_t *metadata_size,
466 struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
467 struct dma_buf *dma_buf;
468 struct drm_gem_object *obj;
469 struct amdgpu_bo *bo;
470 uint64_t metadata_flags;
473 dma_buf = dma_buf_get(dma_buf_fd);
475 return PTR_ERR(dma_buf);
477 if (dma_buf->ops != &amdgpu_dmabuf_ops)
478 /* Can't handle non-graphics buffers */
482 if (obj->dev->driver != adev_to_drm(adev)->driver)
483 /* Can't handle buffers from different drivers */
486 adev = drm_to_adev(obj->dev);
487 bo = gem_to_amdgpu_bo(obj);
488 if (!(bo->preferred_domains & (AMDGPU_GEM_DOMAIN_VRAM |
489 AMDGPU_GEM_DOMAIN_GTT)))
490 /* Only VRAM and GTT BOs are supported */
495 *dma_buf_kgd = (struct kgd_dev *)adev;
497 *bo_size = amdgpu_bo_size(bo);
499 *metadata_size = bo->metadata_size;
501 r = amdgpu_bo_get_metadata(bo, metadata_buffer, buffer_size,
502 metadata_size, &metadata_flags);
504 *flags = (bo->preferred_domains & AMDGPU_GEM_DOMAIN_VRAM) ?
505 KFD_IOC_ALLOC_MEM_FLAGS_VRAM
506 : KFD_IOC_ALLOC_MEM_FLAGS_GTT;
508 if (bo->flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED)
509 *flags |= KFD_IOC_ALLOC_MEM_FLAGS_PUBLIC;
513 dma_buf_put(dma_buf);
517 uint64_t amdgpu_amdkfd_get_vram_usage(struct kgd_dev *kgd)
519 struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
520 struct ttm_resource_manager *vram_man = ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM);
522 return amdgpu_vram_mgr_usage(vram_man);
525 uint64_t amdgpu_amdkfd_get_hive_id(struct kgd_dev *kgd)
527 struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
529 return adev->gmc.xgmi.hive_id;
532 uint64_t amdgpu_amdkfd_get_unique_id(struct kgd_dev *kgd)
534 struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
536 return adev->unique_id;
539 uint8_t amdgpu_amdkfd_get_xgmi_hops_count(struct kgd_dev *dst, struct kgd_dev *src)
541 struct amdgpu_device *peer_adev = (struct amdgpu_device *)src;
542 struct amdgpu_device *adev = (struct amdgpu_device *)dst;
543 int ret = amdgpu_xgmi_get_hops_count(adev, peer_adev);
546 DRM_ERROR("amdgpu: failed to get xgmi hops count between node %d and %d. ret = %d\n",
547 adev->gmc.xgmi.physical_node_id,
548 peer_adev->gmc.xgmi.physical_node_id, ret);
554 uint64_t amdgpu_amdkfd_get_mmio_remap_phys_addr(struct kgd_dev *kgd)
556 struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
558 return adev->rmmio_remap.bus_addr;
561 uint32_t amdgpu_amdkfd_get_num_gws(struct kgd_dev *kgd)
563 struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
565 return adev->gds.gws_size;
568 uint32_t amdgpu_amdkfd_get_asic_rev_id(struct kgd_dev *kgd)
570 struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
575 int amdgpu_amdkfd_get_noretry(struct kgd_dev *kgd)
577 struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
579 return adev->gmc.noretry;
582 int amdgpu_amdkfd_submit_ib(struct kgd_dev *kgd, enum kgd_engine_type engine,
583 uint32_t vmid, uint64_t gpu_addr,
584 uint32_t *ib_cmd, uint32_t ib_len)
586 struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
587 struct amdgpu_job *job;
588 struct amdgpu_ib *ib;
589 struct amdgpu_ring *ring;
590 struct dma_fence *f = NULL;
594 case KGD_ENGINE_MEC1:
595 ring = &adev->gfx.compute_ring[0];
597 case KGD_ENGINE_SDMA1:
598 ring = &adev->sdma.instance[0].ring;
600 case KGD_ENGINE_SDMA2:
601 ring = &adev->sdma.instance[1].ring;
604 pr_err("Invalid engine in IB submission: %d\n", engine);
609 ret = amdgpu_job_alloc(adev, 1, &job, NULL);
614 memset(ib, 0, sizeof(struct amdgpu_ib));
616 ib->gpu_addr = gpu_addr;
618 ib->length_dw = ib_len;
619 /* This works for NO_HWS. TODO: need to handle without knowing VMID */
622 ret = amdgpu_ib_schedule(ring, 1, ib, job, &f);
625 DRM_ERROR("amdgpu: failed to schedule IB.\n");
629 ret = dma_fence_wait(f, false);
633 amdgpu_job_free(job);
638 void amdgpu_amdkfd_set_compute_idle(struct kgd_dev *kgd, bool idle)
640 struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
642 /* Temp workaround to fix the soft hang observed in certain compute
643 * applications if GFXOFF is enabled.
645 if (adev->asic_type == CHIP_SIENNA_CICHLID) {
646 pr_debug("GFXOFF is %s\n", idle ? "enabled" : "disabled");
647 amdgpu_gfx_off_ctrl(adev, idle);
649 amdgpu_dpm_switch_power_profile(adev,
650 PP_SMC_POWER_PROFILE_COMPUTE,
654 bool amdgpu_amdkfd_is_kfd_vmid(struct amdgpu_device *adev, u32 vmid)
657 return vmid >= adev->vm_manager.first_kfd_vmid;
662 int amdgpu_amdkfd_flush_gpu_tlb_vmid(struct kgd_dev *kgd, uint16_t vmid)
664 struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
666 if (adev->family == AMDGPU_FAMILY_AI) {
669 for (i = 0; i < adev->num_vmhubs; i++)
670 amdgpu_gmc_flush_gpu_tlb(adev, vmid, i, 0);
672 amdgpu_gmc_flush_gpu_tlb(adev, vmid, AMDGPU_GFXHUB_0, 0);
678 int amdgpu_amdkfd_flush_gpu_tlb_pasid(struct kgd_dev *kgd, uint16_t pasid)
680 struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
681 const uint32_t flush_type = 0;
682 bool all_hub = false;
684 if (adev->family == AMDGPU_FAMILY_AI)
687 return amdgpu_gmc_flush_gpu_tlb_pasid(adev, pasid, flush_type, all_hub);
690 bool amdgpu_amdkfd_have_atomics_support(struct kgd_dev *kgd)
692 struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
694 return adev->have_atomics_support;