2 * Copyright 2015 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
26 #include <linux/irqdomain.h>
27 #include <linux/pm_domain.h>
28 #include <linux/platform_device.h>
29 #include <sound/designware_i2s.h>
30 #include <sound/pcm.h>
34 #include "amdgpu_acp.h"
36 #include "acp_gfx_if.h"
38 #define ACP_TILE_ON_MASK 0x03
39 #define ACP_TILE_OFF_MASK 0x02
40 #define ACP_TILE_ON_RETAIN_REG_MASK 0x1f
41 #define ACP_TILE_OFF_RETAIN_REG_MASK 0x20
43 #define ACP_TILE_P1_MASK 0x3e
44 #define ACP_TILE_P2_MASK 0x3d
45 #define ACP_TILE_DSP0_MASK 0x3b
46 #define ACP_TILE_DSP1_MASK 0x37
48 #define ACP_TILE_DSP2_MASK 0x2f
50 #define ACP_DMA_REGS_END 0x146c0
51 #define ACP_I2S_PLAY_REGS_START 0x14840
52 #define ACP_I2S_PLAY_REGS_END 0x148b4
53 #define ACP_I2S_CAP_REGS_START 0x148b8
54 #define ACP_I2S_CAP_REGS_END 0x1496c
56 #define ACP_I2S_COMP1_CAP_REG_OFFSET 0xac
57 #define ACP_I2S_COMP2_CAP_REG_OFFSET 0xa8
58 #define ACP_I2S_COMP1_PLAY_REG_OFFSET 0x6c
59 #define ACP_I2S_COMP2_PLAY_REG_OFFSET 0x68
60 #define ACP_BT_PLAY_REGS_START 0x14970
61 #define ACP_BT_PLAY_REGS_END 0x14a24
62 #define ACP_BT_COMP1_REG_OFFSET 0xac
63 #define ACP_BT_COMP2_REG_OFFSET 0xa8
65 #define mmACP_PGFSM_RETAIN_REG 0x51c9
66 #define mmACP_PGFSM_CONFIG_REG 0x51ca
67 #define mmACP_PGFSM_READ_REG_0 0x51cc
69 #define mmACP_MEM_SHUT_DOWN_REQ_LO 0x51f8
70 #define mmACP_MEM_SHUT_DOWN_REQ_HI 0x51f9
71 #define mmACP_MEM_SHUT_DOWN_STS_LO 0x51fa
72 #define mmACP_MEM_SHUT_DOWN_STS_HI 0x51fb
74 #define mmACP_CONTROL 0x5131
75 #define mmACP_STATUS 0x5133
76 #define mmACP_SOFT_RESET 0x5134
77 #define ACP_CONTROL__ClkEn_MASK 0x1
78 #define ACP_SOFT_RESET__SoftResetAud_MASK 0x100
79 #define ACP_SOFT_RESET__SoftResetAudDone_MASK 0x1000000
80 #define ACP_CLOCK_EN_TIME_OUT_VALUE 0x000000FF
81 #define ACP_SOFT_RESET_DONE_TIME_OUT_VALUE 0x000000FF
83 #define ACP_TIMEOUT_LOOP 0x000000FF
85 #define ACP_SRC_ID 162
95 static int acp_sw_init(void *handle)
97 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
99 adev->acp.parent = adev->dev;
101 adev->acp.cgs_device =
102 amdgpu_cgs_create_device(adev);
103 if (!adev->acp.cgs_device)
109 static int acp_sw_fini(void *handle)
111 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
113 if (adev->acp.cgs_device)
114 amdgpu_cgs_destroy_device(adev->acp.cgs_device);
119 struct acp_pm_domain {
121 struct generic_pm_domain gpd;
124 static int acp_poweroff(struct generic_pm_domain *genpd)
126 struct acp_pm_domain *apd;
127 struct amdgpu_device *adev;
129 apd = container_of(genpd, struct acp_pm_domain, gpd);
132 /* call smu to POWER GATE ACP block
134 * 1. turn off the acp clock
135 * 2. power off the acp tiles
136 * 3. check and enter ulv state
138 if (adev->powerplay.pp_funcs &&
139 adev->powerplay.pp_funcs->set_powergating_by_smu)
140 amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP, true);
145 static int acp_poweron(struct generic_pm_domain *genpd)
147 struct acp_pm_domain *apd;
148 struct amdgpu_device *adev;
150 apd = container_of(genpd, struct acp_pm_domain, gpd);
153 /* call smu to UNGATE ACP block
156 * 2. turn on acp clock
157 * 3. power on acp tiles
159 if (adev->powerplay.pp_funcs->set_powergating_by_smu)
160 amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP, false);
165 static struct device *get_mfd_cell_dev(const char *device_name, int r)
167 char auto_dev_name[25];
170 snprintf(auto_dev_name, sizeof(auto_dev_name),
171 "%s.%d.auto", device_name, r);
172 dev = bus_find_device_by_name(&platform_bus_type, NULL, auto_dev_name);
173 dev_info(dev, "device %s added to pm domain\n", auto_dev_name);
179 * acp_hw_init - start and test ACP block
181 * @adev: amdgpu_device pointer
184 static int acp_hw_init(void *handle)
191 struct i2s_platform_data *i2s_pdata;
193 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
195 const struct amdgpu_ip_block *ip_block =
196 amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_ACP);
201 r = amd_acp_hw_init(adev->acp.cgs_device,
202 ip_block->version->major, ip_block->version->minor);
203 /* -ENODEV means board uses AZ rather than ACP */
205 amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP, true);
211 if (adev->rmmio_size == 0 || adev->rmmio_size < 0x5289)
214 acp_base = adev->rmmio_base;
217 adev->acp.acp_genpd = kzalloc(sizeof(struct acp_pm_domain), GFP_KERNEL);
218 if (adev->acp.acp_genpd == NULL)
221 adev->acp.acp_genpd->gpd.name = "ACP_AUDIO";
222 adev->acp.acp_genpd->gpd.power_off = acp_poweroff;
223 adev->acp.acp_genpd->gpd.power_on = acp_poweron;
226 adev->acp.acp_genpd->adev = adev;
228 pm_genpd_init(&adev->acp.acp_genpd->gpd, NULL, false);
230 adev->acp.acp_cell = kcalloc(ACP_DEVS, sizeof(struct mfd_cell),
233 if (adev->acp.acp_cell == NULL)
236 adev->acp.acp_res = kcalloc(5, sizeof(struct resource), GFP_KERNEL);
237 if (adev->acp.acp_res == NULL) {
238 kfree(adev->acp.acp_cell);
242 i2s_pdata = kcalloc(3, sizeof(struct i2s_platform_data), GFP_KERNEL);
243 if (i2s_pdata == NULL) {
244 kfree(adev->acp.acp_res);
245 kfree(adev->acp.acp_cell);
249 switch (adev->asic_type) {
251 i2s_pdata[0].quirks = DW_I2S_QUIRK_COMP_REG_OFFSET |
252 DW_I2S_QUIRK_16BIT_IDX_OVERRIDE;
255 i2s_pdata[0].quirks = DW_I2S_QUIRK_COMP_REG_OFFSET;
257 i2s_pdata[0].cap = DWC_I2S_PLAY;
258 i2s_pdata[0].snd_rates = SNDRV_PCM_RATE_8000_96000;
259 i2s_pdata[0].i2s_reg_comp1 = ACP_I2S_COMP1_PLAY_REG_OFFSET;
260 i2s_pdata[0].i2s_reg_comp2 = ACP_I2S_COMP2_PLAY_REG_OFFSET;
261 switch (adev->asic_type) {
263 i2s_pdata[1].quirks = DW_I2S_QUIRK_COMP_REG_OFFSET |
264 DW_I2S_QUIRK_COMP_PARAM1 |
265 DW_I2S_QUIRK_16BIT_IDX_OVERRIDE;
268 i2s_pdata[1].quirks = DW_I2S_QUIRK_COMP_REG_OFFSET |
269 DW_I2S_QUIRK_COMP_PARAM1;
272 i2s_pdata[1].cap = DWC_I2S_RECORD;
273 i2s_pdata[1].snd_rates = SNDRV_PCM_RATE_8000_96000;
274 i2s_pdata[1].i2s_reg_comp1 = ACP_I2S_COMP1_CAP_REG_OFFSET;
275 i2s_pdata[1].i2s_reg_comp2 = ACP_I2S_COMP2_CAP_REG_OFFSET;
277 i2s_pdata[2].quirks = DW_I2S_QUIRK_COMP_REG_OFFSET;
278 switch (adev->asic_type) {
280 i2s_pdata[2].quirks |= DW_I2S_QUIRK_16BIT_IDX_OVERRIDE;
286 i2s_pdata[2].cap = DWC_I2S_PLAY | DWC_I2S_RECORD;
287 i2s_pdata[2].snd_rates = SNDRV_PCM_RATE_8000_96000;
288 i2s_pdata[2].i2s_reg_comp1 = ACP_BT_COMP1_REG_OFFSET;
289 i2s_pdata[2].i2s_reg_comp2 = ACP_BT_COMP2_REG_OFFSET;
291 adev->acp.acp_res[0].name = "acp2x_dma";
292 adev->acp.acp_res[0].flags = IORESOURCE_MEM;
293 adev->acp.acp_res[0].start = acp_base;
294 adev->acp.acp_res[0].end = acp_base + ACP_DMA_REGS_END;
296 adev->acp.acp_res[1].name = "acp2x_dw_i2s_play";
297 adev->acp.acp_res[1].flags = IORESOURCE_MEM;
298 adev->acp.acp_res[1].start = acp_base + ACP_I2S_PLAY_REGS_START;
299 adev->acp.acp_res[1].end = acp_base + ACP_I2S_PLAY_REGS_END;
301 adev->acp.acp_res[2].name = "acp2x_dw_i2s_cap";
302 adev->acp.acp_res[2].flags = IORESOURCE_MEM;
303 adev->acp.acp_res[2].start = acp_base + ACP_I2S_CAP_REGS_START;
304 adev->acp.acp_res[2].end = acp_base + ACP_I2S_CAP_REGS_END;
306 adev->acp.acp_res[3].name = "acp2x_dw_bt_i2s_play_cap";
307 adev->acp.acp_res[3].flags = IORESOURCE_MEM;
308 adev->acp.acp_res[3].start = acp_base + ACP_BT_PLAY_REGS_START;
309 adev->acp.acp_res[3].end = acp_base + ACP_BT_PLAY_REGS_END;
311 adev->acp.acp_res[4].name = "acp2x_dma_irq";
312 adev->acp.acp_res[4].flags = IORESOURCE_IRQ;
313 adev->acp.acp_res[4].start = amdgpu_irq_create_mapping(adev, 162);
314 adev->acp.acp_res[4].end = adev->acp.acp_res[4].start;
316 adev->acp.acp_cell[0].name = "acp_audio_dma";
317 adev->acp.acp_cell[0].num_resources = 5;
318 adev->acp.acp_cell[0].resources = &adev->acp.acp_res[0];
319 adev->acp.acp_cell[0].platform_data = &adev->asic_type;
320 adev->acp.acp_cell[0].pdata_size = sizeof(adev->asic_type);
322 adev->acp.acp_cell[1].name = "designware-i2s";
323 adev->acp.acp_cell[1].num_resources = 1;
324 adev->acp.acp_cell[1].resources = &adev->acp.acp_res[1];
325 adev->acp.acp_cell[1].platform_data = &i2s_pdata[0];
326 adev->acp.acp_cell[1].pdata_size = sizeof(struct i2s_platform_data);
328 adev->acp.acp_cell[2].name = "designware-i2s";
329 adev->acp.acp_cell[2].num_resources = 1;
330 adev->acp.acp_cell[2].resources = &adev->acp.acp_res[2];
331 adev->acp.acp_cell[2].platform_data = &i2s_pdata[1];
332 adev->acp.acp_cell[2].pdata_size = sizeof(struct i2s_platform_data);
334 adev->acp.acp_cell[3].name = "designware-i2s";
335 adev->acp.acp_cell[3].num_resources = 1;
336 adev->acp.acp_cell[3].resources = &adev->acp.acp_res[3];
337 adev->acp.acp_cell[3].platform_data = &i2s_pdata[2];
338 adev->acp.acp_cell[3].pdata_size = sizeof(struct i2s_platform_data);
340 r = mfd_add_hotplug_devices(adev->acp.parent, adev->acp.acp_cell,
345 for (i = 0; i < ACP_DEVS ; i++) {
346 dev = get_mfd_cell_dev(adev->acp.acp_cell[i].name, i);
347 r = pm_genpd_add_device(&adev->acp.acp_genpd->gpd, dev);
349 dev_err(dev, "Failed to add dev to genpd\n");
355 /* Assert Soft reset of ACP */
356 val = cgs_read_register(adev->acp.cgs_device, mmACP_SOFT_RESET);
358 val |= ACP_SOFT_RESET__SoftResetAud_MASK;
359 cgs_write_register(adev->acp.cgs_device, mmACP_SOFT_RESET, val);
361 count = ACP_SOFT_RESET_DONE_TIME_OUT_VALUE;
363 val = cgs_read_register(adev->acp.cgs_device, mmACP_SOFT_RESET);
364 if (ACP_SOFT_RESET__SoftResetAudDone_MASK ==
365 (val & ACP_SOFT_RESET__SoftResetAudDone_MASK))
368 dev_err(&adev->pdev->dev, "Failed to reset ACP\n");
373 /* Enable clock to ACP and wait until the clock is enabled */
374 val = cgs_read_register(adev->acp.cgs_device, mmACP_CONTROL);
375 val = val | ACP_CONTROL__ClkEn_MASK;
376 cgs_write_register(adev->acp.cgs_device, mmACP_CONTROL, val);
378 count = ACP_CLOCK_EN_TIME_OUT_VALUE;
381 val = cgs_read_register(adev->acp.cgs_device, mmACP_STATUS);
385 dev_err(&adev->pdev->dev, "Failed to reset ACP\n");
390 /* Deassert the SOFT RESET flags */
391 val = cgs_read_register(adev->acp.cgs_device, mmACP_SOFT_RESET);
392 val &= ~ACP_SOFT_RESET__SoftResetAud_MASK;
393 cgs_write_register(adev->acp.cgs_device, mmACP_SOFT_RESET, val);
398 * acp_hw_fini - stop the hardware block
400 * @adev: amdgpu_device pointer
403 static int acp_hw_fini(void *handle)
409 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
411 /* return early if no ACP */
412 if (!adev->acp.acp_genpd) {
413 amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP, false);
417 /* Assert Soft reset of ACP */
418 val = cgs_read_register(adev->acp.cgs_device, mmACP_SOFT_RESET);
420 val |= ACP_SOFT_RESET__SoftResetAud_MASK;
421 cgs_write_register(adev->acp.cgs_device, mmACP_SOFT_RESET, val);
423 count = ACP_SOFT_RESET_DONE_TIME_OUT_VALUE;
425 val = cgs_read_register(adev->acp.cgs_device, mmACP_SOFT_RESET);
426 if (ACP_SOFT_RESET__SoftResetAudDone_MASK ==
427 (val & ACP_SOFT_RESET__SoftResetAudDone_MASK))
430 dev_err(&adev->pdev->dev, "Failed to reset ACP\n");
435 /* Disable ACP clock */
436 val = cgs_read_register(adev->acp.cgs_device, mmACP_CONTROL);
437 val &= ~ACP_CONTROL__ClkEn_MASK;
438 cgs_write_register(adev->acp.cgs_device, mmACP_CONTROL, val);
440 count = ACP_CLOCK_EN_TIME_OUT_VALUE;
443 val = cgs_read_register(adev->acp.cgs_device, mmACP_STATUS);
447 dev_err(&adev->pdev->dev, "Failed to reset ACP\n");
453 for (i = 0; i < ACP_DEVS ; i++) {
454 dev = get_mfd_cell_dev(adev->acp.acp_cell[i].name, i);
455 ret = pm_genpd_remove_device(dev);
456 /* If removal fails, dont giveup and try rest */
458 dev_err(dev, "remove dev from genpd failed\n");
461 mfd_remove_devices(adev->acp.parent);
462 kfree(adev->acp.acp_res);
463 kfree(adev->acp.acp_genpd);
464 kfree(adev->acp.acp_cell);
469 static int acp_suspend(void *handle)
471 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
473 /* power up on suspend */
474 if (!adev->acp.acp_cell)
475 amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP, false);
479 static int acp_resume(void *handle)
481 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
483 /* power down again on resume */
484 if (!adev->acp.acp_cell)
485 amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP, true);
489 static int acp_early_init(void *handle)
494 static bool acp_is_idle(void *handle)
499 static int acp_wait_for_idle(void *handle)
504 static int acp_soft_reset(void *handle)
509 static int acp_set_clockgating_state(void *handle,
510 enum amd_clockgating_state state)
515 static int acp_set_powergating_state(void *handle,
516 enum amd_powergating_state state)
518 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
519 bool enable = state == AMD_PG_STATE_GATE ? true : false;
521 if (adev->powerplay.pp_funcs &&
522 adev->powerplay.pp_funcs->set_powergating_by_smu)
523 amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP, enable);
528 static const struct amd_ip_funcs acp_ip_funcs = {
530 .early_init = acp_early_init,
532 .sw_init = acp_sw_init,
533 .sw_fini = acp_sw_fini,
534 .hw_init = acp_hw_init,
535 .hw_fini = acp_hw_fini,
536 .suspend = acp_suspend,
537 .resume = acp_resume,
538 .is_idle = acp_is_idle,
539 .wait_for_idle = acp_wait_for_idle,
540 .soft_reset = acp_soft_reset,
541 .set_clockgating_state = acp_set_clockgating_state,
542 .set_powergating_state = acp_set_powergating_state,
545 const struct amdgpu_ip_block_version acp_ip_block =
547 .type = AMD_IP_BLOCK_TYPE_ACP,
551 .funcs = &acp_ip_funcs,