2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
35 #define pr_fmt(fmt) "amdgpu: " fmt
41 #define dev_fmt(fmt) "amdgpu: " fmt
43 #include "amdgpu_ctx.h"
45 #include <linux/atomic.h>
46 #include <linux/wait.h>
47 #include <linux/list.h>
48 #include <linux/kref.h>
49 #include <linux/rbtree.h>
50 #include <linux/hashtable.h>
51 #include <linux/dma-fence.h>
53 #include <drm/ttm/ttm_bo_api.h>
54 #include <drm/ttm/ttm_bo_driver.h>
55 #include <drm/ttm/ttm_placement.h>
56 #include <drm/ttm/ttm_module.h>
57 #include <drm/ttm/ttm_execbuf_util.h>
59 #include <drm/amdgpu_drm.h>
60 #include <drm/drm_gem.h>
61 #include <drm/drm_ioctl.h>
62 #include <drm/gpu_scheduler.h>
64 #include <kgd_kfd_interface.h>
65 #include "dm_pp_interface.h"
66 #include "kgd_pp_interface.h"
68 #include "amd_shared.h"
69 #include "amdgpu_mode.h"
70 #include "amdgpu_ih.h"
71 #include "amdgpu_irq.h"
72 #include "amdgpu_ucode.h"
73 #include "amdgpu_ttm.h"
74 #include "amdgpu_psp.h"
75 #include "amdgpu_gds.h"
76 #include "amdgpu_sync.h"
77 #include "amdgpu_ring.h"
78 #include "amdgpu_vm.h"
79 #include "amdgpu_dpm.h"
80 #include "amdgpu_acp.h"
81 #include "amdgpu_uvd.h"
82 #include "amdgpu_vce.h"
83 #include "amdgpu_vcn.h"
84 #include "amdgpu_jpeg.h"
85 #include "amdgpu_mn.h"
86 #include "amdgpu_gmc.h"
87 #include "amdgpu_gfx.h"
88 #include "amdgpu_sdma.h"
89 #include "amdgpu_nbio.h"
90 #include "amdgpu_dm.h"
91 #include "amdgpu_virt.h"
92 #include "amdgpu_csa.h"
93 #include "amdgpu_gart.h"
94 #include "amdgpu_debugfs.h"
95 #include "amdgpu_job.h"
96 #include "amdgpu_bo_list.h"
97 #include "amdgpu_gem.h"
98 #include "amdgpu_doorbell.h"
99 #include "amdgpu_amdkfd.h"
100 #include "amdgpu_smu.h"
101 #include "amdgpu_discovery.h"
102 #include "amdgpu_mes.h"
103 #include "amdgpu_umc.h"
104 #include "amdgpu_mmhub.h"
105 #include "amdgpu_df.h"
107 #define MAX_GPU_INSTANCE 16
109 struct amdgpu_gpu_instance
111 struct amdgpu_device *adev;
112 int mgpu_fan_enabled;
115 struct amdgpu_mgpu_info
117 struct amdgpu_gpu_instance gpu_ins[MAX_GPU_INSTANCE];
124 #define AMDGPU_MAX_TIMEOUT_PARAM_LENGTH 256
127 * Modules parameters.
129 extern int amdgpu_modeset;
130 extern int amdgpu_vram_limit;
131 extern int amdgpu_vis_vram_limit;
132 extern int amdgpu_gart_size;
133 extern int amdgpu_gtt_size;
134 extern int amdgpu_moverate;
135 extern int amdgpu_benchmarking;
136 extern int amdgpu_testing;
137 extern int amdgpu_audio;
138 extern int amdgpu_disp_priority;
139 extern int amdgpu_hw_i2c;
140 extern int amdgpu_pcie_gen2;
141 extern int amdgpu_msi;
142 extern char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENGTH];
143 extern int amdgpu_dpm;
144 extern int amdgpu_fw_load_type;
145 extern int amdgpu_aspm;
146 extern int amdgpu_runtime_pm;
147 extern uint amdgpu_ip_block_mask;
148 extern int amdgpu_bapm;
149 extern int amdgpu_deep_color;
150 extern int amdgpu_vm_size;
151 extern int amdgpu_vm_block_size;
152 extern int amdgpu_vm_fragment_size;
153 extern int amdgpu_vm_fault_stop;
154 extern int amdgpu_vm_debug;
155 extern int amdgpu_vm_update_mode;
156 extern int amdgpu_exp_hw_support;
157 extern int amdgpu_dc;
158 extern int amdgpu_sched_jobs;
159 extern int amdgpu_sched_hw_submission;
160 extern uint amdgpu_pcie_gen_cap;
161 extern uint amdgpu_pcie_lane_cap;
162 extern uint amdgpu_cg_mask;
163 extern uint amdgpu_pg_mask;
164 extern uint amdgpu_sdma_phase_quantum;
165 extern char *amdgpu_disable_cu;
166 extern char *amdgpu_virtual_display;
167 extern uint amdgpu_pp_feature_mask;
168 extern uint amdgpu_force_long_training;
169 extern int amdgpu_job_hang_limit;
170 extern int amdgpu_lbpw;
171 extern int amdgpu_compute_multipipe;
172 extern int amdgpu_gpu_recovery;
173 extern int amdgpu_emu_mode;
174 extern uint amdgpu_smu_memory_pool_size;
175 extern uint amdgpu_dc_feature_mask;
176 extern uint amdgpu_dm_abm_level;
177 extern struct amdgpu_mgpu_info mgpu_info;
178 extern int amdgpu_ras_enable;
179 extern uint amdgpu_ras_mask;
180 extern int amdgpu_async_gfx_ring;
181 extern int amdgpu_mcbp;
182 extern int amdgpu_discovery;
183 extern int amdgpu_mes;
184 extern int amdgpu_noretry;
185 extern int amdgpu_force_asic_type;
186 #ifdef CONFIG_HSA_AMD
187 extern int sched_policy;
189 static const int sched_policy = KFD_SCHED_POLICY_HWS;
192 extern int amdgpu_tmz;
194 #ifdef CONFIG_DRM_AMDGPU_SI
195 extern int amdgpu_si_support;
197 #ifdef CONFIG_DRM_AMDGPU_CIK
198 extern int amdgpu_cik_support;
201 #define AMDGPU_VM_MAX_NUM_CTX 4096
202 #define AMDGPU_SG_THRESHOLD (256*1024*1024)
203 #define AMDGPU_DEFAULT_GTT_SIZE_MB 3072ULL /* 3GB by default */
204 #define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000
205 #define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */
206 #define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2)
207 #define AMDGPU_DEBUGFS_MAX_COMPONENTS 32
208 #define AMDGPUFB_CONN_LIMIT 4
209 #define AMDGPU_BIOS_NUM_SCRATCH 16
211 /* hard reset data */
212 #define AMDGPU_ASIC_RESET_DATA 0x39d5e86b
215 #define AMDGPU_RESET_GFX (1 << 0)
216 #define AMDGPU_RESET_COMPUTE (1 << 1)
217 #define AMDGPU_RESET_DMA (1 << 2)
218 #define AMDGPU_RESET_CP (1 << 3)
219 #define AMDGPU_RESET_GRBM (1 << 4)
220 #define AMDGPU_RESET_DMA1 (1 << 5)
221 #define AMDGPU_RESET_RLC (1 << 6)
222 #define AMDGPU_RESET_SEM (1 << 7)
223 #define AMDGPU_RESET_IH (1 << 8)
224 #define AMDGPU_RESET_VMC (1 << 9)
225 #define AMDGPU_RESET_MC (1 << 10)
226 #define AMDGPU_RESET_DISPLAY (1 << 11)
227 #define AMDGPU_RESET_UVD (1 << 12)
228 #define AMDGPU_RESET_VCE (1 << 13)
229 #define AMDGPU_RESET_VCE1 (1 << 14)
231 /* max cursor sizes (in pixels) */
232 #define CIK_CURSOR_WIDTH 128
233 #define CIK_CURSOR_HEIGHT 128
235 struct amdgpu_device;
237 struct amdgpu_cs_parser;
239 struct amdgpu_irq_src;
241 struct amdgpu_bo_va_mapping;
243 struct kfd_vm_fault_info;
246 AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP = 0,
247 AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP,
248 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP,
249 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP,
250 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP,
251 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP,
252 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP,
253 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP,
254 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP,
255 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP,
260 enum amdgpu_thermal_irq {
261 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0,
262 AMDGPU_THERMAL_IRQ_HIGH_TO_LOW,
264 AMDGPU_THERMAL_IRQ_LAST
267 enum amdgpu_kiq_irq {
268 AMDGPU_CP_KIQ_IRQ_DRIVER0 = 0,
269 AMDGPU_CP_KIQ_IRQ_LAST
272 #define MAX_KIQ_REG_WAIT 5000 /* in usecs, 5ms */
273 #define MAX_KIQ_REG_BAILOUT_INTERVAL 5 /* in msecs, 5ms */
274 #define MAX_KIQ_REG_TRY 80 /* 20 -> 80 */
276 int amdgpu_device_ip_set_clockgating_state(void *dev,
277 enum amd_ip_block_type block_type,
278 enum amd_clockgating_state state);
279 int amdgpu_device_ip_set_powergating_state(void *dev,
280 enum amd_ip_block_type block_type,
281 enum amd_powergating_state state);
282 void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev,
284 int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev,
285 enum amd_ip_block_type block_type);
286 bool amdgpu_device_ip_is_idle(struct amdgpu_device *adev,
287 enum amd_ip_block_type block_type);
289 #define AMDGPU_MAX_IP_NUM 16
291 struct amdgpu_ip_block_status {
295 bool late_initialized;
299 struct amdgpu_ip_block_version {
300 const enum amd_ip_block_type type;
304 const struct amd_ip_funcs *funcs;
307 #define HW_REV(_Major, _Minor, _Rev) \
308 ((((uint32_t) (_Major)) << 16) | ((uint32_t) (_Minor) << 8) | ((uint32_t) (_Rev)))
310 struct amdgpu_ip_block {
311 struct amdgpu_ip_block_status status;
312 const struct amdgpu_ip_block_version *version;
315 int amdgpu_device_ip_block_version_cmp(struct amdgpu_device *adev,
316 enum amd_ip_block_type type,
317 u32 major, u32 minor);
319 struct amdgpu_ip_block *
320 amdgpu_device_ip_get_ip_block(struct amdgpu_device *adev,
321 enum amd_ip_block_type type);
323 int amdgpu_device_ip_block_add(struct amdgpu_device *adev,
324 const struct amdgpu_ip_block_version *ip_block_version);
329 bool amdgpu_get_bios(struct amdgpu_device *adev);
330 bool amdgpu_read_bios(struct amdgpu_device *adev);
336 #define AMDGPU_MAX_PPLL 3
338 struct amdgpu_clock {
339 struct amdgpu_pll ppll[AMDGPU_MAX_PPLL];
340 struct amdgpu_pll spll;
341 struct amdgpu_pll mpll;
343 uint32_t default_mclk;
344 uint32_t default_sclk;
345 uint32_t default_dispclk;
346 uint32_t current_dispclk;
348 uint32_t max_pixel_clock;
351 /* sub-allocation manager, it has to be protected by another lock.
352 * By conception this is an helper for other part of the driver
353 * like the indirect buffer or semaphore, which both have their
356 * Principe is simple, we keep a list of sub allocation in offset
357 * order (first entry has offset == 0, last entry has the highest
360 * When allocating new object we first check if there is room at
361 * the end total_size - (last_object_offset + last_object_size) >=
362 * alloc_size. If so we allocate new object there.
364 * When there is not enough room at the end, we start waiting for
365 * each sub object until we reach object_offset+object_size >=
366 * alloc_size, this object then become the sub object we return.
368 * Alignment can't be bigger than page size.
370 * Hole are not considered for allocation to keep things simple.
371 * Assumption is that there won't be hole (all object on same
375 #define AMDGPU_SA_NUM_FENCE_LISTS 32
377 struct amdgpu_sa_manager {
378 wait_queue_head_t wq;
379 struct amdgpu_bo *bo;
380 struct list_head *hole;
381 struct list_head flist[AMDGPU_SA_NUM_FENCE_LISTS];
382 struct list_head olist;
390 /* sub-allocation buffer */
391 struct amdgpu_sa_bo {
392 struct list_head olist;
393 struct list_head flist;
394 struct amdgpu_sa_manager *manager;
397 struct dma_fence *fence;
400 int amdgpu_fence_slab_init(void);
401 void amdgpu_fence_slab_fini(void);
407 struct amdgpu_flip_work {
408 struct delayed_work flip_work;
409 struct work_struct unpin_work;
410 struct amdgpu_device *adev;
414 struct drm_pending_vblank_event *event;
415 struct amdgpu_bo *old_abo;
416 struct dma_fence *excl;
417 unsigned shared_count;
418 struct dma_fence **shared;
419 struct dma_fence_cb cb;
429 struct amdgpu_sa_bo *sa_bo;
436 extern const struct drm_sched_backend_ops amdgpu_sched_ops;
439 * file private structure
442 struct amdgpu_fpriv {
444 struct amdgpu_bo_va *prt_va;
445 struct amdgpu_bo_va *csa_va;
446 struct mutex bo_list_lock;
447 struct idr bo_list_handles;
448 struct amdgpu_ctx_mgr ctx_mgr;
451 int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv);
453 int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm,
455 enum amdgpu_ib_pool_type pool,
456 struct amdgpu_ib *ib);
457 void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib,
458 struct dma_fence *f);
459 int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
460 struct amdgpu_ib *ibs, struct amdgpu_job *job,
461 struct dma_fence **f);
462 int amdgpu_ib_pool_init(struct amdgpu_device *adev);
463 void amdgpu_ib_pool_fini(struct amdgpu_device *adev);
464 int amdgpu_ib_ring_tests(struct amdgpu_device *adev);
469 struct amdgpu_cs_chunk {
475 struct amdgpu_cs_post_dep {
476 struct drm_syncobj *syncobj;
477 struct dma_fence_chain *chain;
481 struct amdgpu_cs_parser {
482 struct amdgpu_device *adev;
483 struct drm_file *filp;
484 struct amdgpu_ctx *ctx;
488 struct amdgpu_cs_chunk *chunks;
490 /* scheduler job object */
491 struct amdgpu_job *job;
492 struct drm_sched_entity *entity;
495 struct ww_acquire_ctx ticket;
496 struct amdgpu_bo_list *bo_list;
497 struct amdgpu_mn *mn;
498 struct amdgpu_bo_list_entry vm_pd;
499 struct list_head validated;
500 struct dma_fence *fence;
501 uint64_t bytes_moved_threshold;
502 uint64_t bytes_moved_vis_threshold;
503 uint64_t bytes_moved;
504 uint64_t bytes_moved_vis;
507 struct amdgpu_bo_list_entry uf_entry;
509 unsigned num_post_deps;
510 struct amdgpu_cs_post_dep *post_deps;
513 static inline u32 amdgpu_get_ib_value(struct amdgpu_cs_parser *p,
514 uint32_t ib_idx, int idx)
516 return p->job->ibs[ib_idx].ptr[idx];
519 static inline void amdgpu_set_ib_value(struct amdgpu_cs_parser *p,
520 uint32_t ib_idx, int idx,
523 p->job->ibs[ib_idx].ptr[idx] = value;
529 #define AMDGPU_MAX_WB 256 /* Reserve at most 256 WB slots for amdgpu-owned rings. */
532 struct amdgpu_bo *wb_obj;
533 volatile uint32_t *wb;
535 u32 num_wb; /* Number of wb slots actually reserved for amdgpu. */
536 unsigned long used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)];
539 int amdgpu_device_wb_get(struct amdgpu_device *adev, u32 *wb);
540 void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb);
545 void amdgpu_benchmark(struct amdgpu_device *adev, int test_number);
551 void amdgpu_test_moves(struct amdgpu_device *adev);
554 * ASIC specific register table accessible by UMD
556 struct amdgpu_allowed_register_entry {
561 enum amd_reset_method {
562 AMD_RESET_METHOD_LEGACY = 0,
563 AMD_RESET_METHOD_MODE0,
564 AMD_RESET_METHOD_MODE1,
565 AMD_RESET_METHOD_MODE2,
566 AMD_RESET_METHOD_BACO
570 * ASIC specific functions.
572 struct amdgpu_asic_funcs {
573 bool (*read_disabled_bios)(struct amdgpu_device *adev);
574 bool (*read_bios_from_rom)(struct amdgpu_device *adev,
575 u8 *bios, u32 length_bytes);
576 int (*read_register)(struct amdgpu_device *adev, u32 se_num,
577 u32 sh_num, u32 reg_offset, u32 *value);
578 void (*set_vga_state)(struct amdgpu_device *adev, bool state);
579 int (*reset)(struct amdgpu_device *adev);
580 enum amd_reset_method (*reset_method)(struct amdgpu_device *adev);
581 /* get the reference clock */
582 u32 (*get_xclk)(struct amdgpu_device *adev);
583 /* MM block clocks */
584 int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk);
585 int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk);
586 /* static power management */
587 int (*get_pcie_lanes)(struct amdgpu_device *adev);
588 void (*set_pcie_lanes)(struct amdgpu_device *adev, int lanes);
589 /* get config memsize register */
590 u32 (*get_config_memsize)(struct amdgpu_device *adev);
591 /* flush hdp write queue */
592 void (*flush_hdp)(struct amdgpu_device *adev, struct amdgpu_ring *ring);
593 /* invalidate hdp read cache */
594 void (*invalidate_hdp)(struct amdgpu_device *adev,
595 struct amdgpu_ring *ring);
596 void (*reset_hdp_ras_error_count)(struct amdgpu_device *adev);
597 /* check if the asic needs a full reset of if soft reset will work */
598 bool (*need_full_reset)(struct amdgpu_device *adev);
599 /* initialize doorbell layout for specific asic*/
600 void (*init_doorbell_index)(struct amdgpu_device *adev);
601 /* PCIe bandwidth usage */
602 void (*get_pcie_usage)(struct amdgpu_device *adev, uint64_t *count0,
604 /* do we need to reset the asic at init time (e.g., kexec) */
605 bool (*need_reset_on_init)(struct amdgpu_device *adev);
606 /* PCIe replay counter */
607 uint64_t (*get_pcie_replay_count)(struct amdgpu_device *adev);
608 /* device supports BACO */
609 bool (*supports_baco)(struct amdgpu_device *adev);
615 int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data,
616 struct drm_file *filp);
618 int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
619 int amdgpu_cs_fence_to_handle_ioctl(struct drm_device *dev, void *data,
620 struct drm_file *filp);
621 int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
622 int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data,
623 struct drm_file *filp);
625 /* VRAM scratch page for HDP bug, default vram page */
626 struct amdgpu_vram_scratch {
627 struct amdgpu_bo *robj;
628 volatile uint32_t *ptr;
635 struct amdgpu_atcs_functions {
643 struct amdgpu_atcs_functions functions;
647 * Firmware VRAM reservation
649 struct amdgpu_fw_vram_usage {
652 struct amdgpu_bo *reserved_bo;
655 /* GDDR6 training support flag.
657 bool mem_train_support;
663 struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev);
664 void amdgpu_cgs_destroy_device(struct cgs_device *cgs_device);
667 * Core structure, functions and helpers.
669 typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t);
670 typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
672 typedef uint64_t (*amdgpu_rreg64_t)(struct amdgpu_device*, uint32_t);
673 typedef void (*amdgpu_wreg64_t)(struct amdgpu_device*, uint32_t, uint64_t);
675 typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
676 typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t);
678 struct amdgpu_mmio_remap {
680 resource_size_t bus_addr;
683 /* Define the HW IP blocks will be used in driver , add more if necessary */
684 enum amd_hw_ip_block_type {
702 JPEG_HWIP = VCN_HWIP,
717 #define HWIP_MAX_INSTANCE 8
719 struct amd_powerplay {
721 const struct amd_pm_funcs *pp_funcs;
724 #define AMDGPU_RESET_MAGIC_NUM 64
725 #define AMDGPU_MAX_DF_PERFMONS 4
726 struct amdgpu_device {
728 struct drm_device *ddev;
729 struct pci_dev *pdev;
731 #ifdef CONFIG_DRM_AMD_ACP
732 struct amdgpu_acp acp;
736 enum amd_asic_type asic_type;
739 uint32_t external_rev_id;
742 const struct amdgpu_asic_funcs *asic_funcs;
746 struct notifier_block acpi_nb;
747 struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS];
748 struct amdgpu_debugfs debugfs[AMDGPU_DEBUGFS_MAX_COMPONENTS];
749 unsigned debugfs_count;
750 #if defined(CONFIG_DEBUG_FS)
751 struct dentry *debugfs_preempt;
752 struct dentry *debugfs_regs[AMDGPU_DEBUGFS_MAX_COMPONENTS];
754 struct amdgpu_atif *atif;
755 struct amdgpu_atcs atcs;
756 struct mutex srbm_mutex;
757 /* GRBM index mutex. Protects concurrent access to GRBM index */
758 struct mutex grbm_idx_mutex;
759 struct dev_pm_domain vga_pm_domain;
760 bool have_disp_power_ref;
761 bool have_atomics_support;
767 struct amdgpu_bo *stolen_vga_memory;
768 struct amdgpu_bo *discovery_memory;
769 uint32_t bios_scratch_reg_offset;
770 uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH];
772 /* Register/doorbell mmio */
773 resource_size_t rmmio_base;
774 resource_size_t rmmio_size;
776 /* protects concurrent MM_INDEX/DATA based register access */
777 spinlock_t mmio_idx_lock;
778 struct amdgpu_mmio_remap rmmio_remap;
779 /* protects concurrent SMC based register access */
780 spinlock_t smc_idx_lock;
781 amdgpu_rreg_t smc_rreg;
782 amdgpu_wreg_t smc_wreg;
783 /* protects concurrent PCIE register access */
784 spinlock_t pcie_idx_lock;
785 amdgpu_rreg_t pcie_rreg;
786 amdgpu_wreg_t pcie_wreg;
787 amdgpu_rreg_t pciep_rreg;
788 amdgpu_wreg_t pciep_wreg;
789 amdgpu_rreg64_t pcie_rreg64;
790 amdgpu_wreg64_t pcie_wreg64;
791 /* protects concurrent UVD register access */
792 spinlock_t uvd_ctx_idx_lock;
793 amdgpu_rreg_t uvd_ctx_rreg;
794 amdgpu_wreg_t uvd_ctx_wreg;
795 /* protects concurrent DIDT register access */
796 spinlock_t didt_idx_lock;
797 amdgpu_rreg_t didt_rreg;
798 amdgpu_wreg_t didt_wreg;
799 /* protects concurrent gc_cac register access */
800 spinlock_t gc_cac_idx_lock;
801 amdgpu_rreg_t gc_cac_rreg;
802 amdgpu_wreg_t gc_cac_wreg;
803 /* protects concurrent se_cac register access */
804 spinlock_t se_cac_idx_lock;
805 amdgpu_rreg_t se_cac_rreg;
806 amdgpu_wreg_t se_cac_wreg;
807 /* protects concurrent ENDPOINT (audio) register access */
808 spinlock_t audio_endpt_idx_lock;
809 amdgpu_block_rreg_t audio_endpt_rreg;
810 amdgpu_block_wreg_t audio_endpt_wreg;
811 void __iomem *rio_mem;
812 resource_size_t rio_mem_size;
813 struct amdgpu_doorbell doorbell;
816 struct amdgpu_clock clock;
819 struct amdgpu_gmc gmc;
820 struct amdgpu_gart gart;
821 dma_addr_t dummy_page_addr;
822 struct amdgpu_vm_manager vm_manager;
823 struct amdgpu_vmhub vmhub[AMDGPU_MAX_VMHUBS];
826 /* memory management */
827 struct amdgpu_mman mman;
828 struct amdgpu_vram_scratch vram_scratch;
830 atomic64_t num_bytes_moved;
831 atomic64_t num_evictions;
832 atomic64_t num_vram_cpu_page_faults;
833 atomic_t gpu_reset_counter;
834 atomic_t vram_lost_counter;
836 /* data for buffer migration throttling */
840 s64 accum_us; /* accumulated microseconds */
841 s64 accum_us_vis; /* for visible VRAM */
846 bool enable_virtual_display;
847 struct amdgpu_mode_info mode_info;
848 /* For pre-DCE11. DCE11 and later are in "struct amdgpu_device->dm" */
849 struct work_struct hotplug_work;
850 struct amdgpu_irq_src crtc_irq;
851 struct amdgpu_irq_src vupdate_irq;
852 struct amdgpu_irq_src pageflip_irq;
853 struct amdgpu_irq_src hpd_irq;
858 struct amdgpu_ring *rings[AMDGPU_MAX_RINGS];
860 struct amdgpu_sa_manager ib_pools[AMDGPU_IB_POOL_MAX];
861 struct amdgpu_sched gpu_sched[AMDGPU_HW_IP_NUM][AMDGPU_RING_PRIO_MAX];
864 struct amdgpu_irq irq;
867 struct amd_powerplay powerplay;
868 bool pp_force_state_enabled;
871 struct smu_context smu;
879 struct amdgpu_nbio nbio;
882 struct amdgpu_mmhub mmhub;
885 struct amdgpu_gfx gfx;
888 struct amdgpu_sdma sdma;
891 struct amdgpu_uvd uvd;
894 struct amdgpu_vce vce;
897 struct amdgpu_vcn vcn;
900 struct amdgpu_jpeg jpeg;
903 struct amdgpu_firmware firmware;
906 struct psp_context psp;
909 struct amdgpu_gds gds;
912 struct amdgpu_kfd_dev kfd;
915 struct amdgpu_umc umc;
917 /* display related functionality */
918 struct amdgpu_display_manager dm;
925 struct amdgpu_mes mes;
930 struct amdgpu_ip_block ip_blocks[AMDGPU_MAX_IP_NUM];
932 struct mutex mn_lock;
933 DECLARE_HASHTABLE(mn_hash, 7);
935 /* tracking pinned memory */
936 atomic64_t vram_pin_size;
937 atomic64_t visible_pin_size;
938 atomic64_t gart_pin_size;
940 /* soc15 register offset based on ip, instance and segment */
941 uint32_t *reg_offset[MAX_HWIP][HWIP_MAX_INSTANCE];
943 /* delayed work_func for deferring clockgating during resume */
944 struct delayed_work delayed_init_work;
946 struct amdgpu_virt virt;
947 /* firmware VRAM reservation */
948 struct amdgpu_fw_vram_usage fw_vram_usage;
950 /* link all shadow bo */
951 struct list_head shadow_list;
952 struct mutex shadow_list_lock;
954 /* record hw reset is performed */
956 u8 reset_magic[AMDGPU_RESET_MAGIC_NUM];
962 enum pp_mp1_state mp1_state;
963 struct mutex lock_reset;
964 struct amdgpu_doorbell_index doorbell_index;
966 struct mutex notifier_lock;
969 struct work_struct xgmi_reset_work;
974 long compute_timeout;
977 uint64_t df_perfmon_config_assign_mask[AMDGPU_MAX_DF_PERFMONS];
979 /* enable runtime pm on the device */
986 /* Chip product information */
987 char product_number[16];
988 char product_name[32];
992 static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_bo_device *bdev)
994 return container_of(bdev, struct amdgpu_device, mman.bdev);
997 int amdgpu_device_init(struct amdgpu_device *adev,
998 struct drm_device *ddev,
999 struct pci_dev *pdev,
1001 void amdgpu_device_fini(struct amdgpu_device *adev);
1002 int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev);
1004 void amdgpu_device_vram_access(struct amdgpu_device *adev, loff_t pos,
1005 uint32_t *buf, size_t size, bool write);
1006 uint32_t amdgpu_device_rreg(struct amdgpu_device *adev, uint32_t reg,
1007 uint32_t acc_flags);
1008 void amdgpu_device_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v,
1009 uint32_t acc_flags);
1010 void amdgpu_mm_wreg_mmio_rlc(struct amdgpu_device *adev, uint32_t reg, uint32_t v,
1011 uint32_t acc_flags);
1012 void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value);
1013 uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset);
1015 u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg);
1016 void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v);
1018 bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type);
1019 bool amdgpu_device_has_dc_support(struct amdgpu_device *adev);
1021 int emu_soc_asic_init(struct amdgpu_device *adev);
1024 * Registers read & write functions.
1026 #define AMDGPU_REGS_NO_KIQ (1<<1)
1028 #define RREG32_NO_KIQ(reg) amdgpu_device_rreg(adev, (reg), AMDGPU_REGS_NO_KIQ)
1029 #define WREG32_NO_KIQ(reg, v) amdgpu_device_wreg(adev, (reg), (v), AMDGPU_REGS_NO_KIQ)
1031 #define RREG32_KIQ(reg) amdgpu_kiq_rreg(adev, (reg))
1032 #define WREG32_KIQ(reg, v) amdgpu_kiq_wreg(adev, (reg), (v))
1034 #define RREG8(reg) amdgpu_mm_rreg8(adev, (reg))
1035 #define WREG8(reg, v) amdgpu_mm_wreg8(adev, (reg), (v))
1037 #define RREG32(reg) amdgpu_device_rreg(adev, (reg), 0)
1038 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_device_rreg(adev, (reg), 0))
1039 #define WREG32(reg, v) amdgpu_device_wreg(adev, (reg), (v), 0)
1040 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1041 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1042 #define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg))
1043 #define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v))
1044 #define RREG32_PCIE_PORT(reg) adev->pciep_rreg(adev, (reg))
1045 #define WREG32_PCIE_PORT(reg, v) adev->pciep_wreg(adev, (reg), (v))
1046 #define RREG64_PCIE(reg) adev->pcie_rreg64(adev, (reg))
1047 #define WREG64_PCIE(reg, v) adev->pcie_wreg64(adev, (reg), (v))
1048 #define RREG32_SMC(reg) adev->smc_rreg(adev, (reg))
1049 #define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v))
1050 #define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg))
1051 #define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v))
1052 #define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg))
1053 #define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v))
1054 #define RREG32_GC_CAC(reg) adev->gc_cac_rreg(adev, (reg))
1055 #define WREG32_GC_CAC(reg, v) adev->gc_cac_wreg(adev, (reg), (v))
1056 #define RREG32_SE_CAC(reg) adev->se_cac_rreg(adev, (reg))
1057 #define WREG32_SE_CAC(reg, v) adev->se_cac_wreg(adev, (reg), (v))
1058 #define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg))
1059 #define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v))
1060 #define WREG32_P(reg, val, mask) \
1062 uint32_t tmp_ = RREG32(reg); \
1064 tmp_ |= ((val) & ~(mask)); \
1065 WREG32(reg, tmp_); \
1067 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
1068 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))
1069 #define WREG32_PLL_P(reg, val, mask) \
1071 uint32_t tmp_ = RREG32_PLL(reg); \
1073 tmp_ |= ((val) & ~(mask)); \
1074 WREG32_PLL(reg, tmp_); \
1076 #define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_device_rreg((adev), (reg), false))
1077 #define RREG32_IO(reg) amdgpu_io_rreg(adev, (reg))
1078 #define WREG32_IO(reg, v) amdgpu_io_wreg(adev, (reg), (v))
1080 #define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT
1081 #define REG_FIELD_MASK(reg, field) reg##__##field##_MASK
1083 #define REG_SET_FIELD(orig_val, reg, field, field_val) \
1084 (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \
1085 (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field))))
1087 #define REG_GET_FIELD(value, reg, field) \
1088 (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field))
1090 #define WREG32_FIELD(reg, field, val) \
1091 WREG32(mm##reg, (RREG32(mm##reg) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))
1093 #define WREG32_FIELD_OFFSET(reg, offset, field, val) \
1094 WREG32(mm##reg + offset, (RREG32(mm##reg + offset) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))
1099 #define RBIOS8(i) (adev->bios[i])
1100 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
1101 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
1106 #define amdgpu_asic_set_vga_state(adev, state) (adev)->asic_funcs->set_vga_state((adev), (state))
1107 #define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev))
1108 #define amdgpu_asic_reset_method(adev) (adev)->asic_funcs->reset_method((adev))
1109 #define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev))
1110 #define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d))
1111 #define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec))
1112 #define amdgpu_get_pcie_lanes(adev) (adev)->asic_funcs->get_pcie_lanes((adev))
1113 #define amdgpu_set_pcie_lanes(adev, l) (adev)->asic_funcs->set_pcie_lanes((adev), (l))
1114 #define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev))
1115 #define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev))
1116 #define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l))
1117 #define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v)))
1118 #define amdgpu_asic_get_config_memsize(adev) (adev)->asic_funcs->get_config_memsize((adev))
1119 #define amdgpu_asic_flush_hdp(adev, r) (adev)->asic_funcs->flush_hdp((adev), (r))
1120 #define amdgpu_asic_invalidate_hdp(adev, r) (adev)->asic_funcs->invalidate_hdp((adev), (r))
1121 #define amdgpu_asic_need_full_reset(adev) (adev)->asic_funcs->need_full_reset((adev))
1122 #define amdgpu_asic_init_doorbell_index(adev) (adev)->asic_funcs->init_doorbell_index((adev))
1123 #define amdgpu_asic_get_pcie_usage(adev, cnt0, cnt1) ((adev)->asic_funcs->get_pcie_usage((adev), (cnt0), (cnt1)))
1124 #define amdgpu_asic_need_reset_on_init(adev) (adev)->asic_funcs->need_reset_on_init((adev))
1125 #define amdgpu_asic_get_pcie_replay_count(adev) ((adev)->asic_funcs->get_pcie_replay_count((adev)))
1126 #define amdgpu_asic_supports_baco(adev) (adev)->asic_funcs->supports_baco((adev))
1128 #define amdgpu_inc_vram_lost(adev) atomic_inc(&((adev)->vram_lost_counter));
1130 /* Common functions */
1131 bool amdgpu_device_should_recover_gpu(struct amdgpu_device *adev);
1132 int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
1133 struct amdgpu_job* job);
1134 void amdgpu_device_pci_config_reset(struct amdgpu_device *adev);
1135 bool amdgpu_device_need_post(struct amdgpu_device *adev);
1137 void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes,
1139 int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev);
1140 void amdgpu_device_program_register_sequence(struct amdgpu_device *adev,
1141 const u32 *registers,
1142 const u32 array_size);
1144 bool amdgpu_device_supports_boco(struct drm_device *dev);
1145 bool amdgpu_device_supports_baco(struct drm_device *dev);
1146 bool amdgpu_device_is_peer_accessible(struct amdgpu_device *adev,
1147 struct amdgpu_device *peer_adev);
1148 int amdgpu_device_baco_enter(struct drm_device *dev);
1149 int amdgpu_device_baco_exit(struct drm_device *dev);
1152 #if defined(CONFIG_VGA_SWITCHEROO)
1153 void amdgpu_register_atpx_handler(void);
1154 void amdgpu_unregister_atpx_handler(void);
1155 bool amdgpu_has_atpx_dgpu_power_cntl(void);
1156 bool amdgpu_is_atpx_hybrid(void);
1157 bool amdgpu_atpx_dgpu_req_power_for_displays(void);
1158 bool amdgpu_has_atpx(void);
1160 static inline void amdgpu_register_atpx_handler(void) {}
1161 static inline void amdgpu_unregister_atpx_handler(void) {}
1162 static inline bool amdgpu_has_atpx_dgpu_power_cntl(void) { return false; }
1163 static inline bool amdgpu_is_atpx_hybrid(void) { return false; }
1164 static inline bool amdgpu_atpx_dgpu_req_power_for_displays(void) { return false; }
1165 static inline bool amdgpu_has_atpx(void) { return false; }
1168 #if defined(CONFIG_VGA_SWITCHEROO) && defined(CONFIG_ACPI)
1169 void *amdgpu_atpx_get_dhandle(void);
1171 static inline void *amdgpu_atpx_get_dhandle(void) { return NULL; }
1177 extern const struct drm_ioctl_desc amdgpu_ioctls_kms[];
1178 extern const int amdgpu_max_kms_ioctl;
1180 int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags);
1181 void amdgpu_driver_unload_kms(struct drm_device *dev);
1182 void amdgpu_driver_lastclose_kms(struct drm_device *dev);
1183 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv);
1184 void amdgpu_driver_postclose_kms(struct drm_device *dev,
1185 struct drm_file *file_priv);
1186 int amdgpu_device_ip_suspend(struct amdgpu_device *adev);
1187 int amdgpu_device_suspend(struct drm_device *dev, bool fbcon);
1188 int amdgpu_device_resume(struct drm_device *dev, bool fbcon);
1189 u32 amdgpu_get_vblank_counter_kms(struct drm_crtc *crtc);
1190 int amdgpu_enable_vblank_kms(struct drm_crtc *crtc);
1191 void amdgpu_disable_vblank_kms(struct drm_crtc *crtc);
1192 long amdgpu_kms_compat_ioctl(struct file *filp, unsigned int cmd,
1196 * functions used by amdgpu_encoder.c
1198 struct amdgpu_afmt_acr {
1212 struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock);
1215 #if defined(CONFIG_ACPI)
1216 int amdgpu_acpi_init(struct amdgpu_device *adev);
1217 void amdgpu_acpi_fini(struct amdgpu_device *adev);
1218 bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev);
1219 int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev,
1220 u8 perf_req, bool advertise);
1221 int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev);
1223 void amdgpu_acpi_get_backlight_caps(struct amdgpu_device *adev,
1224 struct amdgpu_dm_backlight_caps *caps);
1226 static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; }
1227 static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { }
1230 int amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser,
1231 uint64_t addr, struct amdgpu_bo **bo,
1232 struct amdgpu_bo_va_mapping **mapping);
1234 #if defined(CONFIG_DRM_AMD_DC)
1235 int amdgpu_dm_display_resume(struct amdgpu_device *adev );
1237 static inline int amdgpu_dm_display_resume(struct amdgpu_device *adev) { return 0; }
1241 void amdgpu_register_gpu_instance(struct amdgpu_device *adev);
1242 void amdgpu_unregister_gpu_instance(struct amdgpu_device *adev);
1244 #include "amdgpu_object.h"
1246 /* used by df_v3_6.c and amdgpu_pmu.c */
1247 #define AMDGPU_PMU_ATTR(_name, _object) \
1249 _name##_show(struct device *dev, \
1250 struct device_attribute *attr, \
1253 BUILD_BUG_ON(sizeof(_object) >= PAGE_SIZE - 1); \
1254 return sprintf(page, _object "\n"); \
1257 static struct device_attribute pmu_attr_##_name = __ATTR_RO(_name)
1259 static inline bool amdgpu_is_tmz(struct amdgpu_device *adev)
1261 return adev->gmc.tmz_enabled;