2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
35 #define pr_fmt(fmt) "amdgpu: " fmt
41 #define dev_fmt(fmt) "amdgpu: " fmt
43 #include "amdgpu_ctx.h"
45 #include <linux/atomic.h>
46 #include <linux/wait.h>
47 #include <linux/list.h>
48 #include <linux/kref.h>
49 #include <linux/rbtree.h>
50 #include <linux/hashtable.h>
51 #include <linux/dma-fence.h>
52 #include <linux/pci.h>
54 #include <drm/ttm/ttm_bo.h>
55 #include <drm/ttm/ttm_placement.h>
57 #include <drm/amdgpu_drm.h>
58 #include <drm/drm_gem.h>
59 #include <drm/drm_ioctl.h>
61 #include <kgd_kfd_interface.h>
62 #include "dm_pp_interface.h"
63 #include "kgd_pp_interface.h"
65 #include "amd_shared.h"
66 #include "amdgpu_mode.h"
67 #include "amdgpu_ih.h"
68 #include "amdgpu_irq.h"
69 #include "amdgpu_ucode.h"
70 #include "amdgpu_ttm.h"
71 #include "amdgpu_psp.h"
72 #include "amdgpu_gds.h"
73 #include "amdgpu_sync.h"
74 #include "amdgpu_ring.h"
75 #include "amdgpu_vm.h"
76 #include "amdgpu_dpm.h"
77 #include "amdgpu_acp.h"
78 #include "amdgpu_uvd.h"
79 #include "amdgpu_vce.h"
80 #include "amdgpu_vcn.h"
81 #include "amdgpu_jpeg.h"
82 #include "amdgpu_vpe.h"
83 #include "amdgpu_umsch_mm.h"
84 #include "amdgpu_gmc.h"
85 #include "amdgpu_gfx.h"
86 #include "amdgpu_sdma.h"
87 #include "amdgpu_lsdma.h"
88 #include "amdgpu_nbio.h"
89 #include "amdgpu_hdp.h"
90 #include "amdgpu_dm.h"
91 #include "amdgpu_virt.h"
92 #include "amdgpu_csa.h"
93 #include "amdgpu_mes_ctx.h"
94 #include "amdgpu_gart.h"
95 #include "amdgpu_debugfs.h"
96 #include "amdgpu_job.h"
97 #include "amdgpu_bo_list.h"
98 #include "amdgpu_gem.h"
99 #include "amdgpu_doorbell.h"
100 #include "amdgpu_amdkfd.h"
101 #include "amdgpu_discovery.h"
102 #include "amdgpu_mes.h"
103 #include "amdgpu_umc.h"
104 #include "amdgpu_mmhub.h"
105 #include "amdgpu_gfxhub.h"
106 #include "amdgpu_df.h"
107 #include "amdgpu_smuio.h"
108 #include "amdgpu_fdinfo.h"
109 #include "amdgpu_mca.h"
110 #include "amdgpu_aca.h"
111 #include "amdgpu_ras.h"
112 #include "amdgpu_xcp.h"
113 #include "amdgpu_seq64.h"
114 #include "amdgpu_reg_state.h"
116 #define MAX_GPU_INSTANCE 64
118 struct amdgpu_gpu_instance {
119 struct amdgpu_device *adev;
120 int mgpu_fan_enabled;
123 struct amdgpu_mgpu_info {
124 struct amdgpu_gpu_instance gpu_ins[MAX_GPU_INSTANCE];
130 /* delayed reset_func for XGMI configuration if necessary */
131 struct delayed_work delayed_reset_work;
142 struct amdgpu_watchdog_timer {
143 bool timeout_fatal_disable;
144 uint32_t period; /* maxCycles = (1 << period), the number of cycles before a timeout */
147 #define AMDGPU_MAX_TIMEOUT_PARAM_LENGTH 256
150 * Modules parameters.
152 extern int amdgpu_modeset;
153 extern unsigned int amdgpu_vram_limit;
154 extern int amdgpu_vis_vram_limit;
155 extern int amdgpu_gart_size;
156 extern int amdgpu_gtt_size;
157 extern int amdgpu_moverate;
158 extern int amdgpu_audio;
159 extern int amdgpu_disp_priority;
160 extern int amdgpu_hw_i2c;
161 extern int amdgpu_pcie_gen2;
162 extern int amdgpu_msi;
163 extern char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENGTH];
164 extern int amdgpu_dpm;
165 extern int amdgpu_fw_load_type;
166 extern int amdgpu_aspm;
167 extern int amdgpu_runtime_pm;
168 extern uint amdgpu_ip_block_mask;
169 extern int amdgpu_bapm;
170 extern int amdgpu_deep_color;
171 extern int amdgpu_vm_size;
172 extern int amdgpu_vm_block_size;
173 extern int amdgpu_vm_fragment_size;
174 extern int amdgpu_vm_fault_stop;
175 extern int amdgpu_vm_debug;
176 extern int amdgpu_vm_update_mode;
177 extern int amdgpu_exp_hw_support;
178 extern int amdgpu_dc;
179 extern int amdgpu_sched_jobs;
180 extern int amdgpu_sched_hw_submission;
181 extern uint amdgpu_pcie_gen_cap;
182 extern uint amdgpu_pcie_lane_cap;
183 extern u64 amdgpu_cg_mask;
184 extern uint amdgpu_pg_mask;
185 extern uint amdgpu_sdma_phase_quantum;
186 extern char *amdgpu_disable_cu;
187 extern char *amdgpu_virtual_display;
188 extern uint amdgpu_pp_feature_mask;
189 extern uint amdgpu_force_long_training;
190 extern int amdgpu_lbpw;
191 extern int amdgpu_compute_multipipe;
192 extern int amdgpu_gpu_recovery;
193 extern int amdgpu_emu_mode;
194 extern uint amdgpu_smu_memory_pool_size;
195 extern int amdgpu_smu_pptable_id;
196 extern uint amdgpu_dc_feature_mask;
197 extern uint amdgpu_dc_debug_mask;
198 extern uint amdgpu_dc_visual_confirm;
199 extern int amdgpu_dm_abm_level;
200 extern int amdgpu_backlight;
201 extern int amdgpu_damage_clips;
202 extern struct amdgpu_mgpu_info mgpu_info;
203 extern int amdgpu_ras_enable;
204 extern uint amdgpu_ras_mask;
205 extern int amdgpu_bad_page_threshold;
206 extern bool amdgpu_ignore_bad_page_threshold;
207 extern struct amdgpu_watchdog_timer amdgpu_watchdog_timer;
208 extern int amdgpu_async_gfx_ring;
209 extern int amdgpu_mcbp;
210 extern int amdgpu_discovery;
211 extern int amdgpu_mes;
212 extern int amdgpu_mes_kiq;
213 extern int amdgpu_noretry;
214 extern int amdgpu_force_asic_type;
215 extern int amdgpu_smartshift_bias;
216 extern int amdgpu_use_xgmi_p2p;
217 extern int amdgpu_mtype_local;
218 extern bool enforce_isolation;
219 #ifdef CONFIG_HSA_AMD
220 extern int sched_policy;
221 extern bool debug_evictions;
222 extern bool no_system_mem_limit;
223 extern int halt_if_hws_hang;
225 static const int __maybe_unused sched_policy = KFD_SCHED_POLICY_HWS;
226 static const bool __maybe_unused debug_evictions; /* = false */
227 static const bool __maybe_unused no_system_mem_limit;
228 static const int __maybe_unused halt_if_hws_hang;
230 #ifdef CONFIG_HSA_AMD_P2P
231 extern bool pcie_p2p;
234 extern int amdgpu_tmz;
235 extern int amdgpu_reset_method;
237 #ifdef CONFIG_DRM_AMDGPU_SI
238 extern int amdgpu_si_support;
240 #ifdef CONFIG_DRM_AMDGPU_CIK
241 extern int amdgpu_cik_support;
243 extern int amdgpu_num_kcq;
245 #define AMDGPU_VCNFW_LOG_SIZE (32 * 1024)
246 extern int amdgpu_vcnfw_log;
247 extern int amdgpu_sg_display;
248 extern int amdgpu_umsch_mm;
249 extern int amdgpu_seamless;
251 extern int amdgpu_user_partt_mode;
252 extern int amdgpu_agp;
254 extern int amdgpu_wbrf;
256 #define AMDGPU_VM_MAX_NUM_CTX 4096
257 #define AMDGPU_SG_THRESHOLD (256*1024*1024)
258 #define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000
259 #define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */
260 #define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2)
261 #define AMDGPU_DEBUGFS_MAX_COMPONENTS 32
262 #define AMDGPUFB_CONN_LIMIT 4
263 #define AMDGPU_BIOS_NUM_SCRATCH 16
265 #define AMDGPU_VBIOS_VGA_ALLOCATION (9 * 1024 * 1024) /* reserve 8MB for vga emulator and 1 MB for FB */
267 /* hard reset data */
268 #define AMDGPU_ASIC_RESET_DATA 0x39d5e86b
271 #define AMDGPU_RESET_GFX (1 << 0)
272 #define AMDGPU_RESET_COMPUTE (1 << 1)
273 #define AMDGPU_RESET_DMA (1 << 2)
274 #define AMDGPU_RESET_CP (1 << 3)
275 #define AMDGPU_RESET_GRBM (1 << 4)
276 #define AMDGPU_RESET_DMA1 (1 << 5)
277 #define AMDGPU_RESET_RLC (1 << 6)
278 #define AMDGPU_RESET_SEM (1 << 7)
279 #define AMDGPU_RESET_IH (1 << 8)
280 #define AMDGPU_RESET_VMC (1 << 9)
281 #define AMDGPU_RESET_MC (1 << 10)
282 #define AMDGPU_RESET_DISPLAY (1 << 11)
283 #define AMDGPU_RESET_UVD (1 << 12)
284 #define AMDGPU_RESET_VCE (1 << 13)
285 #define AMDGPU_RESET_VCE1 (1 << 14)
287 /* max cursor sizes (in pixels) */
288 #define CIK_CURSOR_WIDTH 128
289 #define CIK_CURSOR_HEIGHT 128
291 /* smart shift bias level limits */
292 #define AMDGPU_SMARTSHIFT_MAX_BIAS (100)
293 #define AMDGPU_SMARTSHIFT_MIN_BIAS (-100)
295 /* Extra time delay(in ms) to eliminate the influence of temperature momentary fluctuation */
296 #define AMDGPU_SWCTF_EXTRA_DELAY 50
298 struct amdgpu_xcp_mgr;
299 struct amdgpu_device;
300 struct amdgpu_irq_src;
302 struct amdgpu_bo_va_mapping;
303 struct kfd_vm_fault_info;
304 struct amdgpu_hive_info;
305 struct amdgpu_reset_context;
306 struct amdgpu_reset_control;
309 AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP = 0,
310 AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP,
311 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP,
312 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP,
313 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP,
314 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP,
315 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP,
316 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP,
317 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP,
318 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP,
323 enum amdgpu_thermal_irq {
324 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0,
325 AMDGPU_THERMAL_IRQ_HIGH_TO_LOW,
327 AMDGPU_THERMAL_IRQ_LAST
330 enum amdgpu_kiq_irq {
331 AMDGPU_CP_KIQ_IRQ_DRIVER0 = 0,
332 AMDGPU_CP_KIQ_IRQ_LAST
334 #define SRIOV_USEC_TIMEOUT 1200000 /* wait 12 * 100ms for SRIOV */
335 #define MAX_KIQ_REG_WAIT 5000 /* in usecs, 5ms */
336 #define MAX_KIQ_REG_BAILOUT_INTERVAL 5 /* in msecs, 5ms */
337 #define MAX_KIQ_REG_TRY 1000
339 int amdgpu_device_ip_set_clockgating_state(void *dev,
340 enum amd_ip_block_type block_type,
341 enum amd_clockgating_state state);
342 int amdgpu_device_ip_set_powergating_state(void *dev,
343 enum amd_ip_block_type block_type,
344 enum amd_powergating_state state);
345 void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev,
347 int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev,
348 enum amd_ip_block_type block_type);
349 bool amdgpu_device_ip_is_idle(struct amdgpu_device *adev,
350 enum amd_ip_block_type block_type);
352 #define AMDGPU_MAX_IP_NUM 16
354 struct amdgpu_ip_block_status {
358 bool late_initialized;
362 struct amdgpu_ip_block_version {
363 const enum amd_ip_block_type type;
367 const struct amd_ip_funcs *funcs;
370 struct amdgpu_ip_block {
371 struct amdgpu_ip_block_status status;
372 const struct amdgpu_ip_block_version *version;
375 int amdgpu_device_ip_block_version_cmp(struct amdgpu_device *adev,
376 enum amd_ip_block_type type,
377 u32 major, u32 minor);
379 struct amdgpu_ip_block *
380 amdgpu_device_ip_get_ip_block(struct amdgpu_device *adev,
381 enum amd_ip_block_type type);
383 int amdgpu_device_ip_block_add(struct amdgpu_device *adev,
384 const struct amdgpu_ip_block_version *ip_block_version);
389 bool amdgpu_get_bios(struct amdgpu_device *adev);
390 bool amdgpu_read_bios(struct amdgpu_device *adev);
391 bool amdgpu_soc15_read_bios_from_rom(struct amdgpu_device *adev,
392 u8 *bios, u32 length_bytes);
397 #define AMDGPU_MAX_PPLL 3
399 struct amdgpu_clock {
400 struct amdgpu_pll ppll[AMDGPU_MAX_PPLL];
401 struct amdgpu_pll spll;
402 struct amdgpu_pll mpll;
404 uint32_t default_mclk;
405 uint32_t default_sclk;
406 uint32_t default_dispclk;
407 uint32_t current_dispclk;
409 uint32_t max_pixel_clock;
412 /* sub-allocation manager, it has to be protected by another lock.
413 * By conception this is an helper for other part of the driver
414 * like the indirect buffer or semaphore, which both have their
417 * Principe is simple, we keep a list of sub allocation in offset
418 * order (first entry has offset == 0, last entry has the highest
421 * When allocating new object we first check if there is room at
422 * the end total_size - (last_object_offset + last_object_size) >=
423 * alloc_size. If so we allocate new object there.
425 * When there is not enough room at the end, we start waiting for
426 * each sub object until we reach object_offset+object_size >=
427 * alloc_size, this object then become the sub object we return.
429 * Alignment can't be bigger than page size.
431 * Hole are not considered for allocation to keep things simple.
432 * Assumption is that there won't be hole (all object on same
436 struct amdgpu_sa_manager {
437 struct drm_suballoc_manager base;
438 struct amdgpu_bo *bo;
443 int amdgpu_fence_slab_init(void);
444 void amdgpu_fence_slab_fini(void);
450 struct amdgpu_flip_work {
451 struct delayed_work flip_work;
452 struct work_struct unpin_work;
453 struct amdgpu_device *adev;
457 struct drm_pending_vblank_event *event;
458 struct amdgpu_bo *old_abo;
459 unsigned shared_count;
460 struct dma_fence **shared;
461 struct dma_fence_cb cb;
467 * file private structure
470 struct amdgpu_fpriv {
472 struct amdgpu_bo_va *prt_va;
473 struct amdgpu_bo_va *csa_va;
474 struct amdgpu_bo_va *seq64_va;
475 struct mutex bo_list_lock;
476 struct idr bo_list_handles;
477 struct amdgpu_ctx_mgr ctx_mgr;
478 /** GPU partition selection */
482 int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv);
487 #define AMDGPU_MAX_WB 1024 /* Reserve at most 1024 WB slots for amdgpu-owned rings. */
490 struct amdgpu_bo *wb_obj;
491 volatile uint32_t *wb;
493 u32 num_wb; /* Number of wb slots actually reserved for amdgpu. */
494 unsigned long used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)];
497 int amdgpu_device_wb_get(struct amdgpu_device *adev, u32 *wb);
498 void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb);
503 int amdgpu_benchmark(struct amdgpu_device *adev, int test_number);
506 * ASIC specific register table accessible by UMD
508 struct amdgpu_allowed_register_entry {
514 * enum amd_reset_method - Methods for resetting AMD GPU devices
516 * @AMD_RESET_METHOD_NONE: The device will not be reset.
517 * @AMD_RESET_LEGACY: Method reserved for SI, CIK and VI ASICs.
518 * @AMD_RESET_MODE0: Reset the entire ASIC. Not currently available for the
520 * @AMD_RESET_MODE1: Resets all IP blocks on the ASIC (SDMA, GFX, VCN, etc.)
521 * individually. Suitable only for some discrete GPU, not
522 * available for all ASICs.
523 * @AMD_RESET_MODE2: Resets a lesser level of IPs compared to MODE1. Which IPs
524 * are reset depends on the ASIC. Notably doesn't reset IPs
525 * shared with the CPU on APUs or the memory controllers (so
526 * VRAM is not lost). Not available on all ASICs.
527 * @AMD_RESET_BACO: BACO (Bus Alive, Chip Off) method powers off and on the card
528 * but without powering off the PCI bus. Suitable only for
530 * @AMD_RESET_PCI: Does a full bus reset using core Linux subsystem PCI reset
531 * and does a secondary bus reset or FLR, depending on what the
532 * underlying hardware supports.
534 * Methods available for AMD GPU driver for resetting the device. Not all
535 * methods are suitable for every device. User can override the method using
536 * module parameter `reset_method`.
538 enum amd_reset_method {
539 AMD_RESET_METHOD_NONE = -1,
540 AMD_RESET_METHOD_LEGACY = 0,
541 AMD_RESET_METHOD_MODE0,
542 AMD_RESET_METHOD_MODE1,
543 AMD_RESET_METHOD_MODE2,
544 AMD_RESET_METHOD_BACO,
545 AMD_RESET_METHOD_PCI,
548 struct amdgpu_video_codec_info {
552 u32 max_pixels_per_frame;
556 #define codec_info_build(type, width, height, level) \
559 .max_height = height,\
560 .max_pixels_per_frame = height * width,\
563 struct amdgpu_video_codecs {
564 const u32 codec_count;
565 const struct amdgpu_video_codec_info *codec_array;
569 * ASIC specific functions.
571 struct amdgpu_asic_funcs {
572 bool (*read_disabled_bios)(struct amdgpu_device *adev);
573 bool (*read_bios_from_rom)(struct amdgpu_device *adev,
574 u8 *bios, u32 length_bytes);
575 int (*read_register)(struct amdgpu_device *adev, u32 se_num,
576 u32 sh_num, u32 reg_offset, u32 *value);
577 void (*set_vga_state)(struct amdgpu_device *adev, bool state);
578 int (*reset)(struct amdgpu_device *adev);
579 enum amd_reset_method (*reset_method)(struct amdgpu_device *adev);
580 /* get the reference clock */
581 u32 (*get_xclk)(struct amdgpu_device *adev);
582 /* MM block clocks */
583 int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk);
584 int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk);
585 /* static power management */
586 int (*get_pcie_lanes)(struct amdgpu_device *adev);
587 void (*set_pcie_lanes)(struct amdgpu_device *adev, int lanes);
588 /* get config memsize register */
589 u32 (*get_config_memsize)(struct amdgpu_device *adev);
590 /* flush hdp write queue */
591 void (*flush_hdp)(struct amdgpu_device *adev, struct amdgpu_ring *ring);
592 /* invalidate hdp read cache */
593 void (*invalidate_hdp)(struct amdgpu_device *adev,
594 struct amdgpu_ring *ring);
595 /* check if the asic needs a full reset of if soft reset will work */
596 bool (*need_full_reset)(struct amdgpu_device *adev);
597 /* initialize doorbell layout for specific asic*/
598 void (*init_doorbell_index)(struct amdgpu_device *adev);
599 /* PCIe bandwidth usage */
600 void (*get_pcie_usage)(struct amdgpu_device *adev, uint64_t *count0,
602 /* do we need to reset the asic at init time (e.g., kexec) */
603 bool (*need_reset_on_init)(struct amdgpu_device *adev);
604 /* PCIe replay counter */
605 uint64_t (*get_pcie_replay_count)(struct amdgpu_device *adev);
606 /* device supports BACO */
607 bool (*supports_baco)(struct amdgpu_device *adev);
608 /* pre asic_init quirks */
609 void (*pre_asic_init)(struct amdgpu_device *adev);
610 /* enter/exit umd stable pstate */
611 int (*update_umd_stable_pstate)(struct amdgpu_device *adev, bool enter);
612 /* query video codecs */
613 int (*query_video_codecs)(struct amdgpu_device *adev, bool encode,
614 const struct amdgpu_video_codecs **codecs);
615 /* encode "> 32bits" smn addressing */
616 u64 (*encode_ext_smn_addressing)(int ext_id);
618 ssize_t (*get_reg_state)(struct amdgpu_device *adev,
619 enum amdgpu_reg_state reg_state, void *buf,
626 int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data,
627 struct drm_file *filp);
629 int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
630 int amdgpu_cs_fence_to_handle_ioctl(struct drm_device *dev, void *data,
631 struct drm_file *filp);
632 int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
633 int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data,
634 struct drm_file *filp);
636 /* VRAM scratch page for HDP bug, default vram page */
637 struct amdgpu_mem_scratch {
638 struct amdgpu_bo *robj;
639 volatile uint32_t *ptr;
646 struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev);
647 void amdgpu_cgs_destroy_device(struct cgs_device *cgs_device);
650 * Core structure, functions and helpers.
652 typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t);
653 typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
655 typedef uint32_t (*amdgpu_rreg_ext_t)(struct amdgpu_device*, uint64_t);
656 typedef void (*amdgpu_wreg_ext_t)(struct amdgpu_device*, uint64_t, uint32_t);
658 typedef uint64_t (*amdgpu_rreg64_t)(struct amdgpu_device*, uint32_t);
659 typedef void (*amdgpu_wreg64_t)(struct amdgpu_device*, uint32_t, uint64_t);
661 typedef uint64_t (*amdgpu_rreg64_ext_t)(struct amdgpu_device*, uint64_t);
662 typedef void (*amdgpu_wreg64_ext_t)(struct amdgpu_device*, uint64_t, uint64_t);
664 typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
665 typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t);
667 struct amdgpu_mmio_remap {
669 resource_size_t bus_addr;
672 /* Define the HW IP blocks will be used in driver , add more if necessary */
673 enum amd_hw_ip_block_type {
692 JPEG_HWIP = VCN_HWIP,
712 #define HWIP_MAX_INSTANCE 44
714 #define HW_ID_MAX 300
715 #define IP_VERSION_FULL(mj, mn, rv, var, srev) \
716 (((mj) << 24) | ((mn) << 16) | ((rv) << 8) | ((var) << 4) | (srev))
717 #define IP_VERSION(mj, mn, rv) IP_VERSION_FULL(mj, mn, rv, 0, 0)
718 #define IP_VERSION_MAJ(ver) ((ver) >> 24)
719 #define IP_VERSION_MIN(ver) (((ver) >> 16) & 0xFF)
720 #define IP_VERSION_REV(ver) (((ver) >> 8) & 0xFF)
721 #define IP_VERSION_VARIANT(ver) (((ver) >> 4) & 0xF)
722 #define IP_VERSION_SUBREV(ver) ((ver) & 0xF)
723 #define IP_VERSION_MAJ_MIN_REV(ver) ((ver) >> 8)
725 struct amdgpu_ip_map_info {
726 /* Map of logical to actual dev instances/mask */
727 uint32_t dev_inst[MAX_HWIP][HWIP_MAX_INSTANCE];
728 int8_t (*logical_to_dev_inst)(struct amdgpu_device *adev,
729 enum amd_hw_ip_block_type block,
731 uint32_t (*logical_to_dev_mask)(struct amdgpu_device *adev,
732 enum amd_hw_ip_block_type block,
736 struct amd_powerplay {
738 const struct amd_pm_funcs *pp_funcs;
741 struct ip_discovery_top;
743 /* polaris10 kickers */
744 #define ASICID_IS_P20(did, rid) (((did == 0x67DF) && \
750 ((did == 0x6FDF) && \
755 #define ASICID_IS_P30(did, rid) ((did == 0x67DF) && \
759 /* polaris11 kickers */
760 #define ASICID_IS_P21(did, rid) (((did == 0x67EF) && \
763 ((did == 0x67FF) && \
768 #define ASICID_IS_P31(did, rid) ((did == 0x67EF) && \
771 /* polaris12 kickers */
772 #define ASICID_IS_P23(did, rid) (((did == 0x6987) && \
777 ((did == 0x6981) && \
782 struct amdgpu_mqd_prop {
783 uint64_t mqd_gpu_addr;
784 uint64_t hqd_base_gpu_addr;
785 uint64_t rptr_gpu_addr;
786 uint64_t wptr_gpu_addr;
789 uint32_t doorbell_index;
790 uint64_t eop_gpu_addr;
791 uint32_t hqd_pipe_priority;
792 uint32_t hqd_queue_priority;
793 bool allow_tunneling;
799 int (*init_mqd)(struct amdgpu_device *adev, void *mqd,
800 struct amdgpu_mqd_prop *p);
803 #define AMDGPU_RESET_MAGIC_NUM 64
804 #define AMDGPU_MAX_DF_PERFMONS 4
805 struct amdgpu_reset_domain;
806 struct amdgpu_fru_info;
808 struct amdgpu_reset_info {
809 /* reset dump register */
810 u32 *reset_dump_reg_list;
811 u32 *reset_dump_reg_value;
814 #ifdef CONFIG_DEV_COREDUMP
815 struct amdgpu_coredump_info *coredump_info;
820 * Non-zero (true) if the GPU has VRAM. Zero (false) otherwise.
822 #define AMDGPU_HAS_VRAM(_adev) ((_adev)->gmc.real_vram_size)
824 struct amdgpu_device {
826 struct pci_dev *pdev;
827 struct drm_device ddev;
829 #ifdef CONFIG_DRM_AMD_ACP
830 struct amdgpu_acp acp;
832 struct amdgpu_hive_info *hive;
833 struct amdgpu_xcp_mgr *xcp_mgr;
835 enum amd_asic_type asic_type;
838 uint32_t external_rev_id;
840 unsigned long apu_flags;
842 const struct amdgpu_asic_funcs *asic_funcs;
846 struct notifier_block acpi_nb;
847 struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS];
848 struct debugfs_blob_wrapper debugfs_vbios_blob;
849 struct debugfs_blob_wrapper debugfs_discovery_blob;
850 struct mutex srbm_mutex;
851 /* GRBM index mutex. Protects concurrent access to GRBM index */
852 struct mutex grbm_idx_mutex;
853 struct dev_pm_domain vga_pm_domain;
854 bool have_disp_power_ref;
855 bool have_atomics_support;
861 uint32_t bios_scratch_reg_offset;
862 uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH];
864 /* Register/doorbell mmio */
865 resource_size_t rmmio_base;
866 resource_size_t rmmio_size;
868 /* protects concurrent MM_INDEX/DATA based register access */
869 spinlock_t mmio_idx_lock;
870 struct amdgpu_mmio_remap rmmio_remap;
871 /* protects concurrent SMC based register access */
872 spinlock_t smc_idx_lock;
873 amdgpu_rreg_t smc_rreg;
874 amdgpu_wreg_t smc_wreg;
875 /* protects concurrent PCIE register access */
876 spinlock_t pcie_idx_lock;
877 amdgpu_rreg_t pcie_rreg;
878 amdgpu_wreg_t pcie_wreg;
879 amdgpu_rreg_t pciep_rreg;
880 amdgpu_wreg_t pciep_wreg;
881 amdgpu_rreg_ext_t pcie_rreg_ext;
882 amdgpu_wreg_ext_t pcie_wreg_ext;
883 amdgpu_rreg64_t pcie_rreg64;
884 amdgpu_wreg64_t pcie_wreg64;
885 amdgpu_rreg64_ext_t pcie_rreg64_ext;
886 amdgpu_wreg64_ext_t pcie_wreg64_ext;
887 /* protects concurrent UVD register access */
888 spinlock_t uvd_ctx_idx_lock;
889 amdgpu_rreg_t uvd_ctx_rreg;
890 amdgpu_wreg_t uvd_ctx_wreg;
891 /* protects concurrent DIDT register access */
892 spinlock_t didt_idx_lock;
893 amdgpu_rreg_t didt_rreg;
894 amdgpu_wreg_t didt_wreg;
895 /* protects concurrent gc_cac register access */
896 spinlock_t gc_cac_idx_lock;
897 amdgpu_rreg_t gc_cac_rreg;
898 amdgpu_wreg_t gc_cac_wreg;
899 /* protects concurrent se_cac register access */
900 spinlock_t se_cac_idx_lock;
901 amdgpu_rreg_t se_cac_rreg;
902 amdgpu_wreg_t se_cac_wreg;
903 /* protects concurrent ENDPOINT (audio) register access */
904 spinlock_t audio_endpt_idx_lock;
905 amdgpu_block_rreg_t audio_endpt_rreg;
906 amdgpu_block_wreg_t audio_endpt_wreg;
907 struct amdgpu_doorbell doorbell;
910 struct amdgpu_clock clock;
913 struct amdgpu_gmc gmc;
914 struct amdgpu_gart gart;
915 dma_addr_t dummy_page_addr;
916 struct amdgpu_vm_manager vm_manager;
917 struct amdgpu_vmhub vmhub[AMDGPU_MAX_VMHUBS];
918 DECLARE_BITMAP(vmhubs_mask, AMDGPU_MAX_VMHUBS);
920 /* memory management */
921 struct amdgpu_mman mman;
922 struct amdgpu_mem_scratch mem_scratch;
924 atomic64_t num_bytes_moved;
925 atomic64_t num_evictions;
926 atomic64_t num_vram_cpu_page_faults;
927 atomic_t gpu_reset_counter;
928 atomic_t vram_lost_counter;
930 /* data for buffer migration throttling */
934 s64 accum_us; /* accumulated microseconds */
935 s64 accum_us_vis; /* for visible VRAM */
940 bool enable_virtual_display;
941 struct amdgpu_vkms_output *amdgpu_vkms_output;
942 struct amdgpu_mode_info mode_info;
943 /* For pre-DCE11. DCE11 and later are in "struct amdgpu_device->dm" */
944 struct delayed_work hotplug_work;
945 struct amdgpu_irq_src crtc_irq;
946 struct amdgpu_irq_src vline0_irq;
947 struct amdgpu_irq_src vupdate_irq;
948 struct amdgpu_irq_src pageflip_irq;
949 struct amdgpu_irq_src hpd_irq;
950 struct amdgpu_irq_src dmub_trace_irq;
951 struct amdgpu_irq_src dmub_outbox_irq;
956 struct amdgpu_ring *rings[AMDGPU_MAX_RINGS];
957 struct dma_fence __rcu *gang_submit;
959 struct amdgpu_sa_manager ib_pools[AMDGPU_IB_POOL_MAX];
960 struct amdgpu_sched gpu_sched[AMDGPU_HW_IP_NUM][AMDGPU_RING_PRIO_MAX];
963 struct amdgpu_irq irq;
966 struct amd_powerplay powerplay;
972 struct amdgpu_nbio nbio;
975 struct amdgpu_hdp hdp;
978 struct amdgpu_smuio smuio;
981 struct amdgpu_mmhub mmhub;
984 struct amdgpu_gfxhub gfxhub;
987 struct amdgpu_gfx gfx;
990 struct amdgpu_sdma sdma;
993 struct amdgpu_lsdma lsdma;
996 struct amdgpu_uvd uvd;
999 struct amdgpu_vce vce;
1002 struct amdgpu_vcn vcn;
1005 struct amdgpu_jpeg jpeg;
1008 struct amdgpu_vpe vpe;
1011 struct amdgpu_umsch_mm umsch_mm;
1012 bool enable_umsch_mm;
1015 struct amdgpu_firmware firmware;
1018 struct psp_context psp;
1021 struct amdgpu_gds gds;
1023 /* for userq and VM fences */
1024 struct amdgpu_seq64 seq64;
1027 struct amdgpu_kfd_dev kfd;
1030 struct amdgpu_umc umc;
1032 /* display related functionality */
1033 struct amdgpu_display_manager dm;
1037 bool enable_mes_kiq;
1038 struct amdgpu_mes mes;
1039 struct amdgpu_mqd mqds[AMDGPU_HW_IP_NUM];
1042 struct amdgpu_df df;
1045 struct amdgpu_mca mca;
1048 struct amdgpu_aca aca;
1050 struct amdgpu_ip_block ip_blocks[AMDGPU_MAX_IP_NUM];
1051 uint32_t harvest_ip_mask;
1053 struct mutex mn_lock;
1054 DECLARE_HASHTABLE(mn_hash, 7);
1056 /* tracking pinned memory */
1057 atomic64_t vram_pin_size;
1058 atomic64_t visible_pin_size;
1059 atomic64_t gart_pin_size;
1061 /* soc15 register offset based on ip, instance and segment */
1062 uint32_t *reg_offset[MAX_HWIP][HWIP_MAX_INSTANCE];
1063 struct amdgpu_ip_map_info ip_map;
1065 /* delayed work_func for deferring clockgating during resume */
1066 struct delayed_work delayed_init_work;
1068 struct amdgpu_virt virt;
1070 /* link all shadow bo */
1071 struct list_head shadow_list;
1072 struct mutex shadow_list_lock;
1074 /* record hw reset is performed */
1076 u8 reset_magic[AMDGPU_RESET_MAGIC_NUM];
1083 /* indicate amdgpu suspension status */
1084 bool suspend_complete;
1086 enum pp_mp1_state mp1_state;
1087 struct amdgpu_doorbell_index doorbell_index;
1089 struct mutex notifier_lock;
1092 struct work_struct xgmi_reset_work;
1093 struct list_head reset_list;
1098 long compute_timeout;
1102 uint64_t df_perfmon_config_assign_mask[AMDGPU_MAX_DF_PERFMONS];
1104 /* enable runtime pm on the device */
1108 bool ucode_sysfs_en;
1110 struct amdgpu_fru_info *fru_info;
1111 atomic_t throttling_logging_enabled;
1112 struct ratelimit_state throttling_logging_rs;
1113 uint32_t ras_hw_enabled;
1114 uint32_t ras_enabled;
1117 struct pci_saved_state *pci_state;
1118 pci_channel_state_t pci_channel_state;
1120 /* Track auto wait count on s_barrier settings */
1121 bool barrier_has_auto_waitcnt;
1123 struct amdgpu_reset_control *reset_cntl;
1124 uint32_t ip_versions[MAX_HWIP][HWIP_MAX_INSTANCE];
1126 bool ram_is_direct_mapped;
1128 struct list_head ras_list;
1130 struct ip_discovery_top *ip_top;
1132 struct amdgpu_reset_domain *reset_domain;
1134 struct mutex benchmark_mutex;
1136 struct amdgpu_reset_info reset_info;
1139 uint32_t scpm_status;
1141 struct work_struct reset_work;
1145 /* Mask of active clusters */
1150 bool debug_largebar;
1151 bool debug_disable_soft_recovery;
1152 bool debug_use_vram_fw_buf;
1155 static inline uint32_t amdgpu_ip_version(const struct amdgpu_device *adev,
1156 uint8_t ip, uint8_t inst)
1158 /* This considers only major/minor/rev and ignores
1159 * subrevision/variant fields.
1161 return adev->ip_versions[ip][inst] & ~0xFFU;
1164 static inline uint32_t amdgpu_ip_version_full(const struct amdgpu_device *adev,
1165 uint8_t ip, uint8_t inst)
1167 /* This returns full version - major/minor/rev/variant/subrevision */
1168 return adev->ip_versions[ip][inst];
1171 static inline struct amdgpu_device *drm_to_adev(struct drm_device *ddev)
1173 return container_of(ddev, struct amdgpu_device, ddev);
1176 static inline struct drm_device *adev_to_drm(struct amdgpu_device *adev)
1181 static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_device *bdev)
1183 return container_of(bdev, struct amdgpu_device, mman.bdev);
1186 int amdgpu_device_init(struct amdgpu_device *adev,
1188 void amdgpu_device_fini_hw(struct amdgpu_device *adev);
1189 void amdgpu_device_fini_sw(struct amdgpu_device *adev);
1191 int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev);
1193 void amdgpu_device_mm_access(struct amdgpu_device *adev, loff_t pos,
1194 void *buf, size_t size, bool write);
1195 size_t amdgpu_device_aper_access(struct amdgpu_device *adev, loff_t pos,
1196 void *buf, size_t size, bool write);
1198 void amdgpu_device_vram_access(struct amdgpu_device *adev, loff_t pos,
1199 void *buf, size_t size, bool write);
1200 uint32_t amdgpu_device_wait_on_rreg(struct amdgpu_device *adev,
1201 uint32_t inst, uint32_t reg_addr, char reg_name[],
1202 uint32_t expected_value, uint32_t mask);
1203 uint32_t amdgpu_device_rreg(struct amdgpu_device *adev,
1204 uint32_t reg, uint32_t acc_flags);
1205 u32 amdgpu_device_indirect_rreg_ext(struct amdgpu_device *adev,
1207 uint32_t amdgpu_device_xcc_rreg(struct amdgpu_device *adev,
1208 uint32_t reg, uint32_t acc_flags,
1210 void amdgpu_device_wreg(struct amdgpu_device *adev,
1211 uint32_t reg, uint32_t v,
1212 uint32_t acc_flags);
1213 void amdgpu_device_indirect_wreg_ext(struct amdgpu_device *adev,
1214 u64 reg_addr, u32 reg_data);
1215 void amdgpu_device_xcc_wreg(struct amdgpu_device *adev,
1216 uint32_t reg, uint32_t v,
1219 void amdgpu_mm_wreg_mmio_rlc(struct amdgpu_device *adev,
1220 uint32_t reg, uint32_t v, uint32_t xcc_id);
1221 void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value);
1222 uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset);
1224 u32 amdgpu_device_indirect_rreg(struct amdgpu_device *adev,
1226 u64 amdgpu_device_indirect_rreg64(struct amdgpu_device *adev,
1228 u64 amdgpu_device_indirect_rreg64_ext(struct amdgpu_device *adev,
1230 void amdgpu_device_indirect_wreg(struct amdgpu_device *adev,
1231 u32 reg_addr, u32 reg_data);
1232 void amdgpu_device_indirect_wreg64(struct amdgpu_device *adev,
1233 u32 reg_addr, u64 reg_data);
1234 void amdgpu_device_indirect_wreg64_ext(struct amdgpu_device *adev,
1235 u64 reg_addr, u64 reg_data);
1236 u32 amdgpu_device_get_rev_id(struct amdgpu_device *adev);
1237 bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type);
1238 bool amdgpu_device_has_dc_support(struct amdgpu_device *adev);
1240 void amdgpu_device_set_sriov_virtual_display(struct amdgpu_device *adev);
1242 int amdgpu_device_pre_asic_reset(struct amdgpu_device *adev,
1243 struct amdgpu_reset_context *reset_context);
1245 int amdgpu_do_asic_reset(struct list_head *device_list_handle,
1246 struct amdgpu_reset_context *reset_context);
1248 int emu_soc_asic_init(struct amdgpu_device *adev);
1251 * Registers read & write functions.
1253 #define AMDGPU_REGS_NO_KIQ (1<<1)
1254 #define AMDGPU_REGS_RLC (1<<2)
1256 #define RREG32_NO_KIQ(reg) amdgpu_device_rreg(adev, (reg), AMDGPU_REGS_NO_KIQ)
1257 #define WREG32_NO_KIQ(reg, v) amdgpu_device_wreg(adev, (reg), (v), AMDGPU_REGS_NO_KIQ)
1259 #define RREG32_KIQ(reg) amdgpu_kiq_rreg(adev, (reg), 0)
1260 #define WREG32_KIQ(reg, v) amdgpu_kiq_wreg(adev, (reg), (v), 0)
1262 #define RREG8(reg) amdgpu_mm_rreg8(adev, (reg))
1263 #define WREG8(reg, v) amdgpu_mm_wreg8(adev, (reg), (v))
1265 #define RREG32(reg) amdgpu_device_rreg(adev, (reg), 0)
1266 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_device_rreg(adev, (reg), 0))
1267 #define WREG32(reg, v) amdgpu_device_wreg(adev, (reg), (v), 0)
1268 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1269 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1270 #define RREG32_XCC(reg, inst) amdgpu_device_xcc_rreg(adev, (reg), 0, inst)
1271 #define WREG32_XCC(reg, v, inst) amdgpu_device_xcc_wreg(adev, (reg), (v), 0, inst)
1272 #define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg))
1273 #define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v))
1274 #define RREG32_PCIE_PORT(reg) adev->pciep_rreg(adev, (reg))
1275 #define WREG32_PCIE_PORT(reg, v) adev->pciep_wreg(adev, (reg), (v))
1276 #define RREG32_PCIE_EXT(reg) adev->pcie_rreg_ext(adev, (reg))
1277 #define WREG32_PCIE_EXT(reg, v) adev->pcie_wreg_ext(adev, (reg), (v))
1278 #define RREG64_PCIE(reg) adev->pcie_rreg64(adev, (reg))
1279 #define WREG64_PCIE(reg, v) adev->pcie_wreg64(adev, (reg), (v))
1280 #define RREG64_PCIE_EXT(reg) adev->pcie_rreg64_ext(adev, (reg))
1281 #define WREG64_PCIE_EXT(reg, v) adev->pcie_wreg64_ext(adev, (reg), (v))
1282 #define RREG32_SMC(reg) adev->smc_rreg(adev, (reg))
1283 #define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v))
1284 #define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg))
1285 #define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v))
1286 #define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg))
1287 #define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v))
1288 #define RREG32_GC_CAC(reg) adev->gc_cac_rreg(adev, (reg))
1289 #define WREG32_GC_CAC(reg, v) adev->gc_cac_wreg(adev, (reg), (v))
1290 #define RREG32_SE_CAC(reg) adev->se_cac_rreg(adev, (reg))
1291 #define WREG32_SE_CAC(reg, v) adev->se_cac_wreg(adev, (reg), (v))
1292 #define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg))
1293 #define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v))
1294 #define WREG32_P(reg, val, mask) \
1296 uint32_t tmp_ = RREG32(reg); \
1298 tmp_ |= ((val) & ~(mask)); \
1299 WREG32(reg, tmp_); \
1301 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
1302 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))
1303 #define WREG32_PLL_P(reg, val, mask) \
1305 uint32_t tmp_ = RREG32_PLL(reg); \
1307 tmp_ |= ((val) & ~(mask)); \
1308 WREG32_PLL(reg, tmp_); \
1311 #define WREG32_SMC_P(_Reg, _Val, _Mask) \
1313 u32 tmp = RREG32_SMC(_Reg); \
1315 tmp |= ((_Val) & ~(_Mask)); \
1316 WREG32_SMC(_Reg, tmp); \
1319 #define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_device_rreg((adev), (reg), false))
1321 #define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT
1322 #define REG_FIELD_MASK(reg, field) reg##__##field##_MASK
1324 #define REG_SET_FIELD(orig_val, reg, field, field_val) \
1325 (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \
1326 (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field))))
1328 #define REG_GET_FIELD(value, reg, field) \
1329 (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field))
1331 #define WREG32_FIELD(reg, field, val) \
1332 WREG32(mm##reg, (RREG32(mm##reg) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))
1334 #define WREG32_FIELD_OFFSET(reg, offset, field, val) \
1335 WREG32(mm##reg + offset, (RREG32(mm##reg + offset) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))
1337 #define AMDGPU_GET_REG_FIELD(x, h, l) (((x) & GENMASK_ULL(h, l)) >> (l))
1341 #define RBIOS8(i) (adev->bios[i])
1342 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
1343 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
1348 #define amdgpu_asic_set_vga_state(adev, state) \
1349 ((adev)->asic_funcs->set_vga_state ? (adev)->asic_funcs->set_vga_state((adev), (state)) : 0)
1350 #define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev))
1351 #define amdgpu_asic_reset_method(adev) (adev)->asic_funcs->reset_method((adev))
1352 #define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev))
1353 #define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d))
1354 #define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec))
1355 #define amdgpu_get_pcie_lanes(adev) (adev)->asic_funcs->get_pcie_lanes((adev))
1356 #define amdgpu_set_pcie_lanes(adev, l) (adev)->asic_funcs->set_pcie_lanes((adev), (l))
1357 #define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev))
1358 #define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev))
1359 #define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l))
1360 #define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v)))
1361 #define amdgpu_asic_get_config_memsize(adev) (adev)->asic_funcs->get_config_memsize((adev))
1362 #define amdgpu_asic_flush_hdp(adev, r) \
1363 ((adev)->asic_funcs->flush_hdp ? (adev)->asic_funcs->flush_hdp((adev), (r)) : (adev)->hdp.funcs->flush_hdp((adev), (r)))
1364 #define amdgpu_asic_invalidate_hdp(adev, r) \
1365 ((adev)->asic_funcs->invalidate_hdp ? (adev)->asic_funcs->invalidate_hdp((adev), (r)) : \
1366 ((adev)->hdp.funcs->invalidate_hdp ? (adev)->hdp.funcs->invalidate_hdp((adev), (r)) : (void)0))
1367 #define amdgpu_asic_need_full_reset(adev) (adev)->asic_funcs->need_full_reset((adev))
1368 #define amdgpu_asic_init_doorbell_index(adev) (adev)->asic_funcs->init_doorbell_index((adev))
1369 #define amdgpu_asic_get_pcie_usage(adev, cnt0, cnt1) ((adev)->asic_funcs->get_pcie_usage((adev), (cnt0), (cnt1)))
1370 #define amdgpu_asic_need_reset_on_init(adev) (adev)->asic_funcs->need_reset_on_init((adev))
1371 #define amdgpu_asic_get_pcie_replay_count(adev) ((adev)->asic_funcs->get_pcie_replay_count((adev)))
1372 #define amdgpu_asic_supports_baco(adev) (adev)->asic_funcs->supports_baco((adev))
1373 #define amdgpu_asic_pre_asic_init(adev) (adev)->asic_funcs->pre_asic_init((adev))
1374 #define amdgpu_asic_update_umd_stable_pstate(adev, enter) \
1375 ((adev)->asic_funcs->update_umd_stable_pstate ? (adev)->asic_funcs->update_umd_stable_pstate((adev), (enter)) : 0)
1376 #define amdgpu_asic_query_video_codecs(adev, e, c) (adev)->asic_funcs->query_video_codecs((adev), (e), (c))
1378 #define amdgpu_inc_vram_lost(adev) atomic_inc(&((adev)->vram_lost_counter))
1380 #define BIT_MASK_UPPER(i) ((i) >= BITS_PER_LONG ? 0 : ~0UL << (i))
1381 #define for_each_inst(i, inst_mask) \
1382 for (i = ffs(inst_mask); i-- != 0; \
1383 i = ffs(inst_mask & BIT_MASK_UPPER(i + 1)))
1385 /* Common functions */
1386 bool amdgpu_device_has_job_running(struct amdgpu_device *adev);
1387 bool amdgpu_device_should_recover_gpu(struct amdgpu_device *adev);
1388 int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
1389 struct amdgpu_job *job,
1390 struct amdgpu_reset_context *reset_context);
1391 void amdgpu_device_pci_config_reset(struct amdgpu_device *adev);
1392 int amdgpu_device_pci_reset(struct amdgpu_device *adev);
1393 bool amdgpu_device_need_post(struct amdgpu_device *adev);
1394 bool amdgpu_device_seamless_boot_supported(struct amdgpu_device *adev);
1395 bool amdgpu_device_should_use_aspm(struct amdgpu_device *adev);
1397 void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes,
1399 int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev);
1400 void amdgpu_device_program_register_sequence(struct amdgpu_device *adev,
1401 const u32 *registers,
1402 const u32 array_size);
1404 int amdgpu_device_mode1_reset(struct amdgpu_device *adev);
1405 bool amdgpu_device_supports_atpx(struct drm_device *dev);
1406 bool amdgpu_device_supports_px(struct drm_device *dev);
1407 bool amdgpu_device_supports_boco(struct drm_device *dev);
1408 bool amdgpu_device_supports_smart_shift(struct drm_device *dev);
1409 bool amdgpu_device_supports_baco(struct drm_device *dev);
1410 bool amdgpu_device_is_peer_accessible(struct amdgpu_device *adev,
1411 struct amdgpu_device *peer_adev);
1412 int amdgpu_device_baco_enter(struct drm_device *dev);
1413 int amdgpu_device_baco_exit(struct drm_device *dev);
1415 void amdgpu_device_flush_hdp(struct amdgpu_device *adev,
1416 struct amdgpu_ring *ring);
1417 void amdgpu_device_invalidate_hdp(struct amdgpu_device *adev,
1418 struct amdgpu_ring *ring);
1420 void amdgpu_device_halt(struct amdgpu_device *adev);
1421 u32 amdgpu_device_pcie_port_rreg(struct amdgpu_device *adev,
1423 void amdgpu_device_pcie_port_wreg(struct amdgpu_device *adev,
1425 struct dma_fence *amdgpu_device_switch_gang(struct amdgpu_device *adev,
1426 struct dma_fence *gang);
1427 bool amdgpu_device_has_display_hardware(struct amdgpu_device *adev);
1430 #if defined(CONFIG_VGA_SWITCHEROO)
1431 void amdgpu_register_atpx_handler(void);
1432 void amdgpu_unregister_atpx_handler(void);
1433 bool amdgpu_has_atpx_dgpu_power_cntl(void);
1434 bool amdgpu_is_atpx_hybrid(void);
1435 bool amdgpu_atpx_dgpu_req_power_for_displays(void);
1436 bool amdgpu_has_atpx(void);
1438 static inline void amdgpu_register_atpx_handler(void) {}
1439 static inline void amdgpu_unregister_atpx_handler(void) {}
1440 static inline bool amdgpu_has_atpx_dgpu_power_cntl(void) { return false; }
1441 static inline bool amdgpu_is_atpx_hybrid(void) { return false; }
1442 static inline bool amdgpu_atpx_dgpu_req_power_for_displays(void) { return false; }
1443 static inline bool amdgpu_has_atpx(void) { return false; }
1446 #if defined(CONFIG_VGA_SWITCHEROO) && defined(CONFIG_ACPI)
1447 void *amdgpu_atpx_get_dhandle(void);
1449 static inline void *amdgpu_atpx_get_dhandle(void) { return NULL; }
1455 extern const struct drm_ioctl_desc amdgpu_ioctls_kms[];
1456 extern const int amdgpu_max_kms_ioctl;
1458 int amdgpu_driver_load_kms(struct amdgpu_device *adev, unsigned long flags);
1459 void amdgpu_driver_unload_kms(struct drm_device *dev);
1460 void amdgpu_driver_lastclose_kms(struct drm_device *dev);
1461 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv);
1462 void amdgpu_driver_postclose_kms(struct drm_device *dev,
1463 struct drm_file *file_priv);
1464 void amdgpu_driver_release_kms(struct drm_device *dev);
1466 int amdgpu_device_ip_suspend(struct amdgpu_device *adev);
1467 int amdgpu_device_prepare(struct drm_device *dev);
1468 int amdgpu_device_suspend(struct drm_device *dev, bool fbcon);
1469 int amdgpu_device_resume(struct drm_device *dev, bool fbcon);
1470 u32 amdgpu_get_vblank_counter_kms(struct drm_crtc *crtc);
1471 int amdgpu_enable_vblank_kms(struct drm_crtc *crtc);
1472 void amdgpu_disable_vblank_kms(struct drm_crtc *crtc);
1473 int amdgpu_info_ioctl(struct drm_device *dev, void *data,
1474 struct drm_file *filp);
1477 * functions used by amdgpu_encoder.c
1479 struct amdgpu_afmt_acr {
1493 struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock);
1497 struct amdgpu_numa_info {
1503 /* ATCS Device/Driver State */
1504 #define AMDGPU_ATCS_PSC_DEV_STATE_D0 0
1505 #define AMDGPU_ATCS_PSC_DEV_STATE_D3_HOT 3
1506 #define AMDGPU_ATCS_PSC_DRV_STATE_OPR 0
1507 #define AMDGPU_ATCS_PSC_DRV_STATE_NOT_OPR 1
1509 #if defined(CONFIG_ACPI)
1510 int amdgpu_acpi_init(struct amdgpu_device *adev);
1511 void amdgpu_acpi_fini(struct amdgpu_device *adev);
1512 bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev);
1513 bool amdgpu_acpi_is_power_shift_control_supported(void);
1514 int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev,
1515 u8 perf_req, bool advertise);
1516 int amdgpu_acpi_power_shift_control(struct amdgpu_device *adev,
1517 u8 dev_state, bool drv_state);
1518 int amdgpu_acpi_smart_shift_update(struct drm_device *dev, enum amdgpu_ss ss_state);
1519 int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev);
1520 int amdgpu_acpi_get_tmr_info(struct amdgpu_device *adev, u64 *tmr_offset,
1522 int amdgpu_acpi_get_mem_info(struct amdgpu_device *adev, int xcc_id,
1523 struct amdgpu_numa_info *numa_info);
1525 void amdgpu_acpi_get_backlight_caps(struct amdgpu_dm_backlight_caps *caps);
1526 bool amdgpu_acpi_should_gpu_reset(struct amdgpu_device *adev);
1527 void amdgpu_acpi_detect(void);
1528 void amdgpu_acpi_release(void);
1530 static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; }
1531 static inline int amdgpu_acpi_get_tmr_info(struct amdgpu_device *adev,
1532 u64 *tmr_offset, u64 *tmr_size)
1536 static inline int amdgpu_acpi_get_mem_info(struct amdgpu_device *adev,
1538 struct amdgpu_numa_info *numa_info)
1542 static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { }
1543 static inline bool amdgpu_acpi_should_gpu_reset(struct amdgpu_device *adev) { return false; }
1544 static inline void amdgpu_acpi_detect(void) { }
1545 static inline void amdgpu_acpi_release(void) { }
1546 static inline bool amdgpu_acpi_is_power_shift_control_supported(void) { return false; }
1547 static inline int amdgpu_acpi_power_shift_control(struct amdgpu_device *adev,
1548 u8 dev_state, bool drv_state) { return 0; }
1549 static inline int amdgpu_acpi_smart_shift_update(struct drm_device *dev,
1550 enum amdgpu_ss ss_state) { return 0; }
1553 #if defined(CONFIG_ACPI) && defined(CONFIG_SUSPEND)
1554 bool amdgpu_acpi_is_s3_active(struct amdgpu_device *adev);
1555 bool amdgpu_acpi_is_s0ix_active(struct amdgpu_device *adev);
1556 void amdgpu_choose_low_power_state(struct amdgpu_device *adev);
1558 static inline bool amdgpu_acpi_is_s0ix_active(struct amdgpu_device *adev) { return false; }
1559 static inline bool amdgpu_acpi_is_s3_active(struct amdgpu_device *adev) { return false; }
1560 static inline void amdgpu_choose_low_power_state(struct amdgpu_device *adev) { }
1563 #if defined(CONFIG_DRM_AMD_DC)
1564 int amdgpu_dm_display_resume(struct amdgpu_device *adev );
1566 static inline int amdgpu_dm_display_resume(struct amdgpu_device *adev) { return 0; }
1570 void amdgpu_register_gpu_instance(struct amdgpu_device *adev);
1571 void amdgpu_unregister_gpu_instance(struct amdgpu_device *adev);
1573 pci_ers_result_t amdgpu_pci_error_detected(struct pci_dev *pdev,
1574 pci_channel_state_t state);
1575 pci_ers_result_t amdgpu_pci_mmio_enabled(struct pci_dev *pdev);
1576 pci_ers_result_t amdgpu_pci_slot_reset(struct pci_dev *pdev);
1577 void amdgpu_pci_resume(struct pci_dev *pdev);
1579 bool amdgpu_device_cache_pci_state(struct pci_dev *pdev);
1580 bool amdgpu_device_load_pci_state(struct pci_dev *pdev);
1582 bool amdgpu_device_skip_hw_access(struct amdgpu_device *adev);
1584 int amdgpu_device_set_cg_state(struct amdgpu_device *adev,
1585 enum amd_clockgating_state state);
1586 int amdgpu_device_set_pg_state(struct amdgpu_device *adev,
1587 enum amd_powergating_state state);
1589 static inline bool amdgpu_device_has_timeouts_enabled(struct amdgpu_device *adev)
1591 return amdgpu_gpu_recovery != 0 &&
1592 adev->gfx_timeout != MAX_SCHEDULE_TIMEOUT &&
1593 adev->compute_timeout != MAX_SCHEDULE_TIMEOUT &&
1594 adev->sdma_timeout != MAX_SCHEDULE_TIMEOUT &&
1595 adev->video_timeout != MAX_SCHEDULE_TIMEOUT;
1598 #include "amdgpu_object.h"
1600 static inline bool amdgpu_is_tmz(struct amdgpu_device *adev)
1602 return adev->gmc.tmz_enabled;
1605 int amdgpu_in_reset(struct amdgpu_device *adev);
1607 extern const struct attribute_group amdgpu_vram_mgr_attr_group;
1608 extern const struct attribute_group amdgpu_gtt_mgr_attr_group;
1609 extern const struct attribute_group amdgpu_flash_attr_group;