2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
31 #include <linux/atomic.h>
32 #include <linux/wait.h>
33 #include <linux/list.h>
34 #include <linux/kref.h>
35 #include <linux/interval_tree.h>
36 #include <linux/hashtable.h>
37 #include <linux/fence.h>
39 #include <ttm/ttm_bo_api.h>
40 #include <ttm/ttm_bo_driver.h>
41 #include <ttm/ttm_placement.h>
42 #include <ttm/ttm_module.h>
43 #include <ttm/ttm_execbuf_util.h>
46 #include <drm/drm_gem.h>
47 #include <drm/amdgpu_drm.h>
49 #include "amd_shared.h"
50 #include "amdgpu_mode.h"
51 #include "amdgpu_ih.h"
52 #include "amdgpu_irq.h"
53 #include "amdgpu_ucode.h"
54 #include "amdgpu_gds.h"
55 #include "amd_powerplay.h"
57 #include "gpu_scheduler.h"
62 extern int amdgpu_modeset;
63 extern int amdgpu_vram_limit;
64 extern int amdgpu_gart_size;
65 extern int amdgpu_benchmarking;
66 extern int amdgpu_testing;
67 extern int amdgpu_audio;
68 extern int amdgpu_disp_priority;
69 extern int amdgpu_hw_i2c;
70 extern int amdgpu_pcie_gen2;
71 extern int amdgpu_msi;
72 extern int amdgpu_lockup_timeout;
73 extern int amdgpu_dpm;
74 extern int amdgpu_smc_load_fw;
75 extern int amdgpu_aspm;
76 extern int amdgpu_runtime_pm;
77 extern int amdgpu_hard_reset;
78 extern unsigned amdgpu_ip_block_mask;
79 extern int amdgpu_bapm;
80 extern int amdgpu_deep_color;
81 extern int amdgpu_vm_size;
82 extern int amdgpu_vm_block_size;
83 extern int amdgpu_vm_fault_stop;
84 extern int amdgpu_vm_debug;
85 extern int amdgpu_enable_scheduler;
86 extern int amdgpu_sched_jobs;
87 extern int amdgpu_sched_hw_submission;
88 extern int amdgpu_enable_semaphores;
89 extern int amdgpu_powerplay;
91 #define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000
92 #define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */
93 #define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2)
94 /* AMDGPU_IB_POOL_SIZE must be a power of 2 */
95 #define AMDGPU_IB_POOL_SIZE 16
96 #define AMDGPU_DEBUGFS_MAX_COMPONENTS 32
97 #define AMDGPUFB_CONN_LIMIT 4
98 #define AMDGPU_BIOS_NUM_SCRATCH 8
100 /* max number of rings */
101 #define AMDGPU_MAX_RINGS 16
102 #define AMDGPU_MAX_GFX_RINGS 1
103 #define AMDGPU_MAX_COMPUTE_RINGS 8
104 #define AMDGPU_MAX_VCE_RINGS 2
106 /* max number of IP instances */
107 #define AMDGPU_MAX_SDMA_INSTANCES 2
109 /* number of hw syncs before falling back on blocking */
110 #define AMDGPU_NUM_SYNCS 4
112 /* hardcode that limit for now */
113 #define AMDGPU_VA_RESERVED_SIZE (8 << 20)
115 /* hard reset data */
116 #define AMDGPU_ASIC_RESET_DATA 0x39d5e86b
119 #define AMDGPU_RESET_GFX (1 << 0)
120 #define AMDGPU_RESET_COMPUTE (1 << 1)
121 #define AMDGPU_RESET_DMA (1 << 2)
122 #define AMDGPU_RESET_CP (1 << 3)
123 #define AMDGPU_RESET_GRBM (1 << 4)
124 #define AMDGPU_RESET_DMA1 (1 << 5)
125 #define AMDGPU_RESET_RLC (1 << 6)
126 #define AMDGPU_RESET_SEM (1 << 7)
127 #define AMDGPU_RESET_IH (1 << 8)
128 #define AMDGPU_RESET_VMC (1 << 9)
129 #define AMDGPU_RESET_MC (1 << 10)
130 #define AMDGPU_RESET_DISPLAY (1 << 11)
131 #define AMDGPU_RESET_UVD (1 << 12)
132 #define AMDGPU_RESET_VCE (1 << 13)
133 #define AMDGPU_RESET_VCE1 (1 << 14)
136 #define AMDGPU_CG_BLOCK_GFX (1 << 0)
137 #define AMDGPU_CG_BLOCK_MC (1 << 1)
138 #define AMDGPU_CG_BLOCK_SDMA (1 << 2)
139 #define AMDGPU_CG_BLOCK_UVD (1 << 3)
140 #define AMDGPU_CG_BLOCK_VCE (1 << 4)
141 #define AMDGPU_CG_BLOCK_HDP (1 << 5)
142 #define AMDGPU_CG_BLOCK_BIF (1 << 6)
145 #define AMDGPU_CG_SUPPORT_GFX_MGCG (1 << 0)
146 #define AMDGPU_CG_SUPPORT_GFX_MGLS (1 << 1)
147 #define AMDGPU_CG_SUPPORT_GFX_CGCG (1 << 2)
148 #define AMDGPU_CG_SUPPORT_GFX_CGLS (1 << 3)
149 #define AMDGPU_CG_SUPPORT_GFX_CGTS (1 << 4)
150 #define AMDGPU_CG_SUPPORT_GFX_CGTS_LS (1 << 5)
151 #define AMDGPU_CG_SUPPORT_GFX_CP_LS (1 << 6)
152 #define AMDGPU_CG_SUPPORT_GFX_RLC_LS (1 << 7)
153 #define AMDGPU_CG_SUPPORT_MC_LS (1 << 8)
154 #define AMDGPU_CG_SUPPORT_MC_MGCG (1 << 9)
155 #define AMDGPU_CG_SUPPORT_SDMA_LS (1 << 10)
156 #define AMDGPU_CG_SUPPORT_SDMA_MGCG (1 << 11)
157 #define AMDGPU_CG_SUPPORT_BIF_LS (1 << 12)
158 #define AMDGPU_CG_SUPPORT_UVD_MGCG (1 << 13)
159 #define AMDGPU_CG_SUPPORT_VCE_MGCG (1 << 14)
160 #define AMDGPU_CG_SUPPORT_HDP_LS (1 << 15)
161 #define AMDGPU_CG_SUPPORT_HDP_MGCG (1 << 16)
164 #define AMDGPU_PG_SUPPORT_GFX_PG (1 << 0)
165 #define AMDGPU_PG_SUPPORT_GFX_SMG (1 << 1)
166 #define AMDGPU_PG_SUPPORT_GFX_DMG (1 << 2)
167 #define AMDGPU_PG_SUPPORT_UVD (1 << 3)
168 #define AMDGPU_PG_SUPPORT_VCE (1 << 4)
169 #define AMDGPU_PG_SUPPORT_CP (1 << 5)
170 #define AMDGPU_PG_SUPPORT_GDS (1 << 6)
171 #define AMDGPU_PG_SUPPORT_RLC_SMU_HS (1 << 7)
172 #define AMDGPU_PG_SUPPORT_SDMA (1 << 8)
173 #define AMDGPU_PG_SUPPORT_ACP (1 << 9)
174 #define AMDGPU_PG_SUPPORT_SAMU (1 << 10)
176 /* GFX current status */
177 #define AMDGPU_GFX_NORMAL_MODE 0x00000000L
178 #define AMDGPU_GFX_SAFE_MODE 0x00000001L
179 #define AMDGPU_GFX_PG_DISABLED_MODE 0x00000002L
180 #define AMDGPU_GFX_CG_DISABLED_MODE 0x00000004L
181 #define AMDGPU_GFX_LBPW_DISABLED_MODE 0x00000008L
183 /* max cursor sizes (in pixels) */
184 #define CIK_CURSOR_WIDTH 128
185 #define CIK_CURSOR_HEIGHT 128
187 struct amdgpu_device;
192 struct amdgpu_semaphore;
193 struct amdgpu_cs_parser;
195 struct amdgpu_irq_src;
199 AMDGPU_CP_IRQ_GFX_EOP = 0,
200 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP,
201 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP,
202 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP,
203 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP,
204 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP,
205 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP,
206 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP,
207 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP,
212 enum amdgpu_sdma_irq {
213 AMDGPU_SDMA_IRQ_TRAP0 = 0,
214 AMDGPU_SDMA_IRQ_TRAP1,
219 enum amdgpu_thermal_irq {
220 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0,
221 AMDGPU_THERMAL_IRQ_HIGH_TO_LOW,
223 AMDGPU_THERMAL_IRQ_LAST
226 int amdgpu_set_clockgating_state(struct amdgpu_device *adev,
227 enum amd_ip_block_type block_type,
228 enum amd_clockgating_state state);
229 int amdgpu_set_powergating_state(struct amdgpu_device *adev,
230 enum amd_ip_block_type block_type,
231 enum amd_powergating_state state);
233 struct amdgpu_ip_block_version {
234 enum amd_ip_block_type type;
238 const struct amd_ip_funcs *funcs;
241 int amdgpu_ip_block_version_cmp(struct amdgpu_device *adev,
242 enum amd_ip_block_type type,
243 u32 major, u32 minor);
245 const struct amdgpu_ip_block_version * amdgpu_get_ip_block(
246 struct amdgpu_device *adev,
247 enum amd_ip_block_type type);
249 /* provided by hw blocks that can move/clear data. e.g., gfx or sdma */
250 struct amdgpu_buffer_funcs {
251 /* maximum bytes in a single operation */
252 uint32_t copy_max_bytes;
254 /* number of dw to reserve per operation */
255 unsigned copy_num_dw;
257 /* used for buffer migration */
258 void (*emit_copy_buffer)(struct amdgpu_ib *ib,
259 /* src addr in bytes */
261 /* dst addr in bytes */
263 /* number of byte to transfer */
264 uint32_t byte_count);
266 /* maximum bytes in a single operation */
267 uint32_t fill_max_bytes;
269 /* number of dw to reserve per operation */
270 unsigned fill_num_dw;
272 /* used for buffer clearing */
273 void (*emit_fill_buffer)(struct amdgpu_ib *ib,
274 /* value to write to memory */
276 /* dst addr in bytes */
278 /* number of byte to fill */
279 uint32_t byte_count);
282 /* provided by hw blocks that can write ptes, e.g., sdma */
283 struct amdgpu_vm_pte_funcs {
284 /* copy pte entries from GART */
285 void (*copy_pte)(struct amdgpu_ib *ib,
286 uint64_t pe, uint64_t src,
288 /* write pte one entry at a time with addr mapping */
289 void (*write_pte)(struct amdgpu_ib *ib,
291 uint64_t addr, unsigned count,
292 uint32_t incr, uint32_t flags);
293 /* for linear pte/pde updates without addr mapping */
294 void (*set_pte_pde)(struct amdgpu_ib *ib,
296 uint64_t addr, unsigned count,
297 uint32_t incr, uint32_t flags);
298 /* pad the indirect buffer to the necessary number of dw */
299 void (*pad_ib)(struct amdgpu_ib *ib);
302 /* provided by the gmc block */
303 struct amdgpu_gart_funcs {
304 /* flush the vm tlb via mmio */
305 void (*flush_gpu_tlb)(struct amdgpu_device *adev,
307 /* write pte/pde updates using the cpu */
308 int (*set_pte_pde)(struct amdgpu_device *adev,
309 void *cpu_pt_addr, /* cpu addr of page table */
310 uint32_t gpu_page_idx, /* pte/pde to update */
311 uint64_t addr, /* addr to write into pte/pde */
312 uint32_t flags); /* access flags */
315 /* provided by the ih block */
316 struct amdgpu_ih_funcs {
317 /* ring read/write ptr handling, called from interrupt context */
318 u32 (*get_wptr)(struct amdgpu_device *adev);
319 void (*decode_iv)(struct amdgpu_device *adev,
320 struct amdgpu_iv_entry *entry);
321 void (*set_rptr)(struct amdgpu_device *adev);
324 /* provided by hw blocks that expose a ring buffer for commands */
325 struct amdgpu_ring_funcs {
326 /* ring read/write ptr handling */
327 u32 (*get_rptr)(struct amdgpu_ring *ring);
328 u32 (*get_wptr)(struct amdgpu_ring *ring);
329 void (*set_wptr)(struct amdgpu_ring *ring);
330 /* validating and patching of IBs */
331 int (*parse_cs)(struct amdgpu_cs_parser *p, uint32_t ib_idx);
332 /* command emit functions */
333 void (*emit_ib)(struct amdgpu_ring *ring,
334 struct amdgpu_ib *ib);
335 void (*emit_fence)(struct amdgpu_ring *ring, uint64_t addr,
336 uint64_t seq, unsigned flags);
337 bool (*emit_semaphore)(struct amdgpu_ring *ring,
338 struct amdgpu_semaphore *semaphore,
340 void (*emit_vm_flush)(struct amdgpu_ring *ring, unsigned vm_id,
342 void (*emit_hdp_flush)(struct amdgpu_ring *ring);
343 void (*emit_gds_switch)(struct amdgpu_ring *ring, uint32_t vmid,
344 uint32_t gds_base, uint32_t gds_size,
345 uint32_t gws_base, uint32_t gws_size,
346 uint32_t oa_base, uint32_t oa_size);
347 /* testing functions */
348 int (*test_ring)(struct amdgpu_ring *ring);
349 int (*test_ib)(struct amdgpu_ring *ring);
350 /* insert NOP packets */
351 void (*insert_nop)(struct amdgpu_ring *ring, uint32_t count);
357 bool amdgpu_get_bios(struct amdgpu_device *adev);
358 bool amdgpu_read_bios(struct amdgpu_device *adev);
363 struct amdgpu_dummy_page {
367 int amdgpu_dummy_page_init(struct amdgpu_device *adev);
368 void amdgpu_dummy_page_fini(struct amdgpu_device *adev);
375 #define AMDGPU_MAX_PPLL 3
377 struct amdgpu_clock {
378 struct amdgpu_pll ppll[AMDGPU_MAX_PPLL];
379 struct amdgpu_pll spll;
380 struct amdgpu_pll mpll;
382 uint32_t default_mclk;
383 uint32_t default_sclk;
384 uint32_t default_dispclk;
385 uint32_t current_dispclk;
387 uint32_t max_pixel_clock;
393 struct amdgpu_fence_driver {
395 volatile uint32_t *cpu_addr;
396 /* sync_seq is protected by ring emission lock */
397 uint64_t sync_seq[AMDGPU_MAX_RINGS];
400 struct amdgpu_irq_src *irq_src;
402 struct timer_list fallback_timer;
403 wait_queue_head_t fence_queue;
406 /* some special values for the owner field */
407 #define AMDGPU_FENCE_OWNER_UNDEFINED ((void*)0ul)
408 #define AMDGPU_FENCE_OWNER_VM ((void*)1ul)
410 #define AMDGPU_FENCE_FLAG_64BIT (1 << 0)
411 #define AMDGPU_FENCE_FLAG_INT (1 << 1)
413 struct amdgpu_fence {
417 struct amdgpu_ring *ring;
420 /* filp or special value for fence creator */
423 wait_queue_t fence_wake;
426 struct amdgpu_user_fence {
428 struct amdgpu_bo *bo;
429 /* write-back address offset to bo start */
433 int amdgpu_fence_driver_init(struct amdgpu_device *adev);
434 void amdgpu_fence_driver_fini(struct amdgpu_device *adev);
435 void amdgpu_fence_driver_force_completion(struct amdgpu_device *adev);
437 int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring);
438 int amdgpu_fence_driver_start_ring(struct amdgpu_ring *ring,
439 struct amdgpu_irq_src *irq_src,
441 void amdgpu_fence_driver_suspend(struct amdgpu_device *adev);
442 void amdgpu_fence_driver_resume(struct amdgpu_device *adev);
443 int amdgpu_fence_emit(struct amdgpu_ring *ring, void *owner,
444 struct amdgpu_fence **fence);
445 void amdgpu_fence_process(struct amdgpu_ring *ring);
446 int amdgpu_fence_wait_next(struct amdgpu_ring *ring);
447 int amdgpu_fence_wait_empty(struct amdgpu_ring *ring);
448 unsigned amdgpu_fence_count_emitted(struct amdgpu_ring *ring);
450 bool amdgpu_fence_need_sync(struct amdgpu_fence *fence,
451 struct amdgpu_ring *ring);
452 void amdgpu_fence_note_sync(struct amdgpu_fence *fence,
453 struct amdgpu_ring *ring);
459 struct ttm_bo_global_ref bo_global_ref;
460 struct drm_global_reference mem_global_ref;
461 struct ttm_bo_device bdev;
462 bool mem_global_referenced;
465 #if defined(CONFIG_DEBUG_FS)
470 /* buffer handling */
471 const struct amdgpu_buffer_funcs *buffer_funcs;
472 struct amdgpu_ring *buffer_funcs_ring;
475 int amdgpu_copy_buffer(struct amdgpu_ring *ring,
479 struct reservation_object *resv,
480 struct fence **fence);
481 int amdgpu_mmap(struct file *filp, struct vm_area_struct *vma);
483 struct amdgpu_bo_list_entry {
484 struct amdgpu_bo *robj;
485 struct ttm_validate_buffer tv;
486 struct amdgpu_bo_va *bo_va;
487 unsigned prefered_domains;
488 unsigned allowed_domains;
492 struct amdgpu_bo_va_mapping {
493 struct list_head list;
494 struct interval_tree_node it;
499 /* bo virtual addresses in a specific vm */
500 struct amdgpu_bo_va {
502 /* protected by bo being reserved */
503 struct list_head bo_list;
504 struct fence *last_pt_update;
507 /* protected by vm mutex and spinlock */
508 struct list_head vm_status;
510 /* mappings for this bo_va */
511 struct list_head invalids;
512 struct list_head valids;
514 /* constant after initialization */
515 struct amdgpu_vm *vm;
516 struct amdgpu_bo *bo;
519 #define AMDGPU_GEM_DOMAIN_MAX 0x3
522 /* Protected by gem.mutex */
523 struct list_head list;
524 /* Protected by tbo.reserved */
526 struct ttm_place placements[AMDGPU_GEM_DOMAIN_MAX + 1];
527 struct ttm_placement placement;
528 struct ttm_buffer_object tbo;
529 struct ttm_bo_kmap_obj kmap;
537 /* list of all virtual address to which this bo
541 /* Constant after initialization */
542 struct amdgpu_device *adev;
543 struct drm_gem_object gem_base;
545 struct ttm_bo_kmap_obj dma_buf_vmap;
547 struct amdgpu_mn *mn;
548 struct list_head mn_list;
550 #define gem_to_amdgpu_bo(gobj) container_of((gobj), struct amdgpu_bo, gem_base)
552 void amdgpu_gem_object_free(struct drm_gem_object *obj);
553 int amdgpu_gem_object_open(struct drm_gem_object *obj,
554 struct drm_file *file_priv);
555 void amdgpu_gem_object_close(struct drm_gem_object *obj,
556 struct drm_file *file_priv);
557 unsigned long amdgpu_gem_timeout(uint64_t timeout_ns);
558 struct sg_table *amdgpu_gem_prime_get_sg_table(struct drm_gem_object *obj);
559 struct drm_gem_object *amdgpu_gem_prime_import_sg_table(struct drm_device *dev,
560 struct dma_buf_attachment *attach,
561 struct sg_table *sg);
562 struct dma_buf *amdgpu_gem_prime_export(struct drm_device *dev,
563 struct drm_gem_object *gobj,
565 int amdgpu_gem_prime_pin(struct drm_gem_object *obj);
566 void amdgpu_gem_prime_unpin(struct drm_gem_object *obj);
567 struct reservation_object *amdgpu_gem_prime_res_obj(struct drm_gem_object *);
568 void *amdgpu_gem_prime_vmap(struct drm_gem_object *obj);
569 void amdgpu_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr);
570 int amdgpu_gem_debugfs_init(struct amdgpu_device *adev);
572 /* sub-allocation manager, it has to be protected by another lock.
573 * By conception this is an helper for other part of the driver
574 * like the indirect buffer or semaphore, which both have their
577 * Principe is simple, we keep a list of sub allocation in offset
578 * order (first entry has offset == 0, last entry has the highest
581 * When allocating new object we first check if there is room at
582 * the end total_size - (last_object_offset + last_object_size) >=
583 * alloc_size. If so we allocate new object there.
585 * When there is not enough room at the end, we start waiting for
586 * each sub object until we reach object_offset+object_size >=
587 * alloc_size, this object then become the sub object we return.
589 * Alignment can't be bigger than page size.
591 * Hole are not considered for allocation to keep things simple.
592 * Assumption is that there won't be hole (all object on same
595 struct amdgpu_sa_manager {
596 wait_queue_head_t wq;
597 struct amdgpu_bo *bo;
598 struct list_head *hole;
599 struct list_head flist[AMDGPU_MAX_RINGS];
600 struct list_head olist;
610 /* sub-allocation buffer */
611 struct amdgpu_sa_bo {
612 struct list_head olist;
613 struct list_head flist;
614 struct amdgpu_sa_manager *manager;
625 struct list_head objects;
628 int amdgpu_gem_init(struct amdgpu_device *adev);
629 void amdgpu_gem_fini(struct amdgpu_device *adev);
630 int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size,
631 int alignment, u32 initial_domain,
632 u64 flags, bool kernel,
633 struct drm_gem_object **obj);
635 int amdgpu_mode_dumb_create(struct drm_file *file_priv,
636 struct drm_device *dev,
637 struct drm_mode_create_dumb *args);
638 int amdgpu_mode_dumb_mmap(struct drm_file *filp,
639 struct drm_device *dev,
640 uint32_t handle, uint64_t *offset_p);
645 struct amdgpu_semaphore {
646 struct amdgpu_sa_bo *sa_bo;
651 int amdgpu_semaphore_create(struct amdgpu_device *adev,
652 struct amdgpu_semaphore **semaphore);
653 bool amdgpu_semaphore_emit_signal(struct amdgpu_ring *ring,
654 struct amdgpu_semaphore *semaphore);
655 bool amdgpu_semaphore_emit_wait(struct amdgpu_ring *ring,
656 struct amdgpu_semaphore *semaphore);
657 void amdgpu_semaphore_free(struct amdgpu_device *adev,
658 struct amdgpu_semaphore **semaphore,
659 struct fence *fence);
665 struct amdgpu_semaphore *semaphores[AMDGPU_NUM_SYNCS];
666 struct fence *sync_to[AMDGPU_MAX_RINGS];
667 DECLARE_HASHTABLE(fences, 4);
668 struct fence *last_vm_update;
671 void amdgpu_sync_create(struct amdgpu_sync *sync);
672 int amdgpu_sync_fence(struct amdgpu_device *adev, struct amdgpu_sync *sync,
674 int amdgpu_sync_resv(struct amdgpu_device *adev,
675 struct amdgpu_sync *sync,
676 struct reservation_object *resv,
678 int amdgpu_sync_rings(struct amdgpu_sync *sync,
679 struct amdgpu_ring *ring);
680 struct fence *amdgpu_sync_get_fence(struct amdgpu_sync *sync);
681 int amdgpu_sync_wait(struct amdgpu_sync *sync);
682 void amdgpu_sync_free(struct amdgpu_device *adev, struct amdgpu_sync *sync,
683 struct fence *fence);
686 * GART structures, functions & helpers
690 #define AMDGPU_GPU_PAGE_SIZE 4096
691 #define AMDGPU_GPU_PAGE_MASK (AMDGPU_GPU_PAGE_SIZE - 1)
692 #define AMDGPU_GPU_PAGE_SHIFT 12
693 #define AMDGPU_GPU_PAGE_ALIGN(a) (((a) + AMDGPU_GPU_PAGE_MASK) & ~AMDGPU_GPU_PAGE_MASK)
696 dma_addr_t table_addr;
697 struct amdgpu_bo *robj;
699 unsigned num_gpu_pages;
700 unsigned num_cpu_pages;
703 dma_addr_t *pages_addr;
705 const struct amdgpu_gart_funcs *gart_funcs;
708 int amdgpu_gart_table_ram_alloc(struct amdgpu_device *adev);
709 void amdgpu_gart_table_ram_free(struct amdgpu_device *adev);
710 int amdgpu_gart_table_vram_alloc(struct amdgpu_device *adev);
711 void amdgpu_gart_table_vram_free(struct amdgpu_device *adev);
712 int amdgpu_gart_table_vram_pin(struct amdgpu_device *adev);
713 void amdgpu_gart_table_vram_unpin(struct amdgpu_device *adev);
714 int amdgpu_gart_init(struct amdgpu_device *adev);
715 void amdgpu_gart_fini(struct amdgpu_device *adev);
716 void amdgpu_gart_unbind(struct amdgpu_device *adev, unsigned offset,
718 int amdgpu_gart_bind(struct amdgpu_device *adev, unsigned offset,
719 int pages, struct page **pagelist,
720 dma_addr_t *dma_addr, uint32_t flags);
723 * GPU MC structures, functions & helpers
726 resource_size_t aper_size;
727 resource_size_t aper_base;
728 resource_size_t agp_base;
729 /* for some chips with <= 32MB we need to lie
730 * about vram size near mc fb location */
732 u64 visible_vram_size;
743 const struct firmware *fw; /* MC firmware */
745 struct amdgpu_irq_src vm_fault;
750 * GPU doorbell structures, functions & helpers
752 typedef enum _AMDGPU_DOORBELL_ASSIGNMENT
754 AMDGPU_DOORBELL_KIQ = 0x000,
755 AMDGPU_DOORBELL_HIQ = 0x001,
756 AMDGPU_DOORBELL_DIQ = 0x002,
757 AMDGPU_DOORBELL_MEC_RING0 = 0x010,
758 AMDGPU_DOORBELL_MEC_RING1 = 0x011,
759 AMDGPU_DOORBELL_MEC_RING2 = 0x012,
760 AMDGPU_DOORBELL_MEC_RING3 = 0x013,
761 AMDGPU_DOORBELL_MEC_RING4 = 0x014,
762 AMDGPU_DOORBELL_MEC_RING5 = 0x015,
763 AMDGPU_DOORBELL_MEC_RING6 = 0x016,
764 AMDGPU_DOORBELL_MEC_RING7 = 0x017,
765 AMDGPU_DOORBELL_GFX_RING0 = 0x020,
766 AMDGPU_DOORBELL_sDMA_ENGINE0 = 0x1E0,
767 AMDGPU_DOORBELL_sDMA_ENGINE1 = 0x1E1,
768 AMDGPU_DOORBELL_IH = 0x1E8,
769 AMDGPU_DOORBELL_MAX_ASSIGNMENT = 0x3FF,
770 AMDGPU_DOORBELL_INVALID = 0xFFFF
771 } AMDGPU_DOORBELL_ASSIGNMENT;
773 struct amdgpu_doorbell {
775 resource_size_t base;
776 resource_size_t size;
778 u32 num_doorbells; /* Number of doorbells actually reserved for amdgpu. */
781 void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev,
782 phys_addr_t *aperture_base,
783 size_t *aperture_size,
784 size_t *start_offset);
790 struct amdgpu_flip_work {
791 struct work_struct flip_work;
792 struct work_struct unpin_work;
793 struct amdgpu_device *adev;
796 struct drm_pending_vblank_event *event;
797 struct amdgpu_bo *old_rbo;
799 unsigned shared_count;
800 struct fence **shared;
809 struct amdgpu_sa_bo *sa_bo;
813 struct amdgpu_ring *ring;
814 struct amdgpu_fence *fence;
815 struct amdgpu_user_fence *user;
816 struct amdgpu_vm *vm;
817 struct amdgpu_ctx *ctx;
818 struct amdgpu_sync sync;
819 uint32_t gds_base, gds_size;
820 uint32_t gws_base, gws_size;
821 uint32_t oa_base, oa_size;
823 /* resulting sequence number */
827 enum amdgpu_ring_type {
828 AMDGPU_RING_TYPE_GFX,
829 AMDGPU_RING_TYPE_COMPUTE,
830 AMDGPU_RING_TYPE_SDMA,
831 AMDGPU_RING_TYPE_UVD,
835 extern struct amd_sched_backend_ops amdgpu_sched_ops;
837 int amdgpu_sched_ib_submit_kernel_helper(struct amdgpu_device *adev,
838 struct amdgpu_ring *ring,
839 struct amdgpu_ib *ibs,
841 int (*free_job)(struct amdgpu_job *),
843 struct fence **fence);
846 struct amdgpu_device *adev;
847 const struct amdgpu_ring_funcs *funcs;
848 struct amdgpu_fence_driver fence_drv;
849 struct amd_gpu_scheduler sched;
851 spinlock_t fence_lock;
852 struct mutex *ring_lock;
853 struct amdgpu_bo *ring_obj;
854 volatile uint32_t *ring;
856 u64 next_rptr_gpu_addr;
857 volatile u32 *next_rptr_cpu_addr;
861 unsigned ring_free_dw;
869 u64 last_semaphore_signal_addr;
870 u64 last_semaphore_wait_addr;
874 struct amdgpu_bo *mqd_obj;
878 unsigned next_rptr_offs;
880 struct amdgpu_ctx *current_ctx;
881 enum amdgpu_ring_type type;
890 /* maximum number of VMIDs */
891 #define AMDGPU_NUM_VM 16
893 /* number of entries in page table */
894 #define AMDGPU_VM_PTE_COUNT (1 << amdgpu_vm_block_size)
896 /* PTBs (Page Table Blocks) need to be aligned to 32K */
897 #define AMDGPU_VM_PTB_ALIGN_SIZE 32768
898 #define AMDGPU_VM_PTB_ALIGN_MASK (AMDGPU_VM_PTB_ALIGN_SIZE - 1)
899 #define AMDGPU_VM_PTB_ALIGN(a) (((a) + AMDGPU_VM_PTB_ALIGN_MASK) & ~AMDGPU_VM_PTB_ALIGN_MASK)
901 #define AMDGPU_PTE_VALID (1 << 0)
902 #define AMDGPU_PTE_SYSTEM (1 << 1)
903 #define AMDGPU_PTE_SNOOPED (1 << 2)
906 #define AMDGPU_PTE_EXECUTABLE (1 << 4)
908 #define AMDGPU_PTE_READABLE (1 << 5)
909 #define AMDGPU_PTE_WRITEABLE (1 << 6)
911 /* PTE (Page Table Entry) fragment field for different page sizes */
912 #define AMDGPU_PTE_FRAG_4KB (0 << 7)
913 #define AMDGPU_PTE_FRAG_64KB (4 << 7)
914 #define AMDGPU_LOG2_PAGES_PER_FRAG 4
916 /* How to programm VM fault handling */
917 #define AMDGPU_VM_FAULT_STOP_NEVER 0
918 #define AMDGPU_VM_FAULT_STOP_FIRST 1
919 #define AMDGPU_VM_FAULT_STOP_ALWAYS 2
921 struct amdgpu_vm_pt {
922 struct amdgpu_bo_list_entry entry;
926 struct amdgpu_vm_id {
928 uint64_t pd_gpu_addr;
929 /* last flushed PD/PT update */
930 struct fence *flushed_updates;
936 /* protecting invalidated */
937 spinlock_t status_lock;
939 /* BOs moved, but not yet updated in the PT */
940 struct list_head invalidated;
942 /* BOs cleared in the PT because of a move */
943 struct list_head cleared;
945 /* BO mappings freed, but not yet updated in the PT */
946 struct list_head freed;
948 /* contains the page directory */
949 struct amdgpu_bo *page_directory;
950 unsigned max_pde_used;
951 struct fence *page_directory_fence;
953 /* array of page tables, one for each page directory entry */
954 struct amdgpu_vm_pt *page_tables;
956 /* for id and flush management per ring */
957 struct amdgpu_vm_id ids[AMDGPU_MAX_RINGS];
958 /* for interval tree */
960 /* protecting freed */
961 spinlock_t freed_lock;
964 struct amdgpu_vm_manager {
966 struct fence *active;
968 } ids[AMDGPU_NUM_VM];
971 /* number of VMIDs */
973 /* vram base address for page table entry */
974 u64 vram_base_offset;
977 /* vm pte handling */
978 const struct amdgpu_vm_pte_funcs *vm_pte_funcs;
979 struct amdgpu_ring *vm_pte_funcs_ring;
982 void amdgpu_vm_manager_fini(struct amdgpu_device *adev);
983 int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm);
984 void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm);
985 void amdgpu_vm_get_pd_bo(struct amdgpu_vm *vm,
986 struct list_head *validated,
987 struct amdgpu_bo_list_entry *entry);
988 void amdgpu_vm_get_pt_bos(struct amdgpu_vm *vm, struct list_head *duplicates);
989 int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring,
990 struct amdgpu_sync *sync);
991 void amdgpu_vm_flush(struct amdgpu_ring *ring,
992 struct amdgpu_vm *vm,
993 struct fence *updates);
994 void amdgpu_vm_fence(struct amdgpu_device *adev,
995 struct amdgpu_vm *vm,
996 struct fence *fence);
997 uint64_t amdgpu_vm_map_gart(struct amdgpu_device *adev, uint64_t addr);
998 int amdgpu_vm_update_page_directory(struct amdgpu_device *adev,
999 struct amdgpu_vm *vm);
1000 int amdgpu_vm_clear_freed(struct amdgpu_device *adev,
1001 struct amdgpu_vm *vm);
1002 int amdgpu_vm_clear_invalids(struct amdgpu_device *adev, struct amdgpu_vm *vm,
1003 struct amdgpu_sync *sync);
1004 int amdgpu_vm_bo_update(struct amdgpu_device *adev,
1005 struct amdgpu_bo_va *bo_va,
1006 struct ttm_mem_reg *mem);
1007 void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev,
1008 struct amdgpu_bo *bo);
1009 struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm,
1010 struct amdgpu_bo *bo);
1011 struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev,
1012 struct amdgpu_vm *vm,
1013 struct amdgpu_bo *bo);
1014 int amdgpu_vm_bo_map(struct amdgpu_device *adev,
1015 struct amdgpu_bo_va *bo_va,
1016 uint64_t addr, uint64_t offset,
1017 uint64_t size, uint32_t flags);
1018 int amdgpu_vm_bo_unmap(struct amdgpu_device *adev,
1019 struct amdgpu_bo_va *bo_va,
1021 void amdgpu_vm_bo_rmv(struct amdgpu_device *adev,
1022 struct amdgpu_bo_va *bo_va);
1023 int amdgpu_vm_free_job(struct amdgpu_job *job);
1026 * context related structures
1029 struct amdgpu_ctx_ring {
1031 struct fence **fences;
1032 struct amd_sched_entity entity;
1036 struct kref refcount;
1037 struct amdgpu_device *adev;
1038 unsigned reset_counter;
1039 spinlock_t ring_lock;
1040 struct fence **fences;
1041 struct amdgpu_ctx_ring rings[AMDGPU_MAX_RINGS];
1044 struct amdgpu_ctx_mgr {
1045 struct amdgpu_device *adev;
1047 /* protected by lock */
1048 struct idr ctx_handles;
1051 int amdgpu_ctx_init(struct amdgpu_device *adev, enum amd_sched_priority pri,
1052 struct amdgpu_ctx *ctx);
1053 void amdgpu_ctx_fini(struct amdgpu_ctx *ctx);
1055 struct amdgpu_ctx *amdgpu_ctx_get(struct amdgpu_fpriv *fpriv, uint32_t id);
1056 int amdgpu_ctx_put(struct amdgpu_ctx *ctx);
1058 uint64_t amdgpu_ctx_add_fence(struct amdgpu_ctx *ctx, struct amdgpu_ring *ring,
1059 struct fence *fence);
1060 struct fence *amdgpu_ctx_get_fence(struct amdgpu_ctx *ctx,
1061 struct amdgpu_ring *ring, uint64_t seq);
1063 int amdgpu_ctx_ioctl(struct drm_device *dev, void *data,
1064 struct drm_file *filp);
1066 void amdgpu_ctx_mgr_init(struct amdgpu_ctx_mgr *mgr);
1067 void amdgpu_ctx_mgr_fini(struct amdgpu_ctx_mgr *mgr);
1070 * file private structure
1073 struct amdgpu_fpriv {
1074 struct amdgpu_vm vm;
1075 struct mutex bo_list_lock;
1076 struct idr bo_list_handles;
1077 struct amdgpu_ctx_mgr ctx_mgr;
1084 struct amdgpu_bo_list {
1086 struct amdgpu_bo *gds_obj;
1087 struct amdgpu_bo *gws_obj;
1088 struct amdgpu_bo *oa_obj;
1090 unsigned num_entries;
1091 struct amdgpu_bo_list_entry *array;
1094 struct amdgpu_bo_list *
1095 amdgpu_bo_list_get(struct amdgpu_fpriv *fpriv, int id);
1096 void amdgpu_bo_list_put(struct amdgpu_bo_list *list);
1097 void amdgpu_bo_list_free(struct amdgpu_bo_list *list);
1102 #include "clearstate_defs.h"
1105 /* for power gating */
1106 struct amdgpu_bo *save_restore_obj;
1107 uint64_t save_restore_gpu_addr;
1108 volatile uint32_t *sr_ptr;
1109 const u32 *reg_list;
1111 /* for clear state */
1112 struct amdgpu_bo *clear_state_obj;
1113 uint64_t clear_state_gpu_addr;
1114 volatile uint32_t *cs_ptr;
1115 const struct cs_section_def *cs_data;
1116 u32 clear_state_size;
1118 struct amdgpu_bo *cp_table_obj;
1119 uint64_t cp_table_gpu_addr;
1120 volatile uint32_t *cp_table_ptr;
1125 struct amdgpu_bo *hpd_eop_obj;
1126 u64 hpd_eop_gpu_addr;
1133 * GPU scratch registers structures, functions & helpers
1135 struct amdgpu_scratch {
1143 * GFX configurations
1145 struct amdgpu_gca_config {
1146 unsigned max_shader_engines;
1147 unsigned max_tile_pipes;
1148 unsigned max_cu_per_sh;
1149 unsigned max_sh_per_se;
1150 unsigned max_backends_per_se;
1151 unsigned max_texture_channel_caches;
1153 unsigned max_gs_threads;
1154 unsigned max_hw_contexts;
1155 unsigned sc_prim_fifo_size_frontend;
1156 unsigned sc_prim_fifo_size_backend;
1157 unsigned sc_hiz_tile_fifo_size;
1158 unsigned sc_earlyz_tile_fifo_size;
1160 unsigned num_tile_pipes;
1161 unsigned backend_enable_mask;
1162 unsigned mem_max_burst_length_bytes;
1163 unsigned mem_row_size_in_kb;
1164 unsigned shader_engine_tile_size;
1166 unsigned multi_gpu_tile_size;
1167 unsigned mc_arb_ramcfg;
1168 unsigned gb_addr_config;
1170 uint32_t tile_mode_array[32];
1171 uint32_t macrotile_mode_array[16];
1175 struct mutex gpu_clock_mutex;
1176 struct amdgpu_gca_config config;
1177 struct amdgpu_rlc rlc;
1178 struct amdgpu_mec mec;
1179 struct amdgpu_scratch scratch;
1180 const struct firmware *me_fw; /* ME firmware */
1181 uint32_t me_fw_version;
1182 const struct firmware *pfp_fw; /* PFP firmware */
1183 uint32_t pfp_fw_version;
1184 const struct firmware *ce_fw; /* CE firmware */
1185 uint32_t ce_fw_version;
1186 const struct firmware *rlc_fw; /* RLC firmware */
1187 uint32_t rlc_fw_version;
1188 const struct firmware *mec_fw; /* MEC firmware */
1189 uint32_t mec_fw_version;
1190 const struct firmware *mec2_fw; /* MEC2 firmware */
1191 uint32_t mec2_fw_version;
1192 uint32_t me_feature_version;
1193 uint32_t ce_feature_version;
1194 uint32_t pfp_feature_version;
1195 uint32_t rlc_feature_version;
1196 uint32_t mec_feature_version;
1197 uint32_t mec2_feature_version;
1198 struct amdgpu_ring gfx_ring[AMDGPU_MAX_GFX_RINGS];
1199 unsigned num_gfx_rings;
1200 struct amdgpu_ring compute_ring[AMDGPU_MAX_COMPUTE_RINGS];
1201 unsigned num_compute_rings;
1202 struct amdgpu_irq_src eop_irq;
1203 struct amdgpu_irq_src priv_reg_irq;
1204 struct amdgpu_irq_src priv_inst_irq;
1206 uint32_t gfx_current_status;
1208 unsigned ce_ram_size;
1211 int amdgpu_ib_get(struct amdgpu_ring *ring, struct amdgpu_vm *vm,
1212 unsigned size, struct amdgpu_ib *ib);
1213 void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib);
1214 int amdgpu_ib_schedule(struct amdgpu_device *adev, unsigned num_ibs,
1215 struct amdgpu_ib *ib, void *owner);
1216 int amdgpu_ib_pool_init(struct amdgpu_device *adev);
1217 void amdgpu_ib_pool_fini(struct amdgpu_device *adev);
1218 int amdgpu_ib_ring_tests(struct amdgpu_device *adev);
1219 /* Ring access between begin & end cannot sleep */
1220 void amdgpu_ring_free_size(struct amdgpu_ring *ring);
1221 int amdgpu_ring_alloc(struct amdgpu_ring *ring, unsigned ndw);
1222 int amdgpu_ring_lock(struct amdgpu_ring *ring, unsigned ndw);
1223 void amdgpu_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count);
1224 void amdgpu_ring_commit(struct amdgpu_ring *ring);
1225 void amdgpu_ring_unlock_commit(struct amdgpu_ring *ring);
1226 void amdgpu_ring_undo(struct amdgpu_ring *ring);
1227 void amdgpu_ring_unlock_undo(struct amdgpu_ring *ring);
1228 unsigned amdgpu_ring_backup(struct amdgpu_ring *ring,
1230 int amdgpu_ring_restore(struct amdgpu_ring *ring,
1231 unsigned size, uint32_t *data);
1232 int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring,
1233 unsigned ring_size, u32 nop, u32 align_mask,
1234 struct amdgpu_irq_src *irq_src, unsigned irq_type,
1235 enum amdgpu_ring_type ring_type);
1236 void amdgpu_ring_fini(struct amdgpu_ring *ring);
1237 struct amdgpu_ring *amdgpu_ring_from_fence(struct fence *f);
1242 struct amdgpu_cs_chunk {
1246 void __user *user_ptr;
1249 struct amdgpu_cs_parser {
1250 struct amdgpu_device *adev;
1251 struct drm_file *filp;
1252 struct amdgpu_ctx *ctx;
1253 struct amdgpu_bo_list *bo_list;
1256 struct amdgpu_cs_chunk *chunks;
1258 struct amdgpu_bo_list_entry vm_pd;
1259 struct list_head validated;
1260 struct fence *fence;
1262 struct amdgpu_ib *ibs;
1265 struct ww_acquire_ctx ticket;
1268 struct amdgpu_user_fence uf;
1272 struct amd_sched_job base;
1273 struct amdgpu_device *adev;
1274 struct amdgpu_ib *ibs;
1277 struct amdgpu_user_fence uf;
1278 int (*free_job)(struct amdgpu_job *job);
1280 #define to_amdgpu_job(sched_job) \
1281 container_of((sched_job), struct amdgpu_job, base)
1283 static inline u32 amdgpu_get_ib_value(struct amdgpu_cs_parser *p, uint32_t ib_idx, int idx)
1285 return p->ibs[ib_idx].ptr[idx];
1291 #define AMDGPU_MAX_WB 1024 /* Reserve at most 1024 WB slots for amdgpu-owned rings. */
1294 struct amdgpu_bo *wb_obj;
1295 volatile uint32_t *wb;
1297 u32 num_wb; /* Number of wb slots actually reserved for amdgpu. */
1298 unsigned long used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)];
1301 int amdgpu_wb_get(struct amdgpu_device *adev, u32 *wb);
1302 void amdgpu_wb_free(struct amdgpu_device *adev, u32 wb);
1306 enum amdgpu_int_thermal_type {
1308 THERMAL_TYPE_EXTERNAL,
1309 THERMAL_TYPE_EXTERNAL_GPIO,
1312 THERMAL_TYPE_ADT7473_WITH_INTERNAL,
1313 THERMAL_TYPE_EVERGREEN,
1317 THERMAL_TYPE_EMC2103_WITH_INTERNAL,
1322 enum amdgpu_dpm_auto_throttle_src {
1323 AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL,
1324 AMDGPU_DPM_AUTO_THROTTLE_SRC_EXTERNAL
1327 enum amdgpu_dpm_event_src {
1328 AMDGPU_DPM_EVENT_SRC_ANALOG = 0,
1329 AMDGPU_DPM_EVENT_SRC_EXTERNAL = 1,
1330 AMDGPU_DPM_EVENT_SRC_DIGITAL = 2,
1331 AMDGPU_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3,
1332 AMDGPU_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4
1335 #define AMDGPU_MAX_VCE_LEVELS 6
1337 enum amdgpu_vce_level {
1338 AMDGPU_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */
1339 AMDGPU_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */
1340 AMDGPU_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */
1341 AMDGPU_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */
1342 AMDGPU_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */
1343 AMDGPU_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */
1347 u32 caps; /* vbios flags */
1348 u32 class; /* vbios flags */
1349 u32 class2; /* vbios flags */
1357 enum amdgpu_vce_level vce_level;
1362 struct amdgpu_dpm_thermal {
1363 /* thermal interrupt work */
1364 struct work_struct work;
1365 /* low temperature threshold */
1367 /* high temperature threshold */
1369 /* was last interrupt low to high or high to low */
1371 /* interrupt source */
1372 struct amdgpu_irq_src irq;
1375 enum amdgpu_clk_action
1381 struct amdgpu_blacklist_clocks
1385 enum amdgpu_clk_action action;
1388 struct amdgpu_clock_and_voltage_limits {
1395 struct amdgpu_clock_array {
1400 struct amdgpu_clock_voltage_dependency_entry {
1405 struct amdgpu_clock_voltage_dependency_table {
1407 struct amdgpu_clock_voltage_dependency_entry *entries;
1410 union amdgpu_cac_leakage_entry {
1422 struct amdgpu_cac_leakage_table {
1424 union amdgpu_cac_leakage_entry *entries;
1427 struct amdgpu_phase_shedding_limits_entry {
1433 struct amdgpu_phase_shedding_limits_table {
1435 struct amdgpu_phase_shedding_limits_entry *entries;
1438 struct amdgpu_uvd_clock_voltage_dependency_entry {
1444 struct amdgpu_uvd_clock_voltage_dependency_table {
1446 struct amdgpu_uvd_clock_voltage_dependency_entry *entries;
1449 struct amdgpu_vce_clock_voltage_dependency_entry {
1455 struct amdgpu_vce_clock_voltage_dependency_table {
1457 struct amdgpu_vce_clock_voltage_dependency_entry *entries;
1460 struct amdgpu_ppm_table {
1462 u16 cpu_core_number;
1464 u32 small_ac_platform_tdp;
1466 u32 small_ac_platform_tdc;
1473 struct amdgpu_cac_tdp_table {
1475 u16 configurable_tdp;
1477 u16 battery_power_limit;
1478 u16 small_power_limit;
1479 u16 low_cac_leakage;
1480 u16 high_cac_leakage;
1481 u16 maximum_power_delivery_limit;
1484 struct amdgpu_dpm_dynamic_state {
1485 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_sclk;
1486 struct amdgpu_clock_voltage_dependency_table vddci_dependency_on_mclk;
1487 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_mclk;
1488 struct amdgpu_clock_voltage_dependency_table mvdd_dependency_on_mclk;
1489 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_dispclk;
1490 struct amdgpu_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table;
1491 struct amdgpu_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table;
1492 struct amdgpu_clock_voltage_dependency_table samu_clock_voltage_dependency_table;
1493 struct amdgpu_clock_voltage_dependency_table acp_clock_voltage_dependency_table;
1494 struct amdgpu_clock_voltage_dependency_table vddgfx_dependency_on_sclk;
1495 struct amdgpu_clock_array valid_sclk_values;
1496 struct amdgpu_clock_array valid_mclk_values;
1497 struct amdgpu_clock_and_voltage_limits max_clock_voltage_on_dc;
1498 struct amdgpu_clock_and_voltage_limits max_clock_voltage_on_ac;
1499 u32 mclk_sclk_ratio;
1500 u32 sclk_mclk_delta;
1501 u16 vddc_vddci_delta;
1502 u16 min_vddc_for_pcie_gen2;
1503 struct amdgpu_cac_leakage_table cac_leakage_table;
1504 struct amdgpu_phase_shedding_limits_table phase_shedding_limits_table;
1505 struct amdgpu_ppm_table *ppm_table;
1506 struct amdgpu_cac_tdp_table *cac_tdp_table;
1509 struct amdgpu_dpm_fan {
1520 u16 default_max_fan_pwm;
1521 u16 default_fan_output_sensitivity;
1522 u16 fan_output_sensitivity;
1523 bool ucode_fan_control;
1526 enum amdgpu_pcie_gen {
1527 AMDGPU_PCIE_GEN1 = 0,
1528 AMDGPU_PCIE_GEN2 = 1,
1529 AMDGPU_PCIE_GEN3 = 2,
1530 AMDGPU_PCIE_GEN_INVALID = 0xffff
1533 enum amdgpu_dpm_forced_level {
1534 AMDGPU_DPM_FORCED_LEVEL_AUTO = 0,
1535 AMDGPU_DPM_FORCED_LEVEL_LOW = 1,
1536 AMDGPU_DPM_FORCED_LEVEL_HIGH = 2,
1539 struct amdgpu_vce_state {
1550 struct amdgpu_dpm_funcs {
1551 int (*get_temperature)(struct amdgpu_device *adev);
1552 int (*pre_set_power_state)(struct amdgpu_device *adev);
1553 int (*set_power_state)(struct amdgpu_device *adev);
1554 void (*post_set_power_state)(struct amdgpu_device *adev);
1555 void (*display_configuration_changed)(struct amdgpu_device *adev);
1556 u32 (*get_sclk)(struct amdgpu_device *adev, bool low);
1557 u32 (*get_mclk)(struct amdgpu_device *adev, bool low);
1558 void (*print_power_state)(struct amdgpu_device *adev, struct amdgpu_ps *ps);
1559 void (*debugfs_print_current_performance_level)(struct amdgpu_device *adev, struct seq_file *m);
1560 int (*force_performance_level)(struct amdgpu_device *adev, enum amdgpu_dpm_forced_level level);
1561 bool (*vblank_too_short)(struct amdgpu_device *adev);
1562 void (*powergate_uvd)(struct amdgpu_device *adev, bool gate);
1563 void (*powergate_vce)(struct amdgpu_device *adev, bool gate);
1564 void (*enable_bapm)(struct amdgpu_device *adev, bool enable);
1565 void (*set_fan_control_mode)(struct amdgpu_device *adev, u32 mode);
1566 u32 (*get_fan_control_mode)(struct amdgpu_device *adev);
1567 int (*set_fan_speed_percent)(struct amdgpu_device *adev, u32 speed);
1568 int (*get_fan_speed_percent)(struct amdgpu_device *adev, u32 *speed);
1572 struct amdgpu_ps *ps;
1573 /* number of valid power states */
1575 /* current power state that is active */
1576 struct amdgpu_ps *current_ps;
1577 /* requested power state */
1578 struct amdgpu_ps *requested_ps;
1579 /* boot up power state */
1580 struct amdgpu_ps *boot_ps;
1581 /* default uvd power state */
1582 struct amdgpu_ps *uvd_ps;
1583 /* vce requirements */
1584 struct amdgpu_vce_state vce_states[AMDGPU_MAX_VCE_LEVELS];
1585 enum amdgpu_vce_level vce_level;
1586 enum amd_pm_state_type state;
1587 enum amd_pm_state_type user_state;
1589 u32 voltage_response_time;
1590 u32 backbias_response_time;
1592 u32 new_active_crtcs;
1593 int new_active_crtc_count;
1594 u32 current_active_crtcs;
1595 int current_active_crtc_count;
1596 struct amdgpu_dpm_dynamic_state dyn_state;
1597 struct amdgpu_dpm_fan fan;
1600 u32 near_tdp_limit_adjusted;
1601 u32 sq_ramping_threshold;
1605 u16 load_line_slope;
1608 /* special states active */
1609 bool thermal_active;
1612 /* thermal handling */
1613 struct amdgpu_dpm_thermal thermal;
1615 enum amdgpu_dpm_forced_level forced_level;
1624 struct amdgpu_i2c_chan *i2c_bus;
1625 /* internal thermal controller on rv6xx+ */
1626 enum amdgpu_int_thermal_type int_thermal_type;
1627 struct device *int_hwmon_dev;
1628 /* fan control parameters */
1630 u8 fan_pulses_per_revolution;
1635 bool sysfs_initialized;
1636 struct amdgpu_dpm dpm;
1637 const struct firmware *fw; /* SMC firmware */
1638 uint32_t fw_version;
1639 const struct amdgpu_dpm_funcs *funcs;
1645 #define AMDGPU_MAX_UVD_HANDLES 10
1646 #define AMDGPU_UVD_STACK_SIZE (1024*1024)
1647 #define AMDGPU_UVD_HEAP_SIZE (1024*1024)
1648 #define AMDGPU_UVD_FIRMWARE_OFFSET 256
1651 struct amdgpu_bo *vcpu_bo;
1654 atomic_t handles[AMDGPU_MAX_UVD_HANDLES];
1655 struct drm_file *filp[AMDGPU_MAX_UVD_HANDLES];
1656 struct delayed_work idle_work;
1657 const struct firmware *fw; /* UVD firmware */
1658 struct amdgpu_ring ring;
1659 struct amdgpu_irq_src irq;
1660 bool address_64_bit;
1666 #define AMDGPU_MAX_VCE_HANDLES 16
1667 #define AMDGPU_VCE_FIRMWARE_OFFSET 256
1669 #define AMDGPU_VCE_HARVEST_VCE0 (1 << 0)
1670 #define AMDGPU_VCE_HARVEST_VCE1 (1 << 1)
1673 struct amdgpu_bo *vcpu_bo;
1675 unsigned fw_version;
1676 unsigned fb_version;
1677 atomic_t handles[AMDGPU_MAX_VCE_HANDLES];
1678 struct drm_file *filp[AMDGPU_MAX_VCE_HANDLES];
1679 uint32_t img_size[AMDGPU_MAX_VCE_HANDLES];
1680 struct delayed_work idle_work;
1681 const struct firmware *fw; /* VCE firmware */
1682 struct amdgpu_ring ring[AMDGPU_MAX_VCE_RINGS];
1683 struct amdgpu_irq_src irq;
1684 unsigned harvest_config;
1690 struct amdgpu_sdma_instance {
1692 const struct firmware *fw;
1693 uint32_t fw_version;
1694 uint32_t feature_version;
1696 struct amdgpu_ring ring;
1700 struct amdgpu_sdma {
1701 struct amdgpu_sdma_instance instance[AMDGPU_MAX_SDMA_INSTANCES];
1702 struct amdgpu_irq_src trap_irq;
1703 struct amdgpu_irq_src illegal_inst_irq;
1710 struct amdgpu_firmware {
1711 struct amdgpu_firmware_info ucode[AMDGPU_UCODE_ID_MAXIMUM];
1713 struct amdgpu_bo *fw_buf;
1714 unsigned int fw_size;
1720 void amdgpu_benchmark(struct amdgpu_device *adev, int test_number);
1726 void amdgpu_test_moves(struct amdgpu_device *adev);
1727 void amdgpu_test_ring_sync(struct amdgpu_device *adev,
1728 struct amdgpu_ring *cpA,
1729 struct amdgpu_ring *cpB);
1730 void amdgpu_test_syncing(struct amdgpu_device *adev);
1735 #if defined(CONFIG_MMU_NOTIFIER)
1736 int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr);
1737 void amdgpu_mn_unregister(struct amdgpu_bo *bo);
1739 static inline int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr)
1743 static inline void amdgpu_mn_unregister(struct amdgpu_bo *bo) {}
1749 struct amdgpu_debugfs {
1750 struct drm_info_list *files;
1754 int amdgpu_debugfs_add_files(struct amdgpu_device *adev,
1755 struct drm_info_list *files,
1757 int amdgpu_debugfs_fence_init(struct amdgpu_device *adev);
1759 #if defined(CONFIG_DEBUG_FS)
1760 int amdgpu_debugfs_init(struct drm_minor *minor);
1761 void amdgpu_debugfs_cleanup(struct drm_minor *minor);
1765 * amdgpu smumgr functions
1767 struct amdgpu_smumgr_funcs {
1768 int (*check_fw_load_finish)(struct amdgpu_device *adev, uint32_t fwtype);
1769 int (*request_smu_load_fw)(struct amdgpu_device *adev);
1770 int (*request_smu_specific_fw)(struct amdgpu_device *adev, uint32_t fwtype);
1776 struct amdgpu_smumgr {
1777 struct amdgpu_bo *toc_buf;
1778 struct amdgpu_bo *smu_buf;
1779 /* asic priv smu data */
1781 spinlock_t smu_lock;
1782 /* smumgr functions */
1783 const struct amdgpu_smumgr_funcs *smumgr_funcs;
1784 /* ucode loading complete flag */
1789 * ASIC specific register table accessible by UMD
1791 struct amdgpu_allowed_register_entry {
1792 uint32_t reg_offset;
1797 struct amdgpu_cu_info {
1798 uint32_t number; /* total active CU number */
1799 uint32_t ao_cu_mask;
1800 uint32_t bitmap[4][4];
1805 * ASIC specific functions.
1807 struct amdgpu_asic_funcs {
1808 bool (*read_disabled_bios)(struct amdgpu_device *adev);
1809 bool (*read_bios_from_rom)(struct amdgpu_device *adev,
1810 u8 *bios, u32 length_bytes);
1811 int (*read_register)(struct amdgpu_device *adev, u32 se_num,
1812 u32 sh_num, u32 reg_offset, u32 *value);
1813 void (*set_vga_state)(struct amdgpu_device *adev, bool state);
1814 int (*reset)(struct amdgpu_device *adev);
1815 /* wait for mc_idle */
1816 int (*wait_for_mc_idle)(struct amdgpu_device *adev);
1817 /* get the reference clock */
1818 u32 (*get_xclk)(struct amdgpu_device *adev);
1819 /* get the gpu clock counter */
1820 uint64_t (*get_gpu_clock_counter)(struct amdgpu_device *adev);
1821 int (*get_cu_info)(struct amdgpu_device *adev, struct amdgpu_cu_info *info);
1822 /* MM block clocks */
1823 int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk);
1824 int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk);
1830 int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data,
1831 struct drm_file *filp);
1832 int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data,
1833 struct drm_file *filp);
1835 int amdgpu_gem_info_ioctl(struct drm_device *dev, void *data,
1836 struct drm_file *filp);
1837 int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data,
1838 struct drm_file *filp);
1839 int amdgpu_gem_mmap_ioctl(struct drm_device *dev, void *data,
1840 struct drm_file *filp);
1841 int amdgpu_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
1842 struct drm_file *filp);
1843 int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
1844 struct drm_file *filp);
1845 int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data,
1846 struct drm_file *filp);
1847 int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
1848 int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
1850 int amdgpu_gem_metadata_ioctl(struct drm_device *dev, void *data,
1851 struct drm_file *filp);
1853 /* VRAM scratch page for HDP bug, default vram page */
1854 struct amdgpu_vram_scratch {
1855 struct amdgpu_bo *robj;
1856 volatile uint32_t *ptr;
1863 struct amdgpu_atif_notification_cfg {
1868 struct amdgpu_atif_notifications {
1869 bool display_switch;
1870 bool expansion_mode_change;
1872 bool forced_power_state;
1873 bool system_power_state;
1874 bool display_conf_change;
1876 bool brightness_change;
1877 bool dgpu_display_event;
1880 struct amdgpu_atif_functions {
1882 bool sbios_requests;
1883 bool select_active_disp;
1885 bool get_tv_standard;
1886 bool set_tv_standard;
1887 bool get_panel_expansion_mode;
1888 bool set_panel_expansion_mode;
1889 bool temperature_change;
1890 bool graphics_device_types;
1893 struct amdgpu_atif {
1894 struct amdgpu_atif_notifications notifications;
1895 struct amdgpu_atif_functions functions;
1896 struct amdgpu_atif_notification_cfg notification_cfg;
1897 struct amdgpu_encoder *encoder_for_bl;
1900 struct amdgpu_atcs_functions {
1904 bool pcie_bus_width;
1907 struct amdgpu_atcs {
1908 struct amdgpu_atcs_functions functions;
1914 void *amdgpu_cgs_create_device(struct amdgpu_device *adev);
1915 void amdgpu_cgs_destroy_device(void *cgs_device);
1919 * Core structure, functions and helpers.
1921 typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t);
1922 typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
1924 typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
1925 typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t);
1927 struct amdgpu_ip_block_status {
1933 struct amdgpu_device {
1935 struct drm_device *ddev;
1936 struct pci_dev *pdev;
1939 enum amd_asic_type asic_type;
1942 uint32_t external_rev_id;
1943 unsigned long flags;
1945 const struct amdgpu_asic_funcs *asic_funcs;
1950 struct work_struct reset_work;
1951 struct notifier_block acpi_nb;
1952 struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS];
1953 struct amdgpu_debugfs debugfs[AMDGPU_DEBUGFS_MAX_COMPONENTS];
1954 unsigned debugfs_count;
1955 #if defined(CONFIG_DEBUG_FS)
1956 struct dentry *debugfs_regs;
1958 struct amdgpu_atif atif;
1959 struct amdgpu_atcs atcs;
1960 struct mutex srbm_mutex;
1961 /* GRBM index mutex. Protects concurrent access to GRBM index */
1962 struct mutex grbm_idx_mutex;
1963 struct dev_pm_domain vga_pm_domain;
1964 bool have_disp_power_ref;
1969 uint16_t bios_header_start;
1970 struct amdgpu_bo *stollen_vga_memory;
1971 uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH];
1973 /* Register/doorbell mmio */
1974 resource_size_t rmmio_base;
1975 resource_size_t rmmio_size;
1976 void __iomem *rmmio;
1977 /* protects concurrent MM_INDEX/DATA based register access */
1978 spinlock_t mmio_idx_lock;
1979 /* protects concurrent SMC based register access */
1980 spinlock_t smc_idx_lock;
1981 amdgpu_rreg_t smc_rreg;
1982 amdgpu_wreg_t smc_wreg;
1983 /* protects concurrent PCIE register access */
1984 spinlock_t pcie_idx_lock;
1985 amdgpu_rreg_t pcie_rreg;
1986 amdgpu_wreg_t pcie_wreg;
1987 /* protects concurrent UVD register access */
1988 spinlock_t uvd_ctx_idx_lock;
1989 amdgpu_rreg_t uvd_ctx_rreg;
1990 amdgpu_wreg_t uvd_ctx_wreg;
1991 /* protects concurrent DIDT register access */
1992 spinlock_t didt_idx_lock;
1993 amdgpu_rreg_t didt_rreg;
1994 amdgpu_wreg_t didt_wreg;
1995 /* protects concurrent ENDPOINT (audio) register access */
1996 spinlock_t audio_endpt_idx_lock;
1997 amdgpu_block_rreg_t audio_endpt_rreg;
1998 amdgpu_block_wreg_t audio_endpt_wreg;
1999 void __iomem *rio_mem;
2000 resource_size_t rio_mem_size;
2001 struct amdgpu_doorbell doorbell;
2003 /* clock/pll info */
2004 struct amdgpu_clock clock;
2007 struct amdgpu_mc mc;
2008 struct amdgpu_gart gart;
2009 struct amdgpu_dummy_page dummy_page;
2010 struct amdgpu_vm_manager vm_manager;
2012 /* memory management */
2013 struct amdgpu_mman mman;
2014 struct amdgpu_gem gem;
2015 struct amdgpu_vram_scratch vram_scratch;
2016 struct amdgpu_wb wb;
2017 atomic64_t vram_usage;
2018 atomic64_t vram_vis_usage;
2019 atomic64_t gtt_usage;
2020 atomic64_t num_bytes_moved;
2021 atomic_t gpu_reset_counter;
2024 struct amdgpu_mode_info mode_info;
2025 struct work_struct hotplug_work;
2026 struct amdgpu_irq_src crtc_irq;
2027 struct amdgpu_irq_src pageflip_irq;
2028 struct amdgpu_irq_src hpd_irq;
2031 unsigned fence_context;
2032 struct mutex ring_lock;
2034 struct amdgpu_ring *rings[AMDGPU_MAX_RINGS];
2036 struct amdgpu_sa_manager ring_tmp_bo;
2039 struct amdgpu_irq irq;
2042 struct amd_powerplay powerplay;
2045 struct amdgpu_pm pm;
2050 struct amdgpu_smumgr smu;
2053 struct amdgpu_gfx gfx;
2056 struct amdgpu_sdma sdma;
2060 struct amdgpu_uvd uvd;
2063 struct amdgpu_vce vce;
2066 struct amdgpu_firmware firmware;
2069 struct amdgpu_gds gds;
2071 const struct amdgpu_ip_block_version *ip_blocks;
2073 struct amdgpu_ip_block_status *ip_block_status;
2074 struct mutex mn_lock;
2075 DECLARE_HASHTABLE(mn_hash, 7);
2077 /* tracking pinned memory */
2081 /* amdkfd interface */
2082 struct kfd_dev *kfd;
2084 /* kernel conext for IB submission */
2085 struct amdgpu_ctx kernel_ctx;
2088 bool amdgpu_device_is_px(struct drm_device *dev);
2089 int amdgpu_device_init(struct amdgpu_device *adev,
2090 struct drm_device *ddev,
2091 struct pci_dev *pdev,
2093 void amdgpu_device_fini(struct amdgpu_device *adev);
2094 int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev);
2096 uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg,
2097 bool always_indirect);
2098 void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v,
2099 bool always_indirect);
2100 u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg);
2101 void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v);
2103 u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index);
2104 void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v);
2109 extern const struct fence_ops amdgpu_fence_ops;
2110 static inline struct amdgpu_fence *to_amdgpu_fence(struct fence *f)
2112 struct amdgpu_fence *__f = container_of(f, struct amdgpu_fence, base);
2114 if (__f->base.ops == &amdgpu_fence_ops)
2121 * Registers read & write functions.
2123 #define RREG32(reg) amdgpu_mm_rreg(adev, (reg), false)
2124 #define RREG32_IDX(reg) amdgpu_mm_rreg(adev, (reg), true)
2125 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_mm_rreg(adev, (reg), false))
2126 #define WREG32(reg, v) amdgpu_mm_wreg(adev, (reg), (v), false)
2127 #define WREG32_IDX(reg, v) amdgpu_mm_wreg(adev, (reg), (v), true)
2128 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2129 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2130 #define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg))
2131 #define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v))
2132 #define RREG32_SMC(reg) adev->smc_rreg(adev, (reg))
2133 #define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v))
2134 #define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg))
2135 #define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v))
2136 #define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg))
2137 #define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v))
2138 #define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg))
2139 #define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v))
2140 #define WREG32_P(reg, val, mask) \
2142 uint32_t tmp_ = RREG32(reg); \
2144 tmp_ |= ((val) & ~(mask)); \
2145 WREG32(reg, tmp_); \
2147 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
2148 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))
2149 #define WREG32_PLL_P(reg, val, mask) \
2151 uint32_t tmp_ = RREG32_PLL(reg); \
2153 tmp_ |= ((val) & ~(mask)); \
2154 WREG32_PLL(reg, tmp_); \
2156 #define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_mm_rreg((adev), (reg), false))
2157 #define RREG32_IO(reg) amdgpu_io_rreg(adev, (reg))
2158 #define WREG32_IO(reg, v) amdgpu_io_wreg(adev, (reg), (v))
2160 #define RDOORBELL32(index) amdgpu_mm_rdoorbell(adev, (index))
2161 #define WDOORBELL32(index, v) amdgpu_mm_wdoorbell(adev, (index), (v))
2163 #define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT
2164 #define REG_FIELD_MASK(reg, field) reg##__##field##_MASK
2166 #define REG_SET_FIELD(orig_val, reg, field, field_val) \
2167 (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \
2168 (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field))))
2170 #define REG_GET_FIELD(value, reg, field) \
2171 (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field))
2176 #define RBIOS8(i) (adev->bios[i])
2177 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
2178 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
2183 static inline void amdgpu_ring_write(struct amdgpu_ring *ring, uint32_t v)
2185 if (ring->count_dw <= 0)
2186 DRM_ERROR("amdgpu: writing more dwords to the ring than expected!\n");
2187 ring->ring[ring->wptr++] = v;
2188 ring->wptr &= ring->ptr_mask;
2190 ring->ring_free_dw--;
2193 static inline struct amdgpu_sdma_instance *
2194 amdgpu_get_sdma_instance(struct amdgpu_ring *ring)
2196 struct amdgpu_device *adev = ring->adev;
2199 for (i = 0; i < adev->sdma.num_instances; i++)
2200 if (&adev->sdma.instance[i].ring == ring)
2203 if (i < AMDGPU_MAX_SDMA_INSTANCES)
2204 return &adev->sdma.instance[i];
2212 #define amdgpu_asic_set_vga_state(adev, state) (adev)->asic_funcs->set_vga_state((adev), (state))
2213 #define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev))
2214 #define amdgpu_asic_wait_for_mc_idle(adev) (adev)->asic_funcs->wait_for_mc_idle((adev))
2215 #define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev))
2216 #define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d))
2217 #define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec))
2218 #define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev))
2219 #define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev))
2220 #define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l))
2221 #define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v)))
2222 #define amdgpu_asic_get_cu_info(adev, info) (adev)->asic_funcs->get_cu_info((adev), (info))
2223 #define amdgpu_gart_flush_gpu_tlb(adev, vmid) (adev)->gart.gart_funcs->flush_gpu_tlb((adev), (vmid))
2224 #define amdgpu_gart_set_pte_pde(adev, pt, idx, addr, flags) (adev)->gart.gart_funcs->set_pte_pde((adev), (pt), (idx), (addr), (flags))
2225 #define amdgpu_vm_copy_pte(adev, ib, pe, src, count) ((adev)->vm_manager.vm_pte_funcs->copy_pte((ib), (pe), (src), (count)))
2226 #define amdgpu_vm_write_pte(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->write_pte((ib), (pe), (addr), (count), (incr), (flags)))
2227 #define amdgpu_vm_set_pte_pde(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->set_pte_pde((ib), (pe), (addr), (count), (incr), (flags)))
2228 #define amdgpu_vm_pad_ib(adev, ib) ((adev)->vm_manager.vm_pte_funcs->pad_ib((ib)))
2229 #define amdgpu_ring_parse_cs(r, p, ib) ((r)->funcs->parse_cs((p), (ib)))
2230 #define amdgpu_ring_test_ring(r) (r)->funcs->test_ring((r))
2231 #define amdgpu_ring_test_ib(r) (r)->funcs->test_ib((r))
2232 #define amdgpu_ring_get_rptr(r) (r)->funcs->get_rptr((r))
2233 #define amdgpu_ring_get_wptr(r) (r)->funcs->get_wptr((r))
2234 #define amdgpu_ring_set_wptr(r) (r)->funcs->set_wptr((r))
2235 #define amdgpu_ring_emit_ib(r, ib) (r)->funcs->emit_ib((r), (ib))
2236 #define amdgpu_ring_emit_vm_flush(r, vmid, addr) (r)->funcs->emit_vm_flush((r), (vmid), (addr))
2237 #define amdgpu_ring_emit_fence(r, addr, seq, flags) (r)->funcs->emit_fence((r), (addr), (seq), (flags))
2238 #define amdgpu_ring_emit_semaphore(r, semaphore, emit_wait) (r)->funcs->emit_semaphore((r), (semaphore), (emit_wait))
2239 #define amdgpu_ring_emit_gds_switch(r, v, db, ds, wb, ws, ab, as) (r)->funcs->emit_gds_switch((r), (v), (db), (ds), (wb), (ws), (ab), (as))
2240 #define amdgpu_ring_emit_hdp_flush(r) (r)->funcs->emit_hdp_flush((r))
2241 #define amdgpu_ih_get_wptr(adev) (adev)->irq.ih_funcs->get_wptr((adev))
2242 #define amdgpu_ih_decode_iv(adev, iv) (adev)->irq.ih_funcs->decode_iv((adev), (iv))
2243 #define amdgpu_ih_set_rptr(adev) (adev)->irq.ih_funcs->set_rptr((adev))
2244 #define amdgpu_display_set_vga_render_state(adev, r) (adev)->mode_info.funcs->set_vga_render_state((adev), (r))
2245 #define amdgpu_display_vblank_get_counter(adev, crtc) (adev)->mode_info.funcs->vblank_get_counter((adev), (crtc))
2246 #define amdgpu_display_vblank_wait(adev, crtc) (adev)->mode_info.funcs->vblank_wait((adev), (crtc))
2247 #define amdgpu_display_is_display_hung(adev) (adev)->mode_info.funcs->is_display_hung((adev))
2248 #define amdgpu_display_backlight_set_level(adev, e, l) (adev)->mode_info.funcs->backlight_set_level((e), (l))
2249 #define amdgpu_display_backlight_get_level(adev, e) (adev)->mode_info.funcs->backlight_get_level((e))
2250 #define amdgpu_display_hpd_sense(adev, h) (adev)->mode_info.funcs->hpd_sense((adev), (h))
2251 #define amdgpu_display_hpd_set_polarity(adev, h) (adev)->mode_info.funcs->hpd_set_polarity((adev), (h))
2252 #define amdgpu_display_hpd_get_gpio_reg(adev) (adev)->mode_info.funcs->hpd_get_gpio_reg((adev))
2253 #define amdgpu_display_bandwidth_update(adev) (adev)->mode_info.funcs->bandwidth_update((adev))
2254 #define amdgpu_display_page_flip(adev, crtc, base) (adev)->mode_info.funcs->page_flip((adev), (crtc), (base))
2255 #define amdgpu_display_page_flip_get_scanoutpos(adev, crtc, vbl, pos) (adev)->mode_info.funcs->page_flip_get_scanoutpos((adev), (crtc), (vbl), (pos))
2256 #define amdgpu_display_add_encoder(adev, e, s, c) (adev)->mode_info.funcs->add_encoder((adev), (e), (s), (c))
2257 #define amdgpu_display_add_connector(adev, ci, sd, ct, ib, coi, h, r) (adev)->mode_info.funcs->add_connector((adev), (ci), (sd), (ct), (ib), (coi), (h), (r))
2258 #define amdgpu_display_stop_mc_access(adev, s) (adev)->mode_info.funcs->stop_mc_access((adev), (s))
2259 #define amdgpu_display_resume_mc_access(adev, s) (adev)->mode_info.funcs->resume_mc_access((adev), (s))
2260 #define amdgpu_emit_copy_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_copy_buffer((ib), (s), (d), (b))
2261 #define amdgpu_emit_fill_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_fill_buffer((ib), (s), (d), (b))
2262 #define amdgpu_dpm_get_temperature(adev) (adev)->pm.funcs->get_temperature((adev))
2263 #define amdgpu_dpm_pre_set_power_state(adev) (adev)->pm.funcs->pre_set_power_state((adev))
2264 #define amdgpu_dpm_set_power_state(adev) (adev)->pm.funcs->set_power_state((adev))
2265 #define amdgpu_dpm_post_set_power_state(adev) (adev)->pm.funcs->post_set_power_state((adev))
2266 #define amdgpu_dpm_display_configuration_changed(adev) (adev)->pm.funcs->display_configuration_changed((adev))
2267 #define amdgpu_dpm_get_sclk(adev, l) (adev)->pm.funcs->get_sclk((adev), (l))
2268 #define amdgpu_dpm_get_mclk(adev, l) (adev)->pm.funcs->get_mclk((adev), (l))
2269 #define amdgpu_dpm_print_power_state(adev, ps) (adev)->pm.funcs->print_power_state((adev), (ps))
2270 #define amdgpu_dpm_debugfs_print_current_performance_level(adev, m) (adev)->pm.funcs->debugfs_print_current_performance_level((adev), (m))
2271 #define amdgpu_dpm_force_performance_level(adev, l) (adev)->pm.funcs->force_performance_level((adev), (l))
2272 #define amdgpu_dpm_vblank_too_short(adev) (adev)->pm.funcs->vblank_too_short((adev))
2273 #define amdgpu_dpm_powergate_uvd(adev, g) (adev)->pm.funcs->powergate_uvd((adev), (g))
2274 #define amdgpu_dpm_powergate_vce(adev, g) (adev)->pm.funcs->powergate_vce((adev), (g))
2275 #define amdgpu_dpm_enable_bapm(adev, e) (adev)->pm.funcs->enable_bapm((adev), (e))
2276 #define amdgpu_dpm_set_fan_control_mode(adev, m) (adev)->pm.funcs->set_fan_control_mode((adev), (m))
2277 #define amdgpu_dpm_get_fan_control_mode(adev) (adev)->pm.funcs->get_fan_control_mode((adev))
2278 #define amdgpu_dpm_set_fan_speed_percent(adev, s) (adev)->pm.funcs->set_fan_speed_percent((adev), (s))
2279 #define amdgpu_dpm_get_fan_speed_percent(adev, s) (adev)->pm.funcs->get_fan_speed_percent((adev), (s))
2281 #define amdgpu_gds_switch(adev, r, v, d, w, a) (adev)->gds.funcs->patch_gds_switch((r), (v), (d), (w), (a))
2283 /* Common functions */
2284 int amdgpu_gpu_reset(struct amdgpu_device *adev);
2285 void amdgpu_pci_config_reset(struct amdgpu_device *adev);
2286 bool amdgpu_card_posted(struct amdgpu_device *adev);
2287 void amdgpu_update_display_priority(struct amdgpu_device *adev);
2288 bool amdgpu_boot_test_post_card(struct amdgpu_device *adev);
2290 int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, void *data);
2291 int amdgpu_cs_get_ring(struct amdgpu_device *adev, u32 ip_type,
2292 u32 ip_instance, u32 ring,
2293 struct amdgpu_ring **out_ring);
2294 void amdgpu_ttm_placement_from_domain(struct amdgpu_bo *rbo, u32 domain);
2295 bool amdgpu_ttm_bo_is_amdgpu_bo(struct ttm_buffer_object *bo);
2296 int amdgpu_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr,
2298 bool amdgpu_ttm_tt_has_userptr(struct ttm_tt *ttm);
2299 bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm);
2300 uint32_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm,
2301 struct ttm_mem_reg *mem);
2302 void amdgpu_vram_location(struct amdgpu_device *adev, struct amdgpu_mc *mc, u64 base);
2303 void amdgpu_gtt_location(struct amdgpu_device *adev, struct amdgpu_mc *mc);
2304 void amdgpu_ttm_set_active_vram_size(struct amdgpu_device *adev, u64 size);
2305 void amdgpu_program_register_sequence(struct amdgpu_device *adev,
2306 const u32 *registers,
2307 const u32 array_size);
2309 bool amdgpu_device_is_px(struct drm_device *dev);
2311 #if defined(CONFIG_VGA_SWITCHEROO)
2312 void amdgpu_register_atpx_handler(void);
2313 void amdgpu_unregister_atpx_handler(void);
2315 static inline void amdgpu_register_atpx_handler(void) {}
2316 static inline void amdgpu_unregister_atpx_handler(void) {}
2322 extern const struct drm_ioctl_desc amdgpu_ioctls_kms[];
2323 extern int amdgpu_max_kms_ioctl;
2325 int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags);
2326 int amdgpu_driver_unload_kms(struct drm_device *dev);
2327 void amdgpu_driver_lastclose_kms(struct drm_device *dev);
2328 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv);
2329 void amdgpu_driver_postclose_kms(struct drm_device *dev,
2330 struct drm_file *file_priv);
2331 void amdgpu_driver_preclose_kms(struct drm_device *dev,
2332 struct drm_file *file_priv);
2333 int amdgpu_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon);
2334 int amdgpu_resume_kms(struct drm_device *dev, bool resume, bool fbcon);
2335 u32 amdgpu_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe);
2336 int amdgpu_enable_vblank_kms(struct drm_device *dev, unsigned int pipe);
2337 void amdgpu_disable_vblank_kms(struct drm_device *dev, unsigned int pipe);
2338 int amdgpu_get_vblank_timestamp_kms(struct drm_device *dev, unsigned int pipe,
2340 struct timeval *vblank_time,
2342 long amdgpu_kms_compat_ioctl(struct file *filp, unsigned int cmd,
2346 * functions used by amdgpu_encoder.c
2348 struct amdgpu_afmt_acr {
2362 struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock);
2365 #if defined(CONFIG_ACPI)
2366 int amdgpu_acpi_init(struct amdgpu_device *adev);
2367 void amdgpu_acpi_fini(struct amdgpu_device *adev);
2368 bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev);
2369 int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev,
2370 u8 perf_req, bool advertise);
2371 int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev);
2373 static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; }
2374 static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { }
2377 struct amdgpu_bo_va_mapping *
2378 amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser,
2379 uint64_t addr, struct amdgpu_bo **bo);
2381 #include "amdgpu_object.h"