1 // SPDX-License-Identifier: GPL-2.0-only
3 * Xilinx gpio driver for xps/axi_gpio IP.
5 * Copyright 2008 - 2013 Xilinx, Inc.
8 #include <linux/bitmap.h>
9 #include <linux/bitops.h>
10 #include <linux/clk.h>
11 #include <linux/errno.h>
12 #include <linux/gpio/driver.h>
13 #include <linux/init.h>
14 #include <linux/interrupt.h>
16 #include <linux/irq.h>
17 #include <linux/module.h>
18 #include <linux/of_device.h>
19 #include <linux/of_platform.h>
20 #include <linux/pm_runtime.h>
21 #include <linux/slab.h>
23 /* Register Offset Definitions */
24 #define XGPIO_DATA_OFFSET (0x0) /* Data register */
25 #define XGPIO_TRI_OFFSET (0x4) /* I/O direction register */
27 #define XGPIO_CHANNEL0_OFFSET 0x0
28 #define XGPIO_CHANNEL1_OFFSET 0x8
30 #define XGPIO_GIER_OFFSET 0x11c /* Global Interrupt Enable */
31 #define XGPIO_GIER_IE BIT(31)
32 #define XGPIO_IPISR_OFFSET 0x120 /* IP Interrupt Status */
33 #define XGPIO_IPIER_OFFSET 0x128 /* IP Interrupt Enable */
35 /* Read/Write access to the GPIO registers */
36 #if defined(CONFIG_ARCH_ZYNQ) || defined(CONFIG_X86)
37 # define xgpio_readreg(offset) readl(offset)
38 # define xgpio_writereg(offset, val) writel(val, offset)
40 # define xgpio_readreg(offset) __raw_readl(offset)
41 # define xgpio_writereg(offset, val) __raw_writel(val, offset)
45 * struct xgpio_instance - Stores information about GPIO device
47 * @regs: register block
48 * @hw_map: GPIO pin mapping on hardware side
49 * @sw_map: GPIO pin mapping on software side
50 * @state: GPIO write state shadow register
51 * @last_irq_read: GPIO read state register from last interrupt
52 * @dir: GPIO direction shadow register
53 * @gpio_lock: Lock used for synchronization
54 * @irq: IRQ used by GPIO device
56 * @enable: GPIO IRQ enable/disable bitfield
57 * @rising_edge: GPIO IRQ rising edge enable/disable bitfield
58 * @falling_edge: GPIO IRQ falling edge enable/disable bitfield
59 * @clk: clock resource for this driver
61 struct xgpio_instance {
64 DECLARE_BITMAP(hw_map, 64);
65 DECLARE_BITMAP(sw_map, 64);
66 DECLARE_BITMAP(state, 64);
67 DECLARE_BITMAP(last_irq_read, 64);
68 DECLARE_BITMAP(dir, 64);
69 spinlock_t gpio_lock; /* For serializing operations */
71 struct irq_chip irqchip;
72 DECLARE_BITMAP(enable, 64);
73 DECLARE_BITMAP(rising_edge, 64);
74 DECLARE_BITMAP(falling_edge, 64);
78 static inline int xgpio_from_bit(struct xgpio_instance *chip, int bit)
80 return bitmap_bitremap(bit, chip->hw_map, chip->sw_map, 64);
83 static inline int xgpio_to_bit(struct xgpio_instance *chip, int gpio)
85 return bitmap_bitremap(gpio, chip->sw_map, chip->hw_map, 64);
88 static inline u32 xgpio_get_value32(const unsigned long *map, int bit)
90 const size_t index = BIT_WORD(bit);
91 const unsigned long offset = (bit % BITS_PER_LONG) & BIT(5);
93 return (map[index] >> offset) & 0xFFFFFFFFul;
96 static inline void xgpio_set_value32(unsigned long *map, int bit, u32 v)
98 const size_t index = BIT_WORD(bit);
99 const unsigned long offset = (bit % BITS_PER_LONG) & BIT(5);
101 map[index] &= ~(0xFFFFFFFFul << offset);
102 map[index] |= (unsigned long)v << offset;
105 static inline int xgpio_regoffset(struct xgpio_instance *chip, int ch)
109 return XGPIO_CHANNEL0_OFFSET;
111 return XGPIO_CHANNEL1_OFFSET;
117 static void xgpio_read_ch(struct xgpio_instance *chip, int reg, int bit, unsigned long *a)
119 void __iomem *addr = chip->regs + reg + xgpio_regoffset(chip, bit / 32);
121 xgpio_set_value32(a, bit, xgpio_readreg(addr));
124 static void xgpio_write_ch(struct xgpio_instance *chip, int reg, int bit, unsigned long *a)
126 void __iomem *addr = chip->regs + reg + xgpio_regoffset(chip, bit / 32);
128 xgpio_writereg(addr, xgpio_get_value32(a, bit));
131 static void xgpio_read_ch_all(struct xgpio_instance *chip, int reg, unsigned long *a)
133 int bit, lastbit = xgpio_to_bit(chip, chip->gc.ngpio - 1);
135 for (bit = 0; bit <= lastbit ; bit += 32)
136 xgpio_read_ch(chip, reg, bit, a);
139 static void xgpio_write_ch_all(struct xgpio_instance *chip, int reg, unsigned long *a)
141 int bit, lastbit = xgpio_to_bit(chip, chip->gc.ngpio - 1);
143 for (bit = 0; bit <= lastbit ; bit += 32)
144 xgpio_write_ch(chip, reg, bit, a);
148 * xgpio_get - Read the specified signal of the GPIO device.
149 * @gc: Pointer to gpio_chip device structure.
150 * @gpio: GPIO signal number.
152 * This function reads the specified signal of the GPIO device.
155 * 0 if direction of GPIO signals is set as input otherwise it
156 * returns negative error value.
158 static int xgpio_get(struct gpio_chip *gc, unsigned int gpio)
160 struct xgpio_instance *chip = gpiochip_get_data(gc);
161 int bit = xgpio_to_bit(chip, gpio);
162 DECLARE_BITMAP(state, 64);
164 xgpio_read_ch(chip, XGPIO_DATA_OFFSET, bit, state);
166 return test_bit(bit, state);
170 * xgpio_set - Write the specified signal of the GPIO device.
171 * @gc: Pointer to gpio_chip device structure.
172 * @gpio: GPIO signal number.
173 * @val: Value to be written to specified signal.
175 * This function writes the specified value in to the specified signal of the
178 static void xgpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
181 struct xgpio_instance *chip = gpiochip_get_data(gc);
182 int bit = xgpio_to_bit(chip, gpio);
184 spin_lock_irqsave(&chip->gpio_lock, flags);
186 /* Write to GPIO signal and set its direction to output */
187 __assign_bit(bit, chip->state, val);
189 xgpio_write_ch(chip, XGPIO_DATA_OFFSET, bit, chip->state);
191 spin_unlock_irqrestore(&chip->gpio_lock, flags);
195 * xgpio_set_multiple - Write the specified signals of the GPIO device.
196 * @gc: Pointer to gpio_chip device structure.
197 * @mask: Mask of the GPIOS to modify.
198 * @bits: Value to be wrote on each GPIO
200 * This function writes the specified values into the specified signals of the
203 static void xgpio_set_multiple(struct gpio_chip *gc, unsigned long *mask,
206 DECLARE_BITMAP(hw_mask, 64);
207 DECLARE_BITMAP(hw_bits, 64);
208 DECLARE_BITMAP(state, 64);
210 struct xgpio_instance *chip = gpiochip_get_data(gc);
212 bitmap_remap(hw_mask, mask, chip->sw_map, chip->hw_map, 64);
213 bitmap_remap(hw_bits, bits, chip->sw_map, chip->hw_map, 64);
215 spin_lock_irqsave(&chip->gpio_lock, flags);
217 bitmap_replace(state, chip->state, hw_bits, hw_mask, 64);
219 xgpio_write_ch_all(chip, XGPIO_DATA_OFFSET, state);
221 bitmap_copy(chip->state, state, 64);
223 spin_unlock_irqrestore(&chip->gpio_lock, flags);
227 * xgpio_dir_in - Set the direction of the specified GPIO signal as input.
228 * @gc: Pointer to gpio_chip device structure.
229 * @gpio: GPIO signal number.
232 * 0 - if direction of GPIO signals is set as input
233 * otherwise it returns negative error value.
235 static int xgpio_dir_in(struct gpio_chip *gc, unsigned int gpio)
238 struct xgpio_instance *chip = gpiochip_get_data(gc);
239 int bit = xgpio_to_bit(chip, gpio);
241 spin_lock_irqsave(&chip->gpio_lock, flags);
243 /* Set the GPIO bit in shadow register and set direction as input */
244 __set_bit(bit, chip->dir);
245 xgpio_write_ch(chip, XGPIO_TRI_OFFSET, bit, chip->dir);
247 spin_unlock_irqrestore(&chip->gpio_lock, flags);
253 * xgpio_dir_out - Set the direction of the specified GPIO signal as output.
254 * @gc: Pointer to gpio_chip device structure.
255 * @gpio: GPIO signal number.
256 * @val: Value to be written to specified signal.
258 * This function sets the direction of specified GPIO signal as output.
261 * If all GPIO signals of GPIO chip is configured as input then it returns
262 * error otherwise it returns 0.
264 static int xgpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
267 struct xgpio_instance *chip = gpiochip_get_data(gc);
268 int bit = xgpio_to_bit(chip, gpio);
270 spin_lock_irqsave(&chip->gpio_lock, flags);
272 /* Write state of GPIO signal */
273 __assign_bit(bit, chip->state, val);
274 xgpio_write_ch(chip, XGPIO_DATA_OFFSET, bit, chip->state);
276 /* Clear the GPIO bit in shadow register and set direction as output */
277 __clear_bit(bit, chip->dir);
278 xgpio_write_ch(chip, XGPIO_TRI_OFFSET, bit, chip->dir);
280 spin_unlock_irqrestore(&chip->gpio_lock, flags);
286 * xgpio_save_regs - Set initial values of GPIO pins
287 * @chip: Pointer to GPIO instance
289 static void xgpio_save_regs(struct xgpio_instance *chip)
291 xgpio_write_ch_all(chip, XGPIO_DATA_OFFSET, chip->state);
292 xgpio_write_ch_all(chip, XGPIO_TRI_OFFSET, chip->dir);
295 static int xgpio_request(struct gpio_chip *chip, unsigned int offset)
299 ret = pm_runtime_get_sync(chip->parent);
301 * If the device is already active pm_runtime_get() will return 1 on
302 * success, but gpio_request still needs to return 0.
304 return ret < 0 ? ret : 0;
307 static void xgpio_free(struct gpio_chip *chip, unsigned int offset)
309 pm_runtime_put(chip->parent);
312 static int __maybe_unused xgpio_suspend(struct device *dev)
314 struct xgpio_instance *gpio = dev_get_drvdata(dev);
315 struct irq_data *data = irq_get_irq_data(gpio->irq);
318 dev_dbg(dev, "IRQ not connected\n");
319 return pm_runtime_force_suspend(dev);
322 if (!irqd_is_wakeup_set(data))
323 return pm_runtime_force_suspend(dev);
329 * xgpio_remove - Remove method for the GPIO device.
330 * @pdev: pointer to the platform device
332 * This function remove gpiochips and frees all the allocated resources.
336 static int xgpio_remove(struct platform_device *pdev)
338 struct xgpio_instance *gpio = platform_get_drvdata(pdev);
340 pm_runtime_get_sync(&pdev->dev);
341 pm_runtime_put_noidle(&pdev->dev);
342 pm_runtime_disable(&pdev->dev);
343 clk_disable_unprepare(gpio->clk);
349 * xgpio_irq_ack - Acknowledge a child GPIO interrupt.
350 * @irq_data: per IRQ and chip data passed down to chip functions
351 * This currently does nothing, but irq_ack is unconditionally called by
352 * handle_edge_irq and therefore must be defined.
354 static void xgpio_irq_ack(struct irq_data *irq_data)
358 static int __maybe_unused xgpio_resume(struct device *dev)
360 struct xgpio_instance *gpio = dev_get_drvdata(dev);
361 struct irq_data *data = irq_get_irq_data(gpio->irq);
364 dev_dbg(dev, "IRQ not connected\n");
365 return pm_runtime_force_resume(dev);
368 if (!irqd_is_wakeup_set(data))
369 return pm_runtime_force_resume(dev);
374 static int __maybe_unused xgpio_runtime_suspend(struct device *dev)
376 struct xgpio_instance *gpio = dev_get_drvdata(dev);
378 clk_disable(gpio->clk);
383 static int __maybe_unused xgpio_runtime_resume(struct device *dev)
385 struct xgpio_instance *gpio = dev_get_drvdata(dev);
387 return clk_enable(gpio->clk);
390 static const struct dev_pm_ops xgpio_dev_pm_ops = {
391 SET_SYSTEM_SLEEP_PM_OPS(xgpio_suspend, xgpio_resume)
392 SET_RUNTIME_PM_OPS(xgpio_runtime_suspend,
393 xgpio_runtime_resume, NULL)
397 * xgpio_irq_mask - Write the specified signal of the GPIO device.
398 * @irq_data: per IRQ and chip data passed down to chip functions
400 static void xgpio_irq_mask(struct irq_data *irq_data)
403 struct xgpio_instance *chip = irq_data_get_irq_chip_data(irq_data);
404 int irq_offset = irqd_to_hwirq(irq_data);
405 int bit = xgpio_to_bit(chip, irq_offset);
406 u32 mask = BIT(bit / 32), temp;
408 spin_lock_irqsave(&chip->gpio_lock, flags);
410 __clear_bit(bit, chip->enable);
412 if (xgpio_get_value32(chip->enable, bit) == 0) {
413 /* Disable per channel interrupt */
414 temp = xgpio_readreg(chip->regs + XGPIO_IPIER_OFFSET);
416 xgpio_writereg(chip->regs + XGPIO_IPIER_OFFSET, temp);
418 spin_unlock_irqrestore(&chip->gpio_lock, flags);
422 * xgpio_irq_unmask - Write the specified signal of the GPIO device.
423 * @irq_data: per IRQ and chip data passed down to chip functions
425 static void xgpio_irq_unmask(struct irq_data *irq_data)
428 struct xgpio_instance *chip = irq_data_get_irq_chip_data(irq_data);
429 int irq_offset = irqd_to_hwirq(irq_data);
430 int bit = xgpio_to_bit(chip, irq_offset);
431 u32 old_enable = xgpio_get_value32(chip->enable, bit);
432 u32 mask = BIT(bit / 32), val;
434 spin_lock_irqsave(&chip->gpio_lock, flags);
436 __set_bit(bit, chip->enable);
438 if (old_enable == 0) {
439 /* Clear any existing per-channel interrupts */
440 val = xgpio_readreg(chip->regs + XGPIO_IPISR_OFFSET);
442 xgpio_writereg(chip->regs + XGPIO_IPISR_OFFSET, val);
444 /* Update GPIO IRQ read data before enabling interrupt*/
445 xgpio_read_ch(chip, XGPIO_DATA_OFFSET, bit, chip->last_irq_read);
447 /* Enable per channel interrupt */
448 val = xgpio_readreg(chip->regs + XGPIO_IPIER_OFFSET);
450 xgpio_writereg(chip->regs + XGPIO_IPIER_OFFSET, val);
453 spin_unlock_irqrestore(&chip->gpio_lock, flags);
457 * xgpio_set_irq_type - Write the specified signal of the GPIO device.
458 * @irq_data: Per IRQ and chip data passed down to chip functions
459 * @type: Interrupt type that is to be set for the gpio pin
462 * 0 if interrupt type is supported otherwise -EINVAL
464 static int xgpio_set_irq_type(struct irq_data *irq_data, unsigned int type)
466 struct xgpio_instance *chip = irq_data_get_irq_chip_data(irq_data);
467 int irq_offset = irqd_to_hwirq(irq_data);
468 int bit = xgpio_to_bit(chip, irq_offset);
471 * The Xilinx GPIO hardware provides a single interrupt status
472 * indication for any state change in a given GPIO channel (bank).
473 * Therefore, only rising edge or falling edge triggers are
476 switch (type & IRQ_TYPE_SENSE_MASK) {
477 case IRQ_TYPE_EDGE_BOTH:
478 __set_bit(bit, chip->rising_edge);
479 __set_bit(bit, chip->falling_edge);
481 case IRQ_TYPE_EDGE_RISING:
482 __set_bit(bit, chip->rising_edge);
483 __clear_bit(bit, chip->falling_edge);
485 case IRQ_TYPE_EDGE_FALLING:
486 __clear_bit(bit, chip->rising_edge);
487 __set_bit(bit, chip->falling_edge);
493 irq_set_handler_locked(irq_data, handle_edge_irq);
498 * xgpio_irqhandler - Gpio interrupt service routine
499 * @desc: Pointer to interrupt description
501 static void xgpio_irqhandler(struct irq_desc *desc)
503 struct xgpio_instance *chip = irq_desc_get_handler_data(desc);
504 struct gpio_chip *gc = &chip->gc;
505 struct irq_chip *irqchip = irq_desc_get_chip(desc);
506 DECLARE_BITMAP(rising, 64);
507 DECLARE_BITMAP(falling, 64);
508 DECLARE_BITMAP(all, 64);
513 status = xgpio_readreg(chip->regs + XGPIO_IPISR_OFFSET);
514 xgpio_writereg(chip->regs + XGPIO_IPISR_OFFSET, status);
516 chained_irq_enter(irqchip, desc);
518 spin_lock(&chip->gpio_lock);
520 xgpio_read_ch_all(chip, XGPIO_DATA_OFFSET, all);
522 bitmap_complement(rising, chip->last_irq_read, 64);
523 bitmap_and(rising, rising, all, 64);
524 bitmap_and(rising, rising, chip->enable, 64);
525 bitmap_and(rising, rising, chip->rising_edge, 64);
527 bitmap_complement(falling, all, 64);
528 bitmap_and(falling, falling, chip->last_irq_read, 64);
529 bitmap_and(falling, falling, chip->enable, 64);
530 bitmap_and(falling, falling, chip->falling_edge, 64);
532 bitmap_copy(chip->last_irq_read, all, 64);
533 bitmap_or(all, rising, falling, 64);
535 spin_unlock(&chip->gpio_lock);
537 dev_dbg(gc->parent, "IRQ rising %*pb falling %*pb\n", 64, rising, 64, falling);
539 for_each_set_bit(bit, all, 64) {
540 irq_offset = xgpio_from_bit(chip, bit);
541 generic_handle_domain_irq(gc->irq.domain, irq_offset);
544 chained_irq_exit(irqchip, desc);
548 * xgpio_probe - Probe method for the GPIO device.
549 * @pdev: pointer to the platform device
552 * It returns 0, if the driver is bound to the GPIO device, or
553 * a negative value if there is an error.
555 static int xgpio_probe(struct platform_device *pdev)
557 struct xgpio_instance *chip;
559 struct device_node *np = pdev->dev.of_node;
564 struct gpio_irq_chip *girq;
567 chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL);
571 platform_set_drvdata(pdev, chip);
573 /* First, check if the device is dual-channel */
574 of_property_read_u32(np, "xlnx,is-dual", &is_dual);
577 memset32(width, 0, ARRAY_SIZE(width));
578 memset32(state, 0, ARRAY_SIZE(state));
579 memset32(dir, 0xFFFFFFFF, ARRAY_SIZE(dir));
581 /* Update GPIO state shadow register with default value */
582 of_property_read_u32(np, "xlnx,dout-default", &state[0]);
583 of_property_read_u32(np, "xlnx,dout-default-2", &state[1]);
585 bitmap_from_arr32(chip->state, state, 64);
587 /* Update GPIO direction shadow register with default value */
588 of_property_read_u32(np, "xlnx,tri-default", &dir[0]);
589 of_property_read_u32(np, "xlnx,tri-default-2", &dir[1]);
591 bitmap_from_arr32(chip->dir, dir, 64);
594 * Check device node and parent device node for device width
595 * and assume default width of 32
597 if (of_property_read_u32(np, "xlnx,gpio-width", &width[0]))
603 if (is_dual && of_property_read_u32(np, "xlnx,gpio2-width", &width[1]))
609 /* Setup software pin mapping */
610 bitmap_set(chip->sw_map, 0, width[0] + width[1]);
612 /* Setup hardware pin mapping */
613 bitmap_set(chip->hw_map, 0, width[0]);
614 bitmap_set(chip->hw_map, 32, width[1]);
616 spin_lock_init(&chip->gpio_lock);
619 chip->gc.ngpio = bitmap_weight(chip->hw_map, 64);
620 chip->gc.parent = &pdev->dev;
621 chip->gc.direction_input = xgpio_dir_in;
622 chip->gc.direction_output = xgpio_dir_out;
623 chip->gc.get = xgpio_get;
624 chip->gc.set = xgpio_set;
625 chip->gc.request = xgpio_request;
626 chip->gc.free = xgpio_free;
627 chip->gc.set_multiple = xgpio_set_multiple;
629 chip->gc.label = dev_name(&pdev->dev);
631 chip->regs = devm_platform_ioremap_resource(pdev, 0);
632 if (IS_ERR(chip->regs)) {
633 dev_err(&pdev->dev, "failed to ioremap memory resource\n");
634 return PTR_ERR(chip->regs);
637 chip->clk = devm_clk_get_optional(&pdev->dev, NULL);
638 if (IS_ERR(chip->clk))
639 return dev_err_probe(&pdev->dev, PTR_ERR(chip->clk), "input clock not found.\n");
641 status = clk_prepare_enable(chip->clk);
643 dev_err(&pdev->dev, "Failed to prepare clk\n");
646 pm_runtime_get_noresume(&pdev->dev);
647 pm_runtime_set_active(&pdev->dev);
648 pm_runtime_enable(&pdev->dev);
650 xgpio_save_regs(chip);
652 chip->irq = platform_get_irq_optional(pdev, 0);
656 chip->irqchip.name = "gpio-xilinx";
657 chip->irqchip.irq_ack = xgpio_irq_ack;
658 chip->irqchip.irq_mask = xgpio_irq_mask;
659 chip->irqchip.irq_unmask = xgpio_irq_unmask;
660 chip->irqchip.irq_set_type = xgpio_set_irq_type;
662 /* Disable per-channel interrupts */
663 xgpio_writereg(chip->regs + XGPIO_IPIER_OFFSET, 0);
664 /* Clear any existing per-channel interrupts */
665 temp = xgpio_readreg(chip->regs + XGPIO_IPISR_OFFSET);
666 xgpio_writereg(chip->regs + XGPIO_IPISR_OFFSET, temp);
667 /* Enable global interrupts */
668 xgpio_writereg(chip->regs + XGPIO_GIER_OFFSET, XGPIO_GIER_IE);
670 girq = &chip->gc.irq;
671 girq->chip = &chip->irqchip;
672 girq->parent_handler = xgpio_irqhandler;
673 girq->num_parents = 1;
674 girq->parents = devm_kcalloc(&pdev->dev, 1,
675 sizeof(*girq->parents),
677 if (!girq->parents) {
681 girq->parents[0] = chip->irq;
682 girq->default_type = IRQ_TYPE_NONE;
683 girq->handler = handle_bad_irq;
686 status = devm_gpiochip_add_data(&pdev->dev, &chip->gc, chip);
688 dev_err(&pdev->dev, "failed to add GPIO chip\n");
692 pm_runtime_put(&pdev->dev);
696 pm_runtime_disable(&pdev->dev);
697 pm_runtime_put_noidle(&pdev->dev);
698 clk_disable_unprepare(chip->clk);
702 static const struct of_device_id xgpio_of_match[] = {
703 { .compatible = "xlnx,xps-gpio-1.00.a", },
704 { /* end of list */ },
707 MODULE_DEVICE_TABLE(of, xgpio_of_match);
709 static struct platform_driver xgpio_plat_driver = {
710 .probe = xgpio_probe,
711 .remove = xgpio_remove,
713 .name = "gpio-xilinx",
714 .of_match_table = xgpio_of_match,
715 .pm = &xgpio_dev_pm_ops,
719 static int __init xgpio_init(void)
721 return platform_driver_register(&xgpio_plat_driver);
724 subsys_initcall(xgpio_init);
726 static void __exit xgpio_exit(void)
728 platform_driver_unregister(&xgpio_plat_driver);
730 module_exit(xgpio_exit);
732 MODULE_AUTHOR("Xilinx, Inc.");
733 MODULE_DESCRIPTION("Xilinx GPIO driver");
734 MODULE_LICENSE("GPL");