2 * Copyright (C) ST-Ericsson SA 2010
4 * License Terms: GNU General Public License, version 2
5 * Author: Hanumath Prasad <hanumath.prasad@stericsson.com> for ST-Ericsson
6 * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
9 #include <linux/module.h>
10 #include <linux/init.h>
11 #include <linux/platform_device.h>
12 #include <linux/slab.h>
13 #include <linux/gpio/driver.h>
15 #include <linux/interrupt.h>
16 #include <linux/mfd/tc3589x.h>
17 #include <linux/bitops.h>
20 * These registers are modified under the irq bus lock and cached to avoid
21 * unnecessary writes in bus_sync_unlock.
23 enum { REG_IBE, REG_IEV, REG_IS, REG_IE };
25 #define CACHE_NR_REGS 4
26 #define CACHE_NR_BANKS 3
29 struct gpio_chip chip;
30 struct tc3589x *tc3589x;
32 struct mutex irq_lock;
33 /* Caches of interrupt control registers for bus_lock */
34 u8 regs[CACHE_NR_REGS][CACHE_NR_BANKS];
35 u8 oldregs[CACHE_NR_REGS][CACHE_NR_BANKS];
38 static int tc3589x_gpio_get(struct gpio_chip *chip, unsigned offset)
40 struct tc3589x_gpio *tc3589x_gpio = gpiochip_get_data(chip);
41 struct tc3589x *tc3589x = tc3589x_gpio->tc3589x;
42 u8 reg = TC3589x_GPIODATA0 + (offset / 8) * 2;
43 u8 mask = BIT(offset % 8);
46 ret = tc3589x_reg_read(tc3589x, reg);
50 return !!(ret & mask);
53 static void tc3589x_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
55 struct tc3589x_gpio *tc3589x_gpio = gpiochip_get_data(chip);
56 struct tc3589x *tc3589x = tc3589x_gpio->tc3589x;
57 u8 reg = TC3589x_GPIODATA0 + (offset / 8) * 2;
58 unsigned pos = offset % 8;
59 u8 data[] = {val ? BIT(pos) : 0, BIT(pos)};
61 tc3589x_block_write(tc3589x, reg, ARRAY_SIZE(data), data);
64 static int tc3589x_gpio_direction_output(struct gpio_chip *chip,
65 unsigned offset, int val)
67 struct tc3589x_gpio *tc3589x_gpio = gpiochip_get_data(chip);
68 struct tc3589x *tc3589x = tc3589x_gpio->tc3589x;
69 u8 reg = TC3589x_GPIODIR0 + offset / 8;
70 unsigned pos = offset % 8;
72 tc3589x_gpio_set(chip, offset, val);
74 return tc3589x_set_bits(tc3589x, reg, BIT(pos), BIT(pos));
77 static int tc3589x_gpio_direction_input(struct gpio_chip *chip,
80 struct tc3589x_gpio *tc3589x_gpio = gpiochip_get_data(chip);
81 struct tc3589x *tc3589x = tc3589x_gpio->tc3589x;
82 u8 reg = TC3589x_GPIODIR0 + offset / 8;
83 unsigned pos = offset % 8;
85 return tc3589x_set_bits(tc3589x, reg, BIT(pos), 0);
88 static int tc3589x_gpio_single_ended(struct gpio_chip *chip,
90 enum single_ended_mode mode)
92 struct tc3589x_gpio *tc3589x_gpio = gpiochip_get_data(chip);
93 struct tc3589x *tc3589x = tc3589x_gpio->tc3589x;
95 * These registers are alterated at each second address
96 * ODM bit 0 = drive to GND or Hi-Z (open drain)
97 * ODM bit 1 = drive to VDD or Hi-Z (open source)
99 u8 odmreg = TC3589x_GPIOODM0 + (offset / 8) * 2;
100 u8 odereg = TC3589x_GPIOODE0 + (offset / 8) * 2;
101 unsigned pos = offset % 8;
105 case LINE_MODE_OPEN_DRAIN:
106 /* Set open drain mode */
107 ret = tc3589x_set_bits(tc3589x, odmreg, BIT(pos), 0);
110 /* Enable open drain/source mode */
111 return tc3589x_set_bits(tc3589x, odereg, BIT(pos), BIT(pos));
112 case LINE_MODE_OPEN_SOURCE:
113 /* Set open source mode */
114 ret = tc3589x_set_bits(tc3589x, odmreg, BIT(pos), BIT(pos));
117 /* Enable open drain/source mode */
118 return tc3589x_set_bits(tc3589x, odereg, BIT(pos), BIT(pos));
119 case LINE_MODE_PUSH_PULL:
120 /* Disable open drain/source mode */
121 return tc3589x_set_bits(tc3589x, odereg, BIT(pos), 0);
128 static struct gpio_chip template_chip = {
130 .owner = THIS_MODULE,
131 .direction_input = tc3589x_gpio_direction_input,
132 .get = tc3589x_gpio_get,
133 .direction_output = tc3589x_gpio_direction_output,
134 .set = tc3589x_gpio_set,
135 .set_single_ended = tc3589x_gpio_single_ended,
139 static int tc3589x_gpio_irq_set_type(struct irq_data *d, unsigned int type)
141 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
142 struct tc3589x_gpio *tc3589x_gpio = gpiochip_get_data(gc);
143 int offset = d->hwirq;
144 int regoffset = offset / 8;
145 int mask = BIT(offset % 8);
147 if (type == IRQ_TYPE_EDGE_BOTH) {
148 tc3589x_gpio->regs[REG_IBE][regoffset] |= mask;
152 tc3589x_gpio->regs[REG_IBE][regoffset] &= ~mask;
154 if (type == IRQ_TYPE_LEVEL_LOW || type == IRQ_TYPE_LEVEL_HIGH)
155 tc3589x_gpio->regs[REG_IS][regoffset] |= mask;
157 tc3589x_gpio->regs[REG_IS][regoffset] &= ~mask;
159 if (type == IRQ_TYPE_EDGE_RISING || type == IRQ_TYPE_LEVEL_HIGH)
160 tc3589x_gpio->regs[REG_IEV][regoffset] |= mask;
162 tc3589x_gpio->regs[REG_IEV][regoffset] &= ~mask;
167 static void tc3589x_gpio_irq_lock(struct irq_data *d)
169 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
170 struct tc3589x_gpio *tc3589x_gpio = gpiochip_get_data(gc);
172 mutex_lock(&tc3589x_gpio->irq_lock);
175 static void tc3589x_gpio_irq_sync_unlock(struct irq_data *d)
177 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
178 struct tc3589x_gpio *tc3589x_gpio = gpiochip_get_data(gc);
179 struct tc3589x *tc3589x = tc3589x_gpio->tc3589x;
180 static const u8 regmap[] = {
181 [REG_IBE] = TC3589x_GPIOIBE0,
182 [REG_IEV] = TC3589x_GPIOIEV0,
183 [REG_IS] = TC3589x_GPIOIS0,
184 [REG_IE] = TC3589x_GPIOIE0,
188 for (i = 0; i < CACHE_NR_REGS; i++) {
189 for (j = 0; j < CACHE_NR_BANKS; j++) {
190 u8 old = tc3589x_gpio->oldregs[i][j];
191 u8 new = tc3589x_gpio->regs[i][j];
196 tc3589x_gpio->oldregs[i][j] = new;
197 tc3589x_reg_write(tc3589x, regmap[i] + j * 8, new);
201 mutex_unlock(&tc3589x_gpio->irq_lock);
204 static void tc3589x_gpio_irq_mask(struct irq_data *d)
206 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
207 struct tc3589x_gpio *tc3589x_gpio = gpiochip_get_data(gc);
208 int offset = d->hwirq;
209 int regoffset = offset / 8;
210 int mask = BIT(offset % 8);
212 tc3589x_gpio->regs[REG_IE][regoffset] &= ~mask;
215 static void tc3589x_gpio_irq_unmask(struct irq_data *d)
217 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
218 struct tc3589x_gpio *tc3589x_gpio = gpiochip_get_data(gc);
219 int offset = d->hwirq;
220 int regoffset = offset / 8;
221 int mask = BIT(offset % 8);
223 tc3589x_gpio->regs[REG_IE][regoffset] |= mask;
226 static struct irq_chip tc3589x_gpio_irq_chip = {
227 .name = "tc3589x-gpio",
228 .irq_bus_lock = tc3589x_gpio_irq_lock,
229 .irq_bus_sync_unlock = tc3589x_gpio_irq_sync_unlock,
230 .irq_mask = tc3589x_gpio_irq_mask,
231 .irq_unmask = tc3589x_gpio_irq_unmask,
232 .irq_set_type = tc3589x_gpio_irq_set_type,
235 static irqreturn_t tc3589x_gpio_irq(int irq, void *dev)
237 struct tc3589x_gpio *tc3589x_gpio = dev;
238 struct tc3589x *tc3589x = tc3589x_gpio->tc3589x;
239 u8 status[CACHE_NR_BANKS];
243 ret = tc3589x_block_read(tc3589x, TC3589x_GPIOMIS0,
244 ARRAY_SIZE(status), status);
248 for (i = 0; i < ARRAY_SIZE(status); i++) {
249 unsigned int stat = status[i];
254 int bit = __ffs(stat);
255 int line = i * 8 + bit;
256 int irq = irq_find_mapping(tc3589x_gpio->chip.irqdomain,
259 handle_nested_irq(irq);
263 tc3589x_reg_write(tc3589x, TC3589x_GPIOIC0 + i, status[i]);
269 static int tc3589x_gpio_probe(struct platform_device *pdev)
271 struct tc3589x *tc3589x = dev_get_drvdata(pdev->dev.parent);
272 struct device_node *np = pdev->dev.of_node;
273 struct tc3589x_gpio *tc3589x_gpio;
278 dev_err(&pdev->dev, "No Device Tree node found\n");
282 irq = platform_get_irq(pdev, 0);
286 tc3589x_gpio = devm_kzalloc(&pdev->dev, sizeof(struct tc3589x_gpio),
291 mutex_init(&tc3589x_gpio->irq_lock);
293 tc3589x_gpio->dev = &pdev->dev;
294 tc3589x_gpio->tc3589x = tc3589x;
296 tc3589x_gpio->chip = template_chip;
297 tc3589x_gpio->chip.ngpio = tc3589x->num_gpio;
298 tc3589x_gpio->chip.parent = &pdev->dev;
299 tc3589x_gpio->chip.base = -1;
300 tc3589x_gpio->chip.of_node = np;
302 /* Bring the GPIO module out of reset */
303 ret = tc3589x_set_bits(tc3589x, TC3589x_RSTCTRL,
304 TC3589x_RSTCTRL_GPIRST, 0);
308 ret = devm_request_threaded_irq(&pdev->dev,
309 irq, NULL, tc3589x_gpio_irq,
310 IRQF_ONESHOT, "tc3589x-gpio",
313 dev_err(&pdev->dev, "unable to get irq: %d\n", ret);
317 ret = devm_gpiochip_add_data(&pdev->dev, &tc3589x_gpio->chip,
320 dev_err(&pdev->dev, "unable to add gpiochip: %d\n", ret);
324 ret = gpiochip_irqchip_add(&tc3589x_gpio->chip,
325 &tc3589x_gpio_irq_chip,
331 "could not connect irqchip to gpiochip\n");
335 gpiochip_set_chained_irqchip(&tc3589x_gpio->chip,
336 &tc3589x_gpio_irq_chip,
340 platform_set_drvdata(pdev, tc3589x_gpio);
345 static struct platform_driver tc3589x_gpio_driver = {
346 .driver.name = "tc3589x-gpio",
347 .driver.owner = THIS_MODULE,
348 .probe = tc3589x_gpio_probe,
351 static int __init tc3589x_gpio_init(void)
353 return platform_driver_register(&tc3589x_gpio_driver);
355 subsys_initcall(tc3589x_gpio_init);
357 static void __exit tc3589x_gpio_exit(void)
359 platform_driver_unregister(&tc3589x_gpio_driver);
361 module_exit(tc3589x_gpio_exit);
363 MODULE_LICENSE("GPL v2");
364 MODULE_DESCRIPTION("TC3589x GPIO driver");
365 MODULE_AUTHOR("Hanumath Prasad, Rabin Vincent");