2 * GPIO interface for Intel Sodaville SoCs.
4 * Copyright (c) 2010, 2011 Intel Corporation
6 * Author: Hans J. Koch <hjk@linutronix.de>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License 2 as published
10 * by the Free Software Foundation.
14 #include <linux/errno.h>
15 #include <linux/init.h>
17 #include <linux/irq.h>
18 #include <linux/interrupt.h>
19 #include <linux/kernel.h>
20 #include <linux/pci.h>
21 #include <linux/platform_device.h>
22 #include <linux/of_irq.h>
23 #include <linux/gpio/driver.h>
25 #define DRV_NAME "sdv_gpio"
26 #define SDV_NUM_PUB_GPIOS 12
27 #define PCI_DEVICE_ID_SDV_GPIO 0x2e67
41 struct sdv_gpio_chip_data {
43 void __iomem *gpio_pub_base;
44 struct irq_domain *id;
45 struct irq_chip_generic *gc;
46 struct gpio_chip chip;
49 static int sdv_gpio_pub_set_type(struct irq_data *d, unsigned int type)
51 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
52 struct sdv_gpio_chip_data *sd = gc->private;
53 void __iomem *type_reg;
57 type_reg = sd->gpio_pub_base + GPIT1R0;
59 type_reg = sd->gpio_pub_base + GPIT1R1;
61 reg = readl(type_reg);
64 case IRQ_TYPE_LEVEL_HIGH:
65 reg &= ~BIT(4 * (d->hwirq % 8));
68 case IRQ_TYPE_LEVEL_LOW:
69 reg |= BIT(4 * (d->hwirq % 8));
76 writel(reg, type_reg);
80 static irqreturn_t sdv_gpio_pub_irq_handler(int irq, void *data)
82 struct sdv_gpio_chip_data *sd = data;
83 unsigned long irq_stat = readl(sd->gpio_pub_base + GPSTR);
86 irq_stat &= readl(sd->gpio_pub_base + GPIO_INT);
90 for_each_set_bit(irq_bit, &irq_stat, 32)
91 generic_handle_irq(irq_find_mapping(sd->id, irq_bit));
96 static int sdv_xlate(struct irq_domain *h, struct device_node *node,
97 const u32 *intspec, u32 intsize, irq_hw_number_t *out_hwirq,
102 if (node != irq_domain_get_of_node(h))
115 case IRQ_TYPE_LEVEL_LOW:
116 case IRQ_TYPE_LEVEL_HIGH:
125 static const struct irq_domain_ops irq_domain_sdv_ops = {
129 static int sdv_register_irqsupport(struct sdv_gpio_chip_data *sd,
130 struct pci_dev *pdev)
132 struct irq_chip_type *ct;
135 sd->irq_base = devm_irq_alloc_descs(&pdev->dev, -1, 0,
136 SDV_NUM_PUB_GPIOS, -1);
137 if (sd->irq_base < 0)
140 /* mask + ACK all interrupt sources */
141 writel(0, sd->gpio_pub_base + GPIO_INT);
142 writel((1 << 11) - 1, sd->gpio_pub_base + GPSTR);
144 ret = devm_request_irq(&pdev->dev, pdev->irq,
145 sdv_gpio_pub_irq_handler, IRQF_SHARED,
151 * This gpio irq controller latches level irqs. Testing shows that if
152 * we unmask & ACK the IRQ before the source of the interrupt is gone
153 * then the interrupt is active again.
155 sd->gc = devm_irq_alloc_generic_chip(&pdev->dev, "sdv-gpio", 1,
162 sd->gc->private = sd;
163 ct = sd->gc->chip_types;
164 ct->type = IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW;
165 ct->regs.eoi = GPSTR;
166 ct->regs.mask = GPIO_INT;
167 ct->chip.irq_mask = irq_gc_mask_clr_bit;
168 ct->chip.irq_unmask = irq_gc_mask_set_bit;
169 ct->chip.irq_eoi = irq_gc_eoi;
170 ct->chip.irq_set_type = sdv_gpio_pub_set_type;
172 irq_setup_generic_chip(sd->gc, IRQ_MSK(SDV_NUM_PUB_GPIOS),
173 IRQ_GC_INIT_MASK_CACHE, IRQ_NOREQUEST,
174 IRQ_LEVEL | IRQ_NOPROBE);
176 sd->id = irq_domain_add_legacy(pdev->dev.of_node, SDV_NUM_PUB_GPIOS,
177 sd->irq_base, 0, &irq_domain_sdv_ops, sd);
184 static int sdv_gpio_probe(struct pci_dev *pdev,
185 const struct pci_device_id *pci_id)
187 struct sdv_gpio_chip_data *sd;
191 sd = devm_kzalloc(&pdev->dev, sizeof(*sd), GFP_KERNEL);
195 ret = pcim_enable_device(pdev);
197 dev_err(&pdev->dev, "can't enable device.\n");
201 ret = pcim_iomap_regions(pdev, 1 << GPIO_BAR, DRV_NAME);
203 dev_err(&pdev->dev, "can't alloc PCI BAR #%d\n", GPIO_BAR);
207 sd->gpio_pub_base = pcim_iomap_table(pdev)[GPIO_BAR];
209 ret = of_property_read_u32(pdev->dev.of_node, "intel,muxctl", &mux_val);
211 writel(mux_val, sd->gpio_pub_base + GPMUXCTL);
213 ret = bgpio_init(&sd->chip, &pdev->dev, 4,
214 sd->gpio_pub_base + GPINR, sd->gpio_pub_base + GPOUTR,
215 NULL, sd->gpio_pub_base + GPOER, NULL, 0);
219 sd->chip.ngpio = SDV_NUM_PUB_GPIOS;
221 ret = devm_gpiochip_add_data(&pdev->dev, &sd->chip, sd);
223 dev_err(&pdev->dev, "gpiochip_add() failed.\n");
227 ret = sdv_register_irqsupport(sd, pdev);
231 pci_set_drvdata(pdev, sd);
232 dev_info(&pdev->dev, "Sodaville GPIO driver registered.\n");
236 static const struct pci_device_id sdv_gpio_pci_ids[] = {
237 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_SDV_GPIO) },
241 static struct pci_driver sdv_gpio_driver = {
243 .suppress_bind_attrs = true,
246 .id_table = sdv_gpio_pci_ids,
247 .probe = sdv_gpio_probe,
249 builtin_pci_driver(sdv_gpio_driver);