1 // SPDX-License-Identifier: GPL-2.0
3 * Renesas R-Car GPIO Support
5 * Copyright (C) 2014 Renesas Electronics Corporation
6 * Copyright (C) 2013 Magnus Damm
10 #include <linux/gpio/driver.h>
11 #include <linux/init.h>
12 #include <linux/interrupt.h>
14 #include <linux/ioport.h>
15 #include <linux/irq.h>
16 #include <linux/module.h>
18 #include <linux/of_device.h>
19 #include <linux/pinctrl/consumer.h>
20 #include <linux/platform_device.h>
21 #include <linux/pm_runtime.h>
22 #include <linux/spinlock.h>
23 #include <linux/slab.h>
25 struct gpio_rcar_bank_info {
35 struct gpio_rcar_info {
37 bool has_both_edge_trigger;
40 struct gpio_rcar_priv {
44 struct gpio_chip gpio_chip;
45 struct irq_chip irq_chip;
46 unsigned int irq_parent;
48 struct gpio_rcar_info info;
49 struct gpio_rcar_bank_info bank_info;
52 #define IOINTSEL 0x00 /* General IO/Interrupt Switching Register */
53 #define INOUTSEL 0x04 /* General Input/Output Switching Register */
54 #define OUTDT 0x08 /* General Output Register */
55 #define INDT 0x0c /* General Input Register */
56 #define INTDT 0x10 /* Interrupt Display Register */
57 #define INTCLR 0x14 /* Interrupt Clear Register */
58 #define INTMSK 0x18 /* Interrupt Mask Register */
59 #define MSKCLR 0x1c /* Interrupt Mask Clear Register */
60 #define POSNEG 0x20 /* Positive/Negative Logic Select Register */
61 #define EDGLEVEL 0x24 /* Edge/level Select Register */
62 #define FILONOFF 0x28 /* Chattering Prevention On/Off Register */
63 #define OUTDTSEL 0x40 /* Output Data Select Register */
64 #define BOTHEDGE 0x4c /* One Edge/Both Edge Select Register */
66 #define RCAR_MAX_GPIO_PER_BANK 32
68 static inline u32 gpio_rcar_read(struct gpio_rcar_priv *p, int offs)
70 return ioread32(p->base + offs);
73 static inline void gpio_rcar_write(struct gpio_rcar_priv *p, int offs,
76 iowrite32(value, p->base + offs);
79 static void gpio_rcar_modify_bit(struct gpio_rcar_priv *p, int offs,
82 u32 tmp = gpio_rcar_read(p, offs);
89 gpio_rcar_write(p, offs, tmp);
92 static void gpio_rcar_irq_disable(struct irq_data *d)
94 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
95 struct gpio_rcar_priv *p = gpiochip_get_data(gc);
97 gpio_rcar_write(p, INTMSK, ~BIT(irqd_to_hwirq(d)));
100 static void gpio_rcar_irq_enable(struct irq_data *d)
102 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
103 struct gpio_rcar_priv *p = gpiochip_get_data(gc);
105 gpio_rcar_write(p, MSKCLR, BIT(irqd_to_hwirq(d)));
108 static void gpio_rcar_config_interrupt_input_mode(struct gpio_rcar_priv *p,
110 bool active_high_rising_edge,
116 /* follow steps in the GPIO documentation for
117 * "Setting Edge-Sensitive Interrupt Input Mode" and
118 * "Setting Level-Sensitive Interrupt Input Mode"
121 spin_lock_irqsave(&p->lock, flags);
123 /* Configure positive or negative logic in POSNEG */
124 gpio_rcar_modify_bit(p, POSNEG, hwirq, !active_high_rising_edge);
126 /* Configure edge or level trigger in EDGLEVEL */
127 gpio_rcar_modify_bit(p, EDGLEVEL, hwirq, !level_trigger);
129 /* Select one edge or both edges in BOTHEDGE */
130 if (p->info.has_both_edge_trigger)
131 gpio_rcar_modify_bit(p, BOTHEDGE, hwirq, both);
133 /* Select "Interrupt Input Mode" in IOINTSEL */
134 gpio_rcar_modify_bit(p, IOINTSEL, hwirq, true);
136 /* Write INTCLR in case of edge trigger */
138 gpio_rcar_write(p, INTCLR, BIT(hwirq));
140 spin_unlock_irqrestore(&p->lock, flags);
143 static int gpio_rcar_irq_set_type(struct irq_data *d, unsigned int type)
145 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
146 struct gpio_rcar_priv *p = gpiochip_get_data(gc);
147 unsigned int hwirq = irqd_to_hwirq(d);
149 dev_dbg(p->dev, "sense irq = %d, type = %d\n", hwirq, type);
151 switch (type & IRQ_TYPE_SENSE_MASK) {
152 case IRQ_TYPE_LEVEL_HIGH:
153 gpio_rcar_config_interrupt_input_mode(p, hwirq, true, true,
156 case IRQ_TYPE_LEVEL_LOW:
157 gpio_rcar_config_interrupt_input_mode(p, hwirq, false, true,
160 case IRQ_TYPE_EDGE_RISING:
161 gpio_rcar_config_interrupt_input_mode(p, hwirq, true, false,
164 case IRQ_TYPE_EDGE_FALLING:
165 gpio_rcar_config_interrupt_input_mode(p, hwirq, false, false,
168 case IRQ_TYPE_EDGE_BOTH:
169 if (!p->info.has_both_edge_trigger)
171 gpio_rcar_config_interrupt_input_mode(p, hwirq, true, false,
180 static int gpio_rcar_irq_set_wake(struct irq_data *d, unsigned int on)
182 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
183 struct gpio_rcar_priv *p = gpiochip_get_data(gc);
187 error = irq_set_irq_wake(p->irq_parent, on);
189 dev_dbg(p->dev, "irq %u doesn't support irq_set_wake\n",
196 atomic_inc(&p->wakeup_path);
198 atomic_dec(&p->wakeup_path);
203 static irqreturn_t gpio_rcar_irq_handler(int irq, void *dev_id)
205 struct gpio_rcar_priv *p = dev_id;
207 unsigned int offset, irqs_handled = 0;
209 while ((pending = gpio_rcar_read(p, INTDT) &
210 gpio_rcar_read(p, INTMSK))) {
211 offset = __ffs(pending);
212 gpio_rcar_write(p, INTCLR, BIT(offset));
213 generic_handle_irq(irq_find_mapping(p->gpio_chip.irq.domain,
218 return irqs_handled ? IRQ_HANDLED : IRQ_NONE;
221 static void gpio_rcar_config_general_input_output_mode(struct gpio_chip *chip,
225 struct gpio_rcar_priv *p = gpiochip_get_data(chip);
228 /* follow steps in the GPIO documentation for
229 * "Setting General Output Mode" and
230 * "Setting General Input Mode"
233 spin_lock_irqsave(&p->lock, flags);
235 /* Configure positive logic in POSNEG */
236 gpio_rcar_modify_bit(p, POSNEG, gpio, false);
238 /* Select "General Input/Output Mode" in IOINTSEL */
239 gpio_rcar_modify_bit(p, IOINTSEL, gpio, false);
241 /* Select Input Mode or Output Mode in INOUTSEL */
242 gpio_rcar_modify_bit(p, INOUTSEL, gpio, output);
244 /* Select General Output Register to output data in OUTDTSEL */
245 if (p->info.has_outdtsel && output)
246 gpio_rcar_modify_bit(p, OUTDTSEL, gpio, false);
248 spin_unlock_irqrestore(&p->lock, flags);
251 static int gpio_rcar_request(struct gpio_chip *chip, unsigned offset)
253 struct gpio_rcar_priv *p = gpiochip_get_data(chip);
256 error = pm_runtime_get_sync(p->dev);
258 pm_runtime_put(p->dev);
262 error = pinctrl_gpio_request(chip->base + offset);
264 pm_runtime_put(p->dev);
269 static void gpio_rcar_free(struct gpio_chip *chip, unsigned offset)
271 struct gpio_rcar_priv *p = gpiochip_get_data(chip);
273 pinctrl_gpio_free(chip->base + offset);
276 * Set the GPIO as an input to ensure that the next GPIO request won't
277 * drive the GPIO pin as an output.
279 gpio_rcar_config_general_input_output_mode(chip, offset, false);
281 pm_runtime_put(p->dev);
284 static int gpio_rcar_get_direction(struct gpio_chip *chip, unsigned int offset)
286 struct gpio_rcar_priv *p = gpiochip_get_data(chip);
288 if (gpio_rcar_read(p, INOUTSEL) & BIT(offset))
289 return GPIO_LINE_DIRECTION_OUT;
291 return GPIO_LINE_DIRECTION_IN;
294 static int gpio_rcar_direction_input(struct gpio_chip *chip, unsigned offset)
296 gpio_rcar_config_general_input_output_mode(chip, offset, false);
300 static int gpio_rcar_get(struct gpio_chip *chip, unsigned offset)
302 struct gpio_rcar_priv *p = gpiochip_get_data(chip);
303 u32 bit = BIT(offset);
305 /* testing on r8a7790 shows that INDT does not show correct pin state
306 * when configured as output, so use OUTDT in case of output pins */
307 if (gpio_rcar_read(p, INOUTSEL) & bit)
308 return !!(gpio_rcar_read(p, OUTDT) & bit);
310 return !!(gpio_rcar_read(p, INDT) & bit);
313 static int gpio_rcar_get_multiple(struct gpio_chip *chip, unsigned long *mask,
316 struct gpio_rcar_priv *p = gpiochip_get_data(chip);
317 u32 bankmask, outputs, m, val = 0;
320 bankmask = mask[0] & GENMASK(chip->ngpio - 1, 0);
321 if (chip->valid_mask)
322 bankmask &= chip->valid_mask[0];
327 spin_lock_irqsave(&p->lock, flags);
328 outputs = gpio_rcar_read(p, INOUTSEL);
329 m = outputs & bankmask;
331 val |= gpio_rcar_read(p, OUTDT) & m;
333 m = ~outputs & bankmask;
335 val |= gpio_rcar_read(p, INDT) & m;
336 spin_unlock_irqrestore(&p->lock, flags);
342 static void gpio_rcar_set(struct gpio_chip *chip, unsigned offset, int value)
344 struct gpio_rcar_priv *p = gpiochip_get_data(chip);
347 spin_lock_irqsave(&p->lock, flags);
348 gpio_rcar_modify_bit(p, OUTDT, offset, value);
349 spin_unlock_irqrestore(&p->lock, flags);
352 static void gpio_rcar_set_multiple(struct gpio_chip *chip, unsigned long *mask,
355 struct gpio_rcar_priv *p = gpiochip_get_data(chip);
359 bankmask = mask[0] & GENMASK(chip->ngpio - 1, 0);
360 if (chip->valid_mask)
361 bankmask &= chip->valid_mask[0];
366 spin_lock_irqsave(&p->lock, flags);
367 val = gpio_rcar_read(p, OUTDT);
369 val |= (bankmask & bits[0]);
370 gpio_rcar_write(p, OUTDT, val);
371 spin_unlock_irqrestore(&p->lock, flags);
374 static int gpio_rcar_direction_output(struct gpio_chip *chip, unsigned offset,
377 /* write GPIO value to output before selecting output mode of pin */
378 gpio_rcar_set(chip, offset, value);
379 gpio_rcar_config_general_input_output_mode(chip, offset, true);
383 static const struct gpio_rcar_info gpio_rcar_info_gen1 = {
384 .has_outdtsel = false,
385 .has_both_edge_trigger = false,
388 static const struct gpio_rcar_info gpio_rcar_info_gen2 = {
389 .has_outdtsel = true,
390 .has_both_edge_trigger = true,
393 static const struct of_device_id gpio_rcar_of_table[] = {
395 .compatible = "renesas,gpio-r8a7743",
396 /* RZ/G1 GPIO is identical to R-Car Gen2. */
397 .data = &gpio_rcar_info_gen2,
399 .compatible = "renesas,gpio-r8a7790",
400 .data = &gpio_rcar_info_gen2,
402 .compatible = "renesas,gpio-r8a7791",
403 .data = &gpio_rcar_info_gen2,
405 .compatible = "renesas,gpio-r8a7792",
406 .data = &gpio_rcar_info_gen2,
408 .compatible = "renesas,gpio-r8a7793",
409 .data = &gpio_rcar_info_gen2,
411 .compatible = "renesas,gpio-r8a7794",
412 .data = &gpio_rcar_info_gen2,
414 .compatible = "renesas,gpio-r8a7795",
415 /* Gen3 GPIO is identical to Gen2. */
416 .data = &gpio_rcar_info_gen2,
418 .compatible = "renesas,gpio-r8a7796",
419 /* Gen3 GPIO is identical to Gen2. */
420 .data = &gpio_rcar_info_gen2,
422 .compatible = "renesas,rcar-gen1-gpio",
423 .data = &gpio_rcar_info_gen1,
425 .compatible = "renesas,rcar-gen2-gpio",
426 .data = &gpio_rcar_info_gen2,
428 .compatible = "renesas,rcar-gen3-gpio",
429 /* Gen3 GPIO is identical to Gen2. */
430 .data = &gpio_rcar_info_gen2,
432 .compatible = "renesas,gpio-rcar",
433 .data = &gpio_rcar_info_gen1,
439 MODULE_DEVICE_TABLE(of, gpio_rcar_of_table);
441 static int gpio_rcar_parse_dt(struct gpio_rcar_priv *p, unsigned int *npins)
443 struct device_node *np = p->dev->of_node;
444 const struct gpio_rcar_info *info;
445 struct of_phandle_args args;
448 info = of_device_get_match_data(p->dev);
451 ret = of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, 0, &args);
452 *npins = ret == 0 ? args.args[2] : RCAR_MAX_GPIO_PER_BANK;
454 if (*npins == 0 || *npins > RCAR_MAX_GPIO_PER_BANK) {
455 dev_warn(p->dev, "Invalid number of gpio lines %u, using %u\n",
456 *npins, RCAR_MAX_GPIO_PER_BANK);
457 *npins = RCAR_MAX_GPIO_PER_BANK;
463 static int gpio_rcar_probe(struct platform_device *pdev)
465 struct gpio_rcar_priv *p;
466 struct resource *irq;
467 struct gpio_chip *gpio_chip;
468 struct irq_chip *irq_chip;
469 struct gpio_irq_chip *girq;
470 struct device *dev = &pdev->dev;
471 const char *name = dev_name(dev);
475 p = devm_kzalloc(dev, sizeof(*p), GFP_KERNEL);
480 spin_lock_init(&p->lock);
482 /* Get device configuration from DT node */
483 ret = gpio_rcar_parse_dt(p, &npins);
487 platform_set_drvdata(pdev, p);
489 pm_runtime_enable(dev);
491 irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
493 dev_err(dev, "missing IRQ\n");
498 p->base = devm_platform_ioremap_resource(pdev, 0);
499 if (IS_ERR(p->base)) {
500 ret = PTR_ERR(p->base);
504 gpio_chip = &p->gpio_chip;
505 gpio_chip->request = gpio_rcar_request;
506 gpio_chip->free = gpio_rcar_free;
507 gpio_chip->get_direction = gpio_rcar_get_direction;
508 gpio_chip->direction_input = gpio_rcar_direction_input;
509 gpio_chip->get = gpio_rcar_get;
510 gpio_chip->get_multiple = gpio_rcar_get_multiple;
511 gpio_chip->direction_output = gpio_rcar_direction_output;
512 gpio_chip->set = gpio_rcar_set;
513 gpio_chip->set_multiple = gpio_rcar_set_multiple;
514 gpio_chip->label = name;
515 gpio_chip->parent = dev;
516 gpio_chip->owner = THIS_MODULE;
517 gpio_chip->base = -1;
518 gpio_chip->ngpio = npins;
520 irq_chip = &p->irq_chip;
521 irq_chip->name = "gpio-rcar";
522 irq_chip->parent_device = dev;
523 irq_chip->irq_mask = gpio_rcar_irq_disable;
524 irq_chip->irq_unmask = gpio_rcar_irq_enable;
525 irq_chip->irq_set_type = gpio_rcar_irq_set_type;
526 irq_chip->irq_set_wake = gpio_rcar_irq_set_wake;
527 irq_chip->flags = IRQCHIP_SET_TYPE_MASKED | IRQCHIP_MASK_ON_SUSPEND;
529 girq = &gpio_chip->irq;
530 girq->chip = irq_chip;
531 /* This will let us handle the parent IRQ in the driver */
532 girq->parent_handler = NULL;
533 girq->num_parents = 0;
534 girq->parents = NULL;
535 girq->default_type = IRQ_TYPE_NONE;
536 girq->handler = handle_level_irq;
538 ret = gpiochip_add_data(gpio_chip, p);
540 dev_err(dev, "failed to add GPIO controller\n");
544 p->irq_parent = irq->start;
545 if (devm_request_irq(dev, irq->start, gpio_rcar_irq_handler,
546 IRQF_SHARED, name, p)) {
547 dev_err(dev, "failed to request IRQ\n");
552 dev_info(dev, "driving %d GPIOs\n", npins);
557 gpiochip_remove(gpio_chip);
559 pm_runtime_disable(dev);
563 static int gpio_rcar_remove(struct platform_device *pdev)
565 struct gpio_rcar_priv *p = platform_get_drvdata(pdev);
567 gpiochip_remove(&p->gpio_chip);
569 pm_runtime_disable(&pdev->dev);
573 #ifdef CONFIG_PM_SLEEP
574 static int gpio_rcar_suspend(struct device *dev)
576 struct gpio_rcar_priv *p = dev_get_drvdata(dev);
578 p->bank_info.iointsel = gpio_rcar_read(p, IOINTSEL);
579 p->bank_info.inoutsel = gpio_rcar_read(p, INOUTSEL);
580 p->bank_info.outdt = gpio_rcar_read(p, OUTDT);
581 p->bank_info.intmsk = gpio_rcar_read(p, INTMSK);
582 p->bank_info.posneg = gpio_rcar_read(p, POSNEG);
583 p->bank_info.edglevel = gpio_rcar_read(p, EDGLEVEL);
584 if (p->info.has_both_edge_trigger)
585 p->bank_info.bothedge = gpio_rcar_read(p, BOTHEDGE);
587 if (atomic_read(&p->wakeup_path))
588 device_set_wakeup_path(dev);
593 static int gpio_rcar_resume(struct device *dev)
595 struct gpio_rcar_priv *p = dev_get_drvdata(dev);
599 for (offset = 0; offset < p->gpio_chip.ngpio; offset++) {
600 if (!gpiochip_line_is_valid(&p->gpio_chip, offset))
605 if (!(p->bank_info.iointsel & mask)) {
606 if (p->bank_info.inoutsel & mask)
607 gpio_rcar_direction_output(
608 &p->gpio_chip, offset,
609 !!(p->bank_info.outdt & mask));
611 gpio_rcar_direction_input(&p->gpio_chip,
615 gpio_rcar_config_interrupt_input_mode(
618 !(p->bank_info.posneg & mask),
619 !(p->bank_info.edglevel & mask),
620 !!(p->bank_info.bothedge & mask));
622 if (p->bank_info.intmsk & mask)
623 gpio_rcar_write(p, MSKCLR, mask);
629 #endif /* CONFIG_PM_SLEEP*/
631 static SIMPLE_DEV_PM_OPS(gpio_rcar_pm_ops, gpio_rcar_suspend, gpio_rcar_resume);
633 static struct platform_driver gpio_rcar_device_driver = {
634 .probe = gpio_rcar_probe,
635 .remove = gpio_rcar_remove,
638 .pm = &gpio_rcar_pm_ops,
639 .of_match_table = of_match_ptr(gpio_rcar_of_table),
643 module_platform_driver(gpio_rcar_device_driver);
645 MODULE_AUTHOR("Magnus Damm");
646 MODULE_DESCRIPTION("Renesas R-Car GPIO Driver");
647 MODULE_LICENSE("GPL v2");