2 * Renesas R-Car GPIO Support
4 * Copyright (C) 2014 Renesas Electronics Corporation
5 * Copyright (C) 2013 Magnus Damm
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
17 #include <linux/err.h>
18 #include <linux/gpio.h>
19 #include <linux/init.h>
20 #include <linux/interrupt.h>
22 #include <linux/ioport.h>
23 #include <linux/irq.h>
24 #include <linux/module.h>
26 #include <linux/of_device.h>
27 #include <linux/pinctrl/consumer.h>
28 #include <linux/platform_device.h>
29 #include <linux/pm_runtime.h>
30 #include <linux/spinlock.h>
31 #include <linux/slab.h>
33 struct gpio_rcar_priv {
36 struct platform_device *pdev;
37 struct gpio_chip gpio_chip;
38 struct irq_chip irq_chip;
39 unsigned int irq_parent;
41 bool has_both_edge_trigger;
44 #define IOINTSEL 0x00 /* General IO/Interrupt Switching Register */
45 #define INOUTSEL 0x04 /* General Input/Output Switching Register */
46 #define OUTDT 0x08 /* General Output Register */
47 #define INDT 0x0c /* General Input Register */
48 #define INTDT 0x10 /* Interrupt Display Register */
49 #define INTCLR 0x14 /* Interrupt Clear Register */
50 #define INTMSK 0x18 /* Interrupt Mask Register */
51 #define MSKCLR 0x1c /* Interrupt Mask Clear Register */
52 #define POSNEG 0x20 /* Positive/Negative Logic Select Register */
53 #define EDGLEVEL 0x24 /* Edge/level Select Register */
54 #define FILONOFF 0x28 /* Chattering Prevention On/Off Register */
55 #define BOTHEDGE 0x4c /* One Edge/Both Edge Select Register */
57 #define RCAR_MAX_GPIO_PER_BANK 32
59 static inline u32 gpio_rcar_read(struct gpio_rcar_priv *p, int offs)
61 return ioread32(p->base + offs);
64 static inline void gpio_rcar_write(struct gpio_rcar_priv *p, int offs,
67 iowrite32(value, p->base + offs);
70 static void gpio_rcar_modify_bit(struct gpio_rcar_priv *p, int offs,
73 u32 tmp = gpio_rcar_read(p, offs);
80 gpio_rcar_write(p, offs, tmp);
83 static void gpio_rcar_irq_disable(struct irq_data *d)
85 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
86 struct gpio_rcar_priv *p = gpiochip_get_data(gc);
88 gpio_rcar_write(p, INTMSK, ~BIT(irqd_to_hwirq(d)));
91 static void gpio_rcar_irq_enable(struct irq_data *d)
93 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
94 struct gpio_rcar_priv *p = gpiochip_get_data(gc);
96 gpio_rcar_write(p, MSKCLR, BIT(irqd_to_hwirq(d)));
99 static void gpio_rcar_config_interrupt_input_mode(struct gpio_rcar_priv *p,
101 bool active_high_rising_edge,
107 /* follow steps in the GPIO documentation for
108 * "Setting Edge-Sensitive Interrupt Input Mode" and
109 * "Setting Level-Sensitive Interrupt Input Mode"
112 spin_lock_irqsave(&p->lock, flags);
114 /* Configure postive or negative logic in POSNEG */
115 gpio_rcar_modify_bit(p, POSNEG, hwirq, !active_high_rising_edge);
117 /* Configure edge or level trigger in EDGLEVEL */
118 gpio_rcar_modify_bit(p, EDGLEVEL, hwirq, !level_trigger);
120 /* Select one edge or both edges in BOTHEDGE */
121 if (p->has_both_edge_trigger)
122 gpio_rcar_modify_bit(p, BOTHEDGE, hwirq, both);
124 /* Select "Interrupt Input Mode" in IOINTSEL */
125 gpio_rcar_modify_bit(p, IOINTSEL, hwirq, true);
127 /* Write INTCLR in case of edge trigger */
129 gpio_rcar_write(p, INTCLR, BIT(hwirq));
131 spin_unlock_irqrestore(&p->lock, flags);
134 static int gpio_rcar_irq_set_type(struct irq_data *d, unsigned int type)
136 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
137 struct gpio_rcar_priv *p = gpiochip_get_data(gc);
138 unsigned int hwirq = irqd_to_hwirq(d);
140 dev_dbg(&p->pdev->dev, "sense irq = %d, type = %d\n", hwirq, type);
142 switch (type & IRQ_TYPE_SENSE_MASK) {
143 case IRQ_TYPE_LEVEL_HIGH:
144 gpio_rcar_config_interrupt_input_mode(p, hwirq, true, true,
147 case IRQ_TYPE_LEVEL_LOW:
148 gpio_rcar_config_interrupt_input_mode(p, hwirq, false, true,
151 case IRQ_TYPE_EDGE_RISING:
152 gpio_rcar_config_interrupt_input_mode(p, hwirq, true, false,
155 case IRQ_TYPE_EDGE_FALLING:
156 gpio_rcar_config_interrupt_input_mode(p, hwirq, false, false,
159 case IRQ_TYPE_EDGE_BOTH:
160 if (!p->has_both_edge_trigger)
162 gpio_rcar_config_interrupt_input_mode(p, hwirq, true, false,
171 static int gpio_rcar_irq_set_wake(struct irq_data *d, unsigned int on)
173 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
174 struct gpio_rcar_priv *p = gpiochip_get_data(gc);
178 error = irq_set_irq_wake(p->irq_parent, on);
180 dev_dbg(&p->pdev->dev,
181 "irq %u doesn't support irq_set_wake\n",
188 atomic_inc(&p->wakeup_path);
190 atomic_dec(&p->wakeup_path);
195 static irqreturn_t gpio_rcar_irq_handler(int irq, void *dev_id)
197 struct gpio_rcar_priv *p = dev_id;
199 unsigned int offset, irqs_handled = 0;
201 while ((pending = gpio_rcar_read(p, INTDT) &
202 gpio_rcar_read(p, INTMSK))) {
203 offset = __ffs(pending);
204 gpio_rcar_write(p, INTCLR, BIT(offset));
205 generic_handle_irq(irq_find_mapping(p->gpio_chip.irq.domain,
210 return irqs_handled ? IRQ_HANDLED : IRQ_NONE;
213 static void gpio_rcar_config_general_input_output_mode(struct gpio_chip *chip,
217 struct gpio_rcar_priv *p = gpiochip_get_data(chip);
220 /* follow steps in the GPIO documentation for
221 * "Setting General Output Mode" and
222 * "Setting General Input Mode"
225 spin_lock_irqsave(&p->lock, flags);
227 /* Configure postive logic in POSNEG */
228 gpio_rcar_modify_bit(p, POSNEG, gpio, false);
230 /* Select "General Input/Output Mode" in IOINTSEL */
231 gpio_rcar_modify_bit(p, IOINTSEL, gpio, false);
233 /* Select Input Mode or Output Mode in INOUTSEL */
234 gpio_rcar_modify_bit(p, INOUTSEL, gpio, output);
236 spin_unlock_irqrestore(&p->lock, flags);
239 static int gpio_rcar_request(struct gpio_chip *chip, unsigned offset)
241 struct gpio_rcar_priv *p = gpiochip_get_data(chip);
244 error = pm_runtime_get_sync(&p->pdev->dev);
248 error = pinctrl_gpio_request(chip->base + offset);
250 pm_runtime_put(&p->pdev->dev);
255 static void gpio_rcar_free(struct gpio_chip *chip, unsigned offset)
257 struct gpio_rcar_priv *p = gpiochip_get_data(chip);
259 pinctrl_gpio_free(chip->base + offset);
262 * Set the GPIO as an input to ensure that the next GPIO request won't
263 * drive the GPIO pin as an output.
265 gpio_rcar_config_general_input_output_mode(chip, offset, false);
267 pm_runtime_put(&p->pdev->dev);
270 static int gpio_rcar_direction_input(struct gpio_chip *chip, unsigned offset)
272 gpio_rcar_config_general_input_output_mode(chip, offset, false);
276 static int gpio_rcar_get(struct gpio_chip *chip, unsigned offset)
278 u32 bit = BIT(offset);
280 /* testing on r8a7790 shows that INDT does not show correct pin state
281 * when configured as output, so use OUTDT in case of output pins */
282 if (gpio_rcar_read(gpiochip_get_data(chip), INOUTSEL) & bit)
283 return !!(gpio_rcar_read(gpiochip_get_data(chip), OUTDT) & bit);
285 return !!(gpio_rcar_read(gpiochip_get_data(chip), INDT) & bit);
288 static void gpio_rcar_set(struct gpio_chip *chip, unsigned offset, int value)
290 struct gpio_rcar_priv *p = gpiochip_get_data(chip);
293 spin_lock_irqsave(&p->lock, flags);
294 gpio_rcar_modify_bit(p, OUTDT, offset, value);
295 spin_unlock_irqrestore(&p->lock, flags);
298 static void gpio_rcar_set_multiple(struct gpio_chip *chip, unsigned long *mask,
301 struct gpio_rcar_priv *p = gpiochip_get_data(chip);
305 bankmask = mask[0] & GENMASK(chip->ngpio - 1, 0);
309 spin_lock_irqsave(&p->lock, flags);
310 val = gpio_rcar_read(p, OUTDT);
312 val |= (bankmask & bits[0]);
313 gpio_rcar_write(p, OUTDT, val);
314 spin_unlock_irqrestore(&p->lock, flags);
317 static int gpio_rcar_direction_output(struct gpio_chip *chip, unsigned offset,
320 /* write GPIO value to output before selecting output mode of pin */
321 gpio_rcar_set(chip, offset, value);
322 gpio_rcar_config_general_input_output_mode(chip, offset, true);
326 struct gpio_rcar_info {
327 bool has_both_edge_trigger;
330 static const struct gpio_rcar_info gpio_rcar_info_gen1 = {
331 .has_both_edge_trigger = false,
334 static const struct gpio_rcar_info gpio_rcar_info_gen2 = {
335 .has_both_edge_trigger = true,
338 static const struct of_device_id gpio_rcar_of_table[] = {
340 .compatible = "renesas,gpio-r8a7743",
341 /* RZ/G1 GPIO is identical to R-Car Gen2. */
342 .data = &gpio_rcar_info_gen2,
344 .compatible = "renesas,gpio-r8a7790",
345 .data = &gpio_rcar_info_gen2,
347 .compatible = "renesas,gpio-r8a7791",
348 .data = &gpio_rcar_info_gen2,
350 .compatible = "renesas,gpio-r8a7792",
351 .data = &gpio_rcar_info_gen2,
353 .compatible = "renesas,gpio-r8a7793",
354 .data = &gpio_rcar_info_gen2,
356 .compatible = "renesas,gpio-r8a7794",
357 .data = &gpio_rcar_info_gen2,
359 .compatible = "renesas,gpio-r8a7795",
360 /* Gen3 GPIO is identical to Gen2. */
361 .data = &gpio_rcar_info_gen2,
363 .compatible = "renesas,gpio-r8a7796",
364 /* Gen3 GPIO is identical to Gen2. */
365 .data = &gpio_rcar_info_gen2,
367 .compatible = "renesas,rcar-gen1-gpio",
368 .data = &gpio_rcar_info_gen1,
370 .compatible = "renesas,rcar-gen2-gpio",
371 .data = &gpio_rcar_info_gen2,
373 .compatible = "renesas,rcar-gen3-gpio",
374 /* Gen3 GPIO is identical to Gen2. */
375 .data = &gpio_rcar_info_gen2,
377 .compatible = "renesas,gpio-rcar",
378 .data = &gpio_rcar_info_gen1,
384 MODULE_DEVICE_TABLE(of, gpio_rcar_of_table);
386 static int gpio_rcar_parse_dt(struct gpio_rcar_priv *p, unsigned int *npins)
388 struct device_node *np = p->pdev->dev.of_node;
389 const struct gpio_rcar_info *info;
390 struct of_phandle_args args;
393 info = of_device_get_match_data(&p->pdev->dev);
395 ret = of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, 0, &args);
396 *npins = ret == 0 ? args.args[2] : RCAR_MAX_GPIO_PER_BANK;
397 p->has_both_edge_trigger = info->has_both_edge_trigger;
399 if (*npins == 0 || *npins > RCAR_MAX_GPIO_PER_BANK) {
400 dev_warn(&p->pdev->dev,
401 "Invalid number of gpio lines %u, using %u\n", *npins,
402 RCAR_MAX_GPIO_PER_BANK);
403 *npins = RCAR_MAX_GPIO_PER_BANK;
409 static int gpio_rcar_probe(struct platform_device *pdev)
411 struct gpio_rcar_priv *p;
412 struct resource *io, *irq;
413 struct gpio_chip *gpio_chip;
414 struct irq_chip *irq_chip;
415 struct device *dev = &pdev->dev;
416 const char *name = dev_name(dev);
420 p = devm_kzalloc(dev, sizeof(*p), GFP_KERNEL);
425 spin_lock_init(&p->lock);
427 /* Get device configuration from DT node */
428 ret = gpio_rcar_parse_dt(p, &npins);
432 platform_set_drvdata(pdev, p);
434 pm_runtime_enable(dev);
436 irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
438 dev_err(dev, "missing IRQ\n");
443 io = platform_get_resource(pdev, IORESOURCE_MEM, 0);
444 p->base = devm_ioremap_resource(dev, io);
445 if (IS_ERR(p->base)) {
446 ret = PTR_ERR(p->base);
450 gpio_chip = &p->gpio_chip;
451 gpio_chip->request = gpio_rcar_request;
452 gpio_chip->free = gpio_rcar_free;
453 gpio_chip->direction_input = gpio_rcar_direction_input;
454 gpio_chip->get = gpio_rcar_get;
455 gpio_chip->direction_output = gpio_rcar_direction_output;
456 gpio_chip->set = gpio_rcar_set;
457 gpio_chip->set_multiple = gpio_rcar_set_multiple;
458 gpio_chip->label = name;
459 gpio_chip->parent = dev;
460 gpio_chip->owner = THIS_MODULE;
461 gpio_chip->base = -1;
462 gpio_chip->ngpio = npins;
464 irq_chip = &p->irq_chip;
465 irq_chip->name = name;
466 irq_chip->parent_device = dev;
467 irq_chip->irq_mask = gpio_rcar_irq_disable;
468 irq_chip->irq_unmask = gpio_rcar_irq_enable;
469 irq_chip->irq_set_type = gpio_rcar_irq_set_type;
470 irq_chip->irq_set_wake = gpio_rcar_irq_set_wake;
471 irq_chip->flags = IRQCHIP_SET_TYPE_MASKED | IRQCHIP_MASK_ON_SUSPEND;
473 ret = gpiochip_add_data(gpio_chip, p);
475 dev_err(dev, "failed to add GPIO controller\n");
479 ret = gpiochip_irqchip_add(gpio_chip, irq_chip, 0, handle_level_irq,
482 dev_err(dev, "cannot add irqchip\n");
486 p->irq_parent = irq->start;
487 if (devm_request_irq(dev, irq->start, gpio_rcar_irq_handler,
488 IRQF_SHARED, name, p)) {
489 dev_err(dev, "failed to request IRQ\n");
494 dev_info(dev, "driving %d GPIOs\n", npins);
499 gpiochip_remove(gpio_chip);
501 pm_runtime_disable(dev);
505 static int gpio_rcar_remove(struct platform_device *pdev)
507 struct gpio_rcar_priv *p = platform_get_drvdata(pdev);
509 gpiochip_remove(&p->gpio_chip);
511 pm_runtime_disable(&pdev->dev);
515 static int __maybe_unused gpio_rcar_suspend(struct device *dev)
517 struct gpio_rcar_priv *p = dev_get_drvdata(dev);
519 if (atomic_read(&p->wakeup_path))
520 device_set_wakeup_path(dev);
525 static SIMPLE_DEV_PM_OPS(gpio_rcar_pm_ops, gpio_rcar_suspend, NULL);
527 static struct platform_driver gpio_rcar_device_driver = {
528 .probe = gpio_rcar_probe,
529 .remove = gpio_rcar_remove,
532 .pm = &gpio_rcar_pm_ops,
533 .of_match_table = of_match_ptr(gpio_rcar_of_table),
537 module_platform_driver(gpio_rcar_device_driver);
539 MODULE_AUTHOR("Magnus Damm");
540 MODULE_DESCRIPTION("Renesas R-Car GPIO Driver");
541 MODULE_LICENSE("GPL v2");