2 * linux/arch/arm/plat-pxa/gpio.c
4 * Generic PXA GPIO handling
6 * Author: Nicolas Pitre
7 * Created: Jun 15, 2001
8 * Copyright: MontaVista Software Inc.
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
14 #include <linux/module.h>
15 #include <linux/clk.h>
16 #include <linux/err.h>
17 #include <linux/gpio.h>
18 #include <linux/gpio-pxa.h>
19 #include <linux/init.h>
20 #include <linux/interrupt.h>
21 #include <linux/irq.h>
22 #include <linux/irqdomain.h>
23 #include <linux/irqchip/chained_irq.h>
26 #include <linux/of_device.h>
27 #include <linux/pinctrl/consumer.h>
28 #include <linux/platform_device.h>
29 #include <linux/syscore_ops.h>
30 #include <linux/slab.h>
33 * We handle the GPIOs by banks, each bank covers up to 32 GPIOs with
34 * one set of registers. The register offsets are organized below:
36 * GPLR GPDR GPSR GPCR GRER GFER GEDR
37 * BANK 0 - 0x0000 0x000C 0x0018 0x0024 0x0030 0x003C 0x0048
38 * BANK 1 - 0x0004 0x0010 0x001C 0x0028 0x0034 0x0040 0x004C
39 * BANK 2 - 0x0008 0x0014 0x0020 0x002C 0x0038 0x0044 0x0050
41 * BANK 3 - 0x0100 0x010C 0x0118 0x0124 0x0130 0x013C 0x0148
42 * BANK 4 - 0x0104 0x0110 0x011C 0x0128 0x0134 0x0140 0x014C
43 * BANK 5 - 0x0108 0x0114 0x0120 0x012C 0x0138 0x0144 0x0150
45 * BANK 6 - 0x0200 0x020C 0x0218 0x0224 0x0230 0x023C 0x0248
48 * BANK 3 is only available on PXA27x and later processors.
49 * BANK 4 and 5 are only available on PXA935, PXA1928
50 * BANK 6 is only available on PXA1928
53 #define GPLR_OFFSET 0x00
54 #define GPDR_OFFSET 0x0C
55 #define GPSR_OFFSET 0x18
56 #define GPCR_OFFSET 0x24
57 #define GRER_OFFSET 0x30
58 #define GFER_OFFSET 0x3C
59 #define GEDR_OFFSET 0x48
60 #define GAFR_OFFSET 0x54
61 #define ED_MASK_OFFSET 0x9C /* GPIO edge detection for AP side */
63 #define BANK_OFF(n) (((n) / 3) << 8) + (((n) % 3) << 2)
68 struct pxa_gpio_bank {
69 void __iomem *regbase;
70 unsigned long irq_mask;
71 unsigned long irq_edge_rise;
72 unsigned long irq_edge_fall;
75 unsigned long saved_gplr;
76 unsigned long saved_gpdr;
77 unsigned long saved_grer;
78 unsigned long saved_gfer;
82 struct pxa_gpio_chip {
84 struct gpio_chip chip;
85 struct pxa_gpio_bank *banks;
86 struct irq_domain *irqdomain;
90 int (*set_wake)(unsigned int gpio, unsigned int on);
105 enum pxa_gpio_type type;
109 static DEFINE_SPINLOCK(gpio_lock);
110 static struct pxa_gpio_chip *pxa_gpio_chip;
111 static enum pxa_gpio_type gpio_type;
113 static struct pxa_gpio_id pxa25x_id = {
118 static struct pxa_gpio_id pxa26x_id = {
123 static struct pxa_gpio_id pxa27x_id = {
128 static struct pxa_gpio_id pxa3xx_id = {
133 static struct pxa_gpio_id pxa93x_id = {
138 static struct pxa_gpio_id mmp_id = {
143 static struct pxa_gpio_id mmp2_id = {
148 static struct pxa_gpio_id pxa1928_id = {
149 .type = PXA1928_GPIO,
153 #define for_each_gpio_bank(i, b, pc) \
154 for (i = 0, b = pc->banks; i <= pxa_last_gpio; i += 32, b++)
156 static inline struct pxa_gpio_chip *chip_to_pxachip(struct gpio_chip *c)
158 struct pxa_gpio_chip *pxa_chip =
159 container_of(c, struct pxa_gpio_chip, chip);
163 static inline void __iomem *gpio_bank_base(struct gpio_chip *c, int gpio)
165 struct pxa_gpio_bank *bank = chip_to_pxachip(c)->banks + (gpio / 32);
167 return bank->regbase;
170 static inline struct pxa_gpio_bank *gpio_to_pxabank(struct gpio_chip *c,
173 return chip_to_pxachip(c)->banks + gpio / 32;
176 static inline int gpio_is_pxa_type(int type)
178 return (type & MMP_GPIO) == 0;
181 static inline int gpio_is_mmp_type(int type)
183 return (type & MMP_GPIO) != 0;
186 /* GPIO86/87/88/89 on PXA26x have their direction bits in PXA_GPDR(2 inverted,
187 * as well as their Alternate Function value being '1' for GPIO in GAFRx.
189 static inline int __gpio_is_inverted(int gpio)
191 if ((gpio_type == PXA26X_GPIO) && (gpio > 85))
197 * On PXA25x and PXA27x, GAFRx and GPDRx together decide the alternate
198 * function of a GPIO, and GPDRx cannot be altered once configured. It
199 * is attributed as "occupied" here (I know this terminology isn't
200 * accurate, you are welcome to propose a better one :-)
202 static inline int __gpio_is_occupied(struct pxa_gpio_chip *pchip, unsigned gpio)
205 unsigned long gafr = 0, gpdr = 0;
206 int ret, af = 0, dir = 0;
208 base = gpio_bank_base(&pchip->chip, gpio);
209 gpdr = readl_relaxed(base + GPDR_OFFSET);
215 gafr = readl_relaxed(base + GAFR_OFFSET);
216 af = (gafr >> ((gpio & 0xf) * 2)) & 0x3;
217 dir = gpdr & GPIO_bit(gpio);
219 if (__gpio_is_inverted(gpio))
220 ret = (af != 1) || (dir == 0);
222 ret = (af != 0) || (dir != 0);
225 ret = gpdr & GPIO_bit(gpio);
231 int pxa_irq_to_gpio(int irq)
233 struct pxa_gpio_chip *pchip = pxa_gpio_chip;
236 irq_gpio0 = irq_find_mapping(pchip->irqdomain, 0);
238 return irq - irq_gpio0;
243 static int pxa_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
245 struct pxa_gpio_chip *pchip = chip_to_pxachip(chip);
247 return irq_find_mapping(pchip->irqdomain, offset);
250 static int pxa_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
252 void __iomem *base = gpio_bank_base(chip, offset);
253 uint32_t value, mask = GPIO_bit(offset);
257 ret = pinctrl_gpio_direction_input(chip->base + offset);
261 spin_lock_irqsave(&gpio_lock, flags);
263 value = readl_relaxed(base + GPDR_OFFSET);
264 if (__gpio_is_inverted(chip->base + offset))
268 writel_relaxed(value, base + GPDR_OFFSET);
270 spin_unlock_irqrestore(&gpio_lock, flags);
274 static int pxa_gpio_direction_output(struct gpio_chip *chip,
275 unsigned offset, int value)
277 void __iomem *base = gpio_bank_base(chip, offset);
278 uint32_t tmp, mask = GPIO_bit(offset);
282 writel_relaxed(mask, base + (value ? GPSR_OFFSET : GPCR_OFFSET));
284 ret = pinctrl_gpio_direction_output(chip->base + offset);
288 spin_lock_irqsave(&gpio_lock, flags);
290 tmp = readl_relaxed(base + GPDR_OFFSET);
291 if (__gpio_is_inverted(chip->base + offset))
295 writel_relaxed(tmp, base + GPDR_OFFSET);
297 spin_unlock_irqrestore(&gpio_lock, flags);
301 static int pxa_gpio_get(struct gpio_chip *chip, unsigned offset)
303 void __iomem *base = gpio_bank_base(chip, offset);
304 u32 gplr = readl_relaxed(base + GPLR_OFFSET);
306 return !!(gplr & GPIO_bit(offset));
309 static void pxa_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
311 void __iomem *base = gpio_bank_base(chip, offset);
313 writel_relaxed(GPIO_bit(offset),
314 base + (value ? GPSR_OFFSET : GPCR_OFFSET));
317 #ifdef CONFIG_OF_GPIO
318 static int pxa_gpio_of_xlate(struct gpio_chip *gc,
319 const struct of_phandle_args *gpiospec,
322 if (gpiospec->args[0] > pxa_last_gpio)
326 *flags = gpiospec->args[1];
328 return gpiospec->args[0];
332 static int pxa_gpio_request(struct gpio_chip *chip, unsigned int offset)
334 return pinctrl_request_gpio(chip->base + offset);
337 static void pxa_gpio_free(struct gpio_chip *chip, unsigned int offset)
339 pinctrl_free_gpio(chip->base + offset);
342 static int pxa_init_gpio_chip(struct pxa_gpio_chip *pchip, int ngpio,
343 struct device_node *np, void __iomem *regbase)
345 int i, gpio, nbanks = DIV_ROUND_UP(ngpio, 32);
346 struct pxa_gpio_bank *bank;
348 pchip->banks = devm_kcalloc(pchip->dev, nbanks, sizeof(*pchip->banks),
353 pchip->chip.label = "gpio-pxa";
354 pchip->chip.direction_input = pxa_gpio_direction_input;
355 pchip->chip.direction_output = pxa_gpio_direction_output;
356 pchip->chip.get = pxa_gpio_get;
357 pchip->chip.set = pxa_gpio_set;
358 pchip->chip.to_irq = pxa_gpio_to_irq;
359 pchip->chip.ngpio = ngpio;
360 pchip->chip.request = pxa_gpio_request;
361 pchip->chip.free = pxa_gpio_free;
362 #ifdef CONFIG_OF_GPIO
363 pchip->chip.of_node = np;
364 pchip->chip.of_xlate = pxa_gpio_of_xlate;
365 pchip->chip.of_gpio_n_cells = 2;
368 for (i = 0, gpio = 0; i < nbanks; i++, gpio += 32) {
369 bank = pchip->banks + i;
370 bank->regbase = regbase + BANK_OFF(i);
373 return gpiochip_add(&pchip->chip);
376 /* Update only those GRERx and GFERx edge detection register bits if those
377 * bits are set in c->irq_mask
379 static inline void update_edge_detect(struct pxa_gpio_bank *c)
383 grer = readl_relaxed(c->regbase + GRER_OFFSET) & ~c->irq_mask;
384 gfer = readl_relaxed(c->regbase + GFER_OFFSET) & ~c->irq_mask;
385 grer |= c->irq_edge_rise & c->irq_mask;
386 gfer |= c->irq_edge_fall & c->irq_mask;
387 writel_relaxed(grer, c->regbase + GRER_OFFSET);
388 writel_relaxed(gfer, c->regbase + GFER_OFFSET);
391 static int pxa_gpio_irq_type(struct irq_data *d, unsigned int type)
393 struct pxa_gpio_chip *pchip = irq_data_get_irq_chip_data(d);
394 unsigned int gpio = irqd_to_hwirq(d);
395 struct pxa_gpio_bank *c = gpio_to_pxabank(&pchip->chip, gpio);
396 unsigned long gpdr, mask = GPIO_bit(gpio);
398 if (type == IRQ_TYPE_PROBE) {
399 /* Don't mess with enabled GPIOs using preconfigured edges or
400 * GPIOs set to alternate function or to output during probe
402 if ((c->irq_edge_rise | c->irq_edge_fall) & GPIO_bit(gpio))
405 if (__gpio_is_occupied(pchip, gpio))
408 type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
411 gpdr = readl_relaxed(c->regbase + GPDR_OFFSET);
413 if (__gpio_is_inverted(gpio))
414 writel_relaxed(gpdr | mask, c->regbase + GPDR_OFFSET);
416 writel_relaxed(gpdr & ~mask, c->regbase + GPDR_OFFSET);
418 if (type & IRQ_TYPE_EDGE_RISING)
419 c->irq_edge_rise |= mask;
421 c->irq_edge_rise &= ~mask;
423 if (type & IRQ_TYPE_EDGE_FALLING)
424 c->irq_edge_fall |= mask;
426 c->irq_edge_fall &= ~mask;
428 update_edge_detect(c);
430 pr_debug("%s: IRQ%d (GPIO%d) - edge%s%s\n", __func__, d->irq, gpio,
431 ((type & IRQ_TYPE_EDGE_RISING) ? " rising" : ""),
432 ((type & IRQ_TYPE_EDGE_FALLING) ? " falling" : ""));
436 static irqreturn_t pxa_gpio_demux_handler(int in_irq, void *d)
438 int loop, gpio, n, handled = 0;
440 struct pxa_gpio_chip *pchip = d;
441 struct pxa_gpio_bank *c;
445 for_each_gpio_bank(gpio, c, pchip) {
446 gedr = readl_relaxed(c->regbase + GEDR_OFFSET);
447 gedr = gedr & c->irq_mask;
448 writel_relaxed(gedr, c->regbase + GEDR_OFFSET);
450 for_each_set_bit(n, &gedr, BITS_PER_LONG) {
453 generic_handle_irq(gpio_to_irq(gpio + n));
459 return handled ? IRQ_HANDLED : IRQ_NONE;
462 static irqreturn_t pxa_gpio_direct_handler(int in_irq, void *d)
464 struct pxa_gpio_chip *pchip = d;
466 if (in_irq == pchip->irq0) {
467 generic_handle_irq(gpio_to_irq(0));
468 } else if (in_irq == pchip->irq1) {
469 generic_handle_irq(gpio_to_irq(1));
471 pr_err("%s() unknown irq %d\n", __func__, in_irq);
477 static void pxa_ack_muxed_gpio(struct irq_data *d)
479 struct pxa_gpio_chip *pchip = irq_data_get_irq_chip_data(d);
480 unsigned int gpio = irqd_to_hwirq(d);
481 void __iomem *base = gpio_bank_base(&pchip->chip, gpio);
483 writel_relaxed(GPIO_bit(gpio), base + GEDR_OFFSET);
486 static void pxa_mask_muxed_gpio(struct irq_data *d)
488 struct pxa_gpio_chip *pchip = irq_data_get_irq_chip_data(d);
489 unsigned int gpio = irqd_to_hwirq(d);
490 struct pxa_gpio_bank *b = gpio_to_pxabank(&pchip->chip, gpio);
491 void __iomem *base = gpio_bank_base(&pchip->chip, gpio);
494 b->irq_mask &= ~GPIO_bit(gpio);
496 grer = readl_relaxed(base + GRER_OFFSET) & ~GPIO_bit(gpio);
497 gfer = readl_relaxed(base + GFER_OFFSET) & ~GPIO_bit(gpio);
498 writel_relaxed(grer, base + GRER_OFFSET);
499 writel_relaxed(gfer, base + GFER_OFFSET);
502 static int pxa_gpio_set_wake(struct irq_data *d, unsigned int on)
504 struct pxa_gpio_chip *pchip = irq_data_get_irq_chip_data(d);
505 unsigned int gpio = irqd_to_hwirq(d);
508 return pchip->set_wake(gpio, on);
513 static void pxa_unmask_muxed_gpio(struct irq_data *d)
515 struct pxa_gpio_chip *pchip = irq_data_get_irq_chip_data(d);
516 unsigned int gpio = irqd_to_hwirq(d);
517 struct pxa_gpio_bank *c = gpio_to_pxabank(&pchip->chip, gpio);
519 c->irq_mask |= GPIO_bit(gpio);
520 update_edge_detect(c);
523 static struct irq_chip pxa_muxed_gpio_chip = {
525 .irq_ack = pxa_ack_muxed_gpio,
526 .irq_mask = pxa_mask_muxed_gpio,
527 .irq_unmask = pxa_unmask_muxed_gpio,
528 .irq_set_type = pxa_gpio_irq_type,
529 .irq_set_wake = pxa_gpio_set_wake,
532 static int pxa_gpio_nums(struct platform_device *pdev)
534 const struct platform_device_id *id = platform_get_device_id(pdev);
535 struct pxa_gpio_id *pxa_id = (struct pxa_gpio_id *)id->driver_data;
538 switch (pxa_id->type) {
547 gpio_type = pxa_id->type;
548 count = pxa_id->gpio_nums - 1;
558 static const struct of_device_id pxa_gpio_dt_ids[] = {
559 { .compatible = "intel,pxa25x-gpio", .data = &pxa25x_id, },
560 { .compatible = "intel,pxa26x-gpio", .data = &pxa26x_id, },
561 { .compatible = "intel,pxa27x-gpio", .data = &pxa27x_id, },
562 { .compatible = "intel,pxa3xx-gpio", .data = &pxa3xx_id, },
563 { .compatible = "marvell,pxa93x-gpio", .data = &pxa93x_id, },
564 { .compatible = "marvell,mmp-gpio", .data = &mmp_id, },
565 { .compatible = "marvell,mmp2-gpio", .data = &mmp2_id, },
566 { .compatible = "marvell,pxa1928-gpio", .data = &pxa1928_id, },
570 static int pxa_irq_domain_map(struct irq_domain *d, unsigned int irq,
573 irq_set_chip_and_handler(irq, &pxa_muxed_gpio_chip,
575 irq_set_chip_data(irq, d->host_data);
576 irq_set_noprobe(irq);
580 const struct irq_domain_ops pxa_irq_domain_ops = {
581 .map = pxa_irq_domain_map,
582 .xlate = irq_domain_xlate_twocell,
585 static int pxa_gpio_probe_dt(struct platform_device *pdev,
586 struct pxa_gpio_chip *pchip)
589 const struct of_device_id *of_id =
590 of_match_device(pxa_gpio_dt_ids, &pdev->dev);
591 const struct pxa_gpio_id *gpio_id;
593 if (!of_id || !of_id->data) {
594 dev_err(&pdev->dev, "Failed to find gpio controller\n");
597 gpio_id = of_id->data;
598 gpio_type = gpio_id->type;
600 nr_gpios = gpio_id->gpio_nums;
601 pxa_last_gpio = nr_gpios - 1;
603 irq_base = irq_alloc_descs(-1, 0, nr_gpios, 0);
605 dev_err(&pdev->dev, "Failed to allocate IRQ numbers\n");
611 #define pxa_gpio_probe_dt(pdev, pchip) (-1)
614 static int pxa_gpio_probe(struct platform_device *pdev)
616 struct pxa_gpio_chip *pchip;
617 struct pxa_gpio_bank *c;
618 struct resource *res;
620 struct pxa_gpio_platform_data *info;
621 void __iomem *gpio_reg_base;
623 int irq0 = 0, irq1 = 0, irq_mux, gpio_offset = 0;
625 pchip = devm_kzalloc(&pdev->dev, sizeof(*pchip), GFP_KERNEL);
628 pchip->dev = &pdev->dev;
630 info = dev_get_platdata(&pdev->dev);
632 irq_base = info->irq_base;
635 pxa_last_gpio = pxa_gpio_nums(pdev);
636 pchip->set_wake = info->gpio_set_wake;
638 irq_base = pxa_gpio_probe_dt(pdev, pchip);
646 pchip->irqdomain = irq_domain_add_legacy(pdev->dev.of_node,
647 pxa_last_gpio + 1, irq_base,
648 0, &pxa_irq_domain_ops, pchip);
649 if (IS_ERR(pchip->irqdomain))
650 return PTR_ERR(pchip->irqdomain);
652 irq0 = platform_get_irq_byname(pdev, "gpio0");
653 irq1 = platform_get_irq_byname(pdev, "gpio1");
654 irq_mux = platform_get_irq_byname(pdev, "gpio_mux");
655 if ((irq0 > 0 && irq1 <= 0) || (irq0 <= 0 && irq1 > 0)
661 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
662 gpio_reg_base = devm_ioremap(&pdev->dev, res->start,
670 clk = clk_get(&pdev->dev, NULL);
672 dev_err(&pdev->dev, "Error %ld to get gpio clock\n",
676 ret = clk_prepare_enable(clk);
682 /* Initialize GPIO chips */
683 ret = pxa_init_gpio_chip(pchip, pxa_last_gpio + 1, pdev->dev.of_node,
690 /* clear all GPIO edge detects */
691 for_each_gpio_bank(gpio, c, pchip) {
692 writel_relaxed(0, c->regbase + GFER_OFFSET);
693 writel_relaxed(0, c->regbase + GRER_OFFSET);
694 writel_relaxed(~0, c->regbase + GEDR_OFFSET);
695 /* unmask GPIO edge detect for AP side */
696 if (gpio_is_mmp_type(gpio_type))
697 writel_relaxed(~0, c->regbase + ED_MASK_OFFSET);
701 ret = devm_request_irq(&pdev->dev,
702 irq0, pxa_gpio_direct_handler, 0,
705 dev_err(&pdev->dev, "request of gpio0 irq failed: %d\n",
709 ret = devm_request_irq(&pdev->dev,
710 irq1, pxa_gpio_direct_handler, 0,
713 dev_err(&pdev->dev, "request of gpio1 irq failed: %d\n",
716 ret = devm_request_irq(&pdev->dev,
717 irq_mux, pxa_gpio_demux_handler, 0,
720 dev_err(&pdev->dev, "request of gpio-mux irq failed: %d\n",
723 pxa_gpio_chip = pchip;
728 static const struct platform_device_id gpio_id_table[] = {
729 { "pxa25x-gpio", (unsigned long)&pxa25x_id },
730 { "pxa26x-gpio", (unsigned long)&pxa26x_id },
731 { "pxa27x-gpio", (unsigned long)&pxa27x_id },
732 { "pxa3xx-gpio", (unsigned long)&pxa3xx_id },
733 { "pxa93x-gpio", (unsigned long)&pxa93x_id },
734 { "mmp-gpio", (unsigned long)&mmp_id },
735 { "mmp2-gpio", (unsigned long)&mmp2_id },
736 { "pxa1928-gpio", (unsigned long)&pxa1928_id },
740 static struct platform_driver pxa_gpio_driver = {
741 .probe = pxa_gpio_probe,
744 .of_match_table = of_match_ptr(pxa_gpio_dt_ids),
746 .id_table = gpio_id_table,
749 static int __init pxa_gpio_legacy_init(void)
751 if (of_have_populated_dt())
754 return platform_driver_register(&pxa_gpio_driver);
756 postcore_initcall(pxa_gpio_legacy_init);
758 static int __init pxa_gpio_dt_init(void)
760 if (of_have_populated_dt())
761 return platform_driver_register(&pxa_gpio_driver);
765 device_initcall(pxa_gpio_dt_init);
768 static int pxa_gpio_suspend(void)
770 struct pxa_gpio_chip *pchip = pxa_gpio_chip;
771 struct pxa_gpio_bank *c;
774 for_each_gpio_bank(gpio, c, pchip) {
775 c->saved_gplr = readl_relaxed(c->regbase + GPLR_OFFSET);
776 c->saved_gpdr = readl_relaxed(c->regbase + GPDR_OFFSET);
777 c->saved_grer = readl_relaxed(c->regbase + GRER_OFFSET);
778 c->saved_gfer = readl_relaxed(c->regbase + GFER_OFFSET);
780 /* Clear GPIO transition detect bits */
781 writel_relaxed(0xffffffff, c->regbase + GEDR_OFFSET);
786 static void pxa_gpio_resume(void)
788 struct pxa_gpio_chip *pchip = pxa_gpio_chip;
789 struct pxa_gpio_bank *c;
792 for_each_gpio_bank(gpio, c, pchip) {
793 /* restore level with set/clear */
794 writel_relaxed(c->saved_gplr, c->regbase + GPSR_OFFSET);
795 writel_relaxed(~c->saved_gplr, c->regbase + GPCR_OFFSET);
797 writel_relaxed(c->saved_grer, c->regbase + GRER_OFFSET);
798 writel_relaxed(c->saved_gfer, c->regbase + GFER_OFFSET);
799 writel_relaxed(c->saved_gpdr, c->regbase + GPDR_OFFSET);
803 #define pxa_gpio_suspend NULL
804 #define pxa_gpio_resume NULL
807 struct syscore_ops pxa_gpio_syscore_ops = {
808 .suspend = pxa_gpio_suspend,
809 .resume = pxa_gpio_resume,
812 static int __init pxa_gpio_sysinit(void)
814 register_syscore_ops(&pxa_gpio_syscore_ops);
817 postcore_initcall(pxa_gpio_sysinit);