2 * Support functions for OMAP GPIO
4 * Copyright (C) 2003-2005 Nokia Corporation
5 * Written by Juha Yrjölä <juha.yrjola@nokia.com>
7 * Copyright (C) 2009 Texas Instruments
8 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
15 #include <linux/init.h>
16 #include <linux/module.h>
17 #include <linux/interrupt.h>
18 #include <linux/syscore_ops.h>
19 #include <linux/err.h>
20 #include <linux/clk.h>
22 #include <linux/cpu_pm.h>
23 #include <linux/device.h>
24 #include <linux/pm_runtime.h>
27 #include <linux/of_device.h>
28 #include <linux/gpio/driver.h>
29 #include <linux/bitops.h>
30 #include <linux/platform_data/gpio-omap.h>
32 #define OMAP4_GPIO_DEBOUNCINGTIME_MASK 0xFF
34 #define OMAP_GPIO_QUIRK_IDLE_REMOVE_TRIGGER BIT(2)
53 struct gpio_omap_funcs {
54 void (*idle_enable_level_quirk)(struct gpio_bank *bank);
55 void (*idle_disable_level_quirk)(struct gpio_bank *bank);
59 struct list_head node;
63 u32 enabled_non_wakeup_gpios;
64 struct gpio_regs context;
65 struct gpio_omap_funcs funcs;
70 raw_spinlock_t wa_lock;
71 struct gpio_chip chip;
73 struct notifier_block nb;
74 unsigned int is_suspended:1;
85 int context_loss_count;
86 bool workaround_enabled;
89 void (*set_dataout)(struct gpio_bank *bank, unsigned gpio, int enable);
90 void (*set_dataout_multiple)(struct gpio_bank *bank,
91 unsigned long *mask, unsigned long *bits);
92 int (*get_context_loss_count)(struct device *dev);
94 struct omap_gpio_reg_offs *regs;
97 #define GPIO_MOD_CTRL_BIT BIT(0)
99 #define BANK_USED(bank) (bank->mod_usage || bank->irq_usage)
100 #define LINE_USED(line, offset) (line & (BIT(offset)))
102 static void omap_gpio_unmask_irq(struct irq_data *d);
104 static inline struct gpio_bank *omap_irq_data_get_bank(struct irq_data *d)
106 struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
107 return gpiochip_get_data(chip);
110 static void omap_set_gpio_direction(struct gpio_bank *bank, int gpio,
113 void __iomem *reg = bank->base;
116 reg += bank->regs->direction;
117 l = readl_relaxed(reg);
122 writel_relaxed(l, reg);
123 bank->context.oe = l;
127 /* set data out value using dedicate set/clear register */
128 static void omap_set_gpio_dataout_reg(struct gpio_bank *bank, unsigned offset,
131 void __iomem *reg = bank->base;
135 reg += bank->regs->set_dataout;
136 bank->context.dataout |= l;
138 reg += bank->regs->clr_dataout;
139 bank->context.dataout &= ~l;
142 writel_relaxed(l, reg);
145 /* set data out value using mask register */
146 static void omap_set_gpio_dataout_mask(struct gpio_bank *bank, unsigned offset,
149 void __iomem *reg = bank->base + bank->regs->dataout;
150 u32 gpio_bit = BIT(offset);
153 l = readl_relaxed(reg);
158 writel_relaxed(l, reg);
159 bank->context.dataout = l;
162 static int omap_get_gpio_datain(struct gpio_bank *bank, int offset)
164 void __iomem *reg = bank->base + bank->regs->datain;
166 return (readl_relaxed(reg) & (BIT(offset))) != 0;
169 static int omap_get_gpio_dataout(struct gpio_bank *bank, int offset)
171 void __iomem *reg = bank->base + bank->regs->dataout;
173 return (readl_relaxed(reg) & (BIT(offset))) != 0;
176 /* set multiple data out values using dedicate set/clear register */
177 static void omap_set_gpio_dataout_reg_multiple(struct gpio_bank *bank,
181 void __iomem *reg = bank->base;
185 writel_relaxed(l, reg + bank->regs->set_dataout);
186 bank->context.dataout |= l;
189 writel_relaxed(l, reg + bank->regs->clr_dataout);
190 bank->context.dataout &= ~l;
193 /* set multiple data out values using mask register */
194 static void omap_set_gpio_dataout_mask_multiple(struct gpio_bank *bank,
198 void __iomem *reg = bank->base + bank->regs->dataout;
199 u32 l = (readl_relaxed(reg) & ~*mask) | (*bits & *mask);
201 writel_relaxed(l, reg);
202 bank->context.dataout = l;
205 static unsigned long omap_get_gpio_datain_multiple(struct gpio_bank *bank,
208 void __iomem *reg = bank->base + bank->regs->datain;
210 return readl_relaxed(reg) & *mask;
213 static unsigned long omap_get_gpio_dataout_multiple(struct gpio_bank *bank,
216 void __iomem *reg = bank->base + bank->regs->dataout;
218 return readl_relaxed(reg) & *mask;
221 static inline void omap_gpio_rmw(void __iomem *base, u32 reg, u32 mask, bool set)
223 int l = readl_relaxed(base + reg);
230 writel_relaxed(l, base + reg);
233 static inline void omap_gpio_dbck_enable(struct gpio_bank *bank)
235 if (bank->dbck_enable_mask && !bank->dbck_enabled) {
236 clk_enable(bank->dbck);
237 bank->dbck_enabled = true;
239 writel_relaxed(bank->dbck_enable_mask,
240 bank->base + bank->regs->debounce_en);
244 static inline void omap_gpio_dbck_disable(struct gpio_bank *bank)
246 if (bank->dbck_enable_mask && bank->dbck_enabled) {
248 * Disable debounce before cutting it's clock. If debounce is
249 * enabled but the clock is not, GPIO module seems to be unable
250 * to detect events and generate interrupts at least on OMAP3.
252 writel_relaxed(0, bank->base + bank->regs->debounce_en);
254 clk_disable(bank->dbck);
255 bank->dbck_enabled = false;
260 * omap2_set_gpio_debounce - low level gpio debounce time
261 * @bank: the gpio bank we're acting upon
262 * @offset: the gpio number on this @bank
263 * @debounce: debounce time to use
265 * OMAP's debounce time is in 31us steps
266 * <debounce time> = (GPIO_DEBOUNCINGTIME[7:0].DEBOUNCETIME + 1) x 31
267 * so we need to convert and round up to the closest unit.
269 * Return: 0 on success, negative error otherwise.
271 static int omap2_set_gpio_debounce(struct gpio_bank *bank, unsigned offset,
277 bool enable = !!debounce;
279 if (!bank->dbck_flag)
283 debounce = DIV_ROUND_UP(debounce, 31) - 1;
284 if ((debounce & OMAP4_GPIO_DEBOUNCINGTIME_MASK) != debounce)
290 clk_enable(bank->dbck);
291 reg = bank->base + bank->regs->debounce;
292 writel_relaxed(debounce, reg);
294 reg = bank->base + bank->regs->debounce_en;
295 val = readl_relaxed(reg);
301 bank->dbck_enable_mask = val;
303 writel_relaxed(val, reg);
304 clk_disable(bank->dbck);
306 * Enable debounce clock per module.
307 * This call is mandatory because in omap_gpio_request() when
308 * *_runtime_get_sync() is called, _gpio_dbck_enable() within
309 * runtime callbck fails to turn on dbck because dbck_enable_mask
310 * used within _gpio_dbck_enable() is still not initialized at
311 * that point. Therefore we have to enable dbck here.
313 omap_gpio_dbck_enable(bank);
314 if (bank->dbck_enable_mask) {
315 bank->context.debounce = debounce;
316 bank->context.debounce_en = val;
323 * omap_clear_gpio_debounce - clear debounce settings for a gpio
324 * @bank: the gpio bank we're acting upon
325 * @offset: the gpio number on this @bank
327 * If a gpio is using debounce, then clear the debounce enable bit and if
328 * this is the only gpio in this bank using debounce, then clear the debounce
329 * time too. The debounce clock will also be disabled when calling this function
330 * if this is the only gpio in the bank using debounce.
332 static void omap_clear_gpio_debounce(struct gpio_bank *bank, unsigned offset)
334 u32 gpio_bit = BIT(offset);
336 if (!bank->dbck_flag)
339 if (!(bank->dbck_enable_mask & gpio_bit))
342 bank->dbck_enable_mask &= ~gpio_bit;
343 bank->context.debounce_en &= ~gpio_bit;
344 writel_relaxed(bank->context.debounce_en,
345 bank->base + bank->regs->debounce_en);
347 if (!bank->dbck_enable_mask) {
348 bank->context.debounce = 0;
349 writel_relaxed(bank->context.debounce, bank->base +
350 bank->regs->debounce);
351 clk_disable(bank->dbck);
352 bank->dbck_enabled = false;
356 static inline void omap_set_gpio_trigger(struct gpio_bank *bank, int gpio,
359 void __iomem *base = bank->base;
360 u32 gpio_bit = BIT(gpio);
362 omap_gpio_rmw(base, bank->regs->leveldetect0, gpio_bit,
363 trigger & IRQ_TYPE_LEVEL_LOW);
364 omap_gpio_rmw(base, bank->regs->leveldetect1, gpio_bit,
365 trigger & IRQ_TYPE_LEVEL_HIGH);
366 omap_gpio_rmw(base, bank->regs->risingdetect, gpio_bit,
367 trigger & IRQ_TYPE_EDGE_RISING);
368 omap_gpio_rmw(base, bank->regs->fallingdetect, gpio_bit,
369 trigger & IRQ_TYPE_EDGE_FALLING);
371 bank->context.leveldetect0 =
372 readl_relaxed(bank->base + bank->regs->leveldetect0);
373 bank->context.leveldetect1 =
374 readl_relaxed(bank->base + bank->regs->leveldetect1);
375 bank->context.risingdetect =
376 readl_relaxed(bank->base + bank->regs->risingdetect);
377 bank->context.fallingdetect =
378 readl_relaxed(bank->base + bank->regs->fallingdetect);
380 if (likely(!(bank->non_wakeup_gpios & gpio_bit))) {
381 omap_gpio_rmw(base, bank->regs->wkup_en, gpio_bit, trigger != 0);
382 bank->context.wake_en =
383 readl_relaxed(bank->base + bank->regs->wkup_en);
386 /* This part needs to be executed always for OMAP{34xx, 44xx} */
387 if (!bank->regs->irqctrl) {
388 /* On omap24xx proceed only when valid GPIO bit is set */
389 if (bank->non_wakeup_gpios) {
390 if (!(bank->non_wakeup_gpios & gpio_bit))
395 * Log the edge gpio and manually trigger the IRQ
396 * after resume if the input level changes
397 * to avoid irq lost during PER RET/OFF mode
398 * Applies for omap2 non-wakeup gpio and all omap3 gpios
400 if (trigger & IRQ_TYPE_EDGE_BOTH)
401 bank->enabled_non_wakeup_gpios |= gpio_bit;
403 bank->enabled_non_wakeup_gpios &= ~gpio_bit;
408 readl_relaxed(bank->base + bank->regs->leveldetect0) |
409 readl_relaxed(bank->base + bank->regs->leveldetect1);
412 #ifdef CONFIG_ARCH_OMAP1
414 * This only applies to chips that can't do both rising and falling edge
415 * detection at once. For all other chips, this function is a noop.
417 static void omap_toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio)
419 void __iomem *reg = bank->base;
422 if (!bank->regs->irqctrl)
425 reg += bank->regs->irqctrl;
427 l = readl_relaxed(reg);
433 writel_relaxed(l, reg);
436 static void omap_toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio) {}
439 static int omap_set_gpio_triggering(struct gpio_bank *bank, int gpio,
442 void __iomem *reg = bank->base;
443 void __iomem *base = bank->base;
446 if (bank->regs->leveldetect0 && bank->regs->wkup_en) {
447 omap_set_gpio_trigger(bank, gpio, trigger);
448 } else if (bank->regs->irqctrl) {
449 reg += bank->regs->irqctrl;
451 l = readl_relaxed(reg);
452 if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
453 bank->toggle_mask |= BIT(gpio);
454 if (trigger & IRQ_TYPE_EDGE_RISING)
456 else if (trigger & IRQ_TYPE_EDGE_FALLING)
461 writel_relaxed(l, reg);
462 } else if (bank->regs->edgectrl1) {
464 reg += bank->regs->edgectrl2;
466 reg += bank->regs->edgectrl1;
469 l = readl_relaxed(reg);
470 l &= ~(3 << (gpio << 1));
471 if (trigger & IRQ_TYPE_EDGE_RISING)
472 l |= 2 << (gpio << 1);
473 if (trigger & IRQ_TYPE_EDGE_FALLING)
476 /* Enable wake-up during idle for dynamic tick */
477 omap_gpio_rmw(base, bank->regs->wkup_en, BIT(gpio), trigger);
478 bank->context.wake_en =
479 readl_relaxed(bank->base + bank->regs->wkup_en);
480 writel_relaxed(l, reg);
485 static void omap_enable_gpio_module(struct gpio_bank *bank, unsigned offset)
487 if (bank->regs->pinctrl) {
488 void __iomem *reg = bank->base + bank->regs->pinctrl;
490 /* Claim the pin for MPU */
491 writel_relaxed(readl_relaxed(reg) | (BIT(offset)), reg);
494 if (bank->regs->ctrl && !BANK_USED(bank)) {
495 void __iomem *reg = bank->base + bank->regs->ctrl;
498 ctrl = readl_relaxed(reg);
499 /* Module is enabled, clocks are not gated */
500 ctrl &= ~GPIO_MOD_CTRL_BIT;
501 writel_relaxed(ctrl, reg);
502 bank->context.ctrl = ctrl;
506 static void omap_disable_gpio_module(struct gpio_bank *bank, unsigned offset)
508 void __iomem *base = bank->base;
510 if (bank->regs->wkup_en &&
511 !LINE_USED(bank->mod_usage, offset) &&
512 !LINE_USED(bank->irq_usage, offset)) {
513 /* Disable wake-up during idle for dynamic tick */
514 omap_gpio_rmw(base, bank->regs->wkup_en, BIT(offset), 0);
515 bank->context.wake_en =
516 readl_relaxed(bank->base + bank->regs->wkup_en);
519 if (bank->regs->ctrl && !BANK_USED(bank)) {
520 void __iomem *reg = bank->base + bank->regs->ctrl;
523 ctrl = readl_relaxed(reg);
524 /* Module is disabled, clocks are gated */
525 ctrl |= GPIO_MOD_CTRL_BIT;
526 writel_relaxed(ctrl, reg);
527 bank->context.ctrl = ctrl;
531 static int omap_gpio_is_input(struct gpio_bank *bank, unsigned offset)
533 void __iomem *reg = bank->base + bank->regs->direction;
535 return readl_relaxed(reg) & BIT(offset);
538 static void omap_gpio_init_irq(struct gpio_bank *bank, unsigned offset)
540 if (!LINE_USED(bank->mod_usage, offset)) {
541 omap_enable_gpio_module(bank, offset);
542 omap_set_gpio_direction(bank, offset, 1);
544 bank->irq_usage |= BIT(offset);
547 static int omap_gpio_irq_type(struct irq_data *d, unsigned type)
549 struct gpio_bank *bank = omap_irq_data_get_bank(d);
552 unsigned offset = d->hwirq;
554 if (type & ~IRQ_TYPE_SENSE_MASK)
557 if (!bank->regs->leveldetect0 &&
558 (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH)))
561 raw_spin_lock_irqsave(&bank->lock, flags);
562 retval = omap_set_gpio_triggering(bank, offset, type);
564 raw_spin_unlock_irqrestore(&bank->lock, flags);
567 omap_gpio_init_irq(bank, offset);
568 if (!omap_gpio_is_input(bank, offset)) {
569 raw_spin_unlock_irqrestore(&bank->lock, flags);
573 raw_spin_unlock_irqrestore(&bank->lock, flags);
575 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
576 irq_set_handler_locked(d, handle_level_irq);
577 else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
579 * Edge IRQs are already cleared/acked in irq_handler and
580 * not need to be masked, as result handle_edge_irq()
581 * logic is excessed here and may cause lose of interrupts.
582 * So just use handle_simple_irq.
584 irq_set_handler_locked(d, handle_simple_irq);
592 static void omap_clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
594 void __iomem *reg = bank->base;
596 reg += bank->regs->irqstatus;
597 writel_relaxed(gpio_mask, reg);
599 /* Workaround for clearing DSP GPIO interrupts to allow retention */
600 if (bank->regs->irqstatus2) {
601 reg = bank->base + bank->regs->irqstatus2;
602 writel_relaxed(gpio_mask, reg);
605 /* Flush posted write for the irq status to avoid spurious interrupts */
609 static inline void omap_clear_gpio_irqstatus(struct gpio_bank *bank,
612 omap_clear_gpio_irqbank(bank, BIT(offset));
615 static u32 omap_get_gpio_irqbank_mask(struct gpio_bank *bank)
617 void __iomem *reg = bank->base;
619 u32 mask = (BIT(bank->width)) - 1;
621 reg += bank->regs->irqenable;
622 l = readl_relaxed(reg);
623 if (bank->regs->irqenable_inv)
629 static void omap_enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
631 void __iomem *reg = bank->base;
634 if (bank->regs->set_irqenable) {
635 reg += bank->regs->set_irqenable;
637 bank->context.irqenable1 |= gpio_mask;
639 reg += bank->regs->irqenable;
640 l = readl_relaxed(reg);
641 if (bank->regs->irqenable_inv)
645 bank->context.irqenable1 = l;
648 writel_relaxed(l, reg);
651 static void omap_disable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
653 void __iomem *reg = bank->base;
656 if (bank->regs->clr_irqenable) {
657 reg += bank->regs->clr_irqenable;
659 bank->context.irqenable1 &= ~gpio_mask;
661 reg += bank->regs->irqenable;
662 l = readl_relaxed(reg);
663 if (bank->regs->irqenable_inv)
667 bank->context.irqenable1 = l;
670 writel_relaxed(l, reg);
673 static inline void omap_set_gpio_irqenable(struct gpio_bank *bank,
674 unsigned offset, int enable)
677 omap_enable_gpio_irqbank(bank, BIT(offset));
679 omap_disable_gpio_irqbank(bank, BIT(offset));
682 /* Use disable_irq_wake() and enable_irq_wake() functions from drivers */
683 static int omap_gpio_wake_enable(struct irq_data *d, unsigned int enable)
685 struct gpio_bank *bank = omap_irq_data_get_bank(d);
687 return irq_set_irq_wake(bank->irq, enable);
690 static int omap_gpio_request(struct gpio_chip *chip, unsigned offset)
692 struct gpio_bank *bank = gpiochip_get_data(chip);
695 pm_runtime_get_sync(chip->parent);
697 raw_spin_lock_irqsave(&bank->lock, flags);
698 omap_enable_gpio_module(bank, offset);
699 bank->mod_usage |= BIT(offset);
700 raw_spin_unlock_irqrestore(&bank->lock, flags);
705 static void omap_gpio_free(struct gpio_chip *chip, unsigned offset)
707 struct gpio_bank *bank = gpiochip_get_data(chip);
710 raw_spin_lock_irqsave(&bank->lock, flags);
711 bank->mod_usage &= ~(BIT(offset));
712 if (!LINE_USED(bank->irq_usage, offset)) {
713 omap_set_gpio_direction(bank, offset, 1);
714 omap_clear_gpio_debounce(bank, offset);
716 omap_disable_gpio_module(bank, offset);
717 raw_spin_unlock_irqrestore(&bank->lock, flags);
719 pm_runtime_put(chip->parent);
723 * We need to unmask the GPIO bank interrupt as soon as possible to
724 * avoid missing GPIO interrupts for other lines in the bank.
725 * Then we need to mask-read-clear-unmask the triggered GPIO lines
726 * in the bank to avoid missing nested interrupts for a GPIO line.
727 * If we wait to unmask individual GPIO lines in the bank after the
728 * line's interrupt handler has been run, we may miss some nested
731 static irqreturn_t omap_gpio_irq_handler(int irq, void *gpiobank)
733 void __iomem *isr_reg = NULL;
734 u32 enabled, isr, level_mask;
736 struct gpio_bank *bank = gpiobank;
737 unsigned long wa_lock_flags;
738 unsigned long lock_flags;
740 isr_reg = bank->base + bank->regs->irqstatus;
741 if (WARN_ON(!isr_reg))
744 if (WARN_ONCE(!pm_runtime_active(bank->chip.parent),
745 "gpio irq%i while runtime suspended?\n", irq))
749 raw_spin_lock_irqsave(&bank->lock, lock_flags);
751 enabled = omap_get_gpio_irqbank_mask(bank);
752 isr = readl_relaxed(isr_reg) & enabled;
754 if (bank->level_mask)
755 level_mask = bank->level_mask & enabled;
759 /* clear edge sensitive interrupts before handler(s) are
760 called so that we don't miss any interrupt occurred while
762 if (isr & ~level_mask)
763 omap_clear_gpio_irqbank(bank, isr & ~level_mask);
765 raw_spin_unlock_irqrestore(&bank->lock, lock_flags);
774 raw_spin_lock_irqsave(&bank->lock, lock_flags);
776 * Some chips can't respond to both rising and falling
777 * at the same time. If this irq was requested with
778 * both flags, we need to flip the ICR data for the IRQ
779 * to respond to the IRQ for the opposite direction.
780 * This will be indicated in the bank toggle_mask.
782 if (bank->toggle_mask & (BIT(bit)))
783 omap_toggle_gpio_edge_triggering(bank, bit);
785 raw_spin_unlock_irqrestore(&bank->lock, lock_flags);
787 raw_spin_lock_irqsave(&bank->wa_lock, wa_lock_flags);
789 generic_handle_irq(irq_find_mapping(bank->chip.irq.domain,
792 raw_spin_unlock_irqrestore(&bank->wa_lock,
800 static unsigned int omap_gpio_irq_startup(struct irq_data *d)
802 struct gpio_bank *bank = omap_irq_data_get_bank(d);
804 unsigned offset = d->hwirq;
806 raw_spin_lock_irqsave(&bank->lock, flags);
808 if (!LINE_USED(bank->mod_usage, offset))
809 omap_set_gpio_direction(bank, offset, 1);
810 else if (!omap_gpio_is_input(bank, offset))
812 omap_enable_gpio_module(bank, offset);
813 bank->irq_usage |= BIT(offset);
815 raw_spin_unlock_irqrestore(&bank->lock, flags);
816 omap_gpio_unmask_irq(d);
820 raw_spin_unlock_irqrestore(&bank->lock, flags);
824 static void omap_gpio_irq_shutdown(struct irq_data *d)
826 struct gpio_bank *bank = omap_irq_data_get_bank(d);
828 unsigned offset = d->hwirq;
830 raw_spin_lock_irqsave(&bank->lock, flags);
831 bank->irq_usage &= ~(BIT(offset));
832 omap_set_gpio_irqenable(bank, offset, 0);
833 omap_clear_gpio_irqstatus(bank, offset);
834 omap_set_gpio_triggering(bank, offset, IRQ_TYPE_NONE);
835 if (!LINE_USED(bank->mod_usage, offset))
836 omap_clear_gpio_debounce(bank, offset);
837 omap_disable_gpio_module(bank, offset);
838 raw_spin_unlock_irqrestore(&bank->lock, flags);
841 static void omap_gpio_irq_bus_lock(struct irq_data *data)
843 struct gpio_bank *bank = omap_irq_data_get_bank(data);
845 pm_runtime_get_sync(bank->chip.parent);
848 static void gpio_irq_bus_sync_unlock(struct irq_data *data)
850 struct gpio_bank *bank = omap_irq_data_get_bank(data);
852 pm_runtime_put(bank->chip.parent);
855 static void omap_gpio_ack_irq(struct irq_data *d)
857 struct gpio_bank *bank = omap_irq_data_get_bank(d);
858 unsigned offset = d->hwirq;
860 omap_clear_gpio_irqstatus(bank, offset);
863 static void omap_gpio_mask_irq(struct irq_data *d)
865 struct gpio_bank *bank = omap_irq_data_get_bank(d);
866 unsigned offset = d->hwirq;
869 raw_spin_lock_irqsave(&bank->lock, flags);
870 omap_set_gpio_irqenable(bank, offset, 0);
871 omap_set_gpio_triggering(bank, offset, IRQ_TYPE_NONE);
872 raw_spin_unlock_irqrestore(&bank->lock, flags);
875 static void omap_gpio_unmask_irq(struct irq_data *d)
877 struct gpio_bank *bank = omap_irq_data_get_bank(d);
878 unsigned offset = d->hwirq;
879 u32 trigger = irqd_get_trigger_type(d);
882 raw_spin_lock_irqsave(&bank->lock, flags);
884 omap_set_gpio_triggering(bank, offset, trigger);
886 /* For level-triggered GPIOs, the clearing must be done after
887 * the HW source is cleared, thus after the handler has run */
888 if (bank->level_mask & BIT(offset)) {
889 omap_set_gpio_irqenable(bank, offset, 0);
890 omap_clear_gpio_irqstatus(bank, offset);
893 omap_set_gpio_irqenable(bank, offset, 1);
894 raw_spin_unlock_irqrestore(&bank->lock, flags);
898 * Only edges can generate a wakeup event to the PRCM.
900 * Therefore, ensure any wake-up capable GPIOs have
901 * edge-detection enabled before going idle to ensure a wakeup
902 * to the PRCM is generated on a GPIO transition. (c.f. 34xx
905 * The normal values will be restored upon ->runtime_resume()
906 * by writing back the values saved in bank->context.
908 static void __maybe_unused
909 omap2_gpio_enable_level_quirk(struct gpio_bank *bank)
911 u32 wake_low, wake_hi;
913 /* Enable additional edge detection for level gpios for idle */
914 wake_low = bank->context.leveldetect0 & bank->context.wake_en;
916 writel_relaxed(wake_low | bank->context.fallingdetect,
917 bank->base + bank->regs->fallingdetect);
919 wake_hi = bank->context.leveldetect1 & bank->context.wake_en;
921 writel_relaxed(wake_hi | bank->context.risingdetect,
922 bank->base + bank->regs->risingdetect);
925 static void __maybe_unused
926 omap2_gpio_disable_level_quirk(struct gpio_bank *bank)
928 /* Disable edge detection for level gpios after idle */
929 writel_relaxed(bank->context.fallingdetect,
930 bank->base + bank->regs->fallingdetect);
931 writel_relaxed(bank->context.risingdetect,
932 bank->base + bank->regs->risingdetect);
935 /*---------------------------------------------------------------------*/
937 static int omap_mpuio_suspend_noirq(struct device *dev)
939 struct gpio_bank *bank = dev_get_drvdata(dev);
940 void __iomem *mask_reg = bank->base +
941 OMAP_MPUIO_GPIO_MASKIT / bank->stride;
944 raw_spin_lock_irqsave(&bank->lock, flags);
945 writel_relaxed(0xffff & ~bank->context.wake_en, mask_reg);
946 raw_spin_unlock_irqrestore(&bank->lock, flags);
951 static int omap_mpuio_resume_noirq(struct device *dev)
953 struct gpio_bank *bank = dev_get_drvdata(dev);
954 void __iomem *mask_reg = bank->base +
955 OMAP_MPUIO_GPIO_MASKIT / bank->stride;
958 raw_spin_lock_irqsave(&bank->lock, flags);
959 writel_relaxed(bank->context.wake_en, mask_reg);
960 raw_spin_unlock_irqrestore(&bank->lock, flags);
965 static const struct dev_pm_ops omap_mpuio_dev_pm_ops = {
966 .suspend_noirq = omap_mpuio_suspend_noirq,
967 .resume_noirq = omap_mpuio_resume_noirq,
970 /* use platform_driver for this. */
971 static struct platform_driver omap_mpuio_driver = {
974 .pm = &omap_mpuio_dev_pm_ops,
978 static struct platform_device omap_mpuio_device = {
982 .driver = &omap_mpuio_driver.driver,
984 /* could list the /proc/iomem resources */
987 static inline void omap_mpuio_init(struct gpio_bank *bank)
989 platform_set_drvdata(&omap_mpuio_device, bank);
991 if (platform_driver_register(&omap_mpuio_driver) == 0)
992 (void) platform_device_register(&omap_mpuio_device);
995 /*---------------------------------------------------------------------*/
997 static int omap_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
999 struct gpio_bank *bank;
1000 unsigned long flags;
1004 bank = gpiochip_get_data(chip);
1005 reg = bank->base + bank->regs->direction;
1006 raw_spin_lock_irqsave(&bank->lock, flags);
1007 dir = !!(readl_relaxed(reg) & BIT(offset));
1008 raw_spin_unlock_irqrestore(&bank->lock, flags);
1012 static int omap_gpio_input(struct gpio_chip *chip, unsigned offset)
1014 struct gpio_bank *bank;
1015 unsigned long flags;
1017 bank = gpiochip_get_data(chip);
1018 raw_spin_lock_irqsave(&bank->lock, flags);
1019 omap_set_gpio_direction(bank, offset, 1);
1020 raw_spin_unlock_irqrestore(&bank->lock, flags);
1024 static int omap_gpio_get(struct gpio_chip *chip, unsigned offset)
1026 struct gpio_bank *bank;
1028 bank = gpiochip_get_data(chip);
1030 if (omap_gpio_is_input(bank, offset))
1031 return omap_get_gpio_datain(bank, offset);
1033 return omap_get_gpio_dataout(bank, offset);
1036 static int omap_gpio_output(struct gpio_chip *chip, unsigned offset, int value)
1038 struct gpio_bank *bank;
1039 unsigned long flags;
1041 bank = gpiochip_get_data(chip);
1042 raw_spin_lock_irqsave(&bank->lock, flags);
1043 bank->set_dataout(bank, offset, value);
1044 omap_set_gpio_direction(bank, offset, 0);
1045 raw_spin_unlock_irqrestore(&bank->lock, flags);
1049 static int omap_gpio_get_multiple(struct gpio_chip *chip, unsigned long *mask,
1050 unsigned long *bits)
1052 struct gpio_bank *bank = gpiochip_get_data(chip);
1053 void __iomem *reg = bank->base + bank->regs->direction;
1054 unsigned long in = readl_relaxed(reg), l;
1060 *bits |= omap_get_gpio_datain_multiple(bank, &l);
1064 *bits |= omap_get_gpio_dataout_multiple(bank, &l);
1069 static int omap_gpio_debounce(struct gpio_chip *chip, unsigned offset,
1072 struct gpio_bank *bank;
1073 unsigned long flags;
1076 bank = gpiochip_get_data(chip);
1078 raw_spin_lock_irqsave(&bank->lock, flags);
1079 ret = omap2_set_gpio_debounce(bank, offset, debounce);
1080 raw_spin_unlock_irqrestore(&bank->lock, flags);
1083 dev_info(chip->parent,
1084 "Could not set line %u debounce to %u microseconds (%d)",
1085 offset, debounce, ret);
1090 static int omap_gpio_set_config(struct gpio_chip *chip, unsigned offset,
1091 unsigned long config)
1095 if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE)
1098 debounce = pinconf_to_config_argument(config);
1099 return omap_gpio_debounce(chip, offset, debounce);
1102 static void omap_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
1104 struct gpio_bank *bank;
1105 unsigned long flags;
1107 bank = gpiochip_get_data(chip);
1108 raw_spin_lock_irqsave(&bank->lock, flags);
1109 bank->set_dataout(bank, offset, value);
1110 raw_spin_unlock_irqrestore(&bank->lock, flags);
1113 static void omap_gpio_set_multiple(struct gpio_chip *chip, unsigned long *mask,
1114 unsigned long *bits)
1116 struct gpio_bank *bank = gpiochip_get_data(chip);
1117 unsigned long flags;
1119 raw_spin_lock_irqsave(&bank->lock, flags);
1120 bank->set_dataout_multiple(bank, mask, bits);
1121 raw_spin_unlock_irqrestore(&bank->lock, flags);
1124 /*---------------------------------------------------------------------*/
1126 static void omap_gpio_show_rev(struct gpio_bank *bank)
1131 if (called || bank->regs->revision == USHRT_MAX)
1134 rev = readw_relaxed(bank->base + bank->regs->revision);
1135 pr_info("OMAP GPIO hardware version %d.%d\n",
1136 (rev >> 4) & 0x0f, rev & 0x0f);
1141 static void omap_gpio_mod_init(struct gpio_bank *bank)
1143 void __iomem *base = bank->base;
1146 if (bank->width == 16)
1149 if (bank->is_mpuio) {
1150 writel_relaxed(l, bank->base + bank->regs->irqenable);
1154 omap_gpio_rmw(base, bank->regs->irqenable, l,
1155 bank->regs->irqenable_inv);
1156 omap_gpio_rmw(base, bank->regs->irqstatus, l,
1157 !bank->regs->irqenable_inv);
1158 if (bank->regs->debounce_en)
1159 writel_relaxed(0, base + bank->regs->debounce_en);
1161 /* Save OE default value (0xffffffff) in the context */
1162 bank->context.oe = readl_relaxed(bank->base + bank->regs->direction);
1163 /* Initialize interface clk ungated, module enabled */
1164 if (bank->regs->ctrl)
1165 writel_relaxed(0, base + bank->regs->ctrl);
1168 static int omap_gpio_chip_init(struct gpio_bank *bank, struct irq_chip *irqc)
1170 struct gpio_irq_chip *irq;
1177 * REVISIT eventually switch from OMAP-specific gpio structs
1178 * over to the generic ones
1180 bank->chip.request = omap_gpio_request;
1181 bank->chip.free = omap_gpio_free;
1182 bank->chip.get_direction = omap_gpio_get_direction;
1183 bank->chip.direction_input = omap_gpio_input;
1184 bank->chip.get = omap_gpio_get;
1185 bank->chip.get_multiple = omap_gpio_get_multiple;
1186 bank->chip.direction_output = omap_gpio_output;
1187 bank->chip.set_config = omap_gpio_set_config;
1188 bank->chip.set = omap_gpio_set;
1189 bank->chip.set_multiple = omap_gpio_set_multiple;
1190 if (bank->is_mpuio) {
1191 bank->chip.label = "mpuio";
1192 if (bank->regs->wkup_en)
1193 bank->chip.parent = &omap_mpuio_device.dev;
1194 bank->chip.base = OMAP_MPUIO(0);
1196 label = devm_kasprintf(bank->chip.parent, GFP_KERNEL, "gpio-%d-%d",
1197 gpio, gpio + bank->width - 1);
1200 bank->chip.label = label;
1201 bank->chip.base = gpio;
1203 bank->chip.ngpio = bank->width;
1205 #ifdef CONFIG_ARCH_OMAP1
1207 * REVISIT: Once we have OMAP1 supporting SPARSE_IRQ, we can drop
1208 * irq_alloc_descs() since a base IRQ offset will no longer be needed.
1210 irq_base = devm_irq_alloc_descs(bank->chip.parent,
1211 -1, 0, bank->width, 0);
1213 dev_err(bank->chip.parent, "Couldn't allocate IRQ numbers\n");
1218 /* MPUIO is a bit different, reading IRQ status clears it */
1219 if (bank->is_mpuio) {
1220 irqc->irq_ack = dummy_irq_chip.irq_ack;
1221 if (!bank->regs->wkup_en)
1222 irqc->irq_set_wake = NULL;
1225 irq = &bank->chip.irq;
1227 irq->handler = handle_bad_irq;
1228 irq->default_type = IRQ_TYPE_NONE;
1229 irq->num_parents = 1;
1230 irq->parents = &bank->irq;
1231 irq->first = irq_base;
1233 ret = gpiochip_add_data(&bank->chip, bank);
1235 dev_err(bank->chip.parent,
1236 "Could not register gpio chip %d\n", ret);
1240 ret = devm_request_irq(bank->chip.parent, bank->irq,
1241 omap_gpio_irq_handler,
1242 0, dev_name(bank->chip.parent), bank);
1244 gpiochip_remove(&bank->chip);
1246 if (!bank->is_mpuio)
1247 gpio += bank->width;
1252 static void omap_gpio_idle(struct gpio_bank *bank, bool may_lose_context);
1253 static void omap_gpio_unidle(struct gpio_bank *bank);
1255 static int gpio_omap_cpu_notifier(struct notifier_block *nb,
1256 unsigned long cmd, void *v)
1258 struct gpio_bank *bank;
1259 unsigned long flags;
1261 bank = container_of(nb, struct gpio_bank, nb);
1263 raw_spin_lock_irqsave(&bank->lock, flags);
1265 case CPU_CLUSTER_PM_ENTER:
1266 if (bank->is_suspended)
1268 omap_gpio_idle(bank, true);
1270 case CPU_CLUSTER_PM_ENTER_FAILED:
1271 case CPU_CLUSTER_PM_EXIT:
1272 if (bank->is_suspended)
1274 omap_gpio_unidle(bank);
1277 raw_spin_unlock_irqrestore(&bank->lock, flags);
1282 static const struct of_device_id omap_gpio_match[];
1284 static int omap_gpio_probe(struct platform_device *pdev)
1286 struct device *dev = &pdev->dev;
1287 struct device_node *node = dev->of_node;
1288 const struct of_device_id *match;
1289 const struct omap_gpio_platform_data *pdata;
1290 struct resource *res;
1291 struct gpio_bank *bank;
1292 struct irq_chip *irqc;
1295 match = of_match_device(of_match_ptr(omap_gpio_match), dev);
1297 pdata = match ? match->data : dev_get_platdata(dev);
1301 bank = devm_kzalloc(dev, sizeof(*bank), GFP_KERNEL);
1305 irqc = devm_kzalloc(dev, sizeof(*irqc), GFP_KERNEL);
1309 irqc->irq_startup = omap_gpio_irq_startup,
1310 irqc->irq_shutdown = omap_gpio_irq_shutdown,
1311 irqc->irq_ack = omap_gpio_ack_irq,
1312 irqc->irq_mask = omap_gpio_mask_irq,
1313 irqc->irq_unmask = omap_gpio_unmask_irq,
1314 irqc->irq_set_type = omap_gpio_irq_type,
1315 irqc->irq_set_wake = omap_gpio_wake_enable,
1316 irqc->irq_bus_lock = omap_gpio_irq_bus_lock,
1317 irqc->irq_bus_sync_unlock = gpio_irq_bus_sync_unlock,
1318 irqc->name = dev_name(&pdev->dev);
1319 irqc->flags = IRQCHIP_MASK_ON_SUSPEND;
1320 irqc->parent_device = dev;
1322 bank->irq = platform_get_irq(pdev, 0);
1323 if (bank->irq <= 0) {
1326 if (bank->irq != -EPROBE_DEFER)
1328 "can't get irq resource ret=%d\n", bank->irq);
1332 bank->chip.parent = dev;
1333 bank->chip.owner = THIS_MODULE;
1334 bank->dbck_flag = pdata->dbck_flag;
1335 bank->quirks = pdata->quirks;
1336 bank->stride = pdata->bank_stride;
1337 bank->width = pdata->bank_width;
1338 bank->is_mpuio = pdata->is_mpuio;
1339 bank->non_wakeup_gpios = pdata->non_wakeup_gpios;
1340 bank->regs = pdata->regs;
1341 #ifdef CONFIG_OF_GPIO
1342 bank->chip.of_node = of_node_get(node);
1346 if (!of_property_read_bool(node, "ti,gpio-always-on"))
1347 bank->loses_context = true;
1349 bank->loses_context = pdata->loses_context;
1351 if (bank->loses_context)
1352 bank->get_context_loss_count =
1353 pdata->get_context_loss_count;
1356 if (bank->regs->set_dataout && bank->regs->clr_dataout) {
1357 bank->set_dataout = omap_set_gpio_dataout_reg;
1358 bank->set_dataout_multiple = omap_set_gpio_dataout_reg_multiple;
1360 bank->set_dataout = omap_set_gpio_dataout_mask;
1361 bank->set_dataout_multiple =
1362 omap_set_gpio_dataout_mask_multiple;
1365 if (bank->quirks & OMAP_GPIO_QUIRK_IDLE_REMOVE_TRIGGER) {
1366 bank->funcs.idle_enable_level_quirk =
1367 omap2_gpio_enable_level_quirk;
1368 bank->funcs.idle_disable_level_quirk =
1369 omap2_gpio_disable_level_quirk;
1372 raw_spin_lock_init(&bank->lock);
1373 raw_spin_lock_init(&bank->wa_lock);
1375 /* Static mapping, never released */
1376 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1377 bank->base = devm_ioremap_resource(dev, res);
1378 if (IS_ERR(bank->base)) {
1379 return PTR_ERR(bank->base);
1382 if (bank->dbck_flag) {
1383 bank->dbck = devm_clk_get(dev, "dbclk");
1384 if (IS_ERR(bank->dbck)) {
1386 "Could not get gpio dbck. Disable debounce\n");
1387 bank->dbck_flag = false;
1389 clk_prepare(bank->dbck);
1393 platform_set_drvdata(pdev, bank);
1395 pm_runtime_enable(dev);
1396 pm_runtime_get_sync(dev);
1399 omap_mpuio_init(bank);
1401 omap_gpio_mod_init(bank);
1403 ret = omap_gpio_chip_init(bank, irqc);
1405 pm_runtime_put_sync(dev);
1406 pm_runtime_disable(dev);
1407 if (bank->dbck_flag)
1408 clk_unprepare(bank->dbck);
1412 omap_gpio_show_rev(bank);
1414 if (bank->funcs.idle_enable_level_quirk &&
1415 bank->funcs.idle_disable_level_quirk) {
1416 bank->nb.notifier_call = gpio_omap_cpu_notifier;
1417 cpu_pm_register_notifier(&bank->nb);
1420 pm_runtime_put(dev);
1425 static int omap_gpio_remove(struct platform_device *pdev)
1427 struct gpio_bank *bank = platform_get_drvdata(pdev);
1429 if (bank->nb.notifier_call)
1430 cpu_pm_unregister_notifier(&bank->nb);
1431 list_del(&bank->node);
1432 gpiochip_remove(&bank->chip);
1433 pm_runtime_disable(&pdev->dev);
1434 if (bank->dbck_flag)
1435 clk_unprepare(bank->dbck);
1440 static void omap_gpio_restore_context(struct gpio_bank *bank);
1442 static void omap_gpio_idle(struct gpio_bank *bank, bool may_lose_context)
1444 struct device *dev = bank->chip.parent;
1447 if (bank->funcs.idle_enable_level_quirk)
1448 bank->funcs.idle_enable_level_quirk(bank);
1450 if (!bank->enabled_non_wakeup_gpios)
1451 goto update_gpio_context_count;
1453 if (!may_lose_context)
1454 goto update_gpio_context_count;
1457 * If going to OFF, remove triggering for all
1458 * non-wakeup GPIOs. Otherwise spurious IRQs will be
1459 * generated. See OMAP2420 Errata item 1.101.
1461 bank->saved_datain = readl_relaxed(bank->base +
1462 bank->regs->datain);
1463 l1 = bank->context.fallingdetect;
1464 l2 = bank->context.risingdetect;
1466 l1 &= ~bank->enabled_non_wakeup_gpios;
1467 l2 &= ~bank->enabled_non_wakeup_gpios;
1469 writel_relaxed(l1, bank->base + bank->regs->fallingdetect);
1470 writel_relaxed(l2, bank->base + bank->regs->risingdetect);
1472 bank->workaround_enabled = true;
1474 update_gpio_context_count:
1475 if (bank->get_context_loss_count)
1476 bank->context_loss_count =
1477 bank->get_context_loss_count(dev);
1479 omap_gpio_dbck_disable(bank);
1482 static void omap_gpio_init_context(struct gpio_bank *p);
1484 static void omap_gpio_unidle(struct gpio_bank *bank)
1486 struct device *dev = bank->chip.parent;
1487 u32 l = 0, gen, gen0, gen1;
1491 * On the first resume during the probe, the context has not
1492 * been initialised and so initialise it now. Also initialise
1493 * the context loss count.
1495 if (bank->loses_context && !bank->context_valid) {
1496 omap_gpio_init_context(bank);
1498 if (bank->get_context_loss_count)
1499 bank->context_loss_count =
1500 bank->get_context_loss_count(dev);
1503 omap_gpio_dbck_enable(bank);
1505 if (bank->funcs.idle_disable_level_quirk)
1506 bank->funcs.idle_disable_level_quirk(bank);
1508 if (bank->loses_context) {
1509 if (!bank->get_context_loss_count) {
1510 omap_gpio_restore_context(bank);
1512 c = bank->get_context_loss_count(dev);
1513 if (c != bank->context_loss_count) {
1514 omap_gpio_restore_context(bank);
1521 if (!bank->workaround_enabled)
1524 l = readl_relaxed(bank->base + bank->regs->datain);
1527 * Check if any of the non-wakeup interrupt GPIOs have changed
1528 * state. If so, generate an IRQ by software. This is
1529 * horribly racy, but it's the best we can do to work around
1532 l ^= bank->saved_datain;
1533 l &= bank->enabled_non_wakeup_gpios;
1536 * No need to generate IRQs for the rising edge for gpio IRQs
1537 * configured with falling edge only; and vice versa.
1539 gen0 = l & bank->context.fallingdetect;
1540 gen0 &= bank->saved_datain;
1542 gen1 = l & bank->context.risingdetect;
1543 gen1 &= ~(bank->saved_datain);
1545 /* FIXME: Consider GPIO IRQs with level detections properly! */
1546 gen = l & (~(bank->context.fallingdetect) &
1547 ~(bank->context.risingdetect));
1548 /* Consider all GPIO IRQs needed to be updated */
1554 old0 = readl_relaxed(bank->base + bank->regs->leveldetect0);
1555 old1 = readl_relaxed(bank->base + bank->regs->leveldetect1);
1557 if (!bank->regs->irqstatus_raw0) {
1558 writel_relaxed(old0 | gen, bank->base +
1559 bank->regs->leveldetect0);
1560 writel_relaxed(old1 | gen, bank->base +
1561 bank->regs->leveldetect1);
1564 if (bank->regs->irqstatus_raw0) {
1565 writel_relaxed(old0 | l, bank->base +
1566 bank->regs->leveldetect0);
1567 writel_relaxed(old1 | l, bank->base +
1568 bank->regs->leveldetect1);
1570 writel_relaxed(old0, bank->base + bank->regs->leveldetect0);
1571 writel_relaxed(old1, bank->base + bank->regs->leveldetect1);
1574 bank->workaround_enabled = false;
1577 static void omap_gpio_init_context(struct gpio_bank *p)
1579 struct omap_gpio_reg_offs *regs = p->regs;
1580 void __iomem *base = p->base;
1582 p->context.ctrl = readl_relaxed(base + regs->ctrl);
1583 p->context.oe = readl_relaxed(base + regs->direction);
1584 p->context.wake_en = readl_relaxed(base + regs->wkup_en);
1585 p->context.leveldetect0 = readl_relaxed(base + regs->leveldetect0);
1586 p->context.leveldetect1 = readl_relaxed(base + regs->leveldetect1);
1587 p->context.risingdetect = readl_relaxed(base + regs->risingdetect);
1588 p->context.fallingdetect = readl_relaxed(base + regs->fallingdetect);
1589 p->context.irqenable1 = readl_relaxed(base + regs->irqenable);
1590 p->context.irqenable2 = readl_relaxed(base + regs->irqenable2);
1592 if (regs->set_dataout && p->regs->clr_dataout)
1593 p->context.dataout = readl_relaxed(base + regs->set_dataout);
1595 p->context.dataout = readl_relaxed(base + regs->dataout);
1597 p->context_valid = true;
1600 static void omap_gpio_restore_context(struct gpio_bank *bank)
1602 writel_relaxed(bank->context.wake_en,
1603 bank->base + bank->regs->wkup_en);
1604 writel_relaxed(bank->context.ctrl, bank->base + bank->regs->ctrl);
1605 writel_relaxed(bank->context.leveldetect0,
1606 bank->base + bank->regs->leveldetect0);
1607 writel_relaxed(bank->context.leveldetect1,
1608 bank->base + bank->regs->leveldetect1);
1609 writel_relaxed(bank->context.risingdetect,
1610 bank->base + bank->regs->risingdetect);
1611 writel_relaxed(bank->context.fallingdetect,
1612 bank->base + bank->regs->fallingdetect);
1613 if (bank->regs->set_dataout && bank->regs->clr_dataout)
1614 writel_relaxed(bank->context.dataout,
1615 bank->base + bank->regs->set_dataout);
1617 writel_relaxed(bank->context.dataout,
1618 bank->base + bank->regs->dataout);
1619 writel_relaxed(bank->context.oe, bank->base + bank->regs->direction);
1621 if (bank->dbck_enable_mask) {
1622 writel_relaxed(bank->context.debounce, bank->base +
1623 bank->regs->debounce);
1624 writel_relaxed(bank->context.debounce_en,
1625 bank->base + bank->regs->debounce_en);
1628 writel_relaxed(bank->context.irqenable1,
1629 bank->base + bank->regs->irqenable);
1630 writel_relaxed(bank->context.irqenable2,
1631 bank->base + bank->regs->irqenable2);
1634 static int __maybe_unused omap_gpio_runtime_suspend(struct device *dev)
1636 struct gpio_bank *bank = dev_get_drvdata(dev);
1637 unsigned long flags;
1640 raw_spin_lock_irqsave(&bank->lock, flags);
1641 /* Must be idled only by CPU_CLUSTER_PM_ENTER? */
1642 if (bank->irq_usage) {
1646 omap_gpio_idle(bank, true);
1647 bank->is_suspended = true;
1649 raw_spin_unlock_irqrestore(&bank->lock, flags);
1654 static int __maybe_unused omap_gpio_runtime_resume(struct device *dev)
1656 struct gpio_bank *bank = dev_get_drvdata(dev);
1657 unsigned long flags;
1660 raw_spin_lock_irqsave(&bank->lock, flags);
1661 /* Must be unidled only by CPU_CLUSTER_PM_ENTER? */
1662 if (bank->irq_usage) {
1666 omap_gpio_unidle(bank);
1667 bank->is_suspended = false;
1669 raw_spin_unlock_irqrestore(&bank->lock, flags);
1674 #ifdef CONFIG_ARCH_OMAP2PLUS
1675 static const struct dev_pm_ops gpio_pm_ops = {
1676 SET_RUNTIME_PM_OPS(omap_gpio_runtime_suspend, omap_gpio_runtime_resume,
1680 static const struct dev_pm_ops gpio_pm_ops;
1681 #endif /* CONFIG_ARCH_OMAP2PLUS */
1683 #if defined(CONFIG_OF)
1684 static struct omap_gpio_reg_offs omap2_gpio_regs = {
1685 .revision = OMAP24XX_GPIO_REVISION,
1686 .direction = OMAP24XX_GPIO_OE,
1687 .datain = OMAP24XX_GPIO_DATAIN,
1688 .dataout = OMAP24XX_GPIO_DATAOUT,
1689 .set_dataout = OMAP24XX_GPIO_SETDATAOUT,
1690 .clr_dataout = OMAP24XX_GPIO_CLEARDATAOUT,
1691 .irqstatus = OMAP24XX_GPIO_IRQSTATUS1,
1692 .irqstatus2 = OMAP24XX_GPIO_IRQSTATUS2,
1693 .irqenable = OMAP24XX_GPIO_IRQENABLE1,
1694 .irqenable2 = OMAP24XX_GPIO_IRQENABLE2,
1695 .set_irqenable = OMAP24XX_GPIO_SETIRQENABLE1,
1696 .clr_irqenable = OMAP24XX_GPIO_CLEARIRQENABLE1,
1697 .debounce = OMAP24XX_GPIO_DEBOUNCE_VAL,
1698 .debounce_en = OMAP24XX_GPIO_DEBOUNCE_EN,
1699 .ctrl = OMAP24XX_GPIO_CTRL,
1700 .wkup_en = OMAP24XX_GPIO_WAKE_EN,
1701 .leveldetect0 = OMAP24XX_GPIO_LEVELDETECT0,
1702 .leveldetect1 = OMAP24XX_GPIO_LEVELDETECT1,
1703 .risingdetect = OMAP24XX_GPIO_RISINGDETECT,
1704 .fallingdetect = OMAP24XX_GPIO_FALLINGDETECT,
1707 static struct omap_gpio_reg_offs omap4_gpio_regs = {
1708 .revision = OMAP4_GPIO_REVISION,
1709 .direction = OMAP4_GPIO_OE,
1710 .datain = OMAP4_GPIO_DATAIN,
1711 .dataout = OMAP4_GPIO_DATAOUT,
1712 .set_dataout = OMAP4_GPIO_SETDATAOUT,
1713 .clr_dataout = OMAP4_GPIO_CLEARDATAOUT,
1714 .irqstatus = OMAP4_GPIO_IRQSTATUS0,
1715 .irqstatus2 = OMAP4_GPIO_IRQSTATUS1,
1716 .irqenable = OMAP4_GPIO_IRQSTATUSSET0,
1717 .irqenable2 = OMAP4_GPIO_IRQSTATUSSET1,
1718 .set_irqenable = OMAP4_GPIO_IRQSTATUSSET0,
1719 .clr_irqenable = OMAP4_GPIO_IRQSTATUSCLR0,
1720 .debounce = OMAP4_GPIO_DEBOUNCINGTIME,
1721 .debounce_en = OMAP4_GPIO_DEBOUNCENABLE,
1722 .ctrl = OMAP4_GPIO_CTRL,
1723 .wkup_en = OMAP4_GPIO_IRQWAKEN0,
1724 .leveldetect0 = OMAP4_GPIO_LEVELDETECT0,
1725 .leveldetect1 = OMAP4_GPIO_LEVELDETECT1,
1726 .risingdetect = OMAP4_GPIO_RISINGDETECT,
1727 .fallingdetect = OMAP4_GPIO_FALLINGDETECT,
1731 * Note that omap2 does not currently support idle modes with context loss so
1732 * no need to add OMAP_GPIO_QUIRK_IDLE_REMOVE_TRIGGER quirk flag to save
1733 * and restore context.
1735 static const struct omap_gpio_platform_data omap2_pdata = {
1736 .regs = &omap2_gpio_regs,
1741 static const struct omap_gpio_platform_data omap3_pdata = {
1742 .regs = &omap2_gpio_regs,
1745 .quirks = OMAP_GPIO_QUIRK_IDLE_REMOVE_TRIGGER,
1748 static const struct omap_gpio_platform_data omap4_pdata = {
1749 .regs = &omap4_gpio_regs,
1752 .quirks = OMAP_GPIO_QUIRK_IDLE_REMOVE_TRIGGER,
1755 static const struct of_device_id omap_gpio_match[] = {
1757 .compatible = "ti,omap4-gpio",
1758 .data = &omap4_pdata,
1761 .compatible = "ti,omap3-gpio",
1762 .data = &omap3_pdata,
1765 .compatible = "ti,omap2-gpio",
1766 .data = &omap2_pdata,
1770 MODULE_DEVICE_TABLE(of, omap_gpio_match);
1773 static struct platform_driver omap_gpio_driver = {
1774 .probe = omap_gpio_probe,
1775 .remove = omap_gpio_remove,
1777 .name = "omap_gpio",
1779 .of_match_table = of_match_ptr(omap_gpio_match),
1784 * gpio driver register needs to be done before
1785 * machine_init functions access gpio APIs.
1786 * Hence omap_gpio_drv_reg() is a postcore_initcall.
1788 static int __init omap_gpio_drv_reg(void)
1790 return platform_driver_register(&omap_gpio_driver);
1792 postcore_initcall(omap_gpio_drv_reg);
1794 static void __exit omap_gpio_exit(void)
1796 platform_driver_unregister(&omap_gpio_driver);
1798 module_exit(omap_gpio_exit);
1800 MODULE_DESCRIPTION("omap gpio driver");
1801 MODULE_ALIAS("platform:gpio-omap");
1802 MODULE_LICENSE("GPL v2");