drivers/gpio/gpio-omap.c

   1 /*
   2  * Support functions for OMAP GPIO
   3  *
   4  * Copyright (C) 2003-2005 Nokia Corporation
   5  * Written by Juha Yrjölä <juha.yrjola@nokia.com>
   6  *
   7  * Copyright (C) 2009 Texas Instruments
   8  * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License version 2 as
  12  * published by the Free Software Foundation.
  13  */
  14
  15 #include <linux/init.h>
  16 #include <linux/module.h>
  17 #include <linux/interrupt.h>
  18 #include <linux/syscore_ops.h>
  19 #include <linux/err.h>
  20 #include <linux/clk.h>
  21 #include <linux/io.h>
  22 #include <linux/cpu_pm.h>
  23 #include <linux/device.h>
  24 #include <linux/pm_runtime.h>
  25 #include <linux/pm.h>
  26 #include <linux/of.h>
  27 #include <linux/of_device.h>
  28 #include <linux/gpio/driver.h>
  29 #include <linux/bitops.h>
  30 #include <linux/platform_data/gpio-omap.h>
  31
  32 #define OMAP4_GPIO_DEBOUNCINGTIME_MASK 0xFF
  33
  34 struct gpio_regs {
  35         u32 irqenable1;
  36         u32 irqenable2;
  37         u32 wake_en;
  38         u32 ctrl;
  39         u32 oe;
  40         u32 leveldetect0;
  41         u32 leveldetect1;
  42         u32 risingdetect;
  43         u32 fallingdetect;
  44         u32 dataout;
  45         u32 debounce;
  46         u32 debounce_en;
  47 };
  48
  49 struct gpio_bank {
  50         void __iomem *base;
  51         int irq;
  52         u32 non_wakeup_gpios;
  53         u32 enabled_non_wakeup_gpios;
  54         struct gpio_regs context;
  55         u32 saved_datain;
  56         u32 level_mask;
  57         u32 toggle_mask;
  58         raw_spinlock_t lock;
  59         raw_spinlock_t wa_lock;
  60         struct gpio_chip chip;
  61         struct clk *dbck;
  62         struct notifier_block nb;
  63         unsigned int is_suspended:1;
  64         u32 mod_usage;
  65         u32 irq_usage;
  66         u32 dbck_enable_mask;
  67         bool dbck_enabled;
  68         bool is_mpuio;
  69         bool dbck_flag;
  70         bool loses_context;
  71         bool context_valid;
  72         int stride;
  73         u32 width;
  74         int context_loss_count;
  75
  76         void (*set_dataout)(struct gpio_bank *bank, unsigned gpio, int enable);
  77         void (*set_dataout_multiple)(struct gpio_bank *bank,
  78                                      unsigned long *mask, unsigned long *bits);
  79         int (*get_context_loss_count)(struct device *dev);
  80
  81         struct omap_gpio_reg_offs *regs;
  82 };
  83
  84 #define GPIO_MOD_CTRL_BIT       BIT(0)
  85
  86 #define BANK_USED(bank) (bank->mod_usage || bank->irq_usage)
  87 #define LINE_USED(line, offset) (line & (BIT(offset)))
  88
  89 static void omap_gpio_unmask_irq(struct irq_data *d);
  90
  91 static inline struct gpio_bank *omap_irq_data_get_bank(struct irq_data *d)
  92 {
  93         struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
  94         return gpiochip_get_data(chip);
  95 }
  96
  97 static void omap_set_gpio_direction(struct gpio_bank *bank, int gpio,
  98                                     int is_input)
  99 {
 100         void __iomem *reg = bank->base;
 101         u32 l;
 102
 103         reg += bank->regs->direction;
 104         l = readl_relaxed(reg);
 105         if (is_input)
 106                 l |= BIT(gpio);
 107         else
 108                 l &= ~(BIT(gpio));
 109         writel_relaxed(l, reg);
 110         bank->context.oe = l;
 111 }
 112
 113
 114 /* set data out value using dedicate set/clear register */
 115 static void omap_set_gpio_dataout_reg(struct gpio_bank *bank, unsigned offset,
 116                                       int enable)
 117 {
 118         void __iomem *reg = bank->base;
 119         u32 l = BIT(offset);
 120
 121         if (enable) {
 122                 reg += bank->regs->set_dataout;
 123                 bank->context.dataout |= l;
 124         } else {
 125                 reg += bank->regs->clr_dataout;
 126                 bank->context.dataout &= ~l;
 127         }
 128
 129         writel_relaxed(l, reg);
 130 }
 131
 132 /* set data out value using mask register */
 133 static void omap_set_gpio_dataout_mask(struct gpio_bank *bank, unsigned offset,
 134                                        int enable)
 135 {
 136         void __iomem *reg = bank->base + bank->regs->dataout;
 137         u32 gpio_bit = BIT(offset);
 138         u32 l;
 139
 140         l = readl_relaxed(reg);
 141         if (enable)
 142                 l |= gpio_bit;
 143         else
 144                 l &= ~gpio_bit;
 145         writel_relaxed(l, reg);
 146         bank->context.dataout = l;
 147 }
 148
 149 static int omap_get_gpio_datain(struct gpio_bank *bank, int offset)
 150 {
 151         void __iomem *reg = bank->base + bank->regs->datain;
 152
 153         return (readl_relaxed(reg) & (BIT(offset))) != 0;
 154 }
 155
 156 static int omap_get_gpio_dataout(struct gpio_bank *bank, int offset)
 157 {
 158         void __iomem *reg = bank->base + bank->regs->dataout;
 159
 160         return (readl_relaxed(reg) & (BIT(offset))) != 0;
 161 }
 162
 163 /* set multiple data out values using dedicate set/clear register */
 164 static void omap_set_gpio_dataout_reg_multiple(struct gpio_bank *bank,
 165                                                unsigned long *mask,
 166                                                unsigned long *bits)
 167 {
 168         void __iomem *reg = bank->base;
 169         u32 l;
 170
 171         l = *bits & *mask;
 172         writel_relaxed(l, reg + bank->regs->set_dataout);
 173         bank->context.dataout |= l;
 174
 175         l = ~*bits & *mask;
 176         writel_relaxed(l, reg + bank->regs->clr_dataout);
 177         bank->context.dataout &= ~l;
 178 }
 179
 180 /* set multiple data out values using mask register */
 181 static void omap_set_gpio_dataout_mask_multiple(struct gpio_bank *bank,
 182                                                 unsigned long *mask,
 183                                                 unsigned long *bits)
 184 {
 185         void __iomem *reg = bank->base + bank->regs->dataout;
 186         u32 l = (readl_relaxed(reg) & ~*mask) | (*bits & *mask);
 187
 188         writel_relaxed(l, reg);
 189         bank->context.dataout = l;
 190 }
 191
 192 static unsigned long omap_get_gpio_datain_multiple(struct gpio_bank *bank,
 193                                               unsigned long *mask)
 194 {
 195         void __iomem *reg = bank->base + bank->regs->datain;
 196
 197         return readl_relaxed(reg) & *mask;
 198 }
 199
 200 static unsigned long omap_get_gpio_dataout_multiple(struct gpio_bank *bank,
 201                                                unsigned long *mask)
 202 {
 203         void __iomem *reg = bank->base + bank->regs->dataout;
 204
 205         return readl_relaxed(reg) & *mask;
 206 }
 207
 208 static inline void omap_gpio_rmw(void __iomem *base, u32 reg, u32 mask, bool set)
 209 {
 210         int l = readl_relaxed(base + reg);
 211
 212         if (set)
 213                 l |= mask;
 214         else
 215                 l &= ~mask;
 216
 217         writel_relaxed(l, base + reg);
 218 }
 219
 220 static inline void omap_gpio_dbck_enable(struct gpio_bank *bank)
 221 {
 222         if (bank->dbck_enable_mask && !bank->dbck_enabled) {
 223                 clk_enable(bank->dbck);
 224                 bank->dbck_enabled = true;
 225
 226                 writel_relaxed(bank->dbck_enable_mask,
 227                              bank->base + bank->regs->debounce_en);
 228         }
 229 }
 230
 231 static inline void omap_gpio_dbck_disable(struct gpio_bank *bank)
 232 {
 233         if (bank->dbck_enable_mask && bank->dbck_enabled) {
 234                 /*
 235                  * Disable debounce before cutting it's clock. If debounce is
 236                  * enabled but the clock is not, GPIO module seems to be unable
 237                  * to detect events and generate interrupts at least on OMAP3.
 238                  */
 239                 writel_relaxed(0, bank->base + bank->regs->debounce_en);
 240
 241                 clk_disable(bank->dbck);
 242                 bank->dbck_enabled = false;
 243         }
 244 }
 245
 246 /**
 247  * omap2_set_gpio_debounce - low level gpio debounce time
 248  * @bank: the gpio bank we're acting upon
 249  * @offset: the gpio number on this @bank
 250  * @debounce: debounce time to use
 251  *
 252  * OMAP's debounce time is in 31us steps
 253  *   <debounce time> = (GPIO_DEBOUNCINGTIME[7:0].DEBOUNCETIME + 1) x 31
 254  * so we need to convert and round up to the closest unit.
 255  *
 256  * Return: 0 on success, negative error otherwise.
 257  */
 258 static int omap2_set_gpio_debounce(struct gpio_bank *bank, unsigned offset,
 259                                    unsigned debounce)
 260 {
 261         void __iomem            *reg;
 262         u32                     val;
 263         u32                     l;
 264         bool                    enable = !!debounce;
 265
 266         if (!bank->dbck_flag)
 267                 return -ENOTSUPP;
 268
 269         if (enable) {
 270                 debounce = DIV_ROUND_UP(debounce, 31) - 1;
 271                 if ((debounce & OMAP4_GPIO_DEBOUNCINGTIME_MASK) != debounce)
 272                         return -EINVAL;
 273         }
 274
 275         l = BIT(offset);
 276
 277         clk_enable(bank->dbck);
 278         reg = bank->base + bank->regs->debounce;
 279         writel_relaxed(debounce, reg);
 280
 281         reg = bank->base + bank->regs->debounce_en;
 282         val = readl_relaxed(reg);
 283
 284         if (enable)
 285                 val |= l;
 286         else
 287                 val &= ~l;
 288         bank->dbck_enable_mask = val;
 289
 290         writel_relaxed(val, reg);
 291         clk_disable(bank->dbck);
 292         /*
 293          * Enable debounce clock per module.
 294          * This call is mandatory because in omap_gpio_request() when
 295          * *_runtime_get_sync() is called,  _gpio_dbck_enable() within
 296          * runtime callbck fails to turn on dbck because dbck_enable_mask
 297          * used within _gpio_dbck_enable() is still not initialized at
 298          * that point. Therefore we have to enable dbck here.
 299          */
 300         omap_gpio_dbck_enable(bank);
 301         if (bank->dbck_enable_mask) {
 302                 bank->context.debounce = debounce;
 303                 bank->context.debounce_en = val;
 304         }
 305
 306         return 0;
 307 }
 308
 309 /**
 310  * omap_clear_gpio_debounce - clear debounce settings for a gpio
 311  * @bank: the gpio bank we're acting upon
 312  * @offset: the gpio number on this @bank
 313  *
 314  * If a gpio is using debounce, then clear the debounce enable bit and if
 315  * this is the only gpio in this bank using debounce, then clear the debounce
 316  * time too. The debounce clock will also be disabled when calling this function
 317  * if this is the only gpio in the bank using debounce.
 318  */
 319 static void omap_clear_gpio_debounce(struct gpio_bank *bank, unsigned offset)
 320 {
 321         u32 gpio_bit = BIT(offset);
 322
 323         if (!bank->dbck_flag)
 324                 return;
 325
 326         if (!(bank->dbck_enable_mask & gpio_bit))
 327                 return;
 328
 329         bank->dbck_enable_mask &= ~gpio_bit;
 330         bank->context.debounce_en &= ~gpio_bit;
 331         writel_relaxed(bank->context.debounce_en,
 332                      bank->base + bank->regs->debounce_en);
 333
 334         if (!bank->dbck_enable_mask) {
 335                 bank->context.debounce = 0;
 336                 writel_relaxed(bank->context.debounce, bank->base +
 337                              bank->regs->debounce);
 338                 clk_disable(bank->dbck);
 339                 bank->dbck_enabled = false;
 340         }
 341 }
 342
 343 /*
 344  * Off mode wake-up capable GPIOs in bank(s) that are in the wakeup domain.
 345  * See TRM section for GPIO for "Wake-Up Generation" for the list of GPIOs
 346  * in wakeup domain. If bank->non_wakeup_gpios is not configured, assume none
 347  * are capable waking up the system from off mode.
 348  */
 349 static bool omap_gpio_is_off_wakeup_capable(struct gpio_bank *bank, u32 gpio_mask)
 350 {
 351         u32 no_wake = bank->non_wakeup_gpios;
 352
 353         if (no_wake)
 354                 return !!(~no_wake & gpio_mask);
 355
 356         return false;
 357 }
 358
 359 static inline void omap_set_gpio_trigger(struct gpio_bank *bank, int gpio,
 360                                                 unsigned trigger)
 361 {
 362         void __iomem *base = bank->base;
 363         u32 gpio_bit = BIT(gpio);
 364
 365         omap_gpio_rmw(base, bank->regs->leveldetect0, gpio_bit,
 366                       trigger & IRQ_TYPE_LEVEL_LOW);
 367         omap_gpio_rmw(base, bank->regs->leveldetect1, gpio_bit,
 368                       trigger & IRQ_TYPE_LEVEL_HIGH);
 369
 370         /*
 371          * We need the edge detection enabled for to allow the GPIO block
 372          * to be woken from idle state.  Set the appropriate edge detection
 373          * in addition to the level detection.
 374          */
 375         omap_gpio_rmw(base, bank->regs->risingdetect, gpio_bit,
 376                       trigger & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_LEVEL_HIGH));
 377         omap_gpio_rmw(base, bank->regs->fallingdetect, gpio_bit,
 378                       trigger & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_LEVEL_LOW));
 379
 380         bank->context.leveldetect0 =
 381                         readl_relaxed(bank->base + bank->regs->leveldetect0);
 382         bank->context.leveldetect1 =
 383                         readl_relaxed(bank->base + bank->regs->leveldetect1);
 384         bank->context.risingdetect =
 385                         readl_relaxed(bank->base + bank->regs->risingdetect);
 386         bank->context.fallingdetect =
 387                         readl_relaxed(bank->base + bank->regs->fallingdetect);
 388
 389         if (likely(!(bank->non_wakeup_gpios & gpio_bit))) {
 390                 omap_gpio_rmw(base, bank->regs->wkup_en, gpio_bit, trigger != 0);
 391                 bank->context.wake_en =
 392                         readl_relaxed(bank->base + bank->regs->wkup_en);
 393         }
 394
 395         /* This part needs to be executed always for OMAP{34xx, 44xx} */
 396         if (!bank->regs->irqctrl && !omap_gpio_is_off_wakeup_capable(bank, gpio)) {
 397                 /*
 398                  * Log the edge gpio and manually trigger the IRQ
 399                  * after resume if the input level changes
 400                  * to avoid irq lost during PER RET/OFF mode
 401                  * Applies for omap2 non-wakeup gpio and all omap3 gpios
 402                  */
 403                 if (trigger & IRQ_TYPE_EDGE_BOTH)
 404                         bank->enabled_non_wakeup_gpios |= gpio_bit;
 405                 else
 406                         bank->enabled_non_wakeup_gpios &= ~gpio_bit;
 407         }
 408
 409         bank->level_mask =
 410                 readl_relaxed(bank->base + bank->regs->leveldetect0) |
 411                 readl_relaxed(bank->base + bank->regs->leveldetect1);
 412 }
 413
 414 #ifdef CONFIG_ARCH_OMAP1
 415 /*
 416  * This only applies to chips that can't do both rising and falling edge
 417  * detection at once.  For all other chips, this function is a noop.
 418  */
 419 static void omap_toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio)
 420 {
 421         void __iomem *reg = bank->base;
 422         u32 l = 0;
 423
 424         if (!bank->regs->irqctrl)
 425                 return;
 426
 427         reg += bank->regs->irqctrl;
 428
 429         l = readl_relaxed(reg);
 430         if ((l >> gpio) & 1)
 431                 l &= ~(BIT(gpio));
 432         else
 433                 l |= BIT(gpio);
 434
 435         writel_relaxed(l, reg);
 436 }
 437 #else
 438 static void omap_toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio) {}
 439 #endif
 440
 441 static int omap_set_gpio_triggering(struct gpio_bank *bank, int gpio,
 442                                     unsigned trigger)
 443 {
 444         void __iomem *reg = bank->base;
 445         void __iomem *base = bank->base;
 446         u32 l = 0;
 447
 448         if (bank->regs->leveldetect0 && bank->regs->wkup_en) {
 449                 omap_set_gpio_trigger(bank, gpio, trigger);
 450         } else if (bank->regs->irqctrl) {
 451                 reg += bank->regs->irqctrl;
 452
 453                 l = readl_relaxed(reg);
 454                 if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
 455                         bank->toggle_mask |= BIT(gpio);
 456                 if (trigger & IRQ_TYPE_EDGE_RISING)
 457                         l |= BIT(gpio);
 458                 else if (trigger & IRQ_TYPE_EDGE_FALLING)
 459                         l &= ~(BIT(gpio));
 460                 else
 461                         return -EINVAL;
 462
 463                 writel_relaxed(l, reg);
 464         } else if (bank->regs->edgectrl1) {
 465                 if (gpio & 0x08)
 466                         reg += bank->regs->edgectrl2;
 467                 else
 468                         reg += bank->regs->edgectrl1;
 469
 470                 gpio &= 0x07;
 471                 l = readl_relaxed(reg);
 472                 l &= ~(3 << (gpio << 1));
 473                 if (trigger & IRQ_TYPE_EDGE_RISING)
 474                         l |= 2 << (gpio << 1);
 475                 if (trigger & IRQ_TYPE_EDGE_FALLING)
 476                         l |= BIT(gpio << 1);
 477
 478                 /* Enable wake-up during idle for dynamic tick */
 479                 omap_gpio_rmw(base, bank->regs->wkup_en, BIT(gpio), trigger);
 480                 bank->context.wake_en =
 481                         readl_relaxed(bank->base + bank->regs->wkup_en);
 482                 writel_relaxed(l, reg);
 483         }
 484         return 0;
 485 }
 486
 487 static void omap_enable_gpio_module(struct gpio_bank *bank, unsigned offset)
 488 {
 489         if (bank->regs->pinctrl) {
 490                 void __iomem *reg = bank->base + bank->regs->pinctrl;
 491
 492                 /* Claim the pin for MPU */
 493                 writel_relaxed(readl_relaxed(reg) | (BIT(offset)), reg);
 494         }
 495
 496         if (bank->regs->ctrl && !BANK_USED(bank)) {
 497                 void __iomem *reg = bank->base + bank->regs->ctrl;
 498                 u32 ctrl;
 499
 500                 ctrl = readl_relaxed(reg);
 501                 /* Module is enabled, clocks are not gated */
 502                 ctrl &= ~GPIO_MOD_CTRL_BIT;
 503                 writel_relaxed(ctrl, reg);
 504                 bank->context.ctrl = ctrl;
 505         }
 506 }
 507
 508 static void omap_disable_gpio_module(struct gpio_bank *bank, unsigned offset)
 509 {
 510         void __iomem *base = bank->base;
 511
 512         if (bank->regs->wkup_en &&
 513             !LINE_USED(bank->mod_usage, offset) &&
 514             !LINE_USED(bank->irq_usage, offset)) {
 515                 /* Disable wake-up during idle for dynamic tick */
 516                 omap_gpio_rmw(base, bank->regs->wkup_en, BIT(offset), 0);
 517                 bank->context.wake_en =
 518                         readl_relaxed(bank->base + bank->regs->wkup_en);
 519         }
 520
 521         if (bank->regs->ctrl && !BANK_USED(bank)) {
 522                 void __iomem *reg = bank->base + bank->regs->ctrl;
 523                 u32 ctrl;
 524
 525                 ctrl = readl_relaxed(reg);
 526                 /* Module is disabled, clocks are gated */
 527                 ctrl |= GPIO_MOD_CTRL_BIT;
 528                 writel_relaxed(ctrl, reg);
 529                 bank->context.ctrl = ctrl;
 530         }
 531 }
 532
 533 static int omap_gpio_is_input(struct gpio_bank *bank, unsigned offset)
 534 {
 535         void __iomem *reg = bank->base + bank->regs->direction;
 536
 537         return readl_relaxed(reg) & BIT(offset);
 538 }
 539
 540 static void omap_gpio_init_irq(struct gpio_bank *bank, unsigned offset)
 541 {
 542         if (!LINE_USED(bank->mod_usage, offset)) {
 543                 omap_enable_gpio_module(bank, offset);
 544                 omap_set_gpio_direction(bank, offset, 1);
 545         }
 546         bank->irq_usage |= BIT(offset);
 547 }
 548
 549 static int omap_gpio_irq_type(struct irq_data *d, unsigned type)
 550 {
 551         struct gpio_bank *bank = omap_irq_data_get_bank(d);
 552         int retval;
 553         unsigned long flags;
 554         unsigned offset = d->hwirq;
 555
 556         if (type & ~IRQ_TYPE_SENSE_MASK)
 557                 return -EINVAL;
 558
 559         if (!bank->regs->leveldetect0 &&
 560                 (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH)))
 561                 return -EINVAL;
 562
 563         raw_spin_lock_irqsave(&bank->lock, flags);
 564         retval = omap_set_gpio_triggering(bank, offset, type);
 565         if (retval) {
 566                 raw_spin_unlock_irqrestore(&bank->lock, flags);
 567                 goto error;
 568         }
 569         omap_gpio_init_irq(bank, offset);
 570         if (!omap_gpio_is_input(bank, offset)) {
 571                 raw_spin_unlock_irqrestore(&bank->lock, flags);
 572                 retval = -EINVAL;
 573                 goto error;
 574         }
 575         raw_spin_unlock_irqrestore(&bank->lock, flags);
 576
 577         if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
 578                 irq_set_handler_locked(d, handle_level_irq);
 579         else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
 580                 /*
 581                  * Edge IRQs are already cleared/acked in irq_handler and
 582                  * not need to be masked, as result handle_edge_irq()
 583                  * logic is excessed here and may cause lose of interrupts.
 584                  * So just use handle_simple_irq.
 585                  */
 586                 irq_set_handler_locked(d, handle_simple_irq);
 587
 588         return 0;
 589
 590 error:
 591         return retval;
 592 }
 593
 594 static void omap_clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
 595 {
 596         void __iomem *reg = bank->base;
 597
 598         reg += bank->regs->irqstatus;
 599         writel_relaxed(gpio_mask, reg);
 600
 601         /* Workaround for clearing DSP GPIO interrupts to allow retention */
 602         if (bank->regs->irqstatus2) {
 603                 reg = bank->base + bank->regs->irqstatus2;
 604                 writel_relaxed(gpio_mask, reg);
 605         }
 606
 607         /* Flush posted write for the irq status to avoid spurious interrupts */
 608         readl_relaxed(reg);
 609 }
 610
 611 static inline void omap_clear_gpio_irqstatus(struct gpio_bank *bank,
 612                                              unsigned offset)
 613 {
 614         omap_clear_gpio_irqbank(bank, BIT(offset));
 615 }
 616
 617 static u32 omap_get_gpio_irqbank_mask(struct gpio_bank *bank)
 618 {
 619         void __iomem *reg = bank->base;
 620         u32 l;
 621         u32 mask = (BIT(bank->width)) - 1;
 622
 623         reg += bank->regs->irqenable;
 624         l = readl_relaxed(reg);
 625         if (bank->regs->irqenable_inv)
 626                 l = ~l;
 627         l &= mask;
 628         return l;
 629 }
 630
 631 static void omap_enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
 632 {
 633         void __iomem *reg = bank->base;
 634         u32 l;
 635
 636         if (bank->regs->set_irqenable) {
 637                 reg += bank->regs->set_irqenable;
 638                 l = gpio_mask;
 639                 bank->context.irqenable1 |= gpio_mask;
 640         } else {
 641                 reg += bank->regs->irqenable;
 642                 l = readl_relaxed(reg);
 643                 if (bank->regs->irqenable_inv)
 644                         l &= ~gpio_mask;
 645                 else
 646                         l |= gpio_mask;
 647                 bank->context.irqenable1 = l;
 648         }
 649
 650         writel_relaxed(l, reg);
 651 }
 652
 653 static void omap_disable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
 654 {
 655         void __iomem *reg = bank->base;
 656         u32 l;
 657
 658         if (bank->regs->clr_irqenable) {
 659                 reg += bank->regs->clr_irqenable;
 660                 l = gpio_mask;
 661                 bank->context.irqenable1 &= ~gpio_mask;
 662         } else {
 663                 reg += bank->regs->irqenable;
 664                 l = readl_relaxed(reg);
 665                 if (bank->regs->irqenable_inv)
 666                         l |= gpio_mask;
 667                 else
 668                         l &= ~gpio_mask;
 669                 bank->context.irqenable1 = l;
 670         }
 671
 672         writel_relaxed(l, reg);
 673 }
 674
 675 static inline void omap_set_gpio_irqenable(struct gpio_bank *bank,
 676                                            unsigned offset, int enable)
 677 {
 678         if (enable)
 679                 omap_enable_gpio_irqbank(bank, BIT(offset));
 680         else
 681                 omap_disable_gpio_irqbank(bank, BIT(offset));
 682 }
 683
 684 /* Use disable_irq_wake() and enable_irq_wake() functions from drivers */
 685 static int omap_gpio_wake_enable(struct irq_data *d, unsigned int enable)
 686 {
 687         struct gpio_bank *bank = omap_irq_data_get_bank(d);
 688
 689         return irq_set_irq_wake(bank->irq, enable);
 690 }
 691
 692 static int omap_gpio_request(struct gpio_chip *chip, unsigned offset)
 693 {
 694         struct gpio_bank *bank = gpiochip_get_data(chip);
 695         unsigned long flags;
 696
 697         pm_runtime_get_sync(chip->parent);
 698
 699         raw_spin_lock_irqsave(&bank->lock, flags);
 700         omap_enable_gpio_module(bank, offset);
 701         bank->mod_usage |= BIT(offset);
 702         raw_spin_unlock_irqrestore(&bank->lock, flags);
 703
 704         return 0;
 705 }
 706
 707 static void omap_gpio_free(struct gpio_chip *chip, unsigned offset)
 708 {
 709         struct gpio_bank *bank = gpiochip_get_data(chip);
 710         unsigned long flags;
 711
 712         raw_spin_lock_irqsave(&bank->lock, flags);
 713         bank->mod_usage &= ~(BIT(offset));
 714         if (!LINE_USED(bank->irq_usage, offset)) {
 715                 omap_set_gpio_direction(bank, offset, 1);
 716                 omap_clear_gpio_debounce(bank, offset);
 717         }
 718         omap_disable_gpio_module(bank, offset);
 719         raw_spin_unlock_irqrestore(&bank->lock, flags);
 720
 721         pm_runtime_put(chip->parent);
 722 }
 723
 724 /*
 725  * We need to unmask the GPIO bank interrupt as soon as possible to
 726  * avoid missing GPIO interrupts for other lines in the bank.
 727  * Then we need to mask-read-clear-unmask the triggered GPIO lines
 728  * in the bank to avoid missing nested interrupts for a GPIO line.
 729  * If we wait to unmask individual GPIO lines in the bank after the
 730  * line's interrupt handler has been run, we may miss some nested
 731  * interrupts.
 732  */
 733 static irqreturn_t omap_gpio_irq_handler(int irq, void *gpiobank)
 734 {
 735         void __iomem *isr_reg = NULL;
 736         u32 enabled, isr, edge;
 737         unsigned int bit;
 738         struct gpio_bank *bank = gpiobank;
 739         unsigned long wa_lock_flags;
 740         unsigned long lock_flags;
 741
 742         isr_reg = bank->base + bank->regs->irqstatus;
 743         if (WARN_ON(!isr_reg))
 744                 goto exit;
 745
 746         if (WARN_ONCE(!pm_runtime_active(bank->chip.parent),
 747                       "gpio irq%i while runtime suspended?\n", irq))
 748                 return IRQ_NONE;
 749
 750         while (1) {
 751                 raw_spin_lock_irqsave(&bank->lock, lock_flags);
 752
 753                 enabled = omap_get_gpio_irqbank_mask(bank);
 754                 isr = readl_relaxed(isr_reg) & enabled;
 755
 756                 /*
 757                  * Clear edge sensitive interrupts before calling handler(s)
 758                  * so subsequent edge transitions are not missed while the
 759                  * handlers are running.
 760                  */
 761                 edge = isr & ~bank->level_mask;
 762                 if (edge)
 763                         omap_clear_gpio_irqbank(bank, edge);
 764
 765                 raw_spin_unlock_irqrestore(&bank->lock, lock_flags);
 766
 767                 if (!isr)
 768                         break;
 769
 770                 while (isr) {
 771                         bit = __ffs(isr);
 772                         isr &= ~(BIT(bit));
 773
 774                         raw_spin_lock_irqsave(&bank->lock, lock_flags);
 775                         /*
 776                          * Some chips can't respond to both rising and falling
 777                          * at the same time.  If this irq was requested with
 778                          * both flags, we need to flip the ICR data for the IRQ
 779                          * to respond to the IRQ for the opposite direction.
 780                          * This will be indicated in the bank toggle_mask.
 781                          */
 782                         if (bank->toggle_mask & (BIT(bit)))
 783                                 omap_toggle_gpio_edge_triggering(bank, bit);
 784
 785                         raw_spin_unlock_irqrestore(&bank->lock, lock_flags);
 786
 787                         raw_spin_lock_irqsave(&bank->wa_lock, wa_lock_flags);
 788
 789                         generic_handle_irq(irq_find_mapping(bank->chip.irq.domain,
 790                                                             bit));
 791
 792                         raw_spin_unlock_irqrestore(&bank->wa_lock,
 793                                                    wa_lock_flags);
 794                 }
 795         }
 796 exit:
 797         return IRQ_HANDLED;
 798 }
 799
 800 static unsigned int omap_gpio_irq_startup(struct irq_data *d)
 801 {
 802         struct gpio_bank *bank = omap_irq_data_get_bank(d);
 803         unsigned long flags;
 804         unsigned offset = d->hwirq;
 805
 806         raw_spin_lock_irqsave(&bank->lock, flags);
 807
 808         if (!LINE_USED(bank->mod_usage, offset))
 809                 omap_set_gpio_direction(bank, offset, 1);
 810         else if (!omap_gpio_is_input(bank, offset))
 811                 goto err;
 812         omap_enable_gpio_module(bank, offset);
 813         bank->irq_usage |= BIT(offset);
 814
 815         raw_spin_unlock_irqrestore(&bank->lock, flags);
 816         omap_gpio_unmask_irq(d);
 817
 818         return 0;
 819 err:
 820         raw_spin_unlock_irqrestore(&bank->lock, flags);
 821         return -EINVAL;
 822 }
 823
 824 static void omap_gpio_irq_shutdown(struct irq_data *d)
 825 {
 826         struct gpio_bank *bank = omap_irq_data_get_bank(d);
 827         unsigned long flags;
 828         unsigned offset = d->hwirq;
 829
 830         raw_spin_lock_irqsave(&bank->lock, flags);
 831         bank->irq_usage &= ~(BIT(offset));
 832         omap_set_gpio_triggering(bank, offset, IRQ_TYPE_NONE);
 833         omap_clear_gpio_irqstatus(bank, offset);
 834         omap_set_gpio_irqenable(bank, offset, 0);
 835         if (!LINE_USED(bank->mod_usage, offset))
 836                 omap_clear_gpio_debounce(bank, offset);
 837         omap_disable_gpio_module(bank, offset);
 838         raw_spin_unlock_irqrestore(&bank->lock, flags);
 839 }
 840
 841 static void omap_gpio_irq_bus_lock(struct irq_data *data)
 842 {
 843         struct gpio_bank *bank = omap_irq_data_get_bank(data);
 844
 845         pm_runtime_get_sync(bank->chip.parent);
 846 }
 847
 848 static void gpio_irq_bus_sync_unlock(struct irq_data *data)
 849 {
 850         struct gpio_bank *bank = omap_irq_data_get_bank(data);
 851
 852         pm_runtime_put(bank->chip.parent);
 853 }
 854
 855 static void omap_gpio_ack_irq(struct irq_data *d)
 856 {
 857         struct gpio_bank *bank = omap_irq_data_get_bank(d);
 858         unsigned offset = d->hwirq;
 859
 860         omap_clear_gpio_irqstatus(bank, offset);
 861 }
 862
 863 static void omap_gpio_mask_irq(struct irq_data *d)
 864 {
 865         struct gpio_bank *bank = omap_irq_data_get_bank(d);
 866         unsigned offset = d->hwirq;
 867         unsigned long flags;
 868
 869         raw_spin_lock_irqsave(&bank->lock, flags);
 870         omap_set_gpio_triggering(bank, offset, IRQ_TYPE_NONE);
 871         omap_set_gpio_irqenable(bank, offset, 0);
 872         raw_spin_unlock_irqrestore(&bank->lock, flags);
 873 }
 874
 875 static void omap_gpio_unmask_irq(struct irq_data *d)
 876 {
 877         struct gpio_bank *bank = omap_irq_data_get_bank(d);
 878         unsigned offset = d->hwirq;
 879         u32 trigger = irqd_get_trigger_type(d);
 880         unsigned long flags;
 881
 882         raw_spin_lock_irqsave(&bank->lock, flags);
 883         omap_set_gpio_irqenable(bank, offset, 1);
 884
 885         /*
 886          * For level-triggered GPIOs, clearing must be done after the source
 887          * is cleared, thus after the handler has run. OMAP4 needs this done
 888          * after enabing the interrupt to clear the wakeup status.
 889          */
 890         if (bank->regs->leveldetect0 && bank->regs->wkup_en &&
 891             trigger & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW))
 892                 omap_clear_gpio_irqstatus(bank, offset);
 893
 894         if (trigger)
 895                 omap_set_gpio_triggering(bank, offset, trigger);
 896
 897         raw_spin_unlock_irqrestore(&bank->lock, flags);
 898 }
 899
 900 /*---------------------------------------------------------------------*/
 901
 902 static int omap_mpuio_suspend_noirq(struct device *dev)
 903 {
 904         struct gpio_bank        *bank = dev_get_drvdata(dev);
 905         void __iomem            *mask_reg = bank->base +
 906                                         OMAP_MPUIO_GPIO_MASKIT / bank->stride;
 907         unsigned long           flags;
 908
 909         raw_spin_lock_irqsave(&bank->lock, flags);
 910         writel_relaxed(0xffff & ~bank->context.wake_en, mask_reg);
 911         raw_spin_unlock_irqrestore(&bank->lock, flags);
 912
 913         return 0;
 914 }
 915
 916 static int omap_mpuio_resume_noirq(struct device *dev)
 917 {
 918         struct gpio_bank        *bank = dev_get_drvdata(dev);
 919         void __iomem            *mask_reg = bank->base +
 920                                         OMAP_MPUIO_GPIO_MASKIT / bank->stride;
 921         unsigned long           flags;
 922
 923         raw_spin_lock_irqsave(&bank->lock, flags);
 924         writel_relaxed(bank->context.wake_en, mask_reg);
 925         raw_spin_unlock_irqrestore(&bank->lock, flags);
 926
 927         return 0;
 928 }
 929
 930 static const struct dev_pm_ops omap_mpuio_dev_pm_ops = {
 931         .suspend_noirq = omap_mpuio_suspend_noirq,
 932         .resume_noirq = omap_mpuio_resume_noirq,
 933 };
 934
 935 /* use platform_driver for this. */
 936 static struct platform_driver omap_mpuio_driver = {
 937         .driver         = {
 938                 .name   = "mpuio",
 939                 .pm     = &omap_mpuio_dev_pm_ops,
 940         },
 941 };
 942
 943 static struct platform_device omap_mpuio_device = {
 944         .name           = "mpuio",
 945         .id             = -1,
 946         .dev = {
 947                 .driver = &omap_mpuio_driver.driver,
 948         }
 949         /* could list the /proc/iomem resources */
 950 };
 951
 952 static inline void omap_mpuio_init(struct gpio_bank *bank)
 953 {
 954         platform_set_drvdata(&omap_mpuio_device, bank);
 955
 956         if (platform_driver_register(&omap_mpuio_driver) == 0)
 957                 (void) platform_device_register(&omap_mpuio_device);
 958 }
 959
 960 /*---------------------------------------------------------------------*/
 961
 962 static int omap_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
 963 {
 964         struct gpio_bank *bank;
 965         unsigned long flags;
 966         void __iomem *reg;
 967         int dir;
 968
 969         bank = gpiochip_get_data(chip);
 970         reg = bank->base + bank->regs->direction;
 971         raw_spin_lock_irqsave(&bank->lock, flags);
 972         dir = !!(readl_relaxed(reg) & BIT(offset));
 973         raw_spin_unlock_irqrestore(&bank->lock, flags);
 974         return dir;
 975 }
 976
 977 static int omap_gpio_input(struct gpio_chip *chip, unsigned offset)
 978 {
 979         struct gpio_bank *bank;
 980         unsigned long flags;
 981
 982         bank = gpiochip_get_data(chip);
 983         raw_spin_lock_irqsave(&bank->lock, flags);
 984         omap_set_gpio_direction(bank, offset, 1);
 985         raw_spin_unlock_irqrestore(&bank->lock, flags);
 986         return 0;
 987 }
 988
 989 static int omap_gpio_get(struct gpio_chip *chip, unsigned offset)
 990 {
 991         struct gpio_bank *bank;
 992
 993         bank = gpiochip_get_data(chip);
 994
 995         if (omap_gpio_is_input(bank, offset))
 996                 return omap_get_gpio_datain(bank, offset);
 997         else
 998                 return omap_get_gpio_dataout(bank, offset);
 999 }
1000
1001 static int omap_gpio_output(struct gpio_chip *chip, unsigned offset, int value)
1002 {
1003         struct gpio_bank *bank;
1004         unsigned long flags;
1005
1006         bank = gpiochip_get_data(chip);
1007         raw_spin_lock_irqsave(&bank->lock, flags);
1008         bank->set_dataout(bank, offset, value);
1009         omap_set_gpio_direction(bank, offset, 0);
1010         raw_spin_unlock_irqrestore(&bank->lock, flags);
1011         return 0;
1012 }
1013
1014 static int omap_gpio_get_multiple(struct gpio_chip *chip, unsigned long *mask,
1015                                   unsigned long *bits)
1016 {
1017         struct gpio_bank *bank = gpiochip_get_data(chip);
1018         void __iomem *reg = bank->base + bank->regs->direction;
1019         unsigned long in = readl_relaxed(reg), l;
1020
1021         *bits = 0;
1022
1023         l = in & *mask;
1024         if (l)
1025                 *bits |= omap_get_gpio_datain_multiple(bank, &l);
1026
1027         l = ~in & *mask;
1028         if (l)
1029                 *bits |= omap_get_gpio_dataout_multiple(bank, &l);
1030
1031         return 0;
1032 }
1033
1034 static int omap_gpio_debounce(struct gpio_chip *chip, unsigned offset,
1035                               unsigned debounce)
1036 {
1037         struct gpio_bank *bank;
1038         unsigned long flags;
1039         int ret;
1040
1041         bank = gpiochip_get_data(chip);
1042
1043         raw_spin_lock_irqsave(&bank->lock, flags);
1044         ret = omap2_set_gpio_debounce(bank, offset, debounce);
1045         raw_spin_unlock_irqrestore(&bank->lock, flags);
1046
1047         if (ret)
1048                 dev_info(chip->parent,
1049                          "Could not set line %u debounce to %u microseconds (%d)",
1050                          offset, debounce, ret);
1051
1052         return ret;
1053 }
1054
1055 static int omap_gpio_set_config(struct gpio_chip *chip, unsigned offset,
1056                                 unsigned long config)
1057 {
1058         u32 debounce;
1059
1060         if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE)
1061                 return -ENOTSUPP;
1062
1063         debounce = pinconf_to_config_argument(config);
1064         return omap_gpio_debounce(chip, offset, debounce);
1065 }
1066
1067 static void omap_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
1068 {
1069         struct gpio_bank *bank;
1070         unsigned long flags;
1071
1072         bank = gpiochip_get_data(chip);
1073         raw_spin_lock_irqsave(&bank->lock, flags);
1074         bank->set_dataout(bank, offset, value);
1075         raw_spin_unlock_irqrestore(&bank->lock, flags);
1076 }
1077
1078 static void omap_gpio_set_multiple(struct gpio_chip *chip, unsigned long *mask,
1079                                    unsigned long *bits)
1080 {
1081         struct gpio_bank *bank = gpiochip_get_data(chip);
1082         unsigned long flags;
1083
1084         raw_spin_lock_irqsave(&bank->lock, flags);
1085         bank->set_dataout_multiple(bank, mask, bits);
1086         raw_spin_unlock_irqrestore(&bank->lock, flags);
1087 }
1088
1089 /*---------------------------------------------------------------------*/
1090
1091 static void omap_gpio_show_rev(struct gpio_bank *bank)
1092 {
1093         static bool called;
1094         u32 rev;
1095
1096         if (called || bank->regs->revision == USHRT_MAX)
1097                 return;
1098
1099         rev = readw_relaxed(bank->base + bank->regs->revision);
1100         pr_info("OMAP GPIO hardware version %d.%d\n",
1101                 (rev >> 4) & 0x0f, rev & 0x0f);
1102
1103         called = true;
1104 }
1105
1106 static void omap_gpio_mod_init(struct gpio_bank *bank)
1107 {
1108         void __iomem *base = bank->base;
1109         u32 l = 0xffffffff;
1110
1111         if (bank->width == 16)
1112                 l = 0xffff;
1113
1114         if (bank->is_mpuio) {
1115                 writel_relaxed(l, bank->base + bank->regs->irqenable);
1116                 return;
1117         }
1118
1119         omap_gpio_rmw(base, bank->regs->irqenable, l,
1120                       bank->regs->irqenable_inv);
1121         omap_gpio_rmw(base, bank->regs->irqstatus, l,
1122                       !bank->regs->irqenable_inv);
1123         if (bank->regs->debounce_en)
1124                 writel_relaxed(0, base + bank->regs->debounce_en);
1125
1126         /* Save OE default value (0xffffffff) in the context */
1127         bank->context.oe = readl_relaxed(bank->base + bank->regs->direction);
1128          /* Initialize interface clk ungated, module enabled */
1129         if (bank->regs->ctrl)
1130                 writel_relaxed(0, base + bank->regs->ctrl);
1131 }
1132
1133 static int omap_gpio_chip_init(struct gpio_bank *bank, struct irq_chip *irqc)
1134 {
1135         struct gpio_irq_chip *irq;
1136         static int gpio;
1137         const char *label;
1138         int irq_base = 0;
1139         int ret;
1140
1141         /*
1142          * REVISIT eventually switch from OMAP-specific gpio structs
1143          * over to the generic ones
1144          */
1145         bank->chip.request = omap_gpio_request;
1146         bank->chip.free = omap_gpio_free;
1147         bank->chip.get_direction = omap_gpio_get_direction;
1148         bank->chip.direction_input = omap_gpio_input;
1149         bank->chip.get = omap_gpio_get;
1150         bank->chip.get_multiple = omap_gpio_get_multiple;
1151         bank->chip.direction_output = omap_gpio_output;
1152         bank->chip.set_config = omap_gpio_set_config;
1153         bank->chip.set = omap_gpio_set;
1154         bank->chip.set_multiple = omap_gpio_set_multiple;
1155         if (bank->is_mpuio) {
1156                 bank->chip.label = "mpuio";
1157                 if (bank->regs->wkup_en)
1158                         bank->chip.parent = &omap_mpuio_device.dev;
1159                 bank->chip.base = OMAP_MPUIO(0);
1160         } else {
1161                 label = devm_kasprintf(bank->chip.parent, GFP_KERNEL, "gpio-%d-%d",
1162                                        gpio, gpio + bank->width - 1);
1163                 if (!label)
1164                         return -ENOMEM;
1165                 bank->chip.label = label;
1166                 bank->chip.base = gpio;
1167         }
1168         bank->chip.ngpio = bank->width;
1169
1170 #ifdef CONFIG_ARCH_OMAP1
1171         /*
1172          * REVISIT: Once we have OMAP1 supporting SPARSE_IRQ, we can drop
1173          * irq_alloc_descs() since a base IRQ offset will no longer be needed.
1174          */
1175         irq_base = devm_irq_alloc_descs(bank->chip.parent,
1176                                         -1, 0, bank->width, 0);
1177         if (irq_base < 0) {
1178                 dev_err(bank->chip.parent, "Couldn't allocate IRQ numbers\n");
1179                 return -ENODEV;
1180         }
1181 #endif
1182
1183         /* MPUIO is a bit different, reading IRQ status clears it */
1184         if (bank->is_mpuio) {
1185                 irqc->irq_ack = dummy_irq_chip.irq_ack;
1186                 if (!bank->regs->wkup_en)
1187                         irqc->irq_set_wake = NULL;
1188         }
1189
1190         irq = &bank->chip.irq;
1191         irq->chip = irqc;
1192         irq->handler = handle_bad_irq;
1193         irq->default_type = IRQ_TYPE_NONE;
1194         irq->num_parents = 1;
1195         irq->parents = &bank->irq;
1196         irq->first = irq_base;
1197
1198         ret = gpiochip_add_data(&bank->chip, bank);
1199         if (ret) {
1200                 dev_err(bank->chip.parent,
1201                         "Could not register gpio chip %d\n", ret);
1202                 return ret;
1203         }
1204
1205         ret = devm_request_irq(bank->chip.parent, bank->irq,
1206                                omap_gpio_irq_handler,
1207                                0, dev_name(bank->chip.parent), bank);
1208         if (ret)
1209                 gpiochip_remove(&bank->chip);
1210
1211         if (!bank->is_mpuio)
1212                 gpio += bank->width;
1213
1214         return ret;
1215 }
1216
1217 static void omap_gpio_init_context(struct gpio_bank *p)
1218 {
1219         struct omap_gpio_reg_offs *regs = p->regs;
1220         void __iomem *base = p->base;
1221
1222         p->context.ctrl         = readl_relaxed(base + regs->ctrl);
1223         p->context.oe           = readl_relaxed(base + regs->direction);
1224         p->context.wake_en      = readl_relaxed(base + regs->wkup_en);
1225         p->context.leveldetect0 = readl_relaxed(base + regs->leveldetect0);
1226         p->context.leveldetect1 = readl_relaxed(base + regs->leveldetect1);
1227         p->context.risingdetect = readl_relaxed(base + regs->risingdetect);
1228         p->context.fallingdetect = readl_relaxed(base + regs->fallingdetect);
1229         p->context.irqenable1   = readl_relaxed(base + regs->irqenable);
1230         p->context.irqenable2   = readl_relaxed(base + regs->irqenable2);
1231
1232         if (regs->set_dataout && p->regs->clr_dataout)
1233                 p->context.dataout = readl_relaxed(base + regs->set_dataout);
1234         else
1235                 p->context.dataout = readl_relaxed(base + regs->dataout);
1236
1237         p->context_valid = true;
1238 }
1239
1240 static void omap_gpio_restore_context(struct gpio_bank *bank)
1241 {
1242         writel_relaxed(bank->context.wake_en,
1243                                 bank->base + bank->regs->wkup_en);
1244         writel_relaxed(bank->context.ctrl, bank->base + bank->regs->ctrl);
1245         writel_relaxed(bank->context.leveldetect0,
1246                                 bank->base + bank->regs->leveldetect0);
1247         writel_relaxed(bank->context.leveldetect1,
1248                                 bank->base + bank->regs->leveldetect1);
1249         writel_relaxed(bank->context.risingdetect,
1250                                 bank->base + bank->regs->risingdetect);
1251         writel_relaxed(bank->context.fallingdetect,
1252                                 bank->base + bank->regs->fallingdetect);
1253         if (bank->regs->set_dataout && bank->regs->clr_dataout)
1254                 writel_relaxed(bank->context.dataout,
1255                                 bank->base + bank->regs->set_dataout);
1256         else
1257                 writel_relaxed(bank->context.dataout,
1258                                 bank->base + bank->regs->dataout);
1259         writel_relaxed(bank->context.oe, bank->base + bank->regs->direction);
1260
1261         if (bank->dbck_enable_mask) {
1262                 writel_relaxed(bank->context.debounce, bank->base +
1263                                         bank->regs->debounce);
1264                 writel_relaxed(bank->context.debounce_en,
1265                                         bank->base + bank->regs->debounce_en);
1266         }
1267
1268         writel_relaxed(bank->context.irqenable1,
1269                                 bank->base + bank->regs->irqenable);
1270         writel_relaxed(bank->context.irqenable2,
1271                                 bank->base + bank->regs->irqenable2);
1272 }
1273
1274 static void omap_gpio_idle(struct gpio_bank *bank, bool may_lose_context)
1275 {
1276         struct device *dev = bank->chip.parent;
1277         void __iomem *base = bank->base;
1278         u32 nowake;
1279
1280         bank->saved_datain = readl_relaxed(base + bank->regs->datain);
1281
1282         if (!bank->enabled_non_wakeup_gpios)
1283                 goto update_gpio_context_count;
1284
1285         if (!may_lose_context)
1286                 goto update_gpio_context_count;
1287
1288         /*
1289          * If going to OFF, remove triggering for all wkup domain
1290          * non-wakeup GPIOs.  Otherwise spurious IRQs will be
1291          * generated.  See OMAP2420 Errata item 1.101.
1292          */
1293         if (!bank->loses_context && bank->enabled_non_wakeup_gpios) {
1294                 nowake = bank->enabled_non_wakeup_gpios;
1295                 omap_gpio_rmw(base, bank->regs->fallingdetect, nowake, ~nowake);
1296                 omap_gpio_rmw(base, bank->regs->risingdetect, nowake, ~nowake);
1297         }
1298
1299 update_gpio_context_count:
1300         if (bank->get_context_loss_count)
1301                 bank->context_loss_count =
1302                                 bank->get_context_loss_count(dev);
1303
1304         omap_gpio_dbck_disable(bank);
1305 }
1306
1307 static void omap_gpio_unidle(struct gpio_bank *bank)
1308 {
1309         struct device *dev = bank->chip.parent;
1310         u32 l = 0, gen, gen0, gen1;
1311         int c;
1312
1313         /*
1314          * On the first resume during the probe, the context has not
1315          * been initialised and so initialise it now. Also initialise
1316          * the context loss count.
1317          */
1318         if (bank->loses_context && !bank->context_valid) {
1319                 omap_gpio_init_context(bank);
1320
1321                 if (bank->get_context_loss_count)
1322                         bank->context_loss_count =
1323                                 bank->get_context_loss_count(dev);
1324         }
1325
1326         omap_gpio_dbck_enable(bank);
1327
1328         if (bank->loses_context) {
1329                 if (!bank->get_context_loss_count) {
1330                         omap_gpio_restore_context(bank);
1331                 } else {
1332                         c = bank->get_context_loss_count(dev);
1333                         if (c != bank->context_loss_count) {
1334                                 omap_gpio_restore_context(bank);
1335                         } else {
1336                                 return;
1337                         }
1338                 }
1339         } else {
1340                 /* Restore changes done for OMAP2420 errata 1.101 */
1341                 writel_relaxed(bank->context.fallingdetect,
1342                                bank->base + bank->regs->fallingdetect);
1343                 writel_relaxed(bank->context.risingdetect,
1344                                bank->base + bank->regs->risingdetect);
1345         }
1346
1347         l = readl_relaxed(bank->base + bank->regs->datain);
1348
1349         /*
1350          * Check if any of the non-wakeup interrupt GPIOs have changed
1351          * state.  If so, generate an IRQ by software.  This is
1352          * horribly racy, but it's the best we can do to work around
1353          * this silicon bug.
1354          */
1355         l ^= bank->saved_datain;
1356         l &= bank->enabled_non_wakeup_gpios;
1357
1358         /*
1359          * No need to generate IRQs for the rising edge for gpio IRQs
1360          * configured with falling edge only; and vice versa.
1361          */
1362         gen0 = l & bank->context.fallingdetect;
1363         gen0 &= bank->saved_datain;
1364
1365         gen1 = l & bank->context.risingdetect;
1366         gen1 &= ~(bank->saved_datain);
1367
1368         /* FIXME: Consider GPIO IRQs with level detections properly! */
1369         gen = l & (~(bank->context.fallingdetect) &
1370                                          ~(bank->context.risingdetect));
1371         /* Consider all GPIO IRQs needed to be updated */
1372         gen |= gen0 | gen1;
1373
1374         if (gen) {
1375                 u32 old0, old1;
1376
1377                 old0 = readl_relaxed(bank->base + bank->regs->leveldetect0);
1378                 old1 = readl_relaxed(bank->base + bank->regs->leveldetect1);
1379
1380                 if (!bank->regs->irqstatus_raw0) {
1381                         writel_relaxed(old0 | gen, bank->base +
1382                                                 bank->regs->leveldetect0);
1383                         writel_relaxed(old1 | gen, bank->base +
1384                                                 bank->regs->leveldetect1);
1385                 }
1386
1387                 if (bank->regs->irqstatus_raw0) {
1388                         writel_relaxed(old0 | l, bank->base +
1389                                                 bank->regs->leveldetect0);
1390                         writel_relaxed(old1 | l, bank->base +
1391                                                 bank->regs->leveldetect1);
1392                 }
1393                 writel_relaxed(old0, bank->base + bank->regs->leveldetect0);
1394                 writel_relaxed(old1, bank->base + bank->regs->leveldetect1);
1395         }
1396 }
1397
1398 static int gpio_omap_cpu_notifier(struct notifier_block *nb,
1399                                   unsigned long cmd, void *v)
1400 {
1401         struct gpio_bank *bank;
1402         unsigned long flags;
1403
1404         bank = container_of(nb, struct gpio_bank, nb);
1405
1406         raw_spin_lock_irqsave(&bank->lock, flags);
1407         switch (cmd) {
1408         case CPU_CLUSTER_PM_ENTER:
1409                 if (bank->is_suspended)
1410                         break;
1411                 omap_gpio_idle(bank, true);
1412                 break;
1413         case CPU_CLUSTER_PM_ENTER_FAILED:
1414         case CPU_CLUSTER_PM_EXIT:
1415                 if (bank->is_suspended)
1416                         break;
1417                 omap_gpio_unidle(bank);
1418                 break;
1419         }
1420         raw_spin_unlock_irqrestore(&bank->lock, flags);
1421
1422         return NOTIFY_OK;
1423 }
1424
1425 static struct omap_gpio_reg_offs omap2_gpio_regs = {
1426         .revision =             OMAP24XX_GPIO_REVISION,
1427         .direction =            OMAP24XX_GPIO_OE,
1428         .datain =               OMAP24XX_GPIO_DATAIN,
1429         .dataout =              OMAP24XX_GPIO_DATAOUT,
1430         .set_dataout =          OMAP24XX_GPIO_SETDATAOUT,
1431         .clr_dataout =          OMAP24XX_GPIO_CLEARDATAOUT,
1432         .irqstatus =            OMAP24XX_GPIO_IRQSTATUS1,
1433         .irqstatus2 =           OMAP24XX_GPIO_IRQSTATUS2,
1434         .irqenable =            OMAP24XX_GPIO_IRQENABLE1,
1435         .irqenable2 =           OMAP24XX_GPIO_IRQENABLE2,
1436         .set_irqenable =        OMAP24XX_GPIO_SETIRQENABLE1,
1437         .clr_irqenable =        OMAP24XX_GPIO_CLEARIRQENABLE1,
1438         .debounce =             OMAP24XX_GPIO_DEBOUNCE_VAL,
1439         .debounce_en =          OMAP24XX_GPIO_DEBOUNCE_EN,
1440         .ctrl =                 OMAP24XX_GPIO_CTRL,
1441         .wkup_en =              OMAP24XX_GPIO_WAKE_EN,
1442         .leveldetect0 =         OMAP24XX_GPIO_LEVELDETECT0,
1443         .leveldetect1 =         OMAP24XX_GPIO_LEVELDETECT1,
1444         .risingdetect =         OMAP24XX_GPIO_RISINGDETECT,
1445         .fallingdetect =        OMAP24XX_GPIO_FALLINGDETECT,
1446 };
1447
1448 static struct omap_gpio_reg_offs omap4_gpio_regs = {
1449         .revision =             OMAP4_GPIO_REVISION,
1450         .direction =            OMAP4_GPIO_OE,
1451         .datain =               OMAP4_GPIO_DATAIN,
1452         .dataout =              OMAP4_GPIO_DATAOUT,
1453         .set_dataout =          OMAP4_GPIO_SETDATAOUT,
1454         .clr_dataout =          OMAP4_GPIO_CLEARDATAOUT,
1455         .irqstatus =            OMAP4_GPIO_IRQSTATUS0,
1456         .irqstatus2 =           OMAP4_GPIO_IRQSTATUS1,
1457         .irqstatus_raw0 =       OMAP4_GPIO_IRQSTATUSRAW0,
1458         .irqstatus_raw1 =       OMAP4_GPIO_IRQSTATUSRAW1,
1459         .irqenable =            OMAP4_GPIO_IRQSTATUSSET0,
1460         .irqenable2 =           OMAP4_GPIO_IRQSTATUSSET1,
1461         .set_irqenable =        OMAP4_GPIO_IRQSTATUSSET0,
1462         .clr_irqenable =        OMAP4_GPIO_IRQSTATUSCLR0,
1463         .debounce =             OMAP4_GPIO_DEBOUNCINGTIME,
1464         .debounce_en =          OMAP4_GPIO_DEBOUNCENABLE,
1465         .ctrl =                 OMAP4_GPIO_CTRL,
1466         .wkup_en =              OMAP4_GPIO_IRQWAKEN0,
1467         .leveldetect0 =         OMAP4_GPIO_LEVELDETECT0,
1468         .leveldetect1 =         OMAP4_GPIO_LEVELDETECT1,
1469         .risingdetect =         OMAP4_GPIO_RISINGDETECT,
1470         .fallingdetect =        OMAP4_GPIO_FALLINGDETECT,
1471 };
1472
1473 static const struct omap_gpio_platform_data omap2_pdata = {
1474         .regs = &omap2_gpio_regs,
1475         .bank_width = 32,
1476         .dbck_flag = false,
1477 };
1478
1479 static const struct omap_gpio_platform_data omap3_pdata = {
1480         .regs = &omap2_gpio_regs,
1481         .bank_width = 32,
1482         .dbck_flag = true,
1483 };
1484
1485 static const struct omap_gpio_platform_data omap4_pdata = {
1486         .regs = &omap4_gpio_regs,
1487         .bank_width = 32,
1488         .dbck_flag = true,
1489 };
1490
1491 static const struct of_device_id omap_gpio_match[] = {
1492         {
1493                 .compatible = "ti,omap4-gpio",
1494                 .data = &omap4_pdata,
1495         },
1496         {
1497                 .compatible = "ti,omap3-gpio",
1498                 .data = &omap3_pdata,
1499         },
1500         {
1501                 .compatible = "ti,omap2-gpio",
1502                 .data = &omap2_pdata,
1503         },
1504         { },
1505 };
1506 MODULE_DEVICE_TABLE(of, omap_gpio_match);
1507
1508 static int omap_gpio_probe(struct platform_device *pdev)
1509 {
1510         struct device *dev = &pdev->dev;
1511         struct device_node *node = dev->of_node;
1512         const struct of_device_id *match;
1513         const struct omap_gpio_platform_data *pdata;
1514         struct gpio_bank *bank;
1515         struct irq_chip *irqc;
1516         int ret;
1517
1518         match = of_match_device(of_match_ptr(omap_gpio_match), dev);
1519
1520         pdata = match ? match->data : dev_get_platdata(dev);
1521         if (!pdata)
1522                 return -EINVAL;
1523
1524         bank = devm_kzalloc(dev, sizeof(*bank), GFP_KERNEL);
1525         if (!bank)
1526                 return -ENOMEM;
1527
1528         irqc = devm_kzalloc(dev, sizeof(*irqc), GFP_KERNEL);
1529         if (!irqc)
1530                 return -ENOMEM;
1531
1532         irqc->irq_startup = omap_gpio_irq_startup,
1533         irqc->irq_shutdown = omap_gpio_irq_shutdown,
1534         irqc->irq_ack = omap_gpio_ack_irq,
1535         irqc->irq_mask = omap_gpio_mask_irq,
1536         irqc->irq_unmask = omap_gpio_unmask_irq,
1537         irqc->irq_set_type = omap_gpio_irq_type,
1538         irqc->irq_set_wake = omap_gpio_wake_enable,
1539         irqc->irq_bus_lock = omap_gpio_irq_bus_lock,
1540         irqc->irq_bus_sync_unlock = gpio_irq_bus_sync_unlock,
1541         irqc->name = dev_name(&pdev->dev);
1542         irqc->flags = IRQCHIP_MASK_ON_SUSPEND;
1543         irqc->parent_device = dev;
1544
1545         bank->irq = platform_get_irq(pdev, 0);
1546         if (bank->irq <= 0) {
1547                 if (!bank->irq)
1548                         bank->irq = -ENXIO;
1549                 if (bank->irq != -EPROBE_DEFER)
1550                         dev_err(dev,
1551                                 "can't get irq resource ret=%d\n", bank->irq);
1552                 return bank->irq;
1553         }
1554
1555         bank->chip.parent = dev;
1556         bank->chip.owner = THIS_MODULE;
1557         bank->dbck_flag = pdata->dbck_flag;
1558         bank->stride = pdata->bank_stride;
1559         bank->width = pdata->bank_width;
1560         bank->is_mpuio = pdata->is_mpuio;
1561         bank->non_wakeup_gpios = pdata->non_wakeup_gpios;
1562         bank->regs = pdata->regs;
1563 #ifdef CONFIG_OF_GPIO
1564         bank->chip.of_node = of_node_get(node);
1565 #endif
1566
1567         if (node) {
1568                 if (!of_property_read_bool(node, "ti,gpio-always-on"))
1569                         bank->loses_context = true;
1570         } else {
1571                 bank->loses_context = pdata->loses_context;
1572
1573                 if (bank->loses_context)
1574                         bank->get_context_loss_count =
1575                                 pdata->get_context_loss_count;
1576         }
1577
1578         if (bank->regs->set_dataout && bank->regs->clr_dataout) {
1579                 bank->set_dataout = omap_set_gpio_dataout_reg;
1580                 bank->set_dataout_multiple = omap_set_gpio_dataout_reg_multiple;
1581         } else {
1582                 bank->set_dataout = omap_set_gpio_dataout_mask;
1583                 bank->set_dataout_multiple =
1584                                 omap_set_gpio_dataout_mask_multiple;
1585         }
1586
1587         raw_spin_lock_init(&bank->lock);
1588         raw_spin_lock_init(&bank->wa_lock);
1589
1590         /* Static mapping, never released */
1591         bank->base = devm_platform_ioremap_resource(pdev, 0);
1592         if (IS_ERR(bank->base)) {
1593                 return PTR_ERR(bank->base);
1594         }
1595
1596         if (bank->dbck_flag) {
1597                 bank->dbck = devm_clk_get(dev, "dbclk");
1598                 if (IS_ERR(bank->dbck)) {
1599                         dev_err(dev,
1600                                 "Could not get gpio dbck. Disable debounce\n");
1601                         bank->dbck_flag = false;
1602                 } else {
1603                         clk_prepare(bank->dbck);
1604                 }
1605         }
1606
1607         platform_set_drvdata(pdev, bank);
1608
1609         pm_runtime_enable(dev);
1610         pm_runtime_get_sync(dev);
1611
1612         if (bank->is_mpuio)
1613                 omap_mpuio_init(bank);
1614
1615         omap_gpio_mod_init(bank);
1616
1617         ret = omap_gpio_chip_init(bank, irqc);
1618         if (ret) {
1619                 pm_runtime_put_sync(dev);
1620                 pm_runtime_disable(dev);
1621                 if (bank->dbck_flag)
1622                         clk_unprepare(bank->dbck);
1623                 return ret;
1624         }
1625
1626         omap_gpio_show_rev(bank);
1627
1628         bank->nb.notifier_call = gpio_omap_cpu_notifier;
1629         cpu_pm_register_notifier(&bank->nb);
1630
1631         pm_runtime_put(dev);
1632
1633         return 0;
1634 }
1635
1636 static int omap_gpio_remove(struct platform_device *pdev)
1637 {
1638         struct gpio_bank *bank = platform_get_drvdata(pdev);
1639
1640         cpu_pm_unregister_notifier(&bank->nb);
1641         gpiochip_remove(&bank->chip);
1642         pm_runtime_disable(&pdev->dev);
1643         if (bank->dbck_flag)
1644                 clk_unprepare(bank->dbck);
1645
1646         return 0;
1647 }
1648
1649 static int __maybe_unused omap_gpio_runtime_suspend(struct device *dev)
1650 {
1651         struct gpio_bank *bank = dev_get_drvdata(dev);
1652         unsigned long flags;
1653
1654         raw_spin_lock_irqsave(&bank->lock, flags);
1655         omap_gpio_idle(bank, true);
1656         bank->is_suspended = true;
1657         raw_spin_unlock_irqrestore(&bank->lock, flags);
1658
1659         return 0;
1660 }
1661
1662 static int __maybe_unused omap_gpio_runtime_resume(struct device *dev)
1663 {
1664         struct gpio_bank *bank = dev_get_drvdata(dev);
1665         unsigned long flags;
1666
1667         raw_spin_lock_irqsave(&bank->lock, flags);
1668         omap_gpio_unidle(bank);
1669         bank->is_suspended = false;
1670         raw_spin_unlock_irqrestore(&bank->lock, flags);
1671
1672         return 0;
1673 }
1674
1675 static const struct dev_pm_ops gpio_pm_ops = {
1676         SET_RUNTIME_PM_OPS(omap_gpio_runtime_suspend, omap_gpio_runtime_resume,
1677                                                                         NULL)
1678 };
1679
1680 static struct platform_driver omap_gpio_driver = {
1681         .probe          = omap_gpio_probe,
1682         .remove         = omap_gpio_remove,
1683         .driver         = {
1684                 .name   = "omap_gpio",
1685                 .pm     = &gpio_pm_ops,
1686                 .of_match_table = omap_gpio_match,
1687         },
1688 };
1689
1690 /*
1691  * gpio driver register needs to be done before
1692  * machine_init functions access gpio APIs.
1693  * Hence omap_gpio_drv_reg() is a postcore_initcall.
1694  */
1695 static int __init omap_gpio_drv_reg(void)
1696 {
1697         return platform_driver_register(&omap_gpio_driver);
1698 }
1699 postcore_initcall(omap_gpio_drv_reg);
1700
1701 static void __exit omap_gpio_exit(void)
1702 {
1703         platform_driver_unregister(&omap_gpio_driver);
1704 }
1705 module_exit(omap_gpio_exit);
1706
1707 MODULE_DESCRIPTION("omap gpio driver");
1708 MODULE_ALIAS("platform:gpio-omap");
1709 MODULE_LICENSE("GPL v2");