2 * GPIO controller driver for Intel Lynxpoint PCH chipset>
3 * Copyright (c) 2012, Intel Corporation.
5 * Author: Mathias Nyman <mathias.nyman@linux.intel.com>
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms and conditions of the GNU General Public License,
9 * version 2, as published by the Free Software Foundation.
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * You should have received a copy of the GNU General Public License along with
17 * this program; if not, write to the Free Software Foundation, Inc.,
18 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
22 #include <linux/acpi.h>
23 #include <linux/bitops.h>
24 #include <linux/gpio/driver.h>
25 #include <linux/interrupt.h>
27 #include <linux/kernel.h>
28 #include <linux/module.h>
29 #include <linux/platform_device.h>
30 #include <linux/pm_runtime.h>
31 #include <linux/slab.h>
32 #include <linux/types.h>
34 /* LynxPoint chipset has support for 94 gpio pins */
36 #define LP_NUM_GPIO 94
38 /* Bitmapped register offsets */
39 #define LP_ACPI_OWNED 0x00 /* Bitmap, set by bios, 0: pin reserved for ACPI */
40 #define LP_GC 0x7C /* set APIC IRQ to IRQ14 or IRQ15 for all pins */
41 #define LP_INT_STAT 0x80
42 #define LP_INT_ENABLE 0x90
44 /* Each pin has two 32 bit config registers, starting at 0x100 */
45 #define LP_CONFIG1 0x100
46 #define LP_CONFIG2 0x104
48 /* LP_CONFIG1 reg bits */
49 #define OUT_LVL_BIT BIT(31)
50 #define IN_LVL_BIT BIT(30)
51 #define TRIG_SEL_BIT BIT(4) /* 0: Edge, 1: Level */
52 #define INT_INV_BIT BIT(3) /* Invert interrupt triggering */
53 #define DIR_BIT BIT(2) /* 0: Output, 1: Input */
54 #define USE_SEL_BIT BIT(0) /* 0: Native, 1: GPIO */
56 /* LP_CONFIG2 reg bits */
57 #define GPINDIS_BIT BIT(2) /* disable input sensing */
58 #define GPIWP_BIT (BIT(0) | BIT(1)) /* weak pull options */
61 struct gpio_chip chip;
62 struct platform_device *pdev;
64 unsigned long reg_base;
68 * Lynxpoint gpios are controlled through both bitmapped registers and
69 * per gpio specific registers. The bitmapped registers are in chunks of
70 * 3 x 32bit registers to cover all 94 gpios
72 * per gpio specific registers consist of two 32bit registers per gpio
73 * (LP_CONFIG1 and LP_CONFIG2), with 94 gpios there's a total of
74 * 188 config registers.
76 * A simplified view of the register layout look like this:
78 * LP_ACPI_OWNED[31:0] gpio ownerships for gpios 0-31 (bitmapped registers)
79 * LP_ACPI_OWNED[63:32] gpio ownerships for gpios 32-63
80 * LP_ACPI_OWNED[94:64] gpio ownerships for gpios 63-94
82 * LP_INT_ENABLE[31:0] ...
83 * LP_INT_ENABLE[63:31] ...
84 * LP_INT_ENABLE[94:64] ...
85 * LP0_CONFIG1 (gpio 0) config1 reg for gpio 0 (per gpio registers)
86 * LP0_CONFIG2 (gpio 0) config2 reg for gpio 0
87 * LP1_CONFIG1 (gpio 1) config1 reg for gpio 1
88 * LP1_CONFIG2 (gpio 1) config2 reg for gpio 1
89 * LP2_CONFIG1 (gpio 2) ...
90 * LP2_CONFIG2 (gpio 2) ...
92 * LP94_CONFIG1 (gpio 94) ...
93 * LP94_CONFIG2 (gpio 94) ...
96 static unsigned long lp_gpio_reg(struct gpio_chip *chip, unsigned offset,
99 struct lp_gpio *lg = gpiochip_get_data(chip);
102 if (reg == LP_CONFIG1 || reg == LP_CONFIG2)
103 /* per gpio specific config registers */
104 reg_offset = offset * 8;
106 /* bitmapped registers */
107 reg_offset = (offset / 32) * 4;
109 return lg->reg_base + reg + reg_offset;
112 static int lp_gpio_request(struct gpio_chip *chip, unsigned offset)
114 struct lp_gpio *lg = gpiochip_get_data(chip);
115 unsigned long reg = lp_gpio_reg(chip, offset, LP_CONFIG1);
116 unsigned long conf2 = lp_gpio_reg(chip, offset, LP_CONFIG2);
117 unsigned long acpi_use = lp_gpio_reg(chip, offset, LP_ACPI_OWNED);
119 pm_runtime_get(&lg->pdev->dev); /* should we put if failed */
121 /* Fail if BIOS reserved pin for ACPI use */
122 if (!(inl(acpi_use) & BIT(offset % 32))) {
123 dev_err(&lg->pdev->dev, "gpio %d reserved for ACPI\n", offset);
126 /* Fail if pin is in alternate function mode (not GPIO mode) */
127 if (!(inl(reg) & USE_SEL_BIT))
130 /* enable input sensing */
131 outl(inl(conf2) & ~GPINDIS_BIT, conf2);
137 static void lp_gpio_free(struct gpio_chip *chip, unsigned offset)
139 struct lp_gpio *lg = gpiochip_get_data(chip);
140 unsigned long conf2 = lp_gpio_reg(chip, offset, LP_CONFIG2);
142 /* disable input sensing */
143 outl(inl(conf2) | GPINDIS_BIT, conf2);
145 pm_runtime_put(&lg->pdev->dev);
148 static int lp_irq_type(struct irq_data *d, unsigned type)
150 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
151 struct lp_gpio *lg = gpiochip_get_data(gc);
152 u32 hwirq = irqd_to_hwirq(d);
155 unsigned long reg = lp_gpio_reg(&lg->chip, hwirq, LP_CONFIG1);
157 if (hwirq >= lg->chip.ngpio)
160 spin_lock_irqsave(&lg->lock, flags);
163 /* set both TRIG_SEL and INV bits to 0 for rising edge */
164 if (type & IRQ_TYPE_EDGE_RISING)
165 value &= ~(TRIG_SEL_BIT | INT_INV_BIT);
167 /* TRIG_SEL bit 0, INV bit 1 for falling edge */
168 if (type & IRQ_TYPE_EDGE_FALLING)
169 value = (value | INT_INV_BIT) & ~TRIG_SEL_BIT;
171 /* TRIG_SEL bit 1, INV bit 0 for level low */
172 if (type & IRQ_TYPE_LEVEL_LOW)
173 value = (value | TRIG_SEL_BIT) & ~INT_INV_BIT;
175 /* TRIG_SEL bit 1, INV bit 1 for level high */
176 if (type & IRQ_TYPE_LEVEL_HIGH)
177 value |= TRIG_SEL_BIT | INT_INV_BIT;
180 spin_unlock_irqrestore(&lg->lock, flags);
185 static int lp_gpio_get(struct gpio_chip *chip, unsigned offset)
187 unsigned long reg = lp_gpio_reg(chip, offset, LP_CONFIG1);
188 return !!(inl(reg) & IN_LVL_BIT);
191 static void lp_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
193 struct lp_gpio *lg = gpiochip_get_data(chip);
194 unsigned long reg = lp_gpio_reg(chip, offset, LP_CONFIG1);
197 spin_lock_irqsave(&lg->lock, flags);
200 outl(inl(reg) | OUT_LVL_BIT, reg);
202 outl(inl(reg) & ~OUT_LVL_BIT, reg);
204 spin_unlock_irqrestore(&lg->lock, flags);
207 static int lp_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
209 struct lp_gpio *lg = gpiochip_get_data(chip);
210 unsigned long reg = lp_gpio_reg(chip, offset, LP_CONFIG1);
213 spin_lock_irqsave(&lg->lock, flags);
214 outl(inl(reg) | DIR_BIT, reg);
215 spin_unlock_irqrestore(&lg->lock, flags);
220 static int lp_gpio_direction_output(struct gpio_chip *chip,
221 unsigned offset, int value)
223 struct lp_gpio *lg = gpiochip_get_data(chip);
224 unsigned long reg = lp_gpio_reg(chip, offset, LP_CONFIG1);
227 lp_gpio_set(chip, offset, value);
229 spin_lock_irqsave(&lg->lock, flags);
230 outl(inl(reg) & ~DIR_BIT, reg);
231 spin_unlock_irqrestore(&lg->lock, flags);
236 static void lp_gpio_irq_handler(struct irq_desc *desc)
238 struct irq_data *data = irq_desc_get_irq_data(desc);
239 struct gpio_chip *gc = irq_desc_get_handler_data(desc);
240 struct lp_gpio *lg = gpiochip_get_data(gc);
241 struct irq_chip *chip = irq_data_get_irq_chip(data);
242 unsigned long reg, ena, pending;
245 /* check from GPIO controller which pin triggered the interrupt */
246 for (base = 0; base < lg->chip.ngpio; base += 32) {
247 reg = lp_gpio_reg(&lg->chip, base, LP_INT_STAT);
248 ena = lp_gpio_reg(&lg->chip, base, LP_INT_ENABLE);
250 /* Only interrupts that are enabled */
251 pending = inl(reg) & inl(ena);
253 for_each_set_bit(pin, &pending, 32) {
256 /* Clear before handling so we don't lose an edge */
259 irq = irq_find_mapping(lg->chip.irq.domain, base + pin);
260 generic_handle_irq(irq);
266 static void lp_irq_unmask(struct irq_data *d)
270 static void lp_irq_mask(struct irq_data *d)
274 static void lp_irq_enable(struct irq_data *d)
276 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
277 struct lp_gpio *lg = gpiochip_get_data(gc);
278 u32 hwirq = irqd_to_hwirq(d);
279 unsigned long reg = lp_gpio_reg(&lg->chip, hwirq, LP_INT_ENABLE);
282 spin_lock_irqsave(&lg->lock, flags);
283 outl(inl(reg) | BIT(hwirq % 32), reg);
284 spin_unlock_irqrestore(&lg->lock, flags);
287 static void lp_irq_disable(struct irq_data *d)
289 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
290 struct lp_gpio *lg = gpiochip_get_data(gc);
291 u32 hwirq = irqd_to_hwirq(d);
292 unsigned long reg = lp_gpio_reg(&lg->chip, hwirq, LP_INT_ENABLE);
295 spin_lock_irqsave(&lg->lock, flags);
296 outl(inl(reg) & ~BIT(hwirq % 32), reg);
297 spin_unlock_irqrestore(&lg->lock, flags);
300 static struct irq_chip lp_irqchip = {
302 .irq_mask = lp_irq_mask,
303 .irq_unmask = lp_irq_unmask,
304 .irq_enable = lp_irq_enable,
305 .irq_disable = lp_irq_disable,
306 .irq_set_type = lp_irq_type,
307 .flags = IRQCHIP_SKIP_SET_WAKE,
310 static void lp_gpio_irq_init_hw(struct lp_gpio *lg)
315 for (base = 0; base < lg->chip.ngpio; base += 32) {
316 /* disable gpio pin interrupts */
317 reg = lp_gpio_reg(&lg->chip, base, LP_INT_ENABLE);
319 /* Clear interrupt status register */
320 reg = lp_gpio_reg(&lg->chip, base, LP_INT_STAT);
321 outl(0xffffffff, reg);
325 static int lp_gpio_probe(struct platform_device *pdev)
328 struct gpio_chip *gc;
329 struct resource *io_rc, *irq_rc;
330 struct device *dev = &pdev->dev;
331 unsigned long reg_len;
334 lg = devm_kzalloc(dev, sizeof(struct lp_gpio), GFP_KERNEL);
339 platform_set_drvdata(pdev, lg);
341 io_rc = platform_get_resource(pdev, IORESOURCE_IO, 0);
342 irq_rc = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
345 dev_err(dev, "missing IO resources\n");
349 lg->reg_base = io_rc->start;
350 reg_len = resource_size(io_rc);
352 if (!devm_request_region(dev, lg->reg_base, reg_len, "lp-gpio")) {
353 dev_err(dev, "failed requesting IO region 0x%x\n",
354 (unsigned int)lg->reg_base);
358 spin_lock_init(&lg->lock);
361 gc->label = dev_name(dev);
362 gc->owner = THIS_MODULE;
363 gc->request = lp_gpio_request;
364 gc->free = lp_gpio_free;
365 gc->direction_input = lp_gpio_direction_input;
366 gc->direction_output = lp_gpio_direction_output;
367 gc->get = lp_gpio_get;
368 gc->set = lp_gpio_set;
370 gc->ngpio = LP_NUM_GPIO;
371 gc->can_sleep = false;
374 ret = devm_gpiochip_add_data(dev, gc, lg);
376 dev_err(dev, "failed adding lp-gpio chip\n");
380 /* set up interrupts */
381 if (irq_rc && irq_rc->start) {
382 lp_gpio_irq_init_hw(lg);
383 ret = gpiochip_irqchip_add(gc, &lp_irqchip, 0,
384 handle_simple_irq, IRQ_TYPE_NONE);
386 dev_err(dev, "failed to add irqchip\n");
390 gpiochip_set_chained_irqchip(gc, &lp_irqchip,
391 (unsigned)irq_rc->start,
392 lp_gpio_irq_handler);
395 pm_runtime_enable(dev);
400 static int lp_gpio_runtime_suspend(struct device *dev)
405 static int lp_gpio_runtime_resume(struct device *dev)
410 static int lp_gpio_resume(struct device *dev)
412 struct platform_device *pdev = to_platform_device(dev);
413 struct lp_gpio *lg = platform_get_drvdata(pdev);
417 /* on some hardware suspend clears input sensing, re-enable it here */
418 for (i = 0; i < lg->chip.ngpio; i++) {
419 if (gpiochip_is_requested(&lg->chip, i) != NULL) {
420 reg = lp_gpio_reg(&lg->chip, i, LP_CONFIG2);
421 outl(inl(reg) & ~GPINDIS_BIT, reg);
427 static const struct dev_pm_ops lp_gpio_pm_ops = {
428 .runtime_suspend = lp_gpio_runtime_suspend,
429 .runtime_resume = lp_gpio_runtime_resume,
430 .resume = lp_gpio_resume,
433 static const struct acpi_device_id lynxpoint_gpio_acpi_match[] = {
438 MODULE_DEVICE_TABLE(acpi, lynxpoint_gpio_acpi_match);
440 static int lp_gpio_remove(struct platform_device *pdev)
442 pm_runtime_disable(&pdev->dev);
446 static struct platform_driver lp_gpio_driver = {
447 .probe = lp_gpio_probe,
448 .remove = lp_gpio_remove,
451 .pm = &lp_gpio_pm_ops,
452 .acpi_match_table = ACPI_PTR(lynxpoint_gpio_acpi_match),
456 static int __init lp_gpio_init(void)
458 return platform_driver_register(&lp_gpio_driver);
461 static void __exit lp_gpio_exit(void)
463 platform_driver_unregister(&lp_gpio_driver);
466 subsys_initcall(lp_gpio_init);
467 module_exit(lp_gpio_exit);
469 MODULE_AUTHOR("Mathias Nyman (Intel)");
470 MODULE_DESCRIPTION("GPIO interface for Intel Lynxpoint");
471 MODULE_LICENSE("GPL");
472 MODULE_ALIAS("platform:lp_gpio");