1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2018 Spreadtrum Communications Inc.
4 * Copyright (C) 2018 Linaro Ltd.
7 #include <linux/bitops.h>
8 #include <linux/gpio/driver.h>
9 #include <linux/interrupt.h>
10 #include <linux/kernel.h>
11 #include <linux/module.h>
12 #include <linux/notifier.h>
14 #include <linux/platform_device.h>
15 #include <linux/spinlock.h>
17 /* EIC registers definition */
18 #define SPRD_EIC_DBNC_DATA 0x0
19 #define SPRD_EIC_DBNC_DMSK 0x4
20 #define SPRD_EIC_DBNC_IEV 0x14
21 #define SPRD_EIC_DBNC_IE 0x18
22 #define SPRD_EIC_DBNC_RIS 0x1c
23 #define SPRD_EIC_DBNC_MIS 0x20
24 #define SPRD_EIC_DBNC_IC 0x24
25 #define SPRD_EIC_DBNC_TRIG 0x28
26 #define SPRD_EIC_DBNC_CTRL0 0x40
28 #define SPRD_EIC_LATCH_INTEN 0x0
29 #define SPRD_EIC_LATCH_INTRAW 0x4
30 #define SPRD_EIC_LATCH_INTMSK 0x8
31 #define SPRD_EIC_LATCH_INTCLR 0xc
32 #define SPRD_EIC_LATCH_INTPOL 0x10
33 #define SPRD_EIC_LATCH_INTMODE 0x14
35 #define SPRD_EIC_ASYNC_INTIE 0x0
36 #define SPRD_EIC_ASYNC_INTRAW 0x4
37 #define SPRD_EIC_ASYNC_INTMSK 0x8
38 #define SPRD_EIC_ASYNC_INTCLR 0xc
39 #define SPRD_EIC_ASYNC_INTMODE 0x10
40 #define SPRD_EIC_ASYNC_INTBOTH 0x14
41 #define SPRD_EIC_ASYNC_INTPOL 0x18
42 #define SPRD_EIC_ASYNC_DATA 0x1c
44 #define SPRD_EIC_SYNC_INTIE 0x0
45 #define SPRD_EIC_SYNC_INTRAW 0x4
46 #define SPRD_EIC_SYNC_INTMSK 0x8
47 #define SPRD_EIC_SYNC_INTCLR 0xc
48 #define SPRD_EIC_SYNC_INTMODE 0x10
49 #define SPRD_EIC_SYNC_INTBOTH 0x14
50 #define SPRD_EIC_SYNC_INTPOL 0x18
51 #define SPRD_EIC_SYNC_DATA 0x1c
54 * The digital-chip EIC controller can support maximum 3 banks, and each bank
57 #define SPRD_EIC_MAX_BANK 3
58 #define SPRD_EIC_PER_BANK_NR 8
59 #define SPRD_EIC_DATA_MASK GENMASK(7, 0)
60 #define SPRD_EIC_BIT(x) ((x) & (SPRD_EIC_PER_BANK_NR - 1))
61 #define SPRD_EIC_DBNC_MASK GENMASK(11, 0)
64 * The Spreadtrum EIC (external interrupt controller) can be used only in
65 * input mode to generate interrupts if detecting input signals.
67 * The Spreadtrum digital-chip EIC controller contains 4 sub-modules:
68 * debounce EIC, latch EIC, async EIC and sync EIC,
70 * The debounce EIC is used to capture the input signals' stable status
71 * (millisecond resolution) and a single-trigger mechanism is introduced
72 * into this sub-module to enhance the input event detection reliability.
73 * The debounce range is from 1ms to 4s with a step size of 1ms.
75 * The latch EIC is used to latch some special power down signals and
76 * generate interrupts, since the latch EIC does not depend on the APB clock
79 * The async EIC uses a 32k clock to capture the short signals (microsecond
80 * resolution) to generate interrupts by level or edge trigger.
82 * The EIC-sync is similar with GPIO's input function, which is a synchronized
83 * signal input register.
94 struct gpio_chip chip;
95 struct notifier_block irq_nb;
96 void __iomem *base[SPRD_EIC_MAX_BANK];
97 enum sprd_eic_type type;
102 static ATOMIC_NOTIFIER_HEAD(sprd_eic_irq_notifier);
104 static struct sprd_eic *to_sprd_eic(struct notifier_block *nb)
106 return container_of(nb, struct sprd_eic, irq_nb);
109 struct sprd_eic_variant_data {
110 enum sprd_eic_type type;
114 static const char *sprd_eic_label_name[SPRD_EIC_MAX] = {
115 "eic-debounce", "eic-latch", "eic-async",
119 static const struct sprd_eic_variant_data sc9860_eic_dbnc_data = {
120 .type = SPRD_EIC_DEBOUNCE,
124 static const struct sprd_eic_variant_data sc9860_eic_latch_data = {
125 .type = SPRD_EIC_LATCH,
129 static const struct sprd_eic_variant_data sc9860_eic_async_data = {
130 .type = SPRD_EIC_ASYNC,
134 static const struct sprd_eic_variant_data sc9860_eic_sync_data = {
135 .type = SPRD_EIC_SYNC,
139 static inline void __iomem *sprd_eic_offset_base(struct sprd_eic *sprd_eic,
142 if (bank >= SPRD_EIC_MAX_BANK)
145 return sprd_eic->base[bank];
148 static void sprd_eic_update(struct gpio_chip *chip, unsigned int offset,
149 u16 reg, unsigned int val)
151 struct sprd_eic *sprd_eic = gpiochip_get_data(chip);
153 sprd_eic_offset_base(sprd_eic, offset / SPRD_EIC_PER_BANK_NR);
157 spin_lock_irqsave(&sprd_eic->lock, flags);
158 tmp = readl_relaxed(base + reg);
161 tmp |= BIT(SPRD_EIC_BIT(offset));
163 tmp &= ~BIT(SPRD_EIC_BIT(offset));
165 writel_relaxed(tmp, base + reg);
166 spin_unlock_irqrestore(&sprd_eic->lock, flags);
169 static int sprd_eic_read(struct gpio_chip *chip, unsigned int offset, u16 reg)
171 struct sprd_eic *sprd_eic = gpiochip_get_data(chip);
173 sprd_eic_offset_base(sprd_eic, offset / SPRD_EIC_PER_BANK_NR);
175 return !!(readl_relaxed(base + reg) & BIT(SPRD_EIC_BIT(offset)));
178 static int sprd_eic_request(struct gpio_chip *chip, unsigned int offset)
180 sprd_eic_update(chip, offset, SPRD_EIC_DBNC_DMSK, 1);
184 static void sprd_eic_free(struct gpio_chip *chip, unsigned int offset)
186 sprd_eic_update(chip, offset, SPRD_EIC_DBNC_DMSK, 0);
189 static int sprd_eic_get(struct gpio_chip *chip, unsigned int offset)
191 struct sprd_eic *sprd_eic = gpiochip_get_data(chip);
193 switch (sprd_eic->type) {
194 case SPRD_EIC_DEBOUNCE:
195 return sprd_eic_read(chip, offset, SPRD_EIC_DBNC_DATA);
197 return sprd_eic_read(chip, offset, SPRD_EIC_ASYNC_DATA);
199 return sprd_eic_read(chip, offset, SPRD_EIC_SYNC_DATA);
205 static int sprd_eic_direction_input(struct gpio_chip *chip, unsigned int offset)
207 /* EICs are always input, nothing need to do here. */
211 static void sprd_eic_set(struct gpio_chip *chip, unsigned int offset, int value)
213 /* EICs are always input, nothing need to do here. */
216 static int sprd_eic_set_debounce(struct gpio_chip *chip, unsigned int offset,
217 unsigned int debounce)
219 struct sprd_eic *sprd_eic = gpiochip_get_data(chip);
221 sprd_eic_offset_base(sprd_eic, offset / SPRD_EIC_PER_BANK_NR);
222 u32 reg = SPRD_EIC_DBNC_CTRL0 + SPRD_EIC_BIT(offset) * 0x4;
223 u32 value = readl_relaxed(base + reg) & ~SPRD_EIC_DBNC_MASK;
225 value |= (debounce / 1000) & SPRD_EIC_DBNC_MASK;
226 writel_relaxed(value, base + reg);
231 static int sprd_eic_set_config(struct gpio_chip *chip, unsigned int offset,
232 unsigned long config)
234 unsigned long param = pinconf_to_config_param(config);
235 u32 arg = pinconf_to_config_argument(config);
237 if (param == PIN_CONFIG_INPUT_DEBOUNCE)
238 return sprd_eic_set_debounce(chip, offset, arg);
243 static void sprd_eic_irq_mask(struct irq_data *data)
245 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
246 struct sprd_eic *sprd_eic = gpiochip_get_data(chip);
247 u32 offset = irqd_to_hwirq(data);
249 switch (sprd_eic->type) {
250 case SPRD_EIC_DEBOUNCE:
251 sprd_eic_update(chip, offset, SPRD_EIC_DBNC_IE, 0);
252 sprd_eic_update(chip, offset, SPRD_EIC_DBNC_TRIG, 0);
255 sprd_eic_update(chip, offset, SPRD_EIC_LATCH_INTEN, 0);
258 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTIE, 0);
261 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTIE, 0);
264 dev_err(chip->parent, "Unsupported EIC type.\n");
267 gpiochip_disable_irq(chip, offset);
270 static void sprd_eic_irq_unmask(struct irq_data *data)
272 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
273 struct sprd_eic *sprd_eic = gpiochip_get_data(chip);
274 u32 offset = irqd_to_hwirq(data);
276 gpiochip_enable_irq(chip, offset);
278 switch (sprd_eic->type) {
279 case SPRD_EIC_DEBOUNCE:
280 sprd_eic_update(chip, offset, SPRD_EIC_DBNC_IE, 1);
281 sprd_eic_update(chip, offset, SPRD_EIC_DBNC_TRIG, 1);
284 sprd_eic_update(chip, offset, SPRD_EIC_LATCH_INTEN, 1);
287 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTIE, 1);
290 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTIE, 1);
293 dev_err(chip->parent, "Unsupported EIC type.\n");
297 static void sprd_eic_irq_ack(struct irq_data *data)
299 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
300 struct sprd_eic *sprd_eic = gpiochip_get_data(chip);
301 u32 offset = irqd_to_hwirq(data);
303 switch (sprd_eic->type) {
304 case SPRD_EIC_DEBOUNCE:
305 sprd_eic_update(chip, offset, SPRD_EIC_DBNC_IC, 1);
308 sprd_eic_update(chip, offset, SPRD_EIC_LATCH_INTCLR, 1);
311 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTCLR, 1);
314 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTCLR, 1);
317 dev_err(chip->parent, "Unsupported EIC type.\n");
321 static int sprd_eic_irq_set_type(struct irq_data *data, unsigned int flow_type)
323 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
324 struct sprd_eic *sprd_eic = gpiochip_get_data(chip);
325 u32 offset = irqd_to_hwirq(data);
328 switch (sprd_eic->type) {
329 case SPRD_EIC_DEBOUNCE:
331 case IRQ_TYPE_LEVEL_HIGH:
332 sprd_eic_update(chip, offset, SPRD_EIC_DBNC_IEV, 1);
333 sprd_eic_update(chip, offset, SPRD_EIC_DBNC_IC, 1);
335 case IRQ_TYPE_LEVEL_LOW:
336 sprd_eic_update(chip, offset, SPRD_EIC_DBNC_IEV, 0);
337 sprd_eic_update(chip, offset, SPRD_EIC_DBNC_IC, 1);
339 case IRQ_TYPE_EDGE_RISING:
340 case IRQ_TYPE_EDGE_FALLING:
341 case IRQ_TYPE_EDGE_BOTH:
342 state = sprd_eic_get(chip, offset);
344 sprd_eic_update(chip, offset,
345 SPRD_EIC_DBNC_IEV, 0);
346 sprd_eic_update(chip, offset,
347 SPRD_EIC_DBNC_IC, 1);
349 sprd_eic_update(chip, offset,
350 SPRD_EIC_DBNC_IEV, 1);
351 sprd_eic_update(chip, offset,
352 SPRD_EIC_DBNC_IC, 1);
359 irq_set_handler_locked(data, handle_level_irq);
363 case IRQ_TYPE_LEVEL_HIGH:
364 sprd_eic_update(chip, offset, SPRD_EIC_LATCH_INTPOL, 0);
365 sprd_eic_update(chip, offset, SPRD_EIC_LATCH_INTCLR, 1);
367 case IRQ_TYPE_LEVEL_LOW:
368 sprd_eic_update(chip, offset, SPRD_EIC_LATCH_INTPOL, 1);
369 sprd_eic_update(chip, offset, SPRD_EIC_LATCH_INTCLR, 1);
371 case IRQ_TYPE_EDGE_RISING:
372 case IRQ_TYPE_EDGE_FALLING:
373 case IRQ_TYPE_EDGE_BOTH:
374 state = sprd_eic_get(chip, offset);
376 sprd_eic_update(chip, offset,
377 SPRD_EIC_LATCH_INTPOL, 0);
378 sprd_eic_update(chip, offset,
379 SPRD_EIC_LATCH_INTCLR, 1);
381 sprd_eic_update(chip, offset,
382 SPRD_EIC_LATCH_INTPOL, 1);
383 sprd_eic_update(chip, offset,
384 SPRD_EIC_LATCH_INTCLR, 1);
391 irq_set_handler_locked(data, handle_level_irq);
395 case IRQ_TYPE_EDGE_RISING:
396 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTBOTH, 0);
397 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTMODE, 0);
398 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTPOL, 1);
399 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTCLR, 1);
400 irq_set_handler_locked(data, handle_edge_irq);
402 case IRQ_TYPE_EDGE_FALLING:
403 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTBOTH, 0);
404 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTMODE, 0);
405 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTPOL, 0);
406 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTCLR, 1);
407 irq_set_handler_locked(data, handle_edge_irq);
409 case IRQ_TYPE_EDGE_BOTH:
410 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTMODE, 0);
411 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTBOTH, 1);
412 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTCLR, 1);
413 irq_set_handler_locked(data, handle_edge_irq);
415 case IRQ_TYPE_LEVEL_HIGH:
416 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTBOTH, 0);
417 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTMODE, 1);
418 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTPOL, 1);
419 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTCLR, 1);
420 irq_set_handler_locked(data, handle_level_irq);
422 case IRQ_TYPE_LEVEL_LOW:
423 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTBOTH, 0);
424 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTMODE, 1);
425 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTPOL, 0);
426 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTCLR, 1);
427 irq_set_handler_locked(data, handle_level_irq);
435 case IRQ_TYPE_EDGE_RISING:
436 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTBOTH, 0);
437 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTMODE, 0);
438 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTPOL, 1);
439 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTCLR, 1);
440 irq_set_handler_locked(data, handle_edge_irq);
442 case IRQ_TYPE_EDGE_FALLING:
443 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTBOTH, 0);
444 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTMODE, 0);
445 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTPOL, 0);
446 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTCLR, 1);
447 irq_set_handler_locked(data, handle_edge_irq);
449 case IRQ_TYPE_EDGE_BOTH:
450 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTMODE, 0);
451 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTBOTH, 1);
452 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTCLR, 1);
453 irq_set_handler_locked(data, handle_edge_irq);
455 case IRQ_TYPE_LEVEL_HIGH:
456 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTBOTH, 0);
457 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTMODE, 1);
458 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTPOL, 1);
459 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTCLR, 1);
460 irq_set_handler_locked(data, handle_level_irq);
462 case IRQ_TYPE_LEVEL_LOW:
463 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTBOTH, 0);
464 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTMODE, 1);
465 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTPOL, 0);
466 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTCLR, 1);
467 irq_set_handler_locked(data, handle_level_irq);
474 dev_err(chip->parent, "Unsupported EIC type.\n");
481 static void sprd_eic_toggle_trigger(struct gpio_chip *chip, unsigned int irq,
484 struct sprd_eic *sprd_eic = gpiochip_get_data(chip);
485 struct irq_data *data = irq_get_irq_data(irq);
486 u32 trigger = irqd_get_trigger_type(data);
487 int state, post_state;
490 * The debounce EIC and latch EIC can only support level trigger, so we
491 * can toggle the level trigger to emulate the edge trigger.
493 if ((sprd_eic->type != SPRD_EIC_DEBOUNCE &&
494 sprd_eic->type != SPRD_EIC_LATCH) ||
495 !(trigger & IRQ_TYPE_EDGE_BOTH))
498 sprd_eic_irq_mask(data);
499 state = sprd_eic_get(chip, offset);
502 switch (sprd_eic->type) {
503 case SPRD_EIC_DEBOUNCE:
505 sprd_eic_update(chip, offset, SPRD_EIC_DBNC_IEV, 0);
507 sprd_eic_update(chip, offset, SPRD_EIC_DBNC_IEV, 1);
511 sprd_eic_update(chip, offset, SPRD_EIC_LATCH_INTPOL, 0);
513 sprd_eic_update(chip, offset, SPRD_EIC_LATCH_INTPOL, 1);
516 sprd_eic_irq_unmask(data);
520 post_state = sprd_eic_get(chip, offset);
521 if (state != post_state) {
522 dev_warn(chip->parent, "EIC level was changed.\n");
527 sprd_eic_irq_unmask(data);
530 static void sprd_eic_handle_one_type(struct gpio_chip *chip)
532 struct sprd_eic *sprd_eic = gpiochip_get_data(chip);
535 for (bank = 0; bank * SPRD_EIC_PER_BANK_NR < chip->ngpio; bank++) {
536 void __iomem *base = sprd_eic_offset_base(sprd_eic, bank);
539 switch (sprd_eic->type) {
540 case SPRD_EIC_DEBOUNCE:
541 reg = readl_relaxed(base + SPRD_EIC_DBNC_MIS) &
545 reg = readl_relaxed(base + SPRD_EIC_LATCH_INTMSK) &
549 reg = readl_relaxed(base + SPRD_EIC_ASYNC_INTMSK) &
553 reg = readl_relaxed(base + SPRD_EIC_SYNC_INTMSK) &
557 dev_err(chip->parent, "Unsupported EIC type.\n");
561 for_each_set_bit(n, ®, SPRD_EIC_PER_BANK_NR) {
562 u32 offset = bank * SPRD_EIC_PER_BANK_NR + n;
564 girq = irq_find_mapping(chip->irq.domain, offset);
566 generic_handle_irq(girq);
567 sprd_eic_toggle_trigger(chip, girq, offset);
572 static void sprd_eic_irq_handler(struct irq_desc *desc)
574 struct irq_chip *ic = irq_desc_get_chip(desc);
576 chained_irq_enter(ic, desc);
579 * Since the digital-chip EIC 4 sub-modules (debounce, latch, async
580 * and sync) share one same interrupt line, we should notify all of
581 * them to let them check if there are EIC interrupts were triggered.
583 atomic_notifier_call_chain(&sprd_eic_irq_notifier, 0, NULL);
585 chained_irq_exit(ic, desc);
588 static int sprd_eic_irq_notify(struct notifier_block *nb, unsigned long action,
591 struct sprd_eic *sprd_eic = to_sprd_eic(nb);
593 sprd_eic_handle_one_type(&sprd_eic->chip);
598 static const struct irq_chip sprd_eic_irq = {
600 .irq_ack = sprd_eic_irq_ack,
601 .irq_mask = sprd_eic_irq_mask,
602 .irq_unmask = sprd_eic_irq_unmask,
603 .irq_set_type = sprd_eic_irq_set_type,
604 .flags = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_IMMUTABLE,
605 GPIOCHIP_IRQ_RESOURCE_HELPERS,
608 static void sprd_eic_unregister_notifier(void *data)
610 struct notifier_block *nb = data;
612 atomic_notifier_chain_unregister(&sprd_eic_irq_notifier, nb);
615 static int sprd_eic_probe(struct platform_device *pdev)
617 const struct sprd_eic_variant_data *pdata;
618 struct device *dev = &pdev->dev;
619 struct gpio_irq_chip *irq;
620 struct sprd_eic *sprd_eic;
621 struct resource *res;
624 pdata = of_device_get_match_data(dev);
626 dev_err(dev, "No matching driver data found.\n");
630 sprd_eic = devm_kzalloc(dev, sizeof(*sprd_eic), GFP_KERNEL);
634 spin_lock_init(&sprd_eic->lock);
635 sprd_eic->type = pdata->type;
637 sprd_eic->irq = platform_get_irq(pdev, 0);
638 if (sprd_eic->irq < 0)
639 return sprd_eic->irq;
641 for (i = 0; i < SPRD_EIC_MAX_BANK; i++) {
643 * We can have maximum 3 banks EICs, and each EIC has
644 * its own base address. But some platform maybe only
645 * have one bank EIC, thus base[1] and base[2] can be
648 res = platform_get_resource(pdev, IORESOURCE_MEM, i);
652 sprd_eic->base[i] = devm_ioremap_resource(dev, res);
653 if (IS_ERR(sprd_eic->base[i]))
654 return PTR_ERR(sprd_eic->base[i]);
657 sprd_eic->chip.label = sprd_eic_label_name[sprd_eic->type];
658 sprd_eic->chip.ngpio = pdata->num_eics;
659 sprd_eic->chip.base = -1;
660 sprd_eic->chip.parent = dev;
661 sprd_eic->chip.direction_input = sprd_eic_direction_input;
662 switch (sprd_eic->type) {
663 case SPRD_EIC_DEBOUNCE:
664 sprd_eic->chip.request = sprd_eic_request;
665 sprd_eic->chip.free = sprd_eic_free;
666 sprd_eic->chip.set_config = sprd_eic_set_config;
667 sprd_eic->chip.set = sprd_eic_set;
671 sprd_eic->chip.get = sprd_eic_get;
678 irq = &sprd_eic->chip.irq;
679 gpio_irq_chip_set_chip(irq, &sprd_eic_irq);
680 irq->handler = handle_bad_irq;
681 irq->default_type = IRQ_TYPE_NONE;
682 irq->parent_handler = sprd_eic_irq_handler;
683 irq->parent_handler_data = sprd_eic;
684 irq->num_parents = 1;
685 irq->parents = &sprd_eic->irq;
687 ret = devm_gpiochip_add_data(dev, &sprd_eic->chip, sprd_eic);
689 dev_err(dev, "Could not register gpiochip %d.\n", ret);
693 sprd_eic->irq_nb.notifier_call = sprd_eic_irq_notify;
694 ret = atomic_notifier_chain_register(&sprd_eic_irq_notifier,
697 return dev_err_probe(dev, ret,
698 "Failed to register with the interrupt notifier");
700 return devm_add_action_or_reset(dev, sprd_eic_unregister_notifier,
704 static const struct of_device_id sprd_eic_of_match[] = {
706 .compatible = "sprd,sc9860-eic-debounce",
707 .data = &sc9860_eic_dbnc_data,
710 .compatible = "sprd,sc9860-eic-latch",
711 .data = &sc9860_eic_latch_data,
714 .compatible = "sprd,sc9860-eic-async",
715 .data = &sc9860_eic_async_data,
718 .compatible = "sprd,sc9860-eic-sync",
719 .data = &sc9860_eic_sync_data,
725 MODULE_DEVICE_TABLE(of, sprd_eic_of_match);
727 static struct platform_driver sprd_eic_driver = {
728 .probe = sprd_eic_probe,
731 .of_match_table = sprd_eic_of_match,
735 module_platform_driver(sprd_eic_driver);
737 MODULE_DESCRIPTION("Spreadtrum EIC driver");
738 MODULE_LICENSE("GPL v2");