1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2011 Jamie Iles
5 * All enquiries to support@picochip.com
7 #include <linux/acpi.h>
10 #include <linux/gpio/driver.h>
11 #include <linux/init.h>
12 #include <linux/interrupt.h>
14 #include <linux/ioport.h>
15 #include <linux/irq.h>
16 #include <linux/irqdomain.h>
17 #include <linux/module.h>
19 #include <linux/of_address.h>
20 #include <linux/of_device.h>
21 #include <linux/of_irq.h>
22 #include <linux/platform_device.h>
23 #include <linux/property.h>
24 #include <linux/reset.h>
25 #include <linux/spinlock.h>
26 #include <linux/platform_data/gpio-dwapb.h>
27 #include <linux/slab.h>
31 #define GPIO_SWPORTA_DR 0x00
32 #define GPIO_SWPORTA_DDR 0x04
33 #define GPIO_SWPORTB_DR 0x0c
34 #define GPIO_SWPORTB_DDR 0x10
35 #define GPIO_SWPORTC_DR 0x18
36 #define GPIO_SWPORTC_DDR 0x1c
37 #define GPIO_SWPORTD_DR 0x24
38 #define GPIO_SWPORTD_DDR 0x28
39 #define GPIO_INTEN 0x30
40 #define GPIO_INTMASK 0x34
41 #define GPIO_INTTYPE_LEVEL 0x38
42 #define GPIO_INT_POLARITY 0x3c
43 #define GPIO_INTSTATUS 0x40
44 #define GPIO_PORTA_DEBOUNCE 0x48
45 #define GPIO_PORTA_EOI 0x4c
46 #define GPIO_EXT_PORTA 0x50
47 #define GPIO_EXT_PORTB 0x54
48 #define GPIO_EXT_PORTC 0x58
49 #define GPIO_EXT_PORTD 0x5c
51 #define DWAPB_MAX_PORTS 4
52 #define GPIO_EXT_PORT_STRIDE 0x04 /* register stride 32 bits */
53 #define GPIO_SWPORT_DR_STRIDE 0x0c /* register stride 3*32 bits */
54 #define GPIO_SWPORT_DDR_STRIDE 0x0c /* register stride 3*32 bits */
56 #define GPIO_REG_OFFSET_V2 1
58 #define GPIO_INTMASK_V2 0x44
59 #define GPIO_INTTYPE_LEVEL_V2 0x34
60 #define GPIO_INT_POLARITY_V2 0x38
61 #define GPIO_INTSTATUS_V2 0x3c
62 #define GPIO_PORTA_EOI_V2 0x40
66 #ifdef CONFIG_PM_SLEEP
67 /* Store GPIO context across system-wide suspend/resume transitions */
68 struct dwapb_context {
81 struct dwapb_gpio_port {
84 struct dwapb_gpio *gpio;
85 #ifdef CONFIG_PM_SLEEP
86 struct dwapb_context *ctx;
94 struct dwapb_gpio_port *ports;
95 unsigned int nr_ports;
96 struct irq_domain *domain;
98 struct reset_control *rst;
102 static inline u32 gpio_reg_v2_convert(unsigned int offset)
106 return GPIO_INTMASK_V2;
107 case GPIO_INTTYPE_LEVEL:
108 return GPIO_INTTYPE_LEVEL_V2;
109 case GPIO_INT_POLARITY:
110 return GPIO_INT_POLARITY_V2;
112 return GPIO_INTSTATUS_V2;
114 return GPIO_PORTA_EOI_V2;
120 static inline u32 gpio_reg_convert(struct dwapb_gpio *gpio, unsigned int offset)
122 if (gpio->flags & GPIO_REG_OFFSET_V2)
123 return gpio_reg_v2_convert(offset);
128 static inline u32 dwapb_read(struct dwapb_gpio *gpio, unsigned int offset)
130 struct gpio_chip *gc = &gpio->ports[0].gc;
131 void __iomem *reg_base = gpio->regs;
133 return gc->read_reg(reg_base + gpio_reg_convert(gpio, offset));
136 static inline void dwapb_write(struct dwapb_gpio *gpio, unsigned int offset,
139 struct gpio_chip *gc = &gpio->ports[0].gc;
140 void __iomem *reg_base = gpio->regs;
142 gc->write_reg(reg_base + gpio_reg_convert(gpio, offset), val);
145 static int dwapb_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
147 struct dwapb_gpio_port *port = gpiochip_get_data(gc);
148 struct dwapb_gpio *gpio = port->gpio;
150 return irq_find_mapping(gpio->domain, offset);
153 static struct dwapb_gpio_port *dwapb_offs_to_port(struct dwapb_gpio *gpio, unsigned int offs)
155 struct dwapb_gpio_port *port;
158 for (i = 0; i < gpio->nr_ports; i++) {
159 port = &gpio->ports[i];
160 if (port->idx == offs / 32)
167 static void dwapb_toggle_trigger(struct dwapb_gpio *gpio, unsigned int offs)
169 struct dwapb_gpio_port *port = dwapb_offs_to_port(gpio, offs);
170 struct gpio_chip *gc;
178 pol = dwapb_read(gpio, GPIO_INT_POLARITY);
179 /* Just read the current value right out of the data register */
180 val = gc->get(gc, offs % 32);
186 dwapb_write(gpio, GPIO_INT_POLARITY, pol);
189 static u32 dwapb_do_irq(struct dwapb_gpio *gpio)
191 u32 irq_status = dwapb_read(gpio, GPIO_INTSTATUS);
192 u32 ret = irq_status;
195 int hwirq = fls(irq_status) - 1;
196 int gpio_irq = irq_find_mapping(gpio->domain, hwirq);
198 generic_handle_irq(gpio_irq);
199 irq_status &= ~BIT(hwirq);
201 if ((irq_get_trigger_type(gpio_irq) & IRQ_TYPE_SENSE_MASK)
202 == IRQ_TYPE_EDGE_BOTH)
203 dwapb_toggle_trigger(gpio, hwirq);
209 static void dwapb_irq_handler(struct irq_desc *desc)
211 struct dwapb_gpio *gpio = irq_desc_get_handler_data(desc);
212 struct irq_chip *chip = irq_desc_get_chip(desc);
217 chip->irq_eoi(irq_desc_get_irq_data(desc));
220 static void dwapb_irq_enable(struct irq_data *d)
222 struct irq_chip_generic *igc = irq_data_get_irq_chip_data(d);
223 struct dwapb_gpio *gpio = igc->private;
224 struct gpio_chip *gc = &gpio->ports[0].gc;
228 spin_lock_irqsave(&gc->bgpio_lock, flags);
229 val = dwapb_read(gpio, GPIO_INTEN);
230 val |= BIT(d->hwirq);
231 dwapb_write(gpio, GPIO_INTEN, val);
232 spin_unlock_irqrestore(&gc->bgpio_lock, flags);
235 static void dwapb_irq_disable(struct irq_data *d)
237 struct irq_chip_generic *igc = irq_data_get_irq_chip_data(d);
238 struct dwapb_gpio *gpio = igc->private;
239 struct gpio_chip *gc = &gpio->ports[0].gc;
243 spin_lock_irqsave(&gc->bgpio_lock, flags);
244 val = dwapb_read(gpio, GPIO_INTEN);
245 val &= ~BIT(d->hwirq);
246 dwapb_write(gpio, GPIO_INTEN, val);
247 spin_unlock_irqrestore(&gc->bgpio_lock, flags);
250 static int dwapb_irq_reqres(struct irq_data *d)
252 struct irq_chip_generic *igc = irq_data_get_irq_chip_data(d);
253 struct dwapb_gpio *gpio = igc->private;
254 struct gpio_chip *gc = &gpio->ports[0].gc;
257 ret = gpiochip_lock_as_irq(gc, irqd_to_hwirq(d));
259 dev_err(gpio->dev, "unable to lock HW IRQ %lu for IRQ\n",
266 static void dwapb_irq_relres(struct irq_data *d)
268 struct irq_chip_generic *igc = irq_data_get_irq_chip_data(d);
269 struct dwapb_gpio *gpio = igc->private;
270 struct gpio_chip *gc = &gpio->ports[0].gc;
272 gpiochip_unlock_as_irq(gc, irqd_to_hwirq(d));
275 static int dwapb_irq_set_type(struct irq_data *d, u32 type)
277 struct irq_chip_generic *igc = irq_data_get_irq_chip_data(d);
278 struct dwapb_gpio *gpio = igc->private;
279 struct gpio_chip *gc = &gpio->ports[0].gc;
281 unsigned long level, polarity, flags;
283 if (type & ~(IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING |
284 IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW))
287 spin_lock_irqsave(&gc->bgpio_lock, flags);
288 level = dwapb_read(gpio, GPIO_INTTYPE_LEVEL);
289 polarity = dwapb_read(gpio, GPIO_INT_POLARITY);
292 case IRQ_TYPE_EDGE_BOTH:
294 dwapb_toggle_trigger(gpio, bit);
296 case IRQ_TYPE_EDGE_RISING:
298 polarity |= BIT(bit);
300 case IRQ_TYPE_EDGE_FALLING:
302 polarity &= ~BIT(bit);
304 case IRQ_TYPE_LEVEL_HIGH:
306 polarity |= BIT(bit);
308 case IRQ_TYPE_LEVEL_LOW:
310 polarity &= ~BIT(bit);
314 irq_setup_alt_chip(d, type);
316 dwapb_write(gpio, GPIO_INTTYPE_LEVEL, level);
317 if (type != IRQ_TYPE_EDGE_BOTH)
318 dwapb_write(gpio, GPIO_INT_POLARITY, polarity);
319 spin_unlock_irqrestore(&gc->bgpio_lock, flags);
324 #ifdef CONFIG_PM_SLEEP
325 static int dwapb_irq_set_wake(struct irq_data *d, unsigned int enable)
327 struct irq_chip_generic *igc = irq_data_get_irq_chip_data(d);
328 struct dwapb_gpio *gpio = igc->private;
329 struct dwapb_context *ctx = gpio->ports[0].ctx;
332 ctx->wake_en |= BIT(d->hwirq);
334 ctx->wake_en &= ~BIT(d->hwirq);
340 static int dwapb_gpio_set_debounce(struct gpio_chip *gc,
341 unsigned offset, unsigned debounce)
343 struct dwapb_gpio_port *port = gpiochip_get_data(gc);
344 struct dwapb_gpio *gpio = port->gpio;
345 unsigned long flags, val_deb;
346 unsigned long mask = BIT(offset);
348 spin_lock_irqsave(&gc->bgpio_lock, flags);
350 val_deb = dwapb_read(gpio, GPIO_PORTA_DEBOUNCE);
352 dwapb_write(gpio, GPIO_PORTA_DEBOUNCE, val_deb | mask);
354 dwapb_write(gpio, GPIO_PORTA_DEBOUNCE, val_deb & ~mask);
356 spin_unlock_irqrestore(&gc->bgpio_lock, flags);
361 static int dwapb_gpio_set_config(struct gpio_chip *gc, unsigned offset,
362 unsigned long config)
366 if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE)
369 debounce = pinconf_to_config_argument(config);
370 return dwapb_gpio_set_debounce(gc, offset, debounce);
373 static irqreturn_t dwapb_irq_handler_mfd(int irq, void *dev_id)
376 struct dwapb_gpio *gpio = dev_id;
378 worked = dwapb_do_irq(gpio);
380 return worked ? IRQ_HANDLED : IRQ_NONE;
383 static void dwapb_configure_irqs(struct dwapb_gpio *gpio,
384 struct dwapb_gpio_port *port,
385 struct dwapb_port_property *pp)
387 struct gpio_chip *gc = &port->gc;
388 struct fwnode_handle *fwnode = pp->fwnode;
389 struct irq_chip_generic *irq_gc = NULL;
390 unsigned int hwirq, ngpio = gc->ngpio;
391 struct irq_chip_type *ct;
394 gpio->domain = irq_domain_create_linear(fwnode, ngpio,
395 &irq_generic_chip_ops, gpio);
399 err = irq_alloc_domain_generic_chips(gpio->domain, ngpio, 2,
400 "gpio-dwapb", handle_level_irq,
402 IRQ_GC_INIT_NESTED_LOCK);
404 dev_info(gpio->dev, "irq_alloc_domain_generic_chips failed\n");
405 irq_domain_remove(gpio->domain);
410 irq_gc = irq_get_domain_generic_chip(gpio->domain, 0);
412 irq_domain_remove(gpio->domain);
417 irq_gc->reg_base = gpio->regs;
418 irq_gc->private = gpio;
420 for (i = 0; i < 2; i++) {
421 ct = &irq_gc->chip_types[i];
422 ct->chip.irq_ack = irq_gc_ack_set_bit;
423 ct->chip.irq_mask = irq_gc_mask_set_bit;
424 ct->chip.irq_unmask = irq_gc_mask_clr_bit;
425 ct->chip.irq_set_type = dwapb_irq_set_type;
426 ct->chip.irq_enable = dwapb_irq_enable;
427 ct->chip.irq_disable = dwapb_irq_disable;
428 ct->chip.irq_request_resources = dwapb_irq_reqres;
429 ct->chip.irq_release_resources = dwapb_irq_relres;
430 #ifdef CONFIG_PM_SLEEP
431 ct->chip.irq_set_wake = dwapb_irq_set_wake;
433 ct->regs.ack = gpio_reg_convert(gpio, GPIO_PORTA_EOI);
434 ct->regs.mask = gpio_reg_convert(gpio, GPIO_INTMASK);
435 ct->type = IRQ_TYPE_LEVEL_MASK;
438 irq_gc->chip_types[0].type = IRQ_TYPE_LEVEL_MASK;
439 irq_gc->chip_types[1].type = IRQ_TYPE_EDGE_BOTH;
440 irq_gc->chip_types[1].handler = handle_edge_irq;
442 if (!pp->irq_shared) {
445 for (i = 0; i < pp->ngpio; i++) {
447 irq_set_chained_handler_and_data(pp->irq[i],
448 dwapb_irq_handler, gpio);
452 * Request a shared IRQ since where MFD would have devices
453 * using the same irq pin
455 err = devm_request_irq(gpio->dev, pp->irq[0],
456 dwapb_irq_handler_mfd,
457 IRQF_SHARED, "gpio-dwapb-mfd", gpio);
459 dev_err(gpio->dev, "error requesting IRQ\n");
460 irq_domain_remove(gpio->domain);
466 for (hwirq = 0 ; hwirq < ngpio ; hwirq++)
467 irq_create_mapping(gpio->domain, hwirq);
469 port->gc.to_irq = dwapb_gpio_to_irq;
472 static void dwapb_irq_teardown(struct dwapb_gpio *gpio)
474 struct dwapb_gpio_port *port = &gpio->ports[0];
475 struct gpio_chip *gc = &port->gc;
476 unsigned int ngpio = gc->ngpio;
477 irq_hw_number_t hwirq;
482 for (hwirq = 0 ; hwirq < ngpio ; hwirq++)
483 irq_dispose_mapping(irq_find_mapping(gpio->domain, hwirq));
485 irq_domain_remove(gpio->domain);
489 static int dwapb_gpio_add_port(struct dwapb_gpio *gpio,
490 struct dwapb_port_property *pp,
493 struct dwapb_gpio_port *port;
494 void __iomem *dat, *set, *dirout;
497 port = &gpio->ports[offs];
501 #ifdef CONFIG_PM_SLEEP
502 port->ctx = devm_kzalloc(gpio->dev, sizeof(*port->ctx), GFP_KERNEL);
507 dat = gpio->regs + GPIO_EXT_PORTA + (pp->idx * GPIO_EXT_PORT_STRIDE);
508 set = gpio->regs + GPIO_SWPORTA_DR + (pp->idx * GPIO_SWPORT_DR_STRIDE);
509 dirout = gpio->regs + GPIO_SWPORTA_DDR +
510 (pp->idx * GPIO_SWPORT_DDR_STRIDE);
512 /* This registers 32 GPIO lines per port */
513 err = bgpio_init(&port->gc, gpio->dev, 4, dat, set, NULL, dirout,
516 dev_err(gpio->dev, "failed to init gpio chip for port%d\n",
521 #ifdef CONFIG_OF_GPIO
522 port->gc.of_node = to_of_node(pp->fwnode);
524 port->gc.ngpio = pp->ngpio;
525 port->gc.base = pp->gpio_base;
527 /* Only port A support debounce */
529 port->gc.set_config = dwapb_gpio_set_config;
532 dwapb_configure_irqs(gpio, port, pp);
534 err = gpiochip_add_data(&port->gc, port);
536 dev_err(gpio->dev, "failed to register gpiochip for port%d\n",
539 port->is_registered = true;
541 /* Add GPIO-signaled ACPI event support */
543 acpi_gpiochip_request_interrupts(&port->gc);
548 static void dwapb_gpio_unregister(struct dwapb_gpio *gpio)
552 for (m = 0; m < gpio->nr_ports; ++m)
553 if (gpio->ports[m].is_registered)
554 gpiochip_remove(&gpio->ports[m].gc);
557 static struct dwapb_platform_data *
558 dwapb_gpio_get_pdata(struct device *dev)
560 struct fwnode_handle *fwnode;
561 struct dwapb_platform_data *pdata;
562 struct dwapb_port_property *pp;
566 nports = device_get_child_node_count(dev);
568 return ERR_PTR(-ENODEV);
570 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
572 return ERR_PTR(-ENOMEM);
574 pdata->properties = devm_kcalloc(dev, nports, sizeof(*pp), GFP_KERNEL);
575 if (!pdata->properties)
576 return ERR_PTR(-ENOMEM);
578 pdata->nports = nports;
581 device_for_each_child_node(dev, fwnode) {
582 struct device_node *np = NULL;
584 pp = &pdata->properties[i++];
587 if (fwnode_property_read_u32(fwnode, "reg", &pp->idx) ||
588 pp->idx >= DWAPB_MAX_PORTS) {
590 "missing/invalid port index for port%d\n", i);
591 fwnode_handle_put(fwnode);
592 return ERR_PTR(-EINVAL);
595 if (fwnode_property_read_u32(fwnode, "snps,nr-gpios",
598 "failed to get number of gpios for port%d\n",
603 pp->irq_shared = false;
607 * Only port A can provide interrupts in all configurations of
613 if (dev->of_node && fwnode_property_read_bool(fwnode,
614 "interrupt-controller")) {
615 np = to_of_node(fwnode);
618 for (j = 0; j < pp->ngpio; j++) {
622 pp->irq[j] = of_irq_get(np, j);
623 else if (has_acpi_companion(dev))
624 pp->irq[j] = platform_get_irq(to_platform_device(dev), j);
631 dev_warn(dev, "no irq for port%d\n", pp->idx);
637 static const struct of_device_id dwapb_of_match[] = {
638 { .compatible = "snps,dw-apb-gpio", .data = (void *)0},
639 { .compatible = "apm,xgene-gpio-v2", .data = (void *)GPIO_REG_OFFSET_V2},
642 MODULE_DEVICE_TABLE(of, dwapb_of_match);
644 static const struct acpi_device_id dwapb_acpi_match[] = {
647 {"APMC0D81", GPIO_REG_OFFSET_V2},
650 MODULE_DEVICE_TABLE(acpi, dwapb_acpi_match);
652 static int dwapb_gpio_probe(struct platform_device *pdev)
655 struct dwapb_gpio *gpio;
657 struct device *dev = &pdev->dev;
658 struct dwapb_platform_data *pdata = dev_get_platdata(dev);
661 pdata = dwapb_gpio_get_pdata(dev);
663 return PTR_ERR(pdata);
669 gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL);
673 gpio->dev = &pdev->dev;
674 gpio->nr_ports = pdata->nports;
676 gpio->rst = devm_reset_control_get_optional_shared(dev, NULL);
677 if (IS_ERR(gpio->rst))
678 return PTR_ERR(gpio->rst);
680 reset_control_deassert(gpio->rst);
682 gpio->ports = devm_kcalloc(&pdev->dev, gpio->nr_ports,
683 sizeof(*gpio->ports), GFP_KERNEL);
687 gpio->regs = devm_platform_ioremap_resource(pdev, 0);
688 if (IS_ERR(gpio->regs))
689 return PTR_ERR(gpio->regs);
691 /* Optional bus clock */
692 gpio->clk = devm_clk_get(&pdev->dev, "bus");
693 if (!IS_ERR(gpio->clk)) {
694 err = clk_prepare_enable(gpio->clk);
696 dev_info(&pdev->dev, "Cannot enable clock\n");
703 gpio->flags = (uintptr_t)of_device_get_match_data(dev);
704 } else if (has_acpi_companion(dev)) {
705 const struct acpi_device_id *acpi_id;
707 acpi_id = acpi_match_device(dwapb_acpi_match, dev);
709 if (acpi_id->driver_data)
710 gpio->flags = acpi_id->driver_data;
714 for (i = 0; i < gpio->nr_ports; i++) {
715 err = dwapb_gpio_add_port(gpio, &pdata->properties[i], i);
719 platform_set_drvdata(pdev, gpio);
724 dwapb_gpio_unregister(gpio);
725 dwapb_irq_teardown(gpio);
726 clk_disable_unprepare(gpio->clk);
731 static int dwapb_gpio_remove(struct platform_device *pdev)
733 struct dwapb_gpio *gpio = platform_get_drvdata(pdev);
735 dwapb_gpio_unregister(gpio);
736 dwapb_irq_teardown(gpio);
737 reset_control_assert(gpio->rst);
738 clk_disable_unprepare(gpio->clk);
743 #ifdef CONFIG_PM_SLEEP
744 static int dwapb_gpio_suspend(struct device *dev)
746 struct dwapb_gpio *gpio = dev_get_drvdata(dev);
747 struct gpio_chip *gc = &gpio->ports[0].gc;
751 spin_lock_irqsave(&gc->bgpio_lock, flags);
752 for (i = 0; i < gpio->nr_ports; i++) {
754 unsigned int idx = gpio->ports[i].idx;
755 struct dwapb_context *ctx = gpio->ports[i].ctx;
759 offset = GPIO_SWPORTA_DDR + idx * GPIO_SWPORT_DDR_STRIDE;
760 ctx->dir = dwapb_read(gpio, offset);
762 offset = GPIO_SWPORTA_DR + idx * GPIO_SWPORT_DR_STRIDE;
763 ctx->data = dwapb_read(gpio, offset);
765 offset = GPIO_EXT_PORTA + idx * GPIO_EXT_PORT_STRIDE;
766 ctx->ext = dwapb_read(gpio, offset);
768 /* Only port A can provide interrupts */
770 ctx->int_mask = dwapb_read(gpio, GPIO_INTMASK);
771 ctx->int_en = dwapb_read(gpio, GPIO_INTEN);
772 ctx->int_pol = dwapb_read(gpio, GPIO_INT_POLARITY);
773 ctx->int_type = dwapb_read(gpio, GPIO_INTTYPE_LEVEL);
774 ctx->int_deb = dwapb_read(gpio, GPIO_PORTA_DEBOUNCE);
776 /* Mask out interrupts */
777 dwapb_write(gpio, GPIO_INTMASK,
778 0xffffffff & ~ctx->wake_en);
781 spin_unlock_irqrestore(&gc->bgpio_lock, flags);
783 clk_disable_unprepare(gpio->clk);
788 static int dwapb_gpio_resume(struct device *dev)
790 struct dwapb_gpio *gpio = dev_get_drvdata(dev);
791 struct gpio_chip *gc = &gpio->ports[0].gc;
795 if (!IS_ERR(gpio->clk))
796 clk_prepare_enable(gpio->clk);
798 spin_lock_irqsave(&gc->bgpio_lock, flags);
799 for (i = 0; i < gpio->nr_ports; i++) {
801 unsigned int idx = gpio->ports[i].idx;
802 struct dwapb_context *ctx = gpio->ports[i].ctx;
806 offset = GPIO_SWPORTA_DR + idx * GPIO_SWPORT_DR_STRIDE;
807 dwapb_write(gpio, offset, ctx->data);
809 offset = GPIO_SWPORTA_DDR + idx * GPIO_SWPORT_DDR_STRIDE;
810 dwapb_write(gpio, offset, ctx->dir);
812 offset = GPIO_EXT_PORTA + idx * GPIO_EXT_PORT_STRIDE;
813 dwapb_write(gpio, offset, ctx->ext);
815 /* Only port A can provide interrupts */
817 dwapb_write(gpio, GPIO_INTTYPE_LEVEL, ctx->int_type);
818 dwapb_write(gpio, GPIO_INT_POLARITY, ctx->int_pol);
819 dwapb_write(gpio, GPIO_PORTA_DEBOUNCE, ctx->int_deb);
820 dwapb_write(gpio, GPIO_INTEN, ctx->int_en);
821 dwapb_write(gpio, GPIO_INTMASK, ctx->int_mask);
823 /* Clear out spurious interrupts */
824 dwapb_write(gpio, GPIO_PORTA_EOI, 0xffffffff);
827 spin_unlock_irqrestore(&gc->bgpio_lock, flags);
833 static SIMPLE_DEV_PM_OPS(dwapb_gpio_pm_ops, dwapb_gpio_suspend,
836 static struct platform_driver dwapb_gpio_driver = {
838 .name = "gpio-dwapb",
839 .pm = &dwapb_gpio_pm_ops,
840 .of_match_table = of_match_ptr(dwapb_of_match),
841 .acpi_match_table = ACPI_PTR(dwapb_acpi_match),
843 .probe = dwapb_gpio_probe,
844 .remove = dwapb_gpio_remove,
847 module_platform_driver(dwapb_gpio_driver);
849 MODULE_LICENSE("GPL");
850 MODULE_AUTHOR("Jamie Iles");
851 MODULE_DESCRIPTION("Synopsys DesignWare APB GPIO driver");