2 * Copyright (C) 2015-2017 Broadcom
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License as
6 * published by the Free Software Foundation version 2.
8 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
9 * kind, whether express or implied; without even the implied warranty
10 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
14 #include <linux/bitops.h>
15 #include <linux/gpio/driver.h>
16 #include <linux/of_device.h>
17 #include <linux/of_irq.h>
18 #include <linux/module.h>
19 #include <linux/irqdomain.h>
20 #include <linux/irqchip/chained_irq.h>
21 #include <linux/interrupt.h>
22 #include <linux/bitops.h>
33 NUMBER_OF_GIO_REGISTERS
36 #define GIO_BANK_SIZE (NUMBER_OF_GIO_REGISTERS * sizeof(u32))
37 #define GIO_BANK_OFF(bank, off) (((bank) * GIO_BANK_SIZE) + (off * sizeof(u32)))
38 #define GIO_ODEN(bank) GIO_BANK_OFF(bank, GIO_REG_ODEN)
39 #define GIO_DATA(bank) GIO_BANK_OFF(bank, GIO_REG_DATA)
40 #define GIO_IODIR(bank) GIO_BANK_OFF(bank, GIO_REG_IODIR)
41 #define GIO_EC(bank) GIO_BANK_OFF(bank, GIO_REG_EC)
42 #define GIO_EI(bank) GIO_BANK_OFF(bank, GIO_REG_EI)
43 #define GIO_MASK(bank) GIO_BANK_OFF(bank, GIO_REG_MASK)
44 #define GIO_LEVEL(bank) GIO_BANK_OFF(bank, GIO_REG_LEVEL)
45 #define GIO_STAT(bank) GIO_BANK_OFF(bank, GIO_REG_STAT)
47 struct brcmstb_gpio_bank {
48 struct list_head node;
51 struct brcmstb_gpio_priv *parent_priv;
54 u32 saved_regs[GIO_REG_STAT]; /* Don't save and restore GIO_REG_STAT */
57 struct brcmstb_gpio_priv {
58 struct list_head bank_list;
59 void __iomem *reg_base;
60 struct platform_device *pdev;
61 struct irq_domain *irq_domain;
62 struct irq_chip irq_chip;
69 #define MAX_GPIO_PER_BANK 32
70 #define GPIO_BANK(gpio) ((gpio) >> 5)
71 /* assumes MAX_GPIO_PER_BANK is a multiple of 2 */
72 #define GPIO_BIT(gpio) ((gpio) & (MAX_GPIO_PER_BANK - 1))
74 static inline struct brcmstb_gpio_priv *
75 brcmstb_gpio_gc_to_priv(struct gpio_chip *gc)
77 struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);
78 return bank->parent_priv;
82 __brcmstb_gpio_get_active_irqs(struct brcmstb_gpio_bank *bank)
84 void __iomem *reg_base = bank->parent_priv->reg_base;
86 return bank->gc.read_reg(reg_base + GIO_STAT(bank->id)) &
87 bank->gc.read_reg(reg_base + GIO_MASK(bank->id));
91 brcmstb_gpio_get_active_irqs(struct brcmstb_gpio_bank *bank)
96 spin_lock_irqsave(&bank->gc.bgpio_lock, flags);
97 status = __brcmstb_gpio_get_active_irqs(bank);
98 spin_unlock_irqrestore(&bank->gc.bgpio_lock, flags);
103 static int brcmstb_gpio_hwirq_to_offset(irq_hw_number_t hwirq,
104 struct brcmstb_gpio_bank *bank)
106 return hwirq - (bank->gc.base - bank->parent_priv->gpio_base);
109 static void brcmstb_gpio_set_imask(struct brcmstb_gpio_bank *bank,
110 unsigned int hwirq, bool enable)
112 struct gpio_chip *gc = &bank->gc;
113 struct brcmstb_gpio_priv *priv = bank->parent_priv;
114 u32 mask = BIT(brcmstb_gpio_hwirq_to_offset(hwirq, bank));
118 spin_lock_irqsave(&gc->bgpio_lock, flags);
119 imask = gc->read_reg(priv->reg_base + GIO_MASK(bank->id));
124 gc->write_reg(priv->reg_base + GIO_MASK(bank->id), imask);
125 spin_unlock_irqrestore(&gc->bgpio_lock, flags);
128 static int brcmstb_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
130 struct brcmstb_gpio_priv *priv = brcmstb_gpio_gc_to_priv(gc);
131 /* gc_offset is relative to this gpio_chip; want real offset */
132 int hwirq = offset + (gc->base - priv->gpio_base);
134 if (hwirq >= priv->num_gpios)
136 return irq_create_mapping(priv->irq_domain, hwirq);
139 /* -------------------- IRQ chip functions -------------------- */
141 static void brcmstb_gpio_irq_mask(struct irq_data *d)
143 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
144 struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);
146 brcmstb_gpio_set_imask(bank, d->hwirq, false);
149 static void brcmstb_gpio_irq_unmask(struct irq_data *d)
151 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
152 struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);
154 brcmstb_gpio_set_imask(bank, d->hwirq, true);
157 static void brcmstb_gpio_irq_ack(struct irq_data *d)
159 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
160 struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);
161 struct brcmstb_gpio_priv *priv = bank->parent_priv;
162 u32 mask = BIT(brcmstb_gpio_hwirq_to_offset(d->hwirq, bank));
164 gc->write_reg(priv->reg_base + GIO_STAT(bank->id), mask);
167 static int brcmstb_gpio_irq_set_type(struct irq_data *d, unsigned int type)
169 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
170 struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);
171 struct brcmstb_gpio_priv *priv = bank->parent_priv;
172 u32 mask = BIT(brcmstb_gpio_hwirq_to_offset(d->hwirq, bank));
173 u32 edge_insensitive, iedge_insensitive;
174 u32 edge_config, iedge_config;
179 case IRQ_TYPE_LEVEL_LOW:
182 edge_insensitive = 0;
184 case IRQ_TYPE_LEVEL_HIGH:
187 edge_insensitive = 0;
189 case IRQ_TYPE_EDGE_FALLING:
192 edge_insensitive = 0;
194 case IRQ_TYPE_EDGE_RISING:
197 edge_insensitive = 0;
199 case IRQ_TYPE_EDGE_BOTH:
201 edge_config = 0; /* don't care, but want known value */
202 edge_insensitive = mask;
208 spin_lock_irqsave(&bank->gc.bgpio_lock, flags);
210 iedge_config = bank->gc.read_reg(priv->reg_base +
211 GIO_EC(bank->id)) & ~mask;
212 iedge_insensitive = bank->gc.read_reg(priv->reg_base +
213 GIO_EI(bank->id)) & ~mask;
214 ilevel = bank->gc.read_reg(priv->reg_base +
215 GIO_LEVEL(bank->id)) & ~mask;
217 bank->gc.write_reg(priv->reg_base + GIO_EC(bank->id),
218 iedge_config | edge_config);
219 bank->gc.write_reg(priv->reg_base + GIO_EI(bank->id),
220 iedge_insensitive | edge_insensitive);
221 bank->gc.write_reg(priv->reg_base + GIO_LEVEL(bank->id),
224 spin_unlock_irqrestore(&bank->gc.bgpio_lock, flags);
228 static int brcmstb_gpio_priv_set_wake(struct brcmstb_gpio_priv *priv,
234 ret = enable_irq_wake(priv->parent_wake_irq);
236 ret = disable_irq_wake(priv->parent_wake_irq);
238 dev_err(&priv->pdev->dev, "failed to %s wake-up interrupt\n",
239 enable ? "enable" : "disable");
243 static int brcmstb_gpio_irq_set_wake(struct irq_data *d, unsigned int enable)
245 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
246 struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);
247 struct brcmstb_gpio_priv *priv = bank->parent_priv;
248 u32 mask = BIT(brcmstb_gpio_hwirq_to_offset(d->hwirq, bank));
251 * Do not do anything specific for now, suspend/resume callbacks will
252 * configure the interrupt mask appropriately
255 bank->wake_active |= mask;
257 bank->wake_active &= ~mask;
259 return brcmstb_gpio_priv_set_wake(priv, enable);
262 static irqreturn_t brcmstb_gpio_wake_irq_handler(int irq, void *data)
264 struct brcmstb_gpio_priv *priv = data;
266 if (!priv || irq != priv->parent_wake_irq)
273 static void brcmstb_gpio_irq_bank_handler(struct brcmstb_gpio_bank *bank)
275 struct brcmstb_gpio_priv *priv = bank->parent_priv;
276 struct irq_domain *domain = priv->irq_domain;
277 int hwbase = bank->gc.base - priv->gpio_base;
278 unsigned long status;
280 while ((status = brcmstb_gpio_get_active_irqs(bank))) {
281 unsigned int irq, offset;
283 for_each_set_bit(offset, &status, 32) {
284 if (offset >= bank->width)
285 dev_warn(&priv->pdev->dev,
286 "IRQ for invalid GPIO (bank=%d, offset=%d)\n",
288 irq = irq_linear_revmap(domain, hwbase + offset);
289 generic_handle_irq(irq);
294 /* Each UPG GIO block has one IRQ for all banks */
295 static void brcmstb_gpio_irq_handler(struct irq_desc *desc)
297 struct brcmstb_gpio_priv *priv = irq_desc_get_handler_data(desc);
298 struct irq_chip *chip = irq_desc_get_chip(desc);
299 struct brcmstb_gpio_bank *bank;
301 /* Interrupts weren't properly cleared during probe */
302 BUG_ON(!priv || !chip);
304 chained_irq_enter(chip, desc);
305 list_for_each_entry(bank, &priv->bank_list, node)
306 brcmstb_gpio_irq_bank_handler(bank);
307 chained_irq_exit(chip, desc);
310 static struct brcmstb_gpio_bank *brcmstb_gpio_hwirq_to_bank(
311 struct brcmstb_gpio_priv *priv, irq_hw_number_t hwirq)
313 struct brcmstb_gpio_bank *bank;
316 /* banks are in descending order */
317 list_for_each_entry_reverse(bank, &priv->bank_list, node) {
326 * This lock class tells lockdep that GPIO irqs are in a different
327 * category than their parents, so it won't report false recursion.
329 static struct lock_class_key brcmstb_gpio_irq_lock_class;
330 static struct lock_class_key brcmstb_gpio_irq_request_class;
333 static int brcmstb_gpio_irq_map(struct irq_domain *d, unsigned int irq,
334 irq_hw_number_t hwirq)
336 struct brcmstb_gpio_priv *priv = d->host_data;
337 struct brcmstb_gpio_bank *bank =
338 brcmstb_gpio_hwirq_to_bank(priv, hwirq);
339 struct platform_device *pdev = priv->pdev;
345 dev_dbg(&pdev->dev, "Mapping irq %d for gpio line %d (bank %d)\n",
346 irq, (int)hwirq, bank->id);
347 ret = irq_set_chip_data(irq, &bank->gc);
350 irq_set_lockdep_class(irq, &brcmstb_gpio_irq_lock_class,
351 &brcmstb_gpio_irq_request_class);
352 irq_set_chip_and_handler(irq, &priv->irq_chip, handle_level_irq);
353 irq_set_noprobe(irq);
357 static void brcmstb_gpio_irq_unmap(struct irq_domain *d, unsigned int irq)
359 irq_set_chip_and_handler(irq, NULL, NULL);
360 irq_set_chip_data(irq, NULL);
363 static const struct irq_domain_ops brcmstb_gpio_irq_domain_ops = {
364 .map = brcmstb_gpio_irq_map,
365 .unmap = brcmstb_gpio_irq_unmap,
366 .xlate = irq_domain_xlate_twocell,
369 /* Make sure that the number of banks matches up between properties */
370 static int brcmstb_gpio_sanity_check_banks(struct device *dev,
371 struct device_node *np, struct resource *res)
373 int res_num_banks = resource_size(res) / GIO_BANK_SIZE;
375 of_property_count_u32_elems(np, "brcm,gpio-bank-widths");
377 if (res_num_banks != num_banks) {
378 dev_err(dev, "Mismatch in banks: res had %d, bank-widths had %d\n",
379 res_num_banks, num_banks);
386 static int brcmstb_gpio_remove(struct platform_device *pdev)
388 struct brcmstb_gpio_priv *priv = platform_get_drvdata(pdev);
389 struct brcmstb_gpio_bank *bank;
390 int offset, ret = 0, virq;
393 dev_err(&pdev->dev, "called %s without drvdata!\n", __func__);
397 if (priv->parent_irq > 0)
398 irq_set_chained_handler_and_data(priv->parent_irq, NULL, NULL);
400 /* Remove all IRQ mappings and delete the domain */
401 if (priv->irq_domain) {
402 for (offset = 0; offset < priv->num_gpios; offset++) {
403 virq = irq_find_mapping(priv->irq_domain, offset);
404 irq_dispose_mapping(virq);
406 irq_domain_remove(priv->irq_domain);
410 * You can lose return values below, but we report all errors, and it's
411 * more important to actually perform all of the steps.
413 list_for_each_entry(bank, &priv->bank_list, node)
414 gpiochip_remove(&bank->gc);
419 static int brcmstb_gpio_of_xlate(struct gpio_chip *gc,
420 const struct of_phandle_args *gpiospec, u32 *flags)
422 struct brcmstb_gpio_priv *priv = brcmstb_gpio_gc_to_priv(gc);
423 struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);
426 if (gc->of_gpio_n_cells != 2) {
431 if (WARN_ON(gpiospec->args_count < gc->of_gpio_n_cells))
434 offset = gpiospec->args[0] - (gc->base - priv->gpio_base);
435 if (offset >= gc->ngpio || offset < 0)
438 if (unlikely(offset >= bank->width)) {
439 dev_warn_ratelimited(&priv->pdev->dev,
440 "Received request for invalid GPIO offset %d\n",
445 *flags = gpiospec->args[1];
450 /* priv->parent_irq and priv->num_gpios must be set before calling */
451 static int brcmstb_gpio_irq_setup(struct platform_device *pdev,
452 struct brcmstb_gpio_priv *priv)
454 struct device *dev = &pdev->dev;
455 struct device_node *np = dev->of_node;
459 irq_domain_add_linear(np, priv->num_gpios,
460 &brcmstb_gpio_irq_domain_ops,
462 if (!priv->irq_domain) {
463 dev_err(dev, "Couldn't allocate IRQ domain\n");
467 if (of_property_read_bool(np, "wakeup-source")) {
468 priv->parent_wake_irq = platform_get_irq(pdev, 1);
469 if (priv->parent_wake_irq < 0) {
470 priv->parent_wake_irq = 0;
472 "Couldn't get wake IRQ - GPIOs will not be able to wake from sleep");
475 * Set wakeup capability so we can process boot-time
476 * "wakeups" (e.g., from S5 cold boot)
478 device_set_wakeup_capable(dev, true);
479 device_wakeup_enable(dev);
480 err = devm_request_irq(dev, priv->parent_wake_irq,
481 brcmstb_gpio_wake_irq_handler,
483 "brcmstb-gpio-wake", priv);
486 dev_err(dev, "Couldn't request wake IRQ");
487 goto out_free_domain;
492 priv->irq_chip.name = dev_name(dev);
493 priv->irq_chip.irq_disable = brcmstb_gpio_irq_mask;
494 priv->irq_chip.irq_mask = brcmstb_gpio_irq_mask;
495 priv->irq_chip.irq_unmask = brcmstb_gpio_irq_unmask;
496 priv->irq_chip.irq_ack = brcmstb_gpio_irq_ack;
497 priv->irq_chip.irq_set_type = brcmstb_gpio_irq_set_type;
499 if (priv->parent_wake_irq)
500 priv->irq_chip.irq_set_wake = brcmstb_gpio_irq_set_wake;
502 irq_set_chained_handler_and_data(priv->parent_irq,
503 brcmstb_gpio_irq_handler, priv);
504 irq_set_status_flags(priv->parent_irq, IRQ_DISABLE_UNLAZY);
509 irq_domain_remove(priv->irq_domain);
514 static void brcmstb_gpio_bank_save(struct brcmstb_gpio_priv *priv,
515 struct brcmstb_gpio_bank *bank)
517 struct gpio_chip *gc = &bank->gc;
520 for (i = 0; i < GIO_REG_STAT; i++)
521 bank->saved_regs[i] = gc->read_reg(priv->reg_base +
522 GIO_BANK_OFF(bank->id, i));
525 static void brcmstb_gpio_quiesce(struct device *dev, bool save)
527 struct brcmstb_gpio_priv *priv = dev_get_drvdata(dev);
528 struct brcmstb_gpio_bank *bank;
529 struct gpio_chip *gc;
532 /* disable non-wake interrupt */
533 if (priv->parent_irq >= 0)
534 disable_irq(priv->parent_irq);
536 list_for_each_entry(bank, &priv->bank_list, node) {
540 brcmstb_gpio_bank_save(priv, bank);
542 /* Unmask GPIOs which have been flagged as wake-up sources */
543 if (priv->parent_wake_irq)
544 imask = bank->wake_active;
547 gc->write_reg(priv->reg_base + GIO_MASK(bank->id),
552 static void brcmstb_gpio_shutdown(struct platform_device *pdev)
554 /* Enable GPIO for S5 cold boot */
555 brcmstb_gpio_quiesce(&pdev->dev, false);
558 #ifdef CONFIG_PM_SLEEP
559 static void brcmstb_gpio_bank_restore(struct brcmstb_gpio_priv *priv,
560 struct brcmstb_gpio_bank *bank)
562 struct gpio_chip *gc = &bank->gc;
565 for (i = 0; i < GIO_REG_STAT; i++)
566 gc->write_reg(priv->reg_base + GIO_BANK_OFF(bank->id, i),
567 bank->saved_regs[i]);
570 static int brcmstb_gpio_suspend(struct device *dev)
572 brcmstb_gpio_quiesce(dev, true);
576 static int brcmstb_gpio_resume(struct device *dev)
578 struct brcmstb_gpio_priv *priv = dev_get_drvdata(dev);
579 struct brcmstb_gpio_bank *bank;
580 bool need_wakeup_event = false;
582 list_for_each_entry(bank, &priv->bank_list, node) {
583 need_wakeup_event |= !!__brcmstb_gpio_get_active_irqs(bank);
584 brcmstb_gpio_bank_restore(priv, bank);
587 if (priv->parent_wake_irq && need_wakeup_event)
588 pm_wakeup_event(dev, 0);
590 /* enable non-wake interrupt */
591 if (priv->parent_irq >= 0)
592 enable_irq(priv->parent_irq);
598 #define brcmstb_gpio_suspend NULL
599 #define brcmstb_gpio_resume NULL
600 #endif /* CONFIG_PM_SLEEP */
602 static const struct dev_pm_ops brcmstb_gpio_pm_ops = {
603 .suspend_noirq = brcmstb_gpio_suspend,
604 .resume_noirq = brcmstb_gpio_resume,
607 static int brcmstb_gpio_probe(struct platform_device *pdev)
609 struct device *dev = &pdev->dev;
610 struct device_node *np = dev->of_node;
611 void __iomem *reg_base;
612 struct brcmstb_gpio_priv *priv;
613 struct resource *res;
614 struct property *prop;
619 static int gpio_base;
620 unsigned long flags = 0;
621 bool need_wakeup_event = false;
623 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
626 platform_set_drvdata(pdev, priv);
627 INIT_LIST_HEAD(&priv->bank_list);
629 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
630 reg_base = devm_ioremap_resource(dev, res);
631 if (IS_ERR(reg_base))
632 return PTR_ERR(reg_base);
634 priv->gpio_base = gpio_base;
635 priv->reg_base = reg_base;
638 if (of_property_read_bool(np, "interrupt-controller")) {
639 priv->parent_irq = platform_get_irq(pdev, 0);
640 if (priv->parent_irq <= 0) {
641 dev_err(dev, "Couldn't get IRQ");
645 priv->parent_irq = -ENOENT;
648 if (brcmstb_gpio_sanity_check_banks(dev, np, res))
652 * MIPS endianness is configured by boot strap, which also reverses all
653 * bus endianness (i.e., big-endian CPU + big endian bus ==> native
656 * Other architectures (e.g., ARM) either do not support big endian, or
657 * else leave I/O in little endian mode.
659 #if defined(CONFIG_MIPS) && defined(__BIG_ENDIAN)
660 flags = BGPIOF_BIG_ENDIAN_BYTE_ORDER;
663 of_property_for_each_u32(np, "brcm,gpio-bank-widths", prop, p,
665 struct brcmstb_gpio_bank *bank;
666 struct gpio_chip *gc;
668 bank = devm_kzalloc(dev, sizeof(*bank), GFP_KERNEL);
674 bank->parent_priv = priv;
675 bank->id = num_banks;
676 if (bank_width <= 0 || bank_width > MAX_GPIO_PER_BANK) {
677 dev_err(dev, "Invalid bank width %d\n", bank_width);
681 bank->width = bank_width;
685 * Regs are 4 bytes wide, have data reg, no set/clear regs,
686 * and direction bits have 0 = output and 1 = input
689 err = bgpio_init(gc, dev, 4,
690 reg_base + GIO_DATA(bank->id),
692 reg_base + GIO_IODIR(bank->id), flags);
694 dev_err(dev, "bgpio_init() failed\n");
699 gc->owner = THIS_MODULE;
700 gc->label = devm_kasprintf(dev, GFP_KERNEL, "%pOF", dev->of_node);
705 gc->base = gpio_base;
706 gc->of_gpio_n_cells = 2;
707 gc->of_xlate = brcmstb_gpio_of_xlate;
708 /* not all ngpio lines are valid, will use bank width later */
709 gc->ngpio = MAX_GPIO_PER_BANK;
710 if (priv->parent_irq > 0)
711 gc->to_irq = brcmstb_gpio_to_irq;
714 * Mask all interrupts by default, since wakeup interrupts may
715 * be retained from S5 cold boot
717 need_wakeup_event |= !!__brcmstb_gpio_get_active_irqs(bank);
718 gc->write_reg(reg_base + GIO_MASK(bank->id), 0);
720 err = gpiochip_add_data(gc, bank);
722 dev_err(dev, "Could not add gpiochip for bank %d\n",
726 gpio_base += gc->ngpio;
728 dev_dbg(dev, "bank=%d, base=%d, ngpio=%d, width=%d\n", bank->id,
729 gc->base, gc->ngpio, bank->width);
731 /* Everything looks good, so add bank to list */
732 list_add(&bank->node, &priv->bank_list);
737 priv->num_gpios = gpio_base - priv->gpio_base;
738 if (priv->parent_irq > 0) {
739 err = brcmstb_gpio_irq_setup(pdev, priv);
744 dev_info(dev, "Registered %d banks (GPIO(s): %d-%d)\n",
745 num_banks, priv->gpio_base, gpio_base - 1);
747 if (priv->parent_wake_irq && need_wakeup_event)
748 pm_wakeup_event(dev, 0);
753 (void) brcmstb_gpio_remove(pdev);
757 static const struct of_device_id brcmstb_gpio_of_match[] = {
758 { .compatible = "brcm,brcmstb-gpio" },
762 MODULE_DEVICE_TABLE(of, brcmstb_gpio_of_match);
764 static struct platform_driver brcmstb_gpio_driver = {
766 .name = "brcmstb-gpio",
767 .of_match_table = brcmstb_gpio_of_match,
768 .pm = &brcmstb_gpio_pm_ops,
770 .probe = brcmstb_gpio_probe,
771 .remove = brcmstb_gpio_remove,
772 .shutdown = brcmstb_gpio_shutdown,
774 module_platform_driver(brcmstb_gpio_driver);
776 MODULE_AUTHOR("Gregory Fong");
777 MODULE_DESCRIPTION("Driver for Broadcom BRCMSTB SoC UPG GPIO");
778 MODULE_LICENSE("GPL v2");