2 * Copyright (C) 2015 Broadcom Corporation
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License as
6 * published by the Free Software Foundation version 2.
8 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
9 * kind, whether express or implied; without even the implied warranty
10 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
14 #include <linux/bitops.h>
15 #include <linux/gpio/driver.h>
16 #include <linux/of_device.h>
17 #include <linux/of_irq.h>
18 #include <linux/module.h>
19 #include <linux/irqdomain.h>
20 #include <linux/irqchip/chained_irq.h>
21 #include <linux/interrupt.h>
22 #include <linux/reboot.h>
24 #define GIO_BANK_SIZE 0x20
25 #define GIO_ODEN(bank) (((bank) * GIO_BANK_SIZE) + 0x00)
26 #define GIO_DATA(bank) (((bank) * GIO_BANK_SIZE) + 0x04)
27 #define GIO_IODIR(bank) (((bank) * GIO_BANK_SIZE) + 0x08)
28 #define GIO_EC(bank) (((bank) * GIO_BANK_SIZE) + 0x0c)
29 #define GIO_EI(bank) (((bank) * GIO_BANK_SIZE) + 0x10)
30 #define GIO_MASK(bank) (((bank) * GIO_BANK_SIZE) + 0x14)
31 #define GIO_LEVEL(bank) (((bank) * GIO_BANK_SIZE) + 0x18)
32 #define GIO_STAT(bank) (((bank) * GIO_BANK_SIZE) + 0x1c)
34 struct brcmstb_gpio_bank {
35 struct list_head node;
38 struct brcmstb_gpio_priv *parent_priv;
40 struct irq_chip irq_chip;
43 struct brcmstb_gpio_priv {
44 struct list_head bank_list;
45 void __iomem *reg_base;
46 struct platform_device *pdev;
51 struct notifier_block reboot_notifier;
54 #define MAX_GPIO_PER_BANK 32
55 #define GPIO_BANK(gpio) ((gpio) >> 5)
56 /* assumes MAX_GPIO_PER_BANK is a multiple of 2 */
57 #define GPIO_BIT(gpio) ((gpio) & (MAX_GPIO_PER_BANK - 1))
59 static inline struct brcmstb_gpio_priv *
60 brcmstb_gpio_gc_to_priv(struct gpio_chip *gc)
62 struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);
63 return bank->parent_priv;
66 static void brcmstb_gpio_set_imask(struct brcmstb_gpio_bank *bank,
67 unsigned int offset, bool enable)
69 struct gpio_chip *gc = &bank->gc;
70 struct brcmstb_gpio_priv *priv = bank->parent_priv;
71 u32 mask = gc->pin2mask(gc, offset);
75 spin_lock_irqsave(&gc->bgpio_lock, flags);
76 imask = gc->read_reg(priv->reg_base + GIO_MASK(bank->id));
81 gc->write_reg(priv->reg_base + GIO_MASK(bank->id), imask);
82 spin_unlock_irqrestore(&gc->bgpio_lock, flags);
85 /* -------------------- IRQ chip functions -------------------- */
87 static void brcmstb_gpio_irq_mask(struct irq_data *d)
89 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
90 struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);
92 brcmstb_gpio_set_imask(bank, d->hwirq, false);
95 static void brcmstb_gpio_irq_unmask(struct irq_data *d)
97 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
98 struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);
100 brcmstb_gpio_set_imask(bank, d->hwirq, true);
103 static int brcmstb_gpio_irq_set_type(struct irq_data *d, unsigned int type)
105 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
106 struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);
107 struct brcmstb_gpio_priv *priv = bank->parent_priv;
108 u32 mask = BIT(d->hwirq);
109 u32 edge_insensitive, iedge_insensitive;
110 u32 edge_config, iedge_config;
115 case IRQ_TYPE_LEVEL_LOW:
118 edge_insensitive = 0;
120 case IRQ_TYPE_LEVEL_HIGH:
123 edge_insensitive = 0;
125 case IRQ_TYPE_EDGE_FALLING:
128 edge_insensitive = 0;
130 case IRQ_TYPE_EDGE_RISING:
133 edge_insensitive = 0;
135 case IRQ_TYPE_EDGE_BOTH:
137 edge_config = 0; /* don't care, but want known value */
138 edge_insensitive = mask;
144 spin_lock_irqsave(&bank->gc.bgpio_lock, flags);
146 iedge_config = bank->gc.read_reg(priv->reg_base +
147 GIO_EC(bank->id)) & ~mask;
148 iedge_insensitive = bank->gc.read_reg(priv->reg_base +
149 GIO_EI(bank->id)) & ~mask;
150 ilevel = bank->gc.read_reg(priv->reg_base +
151 GIO_LEVEL(bank->id)) & ~mask;
153 bank->gc.write_reg(priv->reg_base + GIO_EC(bank->id),
154 iedge_config | edge_config);
155 bank->gc.write_reg(priv->reg_base + GIO_EI(bank->id),
156 iedge_insensitive | edge_insensitive);
157 bank->gc.write_reg(priv->reg_base + GIO_LEVEL(bank->id),
160 spin_unlock_irqrestore(&bank->gc.bgpio_lock, flags);
164 static int brcmstb_gpio_priv_set_wake(struct brcmstb_gpio_priv *priv,
170 * Only enable wake IRQ once for however many hwirqs can wake
171 * since they all use the same wake IRQ. Mask will be set
172 * up appropriately thanks to IRQCHIP_MASK_ON_SUSPEND flag.
175 ret = enable_irq_wake(priv->parent_wake_irq);
177 ret = disable_irq_wake(priv->parent_wake_irq);
179 dev_err(&priv->pdev->dev, "failed to %s wake-up interrupt\n",
180 enable ? "enable" : "disable");
184 static int brcmstb_gpio_irq_set_wake(struct irq_data *d, unsigned int enable)
186 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
187 struct brcmstb_gpio_priv *priv = brcmstb_gpio_gc_to_priv(gc);
189 return brcmstb_gpio_priv_set_wake(priv, enable);
192 static irqreturn_t brcmstb_gpio_wake_irq_handler(int irq, void *data)
194 struct brcmstb_gpio_priv *priv = data;
196 if (!priv || irq != priv->parent_wake_irq)
198 pm_wakeup_event(&priv->pdev->dev, 0);
202 static void brcmstb_gpio_irq_bank_handler(struct brcmstb_gpio_bank *bank)
204 struct brcmstb_gpio_priv *priv = bank->parent_priv;
205 struct irq_domain *irq_domain = bank->gc.irqdomain;
206 void __iomem *reg_base = priv->reg_base;
207 unsigned long status;
210 spin_lock_irqsave(&bank->gc.bgpio_lock, flags);
211 while ((status = bank->gc.read_reg(reg_base + GIO_STAT(bank->id)) &
212 bank->gc.read_reg(reg_base + GIO_MASK(bank->id)))) {
215 for_each_set_bit(bit, &status, 32) {
216 u32 stat = bank->gc.read_reg(reg_base +
218 if (bit >= bank->width)
219 dev_warn(&priv->pdev->dev,
220 "IRQ for invalid GPIO (bank=%d, offset=%d)\n",
222 bank->gc.write_reg(reg_base + GIO_STAT(bank->id),
224 generic_handle_irq(irq_find_mapping(irq_domain, bit));
227 spin_unlock_irqrestore(&bank->gc.bgpio_lock, flags);
230 /* Each UPG GIO block has one IRQ for all banks */
231 static void brcmstb_gpio_irq_handler(struct irq_desc *desc)
233 struct gpio_chip *gc = irq_desc_get_handler_data(desc);
234 struct brcmstb_gpio_priv *priv = brcmstb_gpio_gc_to_priv(gc);
235 struct irq_chip *chip = irq_desc_get_chip(desc);
236 struct list_head *pos;
238 /* Interrupts weren't properly cleared during probe */
239 BUG_ON(!priv || !chip);
241 chained_irq_enter(chip, desc);
242 list_for_each(pos, &priv->bank_list) {
243 struct brcmstb_gpio_bank *bank =
244 list_entry(pos, struct brcmstb_gpio_bank, node);
245 brcmstb_gpio_irq_bank_handler(bank);
247 chained_irq_exit(chip, desc);
250 static int brcmstb_gpio_reboot(struct notifier_block *nb,
251 unsigned long action, void *data)
253 struct brcmstb_gpio_priv *priv =
254 container_of(nb, struct brcmstb_gpio_priv, reboot_notifier);
256 /* Enable GPIO for S5 cold boot */
257 if (action == SYS_POWER_OFF)
258 brcmstb_gpio_priv_set_wake(priv, 1);
263 /* Make sure that the number of banks matches up between properties */
264 static int brcmstb_gpio_sanity_check_banks(struct device *dev,
265 struct device_node *np, struct resource *res)
267 int res_num_banks = resource_size(res) / GIO_BANK_SIZE;
269 of_property_count_u32_elems(np, "brcm,gpio-bank-widths");
271 if (res_num_banks != num_banks) {
272 dev_err(dev, "Mismatch in banks: res had %d, bank-widths had %d\n",
273 res_num_banks, num_banks);
280 static int brcmstb_gpio_remove(struct platform_device *pdev)
282 struct brcmstb_gpio_priv *priv = platform_get_drvdata(pdev);
283 struct list_head *pos;
284 struct brcmstb_gpio_bank *bank;
288 dev_err(&pdev->dev, "called %s without drvdata!\n", __func__);
293 * You can lose return values below, but we report all errors, and it's
294 * more important to actually perform all of the steps.
296 list_for_each(pos, &priv->bank_list) {
297 bank = list_entry(pos, struct brcmstb_gpio_bank, node);
298 gpiochip_remove(&bank->gc);
300 if (priv->reboot_notifier.notifier_call) {
301 ret = unregister_reboot_notifier(&priv->reboot_notifier);
304 "failed to unregister reboot notifier\n");
309 static int brcmstb_gpio_of_xlate(struct gpio_chip *gc,
310 const struct of_phandle_args *gpiospec, u32 *flags)
312 struct brcmstb_gpio_priv *priv = brcmstb_gpio_gc_to_priv(gc);
313 struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);
316 if (gc->of_gpio_n_cells != 2) {
321 if (WARN_ON(gpiospec->args_count < gc->of_gpio_n_cells))
324 offset = gpiospec->args[0] - (gc->base - priv->gpio_base);
325 if (offset >= gc->ngpio || offset < 0)
328 if (unlikely(offset >= bank->width)) {
329 dev_warn_ratelimited(&priv->pdev->dev,
330 "Received request for invalid GPIO offset %d\n",
335 *flags = gpiospec->args[1];
340 /* Before calling, must have bank->parent_irq set and gpiochip registered */
341 static int brcmstb_gpio_irq_setup(struct platform_device *pdev,
342 struct brcmstb_gpio_bank *bank)
344 struct brcmstb_gpio_priv *priv = bank->parent_priv;
345 struct device *dev = &pdev->dev;
346 struct device_node *np = dev->of_node;
348 bank->irq_chip.name = dev_name(dev);
349 bank->irq_chip.irq_mask = brcmstb_gpio_irq_mask;
350 bank->irq_chip.irq_unmask = brcmstb_gpio_irq_unmask;
351 bank->irq_chip.irq_set_type = brcmstb_gpio_irq_set_type;
353 /* Ensures that all non-wakeup IRQs are disabled at suspend */
354 bank->irq_chip.flags = IRQCHIP_MASK_ON_SUSPEND;
356 if (IS_ENABLED(CONFIG_PM_SLEEP) && !priv->can_wake &&
357 of_property_read_bool(np, "wakeup-source")) {
358 priv->parent_wake_irq = platform_get_irq(pdev, 1);
359 if (priv->parent_wake_irq < 0) {
361 "Couldn't get wake IRQ - GPIOs will not be able to wake from sleep");
366 * Set wakeup capability before requesting wakeup
367 * interrupt, so we can process boot-time "wakeups"
368 * (e.g., from S5 cold boot)
370 device_set_wakeup_capable(dev, true);
371 device_wakeup_enable(dev);
372 err = devm_request_irq(dev, priv->parent_wake_irq,
373 brcmstb_gpio_wake_irq_handler, 0,
374 "brcmstb-gpio-wake", priv);
377 dev_err(dev, "Couldn't request wake IRQ");
381 priv->reboot_notifier.notifier_call =
383 register_reboot_notifier(&priv->reboot_notifier);
384 priv->can_wake = true;
389 bank->irq_chip.irq_set_wake = brcmstb_gpio_irq_set_wake;
391 gpiochip_irqchip_add(&bank->gc, &bank->irq_chip, 0,
392 handle_simple_irq, IRQ_TYPE_NONE);
393 gpiochip_set_chained_irqchip(&bank->gc, &bank->irq_chip,
394 priv->parent_irq, brcmstb_gpio_irq_handler);
399 static int brcmstb_gpio_probe(struct platform_device *pdev)
401 struct device *dev = &pdev->dev;
402 struct device_node *np = dev->of_node;
403 void __iomem *reg_base;
404 struct brcmstb_gpio_priv *priv;
405 struct resource *res;
406 struct property *prop;
411 static int gpio_base;
413 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
416 platform_set_drvdata(pdev, priv);
417 INIT_LIST_HEAD(&priv->bank_list);
419 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
420 reg_base = devm_ioremap_resource(dev, res);
421 if (IS_ERR(reg_base))
422 return PTR_ERR(reg_base);
424 priv->gpio_base = gpio_base;
425 priv->reg_base = reg_base;
428 if (of_property_read_bool(np, "interrupt-controller")) {
429 priv->parent_irq = platform_get_irq(pdev, 0);
430 if (priv->parent_irq <= 0) {
431 dev_err(dev, "Couldn't get IRQ");
435 priv->parent_irq = -ENOENT;
438 if (brcmstb_gpio_sanity_check_banks(dev, np, res))
441 of_property_for_each_u32(np, "brcm,gpio-bank-widths", prop, p,
443 struct brcmstb_gpio_bank *bank;
444 struct gpio_chip *gc;
446 bank = devm_kzalloc(dev, sizeof(*bank), GFP_KERNEL);
452 bank->parent_priv = priv;
453 bank->id = num_banks;
454 if (bank_width <= 0 || bank_width > MAX_GPIO_PER_BANK) {
455 dev_err(dev, "Invalid bank width %d\n", bank_width);
458 bank->width = bank_width;
462 * Regs are 4 bytes wide, have data reg, no set/clear regs,
463 * and direction bits have 0 = output and 1 = input
466 err = bgpio_init(gc, dev, 4,
467 reg_base + GIO_DATA(bank->id),
469 reg_base + GIO_IODIR(bank->id), 0);
471 dev_err(dev, "bgpio_init() failed\n");
476 gc->owner = THIS_MODULE;
477 gc->label = np->full_name;
478 gc->base = gpio_base;
479 gc->of_gpio_n_cells = 2;
480 gc->of_xlate = brcmstb_gpio_of_xlate;
481 /* not all ngpio lines are valid, will use bank width later */
482 gc->ngpio = MAX_GPIO_PER_BANK;
485 * Mask all interrupts by default, since wakeup interrupts may
486 * be retained from S5 cold boot
488 gc->write_reg(reg_base + GIO_MASK(bank->id), 0);
490 err = gpiochip_add_data(gc, bank);
492 dev_err(dev, "Could not add gpiochip for bank %d\n",
496 gpio_base += gc->ngpio;
498 if (priv->parent_irq > 0) {
499 err = brcmstb_gpio_irq_setup(pdev, bank);
504 dev_dbg(dev, "bank=%d, base=%d, ngpio=%d, width=%d\n", bank->id,
505 gc->base, gc->ngpio, bank->width);
507 /* Everything looks good, so add bank to list */
508 list_add(&bank->node, &priv->bank_list);
513 dev_info(dev, "Registered %d banks (GPIO(s): %d-%d)\n",
514 num_banks, priv->gpio_base, gpio_base - 1);
519 (void) brcmstb_gpio_remove(pdev);
523 static const struct of_device_id brcmstb_gpio_of_match[] = {
524 { .compatible = "brcm,brcmstb-gpio" },
528 MODULE_DEVICE_TABLE(of, brcmstb_gpio_of_match);
530 static struct platform_driver brcmstb_gpio_driver = {
532 .name = "brcmstb-gpio",
533 .of_match_table = brcmstb_gpio_of_match,
535 .probe = brcmstb_gpio_probe,
536 .remove = brcmstb_gpio_remove,
538 module_platform_driver(brcmstb_gpio_driver);
540 MODULE_AUTHOR("Gregory Fong");
541 MODULE_DESCRIPTION("Driver for Broadcom BRCMSTB SoC UPG GPIO");
542 MODULE_LICENSE("GPL v2");