1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Driver Header File for FPGA Device Feature List (DFL) Support
5 * Copyright (C) 2017-2018 Intel Corporation, Inc.
8 * Kang Luwei <luwei.kang@intel.com>
9 * Zhang Yi <yi.z.zhang@intel.com>
10 * Wu Hao <hao.wu@intel.com>
11 * Xiao Guangrong <guangrong.xiao@linux.intel.com>
17 #include <linux/bitfield.h>
18 #include <linux/cdev.h>
19 #include <linux/delay.h>
21 #include <linux/iopoll.h>
22 #include <linux/io-64-nonatomic-lo-hi.h>
23 #include <linux/platform_device.h>
24 #include <linux/slab.h>
25 #include <linux/uuid.h>
26 #include <linux/fpga/fpga-region.h>
28 /* maximum supported number of ports */
29 #define MAX_DFL_FPGA_PORT_NUM 4
30 /* plus one for fme device */
31 #define MAX_DFL_FEATURE_DEV_NUM (MAX_DFL_FPGA_PORT_NUM + 1)
33 /* Reserved 0xfe for Header Group Register and 0xff for AFU */
34 #define FEATURE_ID_FIU_HEADER 0xfe
35 #define FEATURE_ID_AFU 0xff
37 #define FME_FEATURE_ID_HEADER FEATURE_ID_FIU_HEADER
38 #define FME_FEATURE_ID_THERMAL_MGMT 0x1
39 #define FME_FEATURE_ID_POWER_MGMT 0x2
40 #define FME_FEATURE_ID_GLOBAL_IPERF 0x3
41 #define FME_FEATURE_ID_GLOBAL_ERR 0x4
42 #define FME_FEATURE_ID_PR_MGMT 0x5
43 #define FME_FEATURE_ID_HSSI 0x6
44 #define FME_FEATURE_ID_GLOBAL_DPERF 0x7
46 #define PORT_FEATURE_ID_HEADER FEATURE_ID_FIU_HEADER
47 #define PORT_FEATURE_ID_AFU FEATURE_ID_AFU
48 #define PORT_FEATURE_ID_ERROR 0x10
49 #define PORT_FEATURE_ID_UMSG 0x11
50 #define PORT_FEATURE_ID_UINT 0x12
51 #define PORT_FEATURE_ID_STP 0x13
54 * Device Feature Header Register Set
56 * For FIUs, they all have DFH + GUID + NEXT_AFU as common header registers.
57 * For AFUs, they have DFH + GUID as common header registers.
58 * For private features, they only have DFH register as common header.
67 /* Device Feature Header Register Bitfield */
68 #define DFH_ID GENMASK_ULL(11, 0) /* Feature ID */
69 #define DFH_ID_FIU_FME 0
70 #define DFH_ID_FIU_PORT 1
71 #define DFH_REVISION GENMASK_ULL(15, 12) /* Feature revision */
72 #define DFH_NEXT_HDR_OFST GENMASK_ULL(39, 16) /* Offset to next DFH */
73 #define DFH_EOL BIT_ULL(40) /* End of list */
74 #define DFH_TYPE GENMASK_ULL(63, 60) /* Feature type */
75 #define DFH_TYPE_AFU 1
76 #define DFH_TYPE_PRIVATE 3
77 #define DFH_TYPE_FIU 4
79 /* Next AFU Register Bitfield */
80 #define NEXT_AFU_NEXT_DFH_OFST GENMASK_ULL(23, 0) /* Offset to next AFU */
82 /* FME Header Register Set */
83 #define FME_HDR_DFH DFH
84 #define FME_HDR_GUID_L GUID_L
85 #define FME_HDR_GUID_H GUID_H
86 #define FME_HDR_NEXT_AFU NEXT_AFU
87 #define FME_HDR_CAP 0x30
88 #define FME_HDR_PORT_OFST(n) (0x38 + ((n) * 0x8))
89 #define FME_HDR_BITSTREAM_ID 0x60
90 #define FME_HDR_BITSTREAM_MD 0x68
92 /* FME Fab Capability Register Bitfield */
93 #define FME_CAP_FABRIC_VERID GENMASK_ULL(7, 0) /* Fabric version ID */
94 #define FME_CAP_SOCKET_ID BIT_ULL(8) /* Socket ID */
95 #define FME_CAP_PCIE0_LINK_AVL BIT_ULL(12) /* PCIE0 Link */
96 #define FME_CAP_PCIE1_LINK_AVL BIT_ULL(13) /* PCIE1 Link */
97 #define FME_CAP_COHR_LINK_AVL BIT_ULL(14) /* Coherent Link */
98 #define FME_CAP_IOMMU_AVL BIT_ULL(16) /* IOMMU available */
99 #define FME_CAP_NUM_PORTS GENMASK_ULL(19, 17) /* Number of ports */
100 #define FME_CAP_ADDR_WIDTH GENMASK_ULL(29, 24) /* Address bus width */
101 #define FME_CAP_CACHE_SIZE GENMASK_ULL(43, 32) /* cache size in KB */
102 #define FME_CAP_CACHE_ASSOC GENMASK_ULL(47, 44) /* Associativity */
104 /* FME Port Offset Register Bitfield */
105 /* Offset to port device feature header */
106 #define FME_PORT_OFST_DFH_OFST GENMASK_ULL(23, 0)
107 /* PCI Bar ID for this port */
108 #define FME_PORT_OFST_BAR_ID GENMASK_ULL(34, 32)
109 /* AFU MMIO access permission. 1 - VF, 0 - PF. */
110 #define FME_PORT_OFST_ACC_CTRL BIT_ULL(55)
111 #define FME_PORT_OFST_ACC_PF 0
112 #define FME_PORT_OFST_ACC_VF 1
113 #define FME_PORT_OFST_IMP BIT_ULL(60)
115 /* PORT Header Register Set */
116 #define PORT_HDR_DFH DFH
117 #define PORT_HDR_GUID_L GUID_L
118 #define PORT_HDR_GUID_H GUID_H
119 #define PORT_HDR_NEXT_AFU NEXT_AFU
120 #define PORT_HDR_CAP 0x30
121 #define PORT_HDR_CTRL 0x38
122 #define PORT_HDR_STS 0x40
124 /* Port Capability Register Bitfield */
125 #define PORT_CAP_PORT_NUM GENMASK_ULL(1, 0) /* ID of this port */
126 #define PORT_CAP_MMIO_SIZE GENMASK_ULL(23, 8) /* MMIO size in KB */
127 #define PORT_CAP_SUPP_INT_NUM GENMASK_ULL(35, 32) /* Interrupts num */
129 /* Port Control Register Bitfield */
130 #define PORT_CTRL_SFTRST BIT_ULL(0) /* Port soft reset */
131 /* Latency tolerance reporting. '1' >= 40us, '0' < 40us.*/
132 #define PORT_CTRL_LATENCY BIT_ULL(2)
133 #define PORT_CTRL_SFTRST_ACK BIT_ULL(4) /* HW ack for reset */
135 /* Port Status Register Bitfield */
136 #define PORT_STS_AP2_EVT BIT_ULL(13) /* AP2 event detected */
137 #define PORT_STS_AP1_EVT BIT_ULL(12) /* AP1 event detected */
138 #define PORT_STS_PWR_STATE GENMASK_ULL(11, 8) /* AFU power states */
139 #define PORT_STS_PWR_STATE_NORM 0
140 #define PORT_STS_PWR_STATE_AP1 1 /* 50% throttling */
141 #define PORT_STS_PWR_STATE_AP2 2 /* 90% throttling */
142 #define PORT_STS_PWR_STATE_AP6 6 /* 100% throttling */
145 * struct dfl_fpga_port_ops - port ops
147 * @name: name of this port ops, to match with port platform device.
148 * @owner: pointer to the module which owns this port ops.
149 * @node: node to link port ops to global list.
150 * @get_id: get port id from hardware.
151 * @enable_set: enable/disable the port.
153 struct dfl_fpga_port_ops {
155 struct module *owner;
156 struct list_head node;
157 int (*get_id)(struct platform_device *pdev);
158 int (*enable_set)(struct platform_device *pdev, bool enable);
161 void dfl_fpga_port_ops_add(struct dfl_fpga_port_ops *ops);
162 void dfl_fpga_port_ops_del(struct dfl_fpga_port_ops *ops);
163 struct dfl_fpga_port_ops *dfl_fpga_port_ops_get(struct platform_device *pdev);
164 void dfl_fpga_port_ops_put(struct dfl_fpga_port_ops *ops);
165 int dfl_fpga_check_port_id(struct platform_device *pdev, void *pport_id);
168 * struct dfl_feature_id - dfl private feature id
170 * @id: unique dfl private feature id.
172 struct dfl_feature_id {
177 * struct dfl_feature_driver - dfl private feature driver
179 * @id_table: id_table for dfl private features supported by this driver.
180 * @ops: ops of this dfl private feature driver.
182 struct dfl_feature_driver {
183 const struct dfl_feature_id *id_table;
184 const struct dfl_feature_ops *ops;
188 * struct dfl_feature - sub feature of the feature devices
190 * @id: sub feature id.
191 * @resource_index: each sub feature has one mmio resource for its registers.
192 * this index is used to find its mmio resource from the
193 * feature dev (platform device)'s reources.
194 * @ioaddr: mapped mmio resource address.
195 * @ops: ops of this sub feature.
200 void __iomem *ioaddr;
201 const struct dfl_feature_ops *ops;
204 #define DEV_STATUS_IN_USE 0
206 #define FEATURE_DEV_ID_UNUSED (-1)
209 * struct dfl_feature_platform_data - platform data for feature devices
211 * @node: node to link feature devs to container device's port_dev_list.
212 * @lock: mutex to protect platform data.
213 * @cdev: cdev of feature dev.
214 * @dev: ptr to platform device linked with this platform data.
215 * @dfl_cdev: ptr to container device.
216 * @id: id used for this feature device.
217 * @disable_count: count for port disable.
218 * @num: number for sub features.
219 * @dev_status: dev status (e.g. DEV_STATUS_IN_USE).
220 * @private: ptr to feature dev private data.
221 * @features: sub features of this feature dev.
223 struct dfl_feature_platform_data {
224 struct list_head node;
227 struct platform_device *dev;
228 struct dfl_fpga_cdev *dfl_cdev;
230 unsigned int disable_count;
231 unsigned long dev_status;
234 struct dfl_feature features[0];
238 int dfl_feature_dev_use_begin(struct dfl_feature_platform_data *pdata)
240 /* Test and set IN_USE flags to ensure file is exclusively used */
241 if (test_and_set_bit_lock(DEV_STATUS_IN_USE, &pdata->dev_status))
248 void dfl_feature_dev_use_end(struct dfl_feature_platform_data *pdata)
250 clear_bit_unlock(DEV_STATUS_IN_USE, &pdata->dev_status);
254 void dfl_fpga_pdata_set_private(struct dfl_feature_platform_data *pdata,
257 pdata->private = private;
261 void *dfl_fpga_pdata_get_private(struct dfl_feature_platform_data *pdata)
263 return pdata->private;
266 struct dfl_feature_ops {
267 int (*init)(struct platform_device *pdev, struct dfl_feature *feature);
268 void (*uinit)(struct platform_device *pdev,
269 struct dfl_feature *feature);
270 long (*ioctl)(struct platform_device *pdev, struct dfl_feature *feature,
271 unsigned int cmd, unsigned long arg);
274 #define DFL_FPGA_FEATURE_DEV_FME "dfl-fme"
275 #define DFL_FPGA_FEATURE_DEV_PORT "dfl-port"
277 static inline int dfl_feature_platform_data_size(const int num)
279 return sizeof(struct dfl_feature_platform_data) +
280 num * sizeof(struct dfl_feature);
283 void dfl_fpga_dev_feature_uinit(struct platform_device *pdev);
284 int dfl_fpga_dev_feature_init(struct platform_device *pdev,
285 struct dfl_feature_driver *feature_drvs);
287 int dfl_fpga_dev_ops_register(struct platform_device *pdev,
288 const struct file_operations *fops,
289 struct module *owner);
290 void dfl_fpga_dev_ops_unregister(struct platform_device *pdev);
293 struct platform_device *dfl_fpga_inode_to_feature_dev(struct inode *inode)
295 struct dfl_feature_platform_data *pdata;
297 pdata = container_of(inode->i_cdev, struct dfl_feature_platform_data,
302 #define dfl_fpga_dev_for_each_feature(pdata, feature) \
303 for ((feature) = (pdata)->features; \
304 (feature) < (pdata)->features + (pdata)->num; (feature)++)
307 struct dfl_feature *dfl_get_feature_by_id(struct device *dev, u64 id)
309 struct dfl_feature_platform_data *pdata = dev_get_platdata(dev);
310 struct dfl_feature *feature;
312 dfl_fpga_dev_for_each_feature(pdata, feature)
313 if (feature->id == id)
320 void __iomem *dfl_get_feature_ioaddr_by_id(struct device *dev, u64 id)
322 struct dfl_feature *feature = dfl_get_feature_by_id(dev, id);
324 if (feature && feature->ioaddr)
325 return feature->ioaddr;
331 static inline bool is_dfl_feature_present(struct device *dev, u64 id)
333 return !!dfl_get_feature_ioaddr_by_id(dev, id);
337 struct device *dfl_fpga_pdata_to_parent(struct dfl_feature_platform_data *pdata)
339 return pdata->dev->dev.parent->parent;
342 static inline bool dfl_feature_is_fme(void __iomem *base)
344 u64 v = readq(base + DFH);
346 return (FIELD_GET(DFH_TYPE, v) == DFH_TYPE_FIU) &&
347 (FIELD_GET(DFH_ID, v) == DFH_ID_FIU_FME);
350 static inline bool dfl_feature_is_port(void __iomem *base)
352 u64 v = readq(base + DFH);
354 return (FIELD_GET(DFH_TYPE, v) == DFH_TYPE_FIU) &&
355 (FIELD_GET(DFH_ID, v) == DFH_ID_FIU_PORT);
359 * struct dfl_fpga_enum_info - DFL FPGA enumeration information
361 * @dev: parent device.
362 * @dfls: list of device feature lists.
364 struct dfl_fpga_enum_info {
366 struct list_head dfls;
370 * struct dfl_fpga_enum_dfl - DFL FPGA enumeration device feature list info
372 * @start: base address of this device feature list.
373 * @len: size of this device feature list.
374 * @ioaddr: mapped base address of this device feature list.
375 * @node: node in list of device feature lists.
377 struct dfl_fpga_enum_dfl {
378 resource_size_t start;
381 void __iomem *ioaddr;
383 struct list_head node;
386 struct dfl_fpga_enum_info *dfl_fpga_enum_info_alloc(struct device *dev);
387 int dfl_fpga_enum_info_add_dfl(struct dfl_fpga_enum_info *info,
388 resource_size_t start, resource_size_t len,
389 void __iomem *ioaddr);
390 void dfl_fpga_enum_info_free(struct dfl_fpga_enum_info *info);
393 * struct dfl_fpga_cdev - container device of DFL based FPGA
395 * @parent: parent device of this container device.
396 * @region: base fpga region.
397 * @fme_dev: FME feature device under this container device.
398 * @lock: mutex lock to protect the port device list.
399 * @port_dev_list: list of all port feature devices under this container device.
400 * @released_port_num: released port number under this container device.
402 struct dfl_fpga_cdev {
403 struct device *parent;
404 struct fpga_region *region;
405 struct device *fme_dev;
407 struct list_head port_dev_list;
408 int released_port_num;
411 struct dfl_fpga_cdev *
412 dfl_fpga_feature_devs_enumerate(struct dfl_fpga_enum_info *info);
413 void dfl_fpga_feature_devs_remove(struct dfl_fpga_cdev *cdev);
416 * need to drop the device reference with put_device() after use port platform
417 * device returned by __dfl_fpga_cdev_find_port and dfl_fpga_cdev_find_port
420 struct platform_device *
421 __dfl_fpga_cdev_find_port(struct dfl_fpga_cdev *cdev, void *data,
422 int (*match)(struct platform_device *, void *));
424 static inline struct platform_device *
425 dfl_fpga_cdev_find_port(struct dfl_fpga_cdev *cdev, void *data,
426 int (*match)(struct platform_device *, void *))
428 struct platform_device *pdev;
430 mutex_lock(&cdev->lock);
431 pdev = __dfl_fpga_cdev_find_port(cdev, data, match);
432 mutex_unlock(&cdev->lock);
437 int dfl_fpga_cdev_release_port(struct dfl_fpga_cdev *cdev, int port_id);
438 int dfl_fpga_cdev_assign_port(struct dfl_fpga_cdev *cdev, int port_id);
439 void dfl_fpga_cdev_config_ports_pf(struct dfl_fpga_cdev *cdev);
440 int dfl_fpga_cdev_config_ports_vf(struct dfl_fpga_cdev *cdev, int num_vf);
441 #endif /* __FPGA_DFL_H */