1 # SPDX-License-Identifier: GPL-2.0-only
3 # FPGA framework configuration
7 tristate "FPGA Configuration Framework"
9 Say Y here if you want support for configuring FPGAs from the
10 kernel. The FPGA framework adds a FPGA manager class and FPGA
15 config FPGA_MGR_SOCFPGA
16 tristate "Altera SOCFPGA FPGA Manager"
17 depends on ARCH_INTEL_SOCFPGA || COMPILE_TEST
19 FPGA manager driver support for Altera SOCFPGA.
21 config FPGA_MGR_SOCFPGA_A10
22 tristate "Altera SoCFPGA Arria10"
23 depends on ARCH_INTEL_SOCFPGA || COMPILE_TEST
26 FPGA manager driver support for Altera Arria10 SoCFPGA.
28 config ALTERA_PR_IP_CORE
29 tristate "Altera Partial Reconfiguration IP Core"
31 Core driver support for Altera Partial Reconfiguration IP component
33 config ALTERA_PR_IP_CORE_PLAT
34 tristate "Platform support of Altera Partial Reconfiguration IP Core"
35 depends on ALTERA_PR_IP_CORE && OF && HAS_IOMEM
37 Platform driver support for Altera Partial Reconfiguration IP
40 config FPGA_MGR_ALTERA_PS_SPI
41 tristate "Altera FPGA Passive Serial over SPI"
45 FPGA manager driver support for Altera Arria/Cyclone/Stratix
46 using the passive serial interface over SPI.
48 config FPGA_MGR_ALTERA_CVP
49 tristate "Altera CvP FPGA Manager"
52 FPGA manager driver support for Arria-V, Cyclone-V, Stratix-V,
53 Arria 10 and Stratix10 Altera FPGAs using the CvP interface over PCIe.
55 config FPGA_MGR_ZYNQ_FPGA
56 tristate "Xilinx Zynq FPGA"
57 depends on ARCH_ZYNQ || COMPILE_TEST
59 FPGA manager driver support for Xilinx Zynq FPGAs.
61 config FPGA_MGR_STRATIX10_SOC
62 tristate "Intel Stratix10 SoC FPGA Manager"
63 depends on (ARCH_INTEL_SOCFPGA && INTEL_STRATIX10_SERVICE)
65 FPGA manager driver support for the Intel Stratix10 SoC.
67 config FPGA_MGR_XILINX_SPI
68 tristate "Xilinx Configuration over Slave Serial (SPI)"
71 FPGA manager driver support for Xilinx FPGA configuration
72 over slave serial interface.
74 config FPGA_MGR_ICE40_SPI
75 tristate "Lattice iCE40 SPI"
78 FPGA manager driver support for Lattice iCE40 FPGAs over SPI.
80 config FPGA_MGR_MACHXO2_SPI
81 tristate "Lattice MachXO2 SPI"
84 FPGA manager driver support for Lattice MachXO2 configuration
85 over slave SPI interface.
87 config FPGA_MGR_TS73XX
88 tristate "Technologic Systems TS-73xx SBC FPGA Manager"
89 depends on ARCH_EP93XX && MACH_TS72XX
91 FPGA manager driver support for the Altera Cyclone II FPGA
92 present on the TS-73xx SBC boards.
95 tristate "FPGA Bridge Framework"
97 Say Y here if you want to support bridges connected between host
98 processors and FPGAs or between FPGAs.
100 config SOCFPGA_FPGA_BRIDGE
101 tristate "Altera SoCFPGA FPGA Bridges"
102 depends on ARCH_INTEL_SOCFPGA && FPGA_BRIDGE
104 Say Y to enable drivers for FPGA bridges for Altera SOCFPGA
107 config ALTERA_FREEZE_BRIDGE
108 tristate "Altera FPGA Freeze Bridge"
109 depends on FPGA_BRIDGE && HAS_IOMEM
111 Say Y to enable drivers for Altera FPGA Freeze bridges. A
112 freeze bridge is a bridge that exists in the FPGA fabric to
113 isolate one region of the FPGA from the busses while that
114 region is being reprogrammed.
116 config XILINX_PR_DECOUPLER
117 tristate "Xilinx LogiCORE PR Decoupler"
118 depends on FPGA_BRIDGE
121 Say Y to enable drivers for Xilinx LogiCORE PR Decoupler.
122 The PR Decoupler exists in the FPGA fabric to isolate one
123 region of the FPGA from the busses while that region is
124 being reprogrammed during partial reconfig.
127 tristate "FPGA Region"
128 depends on FPGA_BRIDGE
130 FPGA Region common code. A FPGA Region controls a FPGA Manager
131 and the FPGA Bridges associated with either a reconfigurable
132 region of an FPGA or a whole FPGA.
134 config OF_FPGA_REGION
135 tristate "FPGA Region Device Tree Overlay Support"
136 depends on OF && FPGA_REGION
138 Support for loading FPGA images by applying a Device Tree
142 tristate "FPGA Device Feature List (DFL) support"
147 Device Feature List (DFL) defines a feature list structure that
148 creates a linked list of feature headers within the MMIO space
149 to provide an extensible way of adding features for FPGA.
150 Driver can walk through the feature headers to enumerate feature
151 devices (e.g. FPGA Management Engine, Port and Accelerator
152 Function Unit) and their private features for target FPGA devices.
154 Select this option to enable common support for Field-Programmable
155 Gate Array (FPGA) solutions which implement Device Feature List.
156 It provides enumeration APIs and feature device infrastructure.
159 tristate "FPGA DFL FME Driver"
160 depends on FPGA_DFL && HWMON && PERF_EVENTS
162 The FPGA Management Engine (FME) is a feature device implemented
163 under Device Feature List (DFL) framework. Select this option to
164 enable the platform device driver for FME which implements all
165 FPGA platform level management features. There shall be one FME
166 per DFL based FPGA device.
168 config FPGA_DFL_FME_MGR
169 tristate "FPGA DFL FME Manager Driver"
170 depends on FPGA_DFL_FME && HAS_IOMEM
172 Say Y to enable FPGA Manager driver for FPGA Management Engine.
174 config FPGA_DFL_FME_BRIDGE
175 tristate "FPGA DFL FME Bridge Driver"
176 depends on FPGA_DFL_FME && HAS_IOMEM
178 Say Y to enable FPGA Bridge driver for FPGA Management Engine.
180 config FPGA_DFL_FME_REGION
181 tristate "FPGA DFL FME Region Driver"
182 depends on FPGA_DFL_FME && HAS_IOMEM
184 Say Y to enable FPGA Region driver for FPGA Management Engine.
187 tristate "FPGA DFL AFU Driver"
190 This is the driver for FPGA Accelerated Function Unit (AFU) which
191 implements AFU and Port management features. A User AFU connects
192 to the FPGA infrastructure via a Port. There may be more than one
193 Port/AFU per DFL based FPGA device.
195 config FPGA_DFL_NIOS_INTEL_PAC_N3000
196 tristate "FPGA DFL NIOS Driver for Intel PAC N3000"
200 This is the driver for the N3000 Nios private feature on Intel
201 PAC (Programmable Acceleration Card) N3000. It communicates
202 with the embedded Nios processor to configure the retimers on
203 the card. It also instantiates the SPI master (spi-altera) for
204 the card's BMC (Board Management Controller).
207 tristate "FPGA DFL PCIe Device Driver"
208 depends on PCI && FPGA_DFL
210 Select this option to enable PCIe driver for PCIe-based
211 Field-Programmable Gate Array (FPGA) solutions which implement
212 the Device Feature List (DFL). This driver provides interfaces
213 for userspace applications to configure, enumerate, open and access
214 FPGA accelerators on the FPGA DFL devices, enables system level
215 management functions such as FPGA partial reconfiguration, power
216 management and virtualization with DFL framework and DFL feature
219 To compile this as a module, choose M here.
221 config FPGA_MGR_ZYNQMP_FPGA
222 tristate "Xilinx ZynqMP FPGA"
223 depends on ZYNQMP_FIRMWARE || (!ZYNQMP_FIRMWARE && COMPILE_TEST)
225 FPGA manager driver support for Xilinx ZynqMP FPGAs.
226 This driver uses the processor configuration port(PCAP)
227 to configure the programmable logic(PL) through PS