drivers/edac/sb_edac.c

   1 /* Intel Sandy Bridge -EN/-EP/-EX Memory Controller kernel module
   2  *
   3  * This driver supports the memory controllers found on the Intel
   4  * processor family Sandy Bridge.
   5  *
   6  * This file may be distributed under the terms of the
   7  * GNU General Public License version 2 only.
   8  *
   9  * Copyright (c) 2011 by:
  10  *       Mauro Carvalho Chehab
  11  */
  12
  13 #include <linux/module.h>
  14 #include <linux/init.h>
  15 #include <linux/pci.h>
  16 #include <linux/pci_ids.h>
  17 #include <linux/slab.h>
  18 #include <linux/delay.h>
  19 #include <linux/edac.h>
  20 #include <linux/mmzone.h>
  21 #include <linux/smp.h>
  22 #include <linux/bitmap.h>
  23 #include <linux/math64.h>
  24 #include <linux/mod_devicetable.h>
  25 #include <asm/cpu_device_id.h>
  26 #include <asm/processor.h>
  27 #include <asm/mce.h>
  28
  29 #include "edac_core.h"
  30
  31 /* Static vars */
  32 static LIST_HEAD(sbridge_edac_list);
  33
  34 /*
  35  * Alter this version for the module when modifications are made
  36  */
  37 #define SBRIDGE_REVISION    " Ver: 1.1.1 "
  38 #define EDAC_MOD_STR      "sbridge_edac"
  39
  40 /*
  41  * Debug macros
  42  */
  43 #define sbridge_printk(level, fmt, arg...)                      \
  44         edac_printk(level, "sbridge", fmt, ##arg)
  45
  46 #define sbridge_mc_printk(mci, level, fmt, arg...)              \
  47         edac_mc_chipset_printk(mci, level, "sbridge", fmt, ##arg)
  48
  49 /*
  50  * Get a bit field at register value <v>, from bit <lo> to bit <hi>
  51  */
  52 #define GET_BITFIELD(v, lo, hi) \
  53         (((v) & GENMASK_ULL(hi, lo)) >> (lo))
  54
  55 /* Devices 12 Function 6, Offsets 0x80 to 0xcc */
  56 static const u32 sbridge_dram_rule[] = {
  57         0x80, 0x88, 0x90, 0x98, 0xa0,
  58         0xa8, 0xb0, 0xb8, 0xc0, 0xc8,
  59 };
  60
  61 static const u32 ibridge_dram_rule[] = {
  62         0x60, 0x68, 0x70, 0x78, 0x80,
  63         0x88, 0x90, 0x98, 0xa0, 0xa8,
  64         0xb0, 0xb8, 0xc0, 0xc8, 0xd0,
  65         0xd8, 0xe0, 0xe8, 0xf0, 0xf8,
  66 };
  67
  68 static const u32 knl_dram_rule[] = {
  69         0x60, 0x68, 0x70, 0x78, 0x80, /* 0-4 */
  70         0x88, 0x90, 0x98, 0xa0, 0xa8, /* 5-9 */
  71         0xb0, 0xb8, 0xc0, 0xc8, 0xd0, /* 10-14 */
  72         0xd8, 0xe0, 0xe8, 0xf0, 0xf8, /* 15-19 */
  73         0x100, 0x108, 0x110, 0x118,   /* 20-23 */
  74 };
  75
  76 #define DRAM_RULE_ENABLE(reg)   GET_BITFIELD(reg, 0,  0)
  77 #define A7MODE(reg)             GET_BITFIELD(reg, 26, 26)
  78
  79 static char *show_dram_attr(u32 attr)
  80 {
  81         switch (attr) {
  82                 case 0:
  83                         return "DRAM";
  84                 case 1:
  85                         return "MMCFG";
  86                 case 2:
  87                         return "NXM";
  88                 default:
  89                         return "unknown";
  90         }
  91 }
  92
  93 static const u32 sbridge_interleave_list[] = {
  94         0x84, 0x8c, 0x94, 0x9c, 0xa4,
  95         0xac, 0xb4, 0xbc, 0xc4, 0xcc,
  96 };
  97
  98 static const u32 ibridge_interleave_list[] = {
  99         0x64, 0x6c, 0x74, 0x7c, 0x84,
 100         0x8c, 0x94, 0x9c, 0xa4, 0xac,
 101         0xb4, 0xbc, 0xc4, 0xcc, 0xd4,
 102         0xdc, 0xe4, 0xec, 0xf4, 0xfc,
 103 };
 104
 105 static const u32 knl_interleave_list[] = {
 106         0x64, 0x6c, 0x74, 0x7c, 0x84, /* 0-4 */
 107         0x8c, 0x94, 0x9c, 0xa4, 0xac, /* 5-9 */
 108         0xb4, 0xbc, 0xc4, 0xcc, 0xd4, /* 10-14 */
 109         0xdc, 0xe4, 0xec, 0xf4, 0xfc, /* 15-19 */
 110         0x104, 0x10c, 0x114, 0x11c,   /* 20-23 */
 111 };
 112
 113 struct interleave_pkg {
 114         unsigned char start;
 115         unsigned char end;
 116 };
 117
 118 static const struct interleave_pkg sbridge_interleave_pkg[] = {
 119         { 0, 2 },
 120         { 3, 5 },
 121         { 8, 10 },
 122         { 11, 13 },
 123         { 16, 18 },
 124         { 19, 21 },
 125         { 24, 26 },
 126         { 27, 29 },
 127 };
 128
 129 static const struct interleave_pkg ibridge_interleave_pkg[] = {
 130         { 0, 3 },
 131         { 4, 7 },
 132         { 8, 11 },
 133         { 12, 15 },
 134         { 16, 19 },
 135         { 20, 23 },
 136         { 24, 27 },
 137         { 28, 31 },
 138 };
 139
 140 static inline int sad_pkg(const struct interleave_pkg *table, u32 reg,
 141                           int interleave)
 142 {
 143         return GET_BITFIELD(reg, table[interleave].start,
 144                             table[interleave].end);
 145 }
 146
 147 /* Devices 12 Function 7 */
 148
 149 #define TOLM            0x80
 150 #define TOHM            0x84
 151 #define HASWELL_TOLM    0xd0
 152 #define HASWELL_TOHM_0  0xd4
 153 #define HASWELL_TOHM_1  0xd8
 154 #define KNL_TOLM        0xd0
 155 #define KNL_TOHM_0      0xd4
 156 #define KNL_TOHM_1      0xd8
 157
 158 #define GET_TOLM(reg)           ((GET_BITFIELD(reg, 0,  3) << 28) | 0x3ffffff)
 159 #define GET_TOHM(reg)           ((GET_BITFIELD(reg, 0, 20) << 25) | 0x3ffffff)
 160
 161 /* Device 13 Function 6 */
 162
 163 #define SAD_TARGET      0xf0
 164
 165 #define SOURCE_ID(reg)          GET_BITFIELD(reg, 9, 11)
 166
 167 #define SOURCE_ID_KNL(reg)      GET_BITFIELD(reg, 12, 14)
 168
 169 #define SAD_CONTROL     0xf4
 170
 171 /* Device 14 function 0 */
 172
 173 static const u32 tad_dram_rule[] = {
 174         0x40, 0x44, 0x48, 0x4c,
 175         0x50, 0x54, 0x58, 0x5c,
 176         0x60, 0x64, 0x68, 0x6c,
 177 };
 178 #define MAX_TAD ARRAY_SIZE(tad_dram_rule)
 179
 180 #define TAD_LIMIT(reg)          ((GET_BITFIELD(reg, 12, 31) << 26) | 0x3ffffff)
 181 #define TAD_SOCK(reg)           GET_BITFIELD(reg, 10, 11)
 182 #define TAD_CH(reg)             GET_BITFIELD(reg,  8,  9)
 183 #define TAD_TGT3(reg)           GET_BITFIELD(reg,  6,  7)
 184 #define TAD_TGT2(reg)           GET_BITFIELD(reg,  4,  5)
 185 #define TAD_TGT1(reg)           GET_BITFIELD(reg,  2,  3)
 186 #define TAD_TGT0(reg)           GET_BITFIELD(reg,  0,  1)
 187
 188 /* Device 15, function 0 */
 189
 190 #define MCMTR                   0x7c
 191 #define KNL_MCMTR               0x624
 192
 193 #define IS_ECC_ENABLED(mcmtr)           GET_BITFIELD(mcmtr, 2, 2)
 194 #define IS_LOCKSTEP_ENABLED(mcmtr)      GET_BITFIELD(mcmtr, 1, 1)
 195 #define IS_CLOSE_PG(mcmtr)              GET_BITFIELD(mcmtr, 0, 0)
 196
 197 /* Device 15, function 1 */
 198
 199 #define RASENABLES              0xac
 200 #define IS_MIRROR_ENABLED(reg)          GET_BITFIELD(reg, 0, 0)
 201
 202 /* Device 15, functions 2-5 */
 203
 204 static const int mtr_regs[] = {
 205         0x80, 0x84, 0x88,
 206 };
 207
 208 static const int knl_mtr_reg = 0xb60;
 209
 210 #define RANK_DISABLE(mtr)               GET_BITFIELD(mtr, 16, 19)
 211 #define IS_DIMM_PRESENT(mtr)            GET_BITFIELD(mtr, 14, 14)
 212 #define RANK_CNT_BITS(mtr)              GET_BITFIELD(mtr, 12, 13)
 213 #define RANK_WIDTH_BITS(mtr)            GET_BITFIELD(mtr, 2, 4)
 214 #define COL_WIDTH_BITS(mtr)             GET_BITFIELD(mtr, 0, 1)
 215
 216 static const u32 tad_ch_nilv_offset[] = {
 217         0x90, 0x94, 0x98, 0x9c,
 218         0xa0, 0xa4, 0xa8, 0xac,
 219         0xb0, 0xb4, 0xb8, 0xbc,
 220 };
 221 #define CHN_IDX_OFFSET(reg)             GET_BITFIELD(reg, 28, 29)
 222 #define TAD_OFFSET(reg)                 (GET_BITFIELD(reg,  6, 25) << 26)
 223
 224 static const u32 rir_way_limit[] = {
 225         0x108, 0x10c, 0x110, 0x114, 0x118,
 226 };
 227 #define MAX_RIR_RANGES ARRAY_SIZE(rir_way_limit)
 228
 229 #define IS_RIR_VALID(reg)       GET_BITFIELD(reg, 31, 31)
 230 #define RIR_WAY(reg)            GET_BITFIELD(reg, 28, 29)
 231
 232 #define MAX_RIR_WAY     8
 233
 234 static const u32 rir_offset[MAX_RIR_RANGES][MAX_RIR_WAY] = {
 235         { 0x120, 0x124, 0x128, 0x12c, 0x130, 0x134, 0x138, 0x13c },
 236         { 0x140, 0x144, 0x148, 0x14c, 0x150, 0x154, 0x158, 0x15c },
 237         { 0x160, 0x164, 0x168, 0x16c, 0x170, 0x174, 0x178, 0x17c },
 238         { 0x180, 0x184, 0x188, 0x18c, 0x190, 0x194, 0x198, 0x19c },
 239         { 0x1a0, 0x1a4, 0x1a8, 0x1ac, 0x1b0, 0x1b4, 0x1b8, 0x1bc },
 240 };
 241
 242 #define RIR_RNK_TGT(reg)                GET_BITFIELD(reg, 16, 19)
 243 #define RIR_OFFSET(reg)         GET_BITFIELD(reg,  2, 14)
 244
 245 /* Device 16, functions 2-7 */
 246
 247 /*
 248  * FIXME: Implement the error count reads directly
 249  */
 250
 251 static const u32 correrrcnt[] = {
 252         0x104, 0x108, 0x10c, 0x110,
 253 };
 254
 255 #define RANK_ODD_OV(reg)                GET_BITFIELD(reg, 31, 31)
 256 #define RANK_ODD_ERR_CNT(reg)           GET_BITFIELD(reg, 16, 30)
 257 #define RANK_EVEN_OV(reg)               GET_BITFIELD(reg, 15, 15)
 258 #define RANK_EVEN_ERR_CNT(reg)          GET_BITFIELD(reg,  0, 14)
 259
 260 static const u32 correrrthrsld[] = {
 261         0x11c, 0x120, 0x124, 0x128,
 262 };
 263
 264 #define RANK_ODD_ERR_THRSLD(reg)        GET_BITFIELD(reg, 16, 30)
 265 #define RANK_EVEN_ERR_THRSLD(reg)       GET_BITFIELD(reg,  0, 14)
 266
 267
 268 /* Device 17, function 0 */
 269
 270 #define SB_RANK_CFG_A           0x0328
 271
 272 #define IB_RANK_CFG_A           0x0320
 273
 274 /*
 275  * sbridge structs
 276  */
 277
 278 #define NUM_CHANNELS            8       /* 2MC per socket, four chan per MC */
 279 #define MAX_DIMMS               3       /* Max DIMMS per channel */
 280 #define KNL_MAX_CHAS            38      /* KNL max num. of Cache Home Agents */
 281 #define KNL_MAX_CHANNELS        6       /* KNL max num. of PCI channels */
 282 #define KNL_MAX_EDCS            8       /* Embedded DRAM controllers */
 283 #define CHANNEL_UNSPECIFIED     0xf     /* Intel IA32 SDM 15-14 */
 284
 285 enum type {
 286         SANDY_BRIDGE,
 287         IVY_BRIDGE,
 288         HASWELL,
 289         BROADWELL,
 290         KNIGHTS_LANDING,
 291 };
 292
 293 struct sbridge_pvt;
 294 struct sbridge_info {
 295         enum type       type;
 296         u32             mcmtr;
 297         u32             rankcfgr;
 298         u64             (*get_tolm)(struct sbridge_pvt *pvt);
 299         u64             (*get_tohm)(struct sbridge_pvt *pvt);
 300         u64             (*rir_limit)(u32 reg);
 301         u64             (*sad_limit)(u32 reg);
 302         u32             (*interleave_mode)(u32 reg);
 303         char*           (*show_interleave_mode)(u32 reg);
 304         u32             (*dram_attr)(u32 reg);
 305         const u32       *dram_rule;
 306         const u32       *interleave_list;
 307         const struct interleave_pkg *interleave_pkg;
 308         u8              max_sad;
 309         u8              max_interleave;
 310         u8              (*get_node_id)(struct sbridge_pvt *pvt);
 311         enum mem_type   (*get_memory_type)(struct sbridge_pvt *pvt);
 312         enum dev_type   (*get_width)(struct sbridge_pvt *pvt, u32 mtr);
 313         struct pci_dev  *pci_vtd;
 314 };
 315
 316 struct sbridge_channel {
 317         u32             ranks;
 318         u32             dimms;
 319 };
 320
 321 struct pci_id_descr {
 322         int                     dev_id;
 323         int                     optional;
 324 };
 325
 326 struct pci_id_table {
 327         const struct pci_id_descr       *descr;
 328         int                             n_devs;
 329 };
 330
 331 struct sbridge_dev {
 332         struct list_head        list;
 333         u8                      bus, mc;
 334         u8                      node_id, source_id;
 335         struct pci_dev          **pdev;
 336         int                     n_devs;
 337         struct mem_ctl_info     *mci;
 338 };
 339
 340 struct knl_pvt {
 341         struct pci_dev          *pci_cha[KNL_MAX_CHAS];
 342         struct pci_dev          *pci_channel[KNL_MAX_CHANNELS];
 343         struct pci_dev          *pci_mc0;
 344         struct pci_dev          *pci_mc1;
 345         struct pci_dev          *pci_mc0_misc;
 346         struct pci_dev          *pci_mc1_misc;
 347         struct pci_dev          *pci_mc_info; /* tolm, tohm */
 348 };
 349
 350 struct sbridge_pvt {
 351         struct pci_dev          *pci_ta, *pci_ddrio, *pci_ras;
 352         struct pci_dev          *pci_sad0, *pci_sad1;
 353         struct pci_dev          *pci_ha0, *pci_ha1;
 354         struct pci_dev          *pci_br0, *pci_br1;
 355         struct pci_dev          *pci_ha1_ta;
 356         struct pci_dev          *pci_tad[NUM_CHANNELS];
 357
 358         struct sbridge_dev      *sbridge_dev;
 359
 360         struct sbridge_info     info;
 361         struct sbridge_channel  channel[NUM_CHANNELS];
 362
 363         /* Memory type detection */
 364         bool                    is_mirrored, is_lockstep, is_close_pg;
 365
 366         /* Memory description */
 367         u64                     tolm, tohm;
 368         struct knl_pvt knl;
 369 };
 370
 371 #define PCI_DESCR(device_id, opt)       \
 372         .dev_id = (device_id),          \
 373         .optional = opt
 374
 375 static const struct pci_id_descr pci_dev_descr_sbridge[] = {
 376                 /* Processor Home Agent */
 377         { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_HA0, 0)     },
 378
 379                 /* Memory controller */
 380         { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TA, 0)      },
 381         { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_RAS, 0)     },
 382         { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD0, 0)    },
 383         { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD1, 0)    },
 384         { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD2, 0)    },
 385         { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD3, 0)    },
 386         { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_DDRIO, 1)   },
 387
 388                 /* System Address Decoder */
 389         { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_SAD0, 0)        },
 390         { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_SAD1, 0)        },
 391
 392                 /* Broadcast Registers */
 393         { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_BR, 0)          },
 394 };
 395
 396 #define PCI_ID_TABLE_ENTRY(A) { .descr=A, .n_devs = ARRAY_SIZE(A) }
 397 static const struct pci_id_table pci_dev_descr_sbridge_table[] = {
 398         PCI_ID_TABLE_ENTRY(pci_dev_descr_sbridge),
 399         {0,}                    /* 0 terminated list. */
 400 };
 401
 402 /* This changes depending if 1HA or 2HA:
 403  * 1HA:
 404  *      0x0eb8 (17.0) is DDRIO0
 405  * 2HA:
 406  *      0x0ebc (17.4) is DDRIO0
 407  */
 408 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_1HA_DDRIO0      0x0eb8
 409 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_2HA_DDRIO0      0x0ebc
 410
 411 /* pci ids */
 412 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0             0x0ea0
 413 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TA          0x0ea8
 414 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_RAS         0x0e71
 415 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD0        0x0eaa
 416 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD1        0x0eab
 417 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD2        0x0eac
 418 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD3        0x0ead
 419 #define PCI_DEVICE_ID_INTEL_IBRIDGE_SAD                 0x0ec8
 420 #define PCI_DEVICE_ID_INTEL_IBRIDGE_BR0                 0x0ec9
 421 #define PCI_DEVICE_ID_INTEL_IBRIDGE_BR1                 0x0eca
 422 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1             0x0e60
 423 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TA          0x0e68
 424 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_RAS         0x0e79
 425 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD0        0x0e6a
 426 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD1        0x0e6b
 427 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD2        0x0e6c
 428 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD3        0x0e6d
 429
 430 static const struct pci_id_descr pci_dev_descr_ibridge[] = {
 431                 /* Processor Home Agent */
 432         { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0, 0)             },
 433
 434                 /* Memory controller */
 435         { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TA, 0)          },
 436         { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_RAS, 0)         },
 437         { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD0, 0)        },
 438         { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD1, 0)        },
 439         { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD2, 0)        },
 440         { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD3, 0)        },
 441
 442                 /* System Address Decoder */
 443         { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_SAD, 0)                 },
 444
 445                 /* Broadcast Registers */
 446         { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_BR0, 1)                 },
 447         { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_BR1, 0)                 },
 448
 449                 /* Optional, mode 2HA */
 450         { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1, 1)             },
 451 #if 0
 452         { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TA, 1)  },
 453         { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_RAS, 1) },
 454 #endif
 455         { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD0, 1)        },
 456         { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD1, 1)        },
 457         { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD2, 1)        },
 458         { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD3, 1)        },
 459
 460         { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_1HA_DDRIO0, 1)      },
 461         { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_2HA_DDRIO0, 1)      },
 462 };
 463
 464 static const struct pci_id_table pci_dev_descr_ibridge_table[] = {
 465         PCI_ID_TABLE_ENTRY(pci_dev_descr_ibridge),
 466         {0,}                    /* 0 terminated list. */
 467 };
 468
 469 /* Haswell support */
 470 /* EN processor:
 471  *      - 1 IMC
 472  *      - 3 DDR3 channels, 2 DPC per channel
 473  * EP processor:
 474  *      - 1 or 2 IMC
 475  *      - 4 DDR4 channels, 3 DPC per channel
 476  * EP 4S processor:
 477  *      - 2 IMC
 478  *      - 4 DDR4 channels, 3 DPC per channel
 479  * EX processor:
 480  *      - 2 IMC
 481  *      - each IMC interfaces with a SMI 2 channel
 482  *      - each SMI channel interfaces with a scalable memory buffer
 483  *      - each scalable memory buffer supports 4 DDR3/DDR4 channels, 3 DPC
 484  */
 485 #define HASWELL_DDRCRCLKCONTROLS 0xa10 /* Ditto on Broadwell */
 486 #define HASWELL_HASYSDEFEATURE2 0x84
 487 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_VTD_MISC 0x2f28
 488 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0     0x2fa0
 489 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1     0x2f60
 490 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TA  0x2fa8
 491 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_THERMAL 0x2f71
 492 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TA  0x2f68
 493 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_THERMAL 0x2f79
 494 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_CBO_SAD0 0x2ffc
 495 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_CBO_SAD1 0x2ffd
 496 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD0 0x2faa
 497 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD1 0x2fab
 498 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD2 0x2fac
 499 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD3 0x2fad
 500 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD0 0x2f6a
 501 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD1 0x2f6b
 502 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD2 0x2f6c
 503 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD3 0x2f6d
 504 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO0 0x2fbd
 505 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO1 0x2fbf
 506 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO2 0x2fb9
 507 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO3 0x2fbb
 508 static const struct pci_id_descr pci_dev_descr_haswell[] = {
 509         /* first item must be the HA */
 510         { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0, 0)             },
 511
 512         { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_CBO_SAD0, 0)        },
 513         { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_CBO_SAD1, 0)        },
 514
 515         { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1, 1)             },
 516
 517         { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TA, 0)          },
 518         { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_THERMAL, 0)     },
 519         { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD0, 0)        },
 520         { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD1, 0)        },
 521         { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD2, 1)        },
 522         { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD3, 1)        },
 523
 524         { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO0, 1)          },
 525         { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO1, 1)          },
 526         { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO2, 1)          },
 527         { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO3, 1)          },
 528
 529         { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TA, 1)          },
 530         { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_THERMAL, 1)     },
 531         { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD0, 1)        },
 532         { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD1, 1)        },
 533         { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD2, 1)        },
 534         { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD3, 1)        },
 535 };
 536
 537 static const struct pci_id_table pci_dev_descr_haswell_table[] = {
 538         PCI_ID_TABLE_ENTRY(pci_dev_descr_haswell),
 539         {0,}                    /* 0 terminated list. */
 540 };
 541
 542 /* Knight's Landing Support */
 543 /*
 544  * KNL's memory channels are swizzled between memory controllers.
 545  * MC0 is mapped to CH3,5,6 and MC1 is mapped to CH0,1,2
 546  */
 547 #define knl_channel_remap(channel) ((channel + 3) % 6)
 548
 549 /* Memory controller, TAD tables, error injection - 2-8-0, 2-9-0 (2 of these) */
 550 #define PCI_DEVICE_ID_INTEL_KNL_IMC_MC       0x7840
 551 /* DRAM channel stuff; bank addrs, dimmmtr, etc.. 2-8-2 - 2-9-4 (6 of these) */
 552 #define PCI_DEVICE_ID_INTEL_KNL_IMC_CHANNEL  0x7843
 553 /* kdrwdbu TAD limits/offsets, MCMTR - 2-10-1, 2-11-1 (2 of these) */
 554 #define PCI_DEVICE_ID_INTEL_KNL_IMC_TA       0x7844
 555 /* CHA broadcast registers, dram rules - 1-29-0 (1 of these) */
 556 #define PCI_DEVICE_ID_INTEL_KNL_IMC_SAD0     0x782a
 557 /* SAD target - 1-29-1 (1 of these) */
 558 #define PCI_DEVICE_ID_INTEL_KNL_IMC_SAD1     0x782b
 559 /* Caching / Home Agent */
 560 #define PCI_DEVICE_ID_INTEL_KNL_IMC_CHA      0x782c
 561 /* Device with TOLM and TOHM, 0-5-0 (1 of these) */
 562 #define PCI_DEVICE_ID_INTEL_KNL_IMC_TOLHM    0x7810
 563
 564 /*
 565  * KNL differs from SB, IB, and Haswell in that it has multiple
 566  * instances of the same device with the same device ID, so we handle that
 567  * by creating as many copies in the table as we expect to find.
 568  * (Like device ID must be grouped together.)
 569  */
 570
 571 static const struct pci_id_descr pci_dev_descr_knl[] = {
 572         [0]         = { PCI_DESCR(PCI_DEVICE_ID_INTEL_KNL_IMC_SAD0, 0) },
 573         [1]         = { PCI_DESCR(PCI_DEVICE_ID_INTEL_KNL_IMC_SAD1, 0) },
 574         [2 ... 3]   = { PCI_DESCR(PCI_DEVICE_ID_INTEL_KNL_IMC_MC, 0)},
 575         [4 ... 41]  = { PCI_DESCR(PCI_DEVICE_ID_INTEL_KNL_IMC_CHA, 0) },
 576         [42 ... 47] = { PCI_DESCR(PCI_DEVICE_ID_INTEL_KNL_IMC_CHANNEL, 0) },
 577         [48]        = { PCI_DESCR(PCI_DEVICE_ID_INTEL_KNL_IMC_TA, 0) },
 578         [49]        = { PCI_DESCR(PCI_DEVICE_ID_INTEL_KNL_IMC_TOLHM, 0) },
 579 };
 580
 581 static const struct pci_id_table pci_dev_descr_knl_table[] = {
 582         PCI_ID_TABLE_ENTRY(pci_dev_descr_knl),
 583         {0,}
 584 };
 585
 586 /*
 587  * Broadwell support
 588  *
 589  * DE processor:
 590  *      - 1 IMC
 591  *      - 2 DDR3 channels, 2 DPC per channel
 592  * EP processor:
 593  *      - 1 or 2 IMC
 594  *      - 4 DDR4 channels, 3 DPC per channel
 595  * EP 4S processor:
 596  *      - 2 IMC
 597  *      - 4 DDR4 channels, 3 DPC per channel
 598  * EX processor:
 599  *      - 2 IMC
 600  *      - each IMC interfaces with a SMI 2 channel
 601  *      - each SMI channel interfaces with a scalable memory buffer
 602  *      - each scalable memory buffer supports 4 DDR3/DDR4 channels, 3 DPC
 603  */
 604 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_VTD_MISC 0x6f28
 605 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0   0x6fa0
 606 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1   0x6f60
 607 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TA        0x6fa8
 608 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_THERMAL 0x6f71
 609 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TA        0x6f68
 610 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_THERMAL 0x6f79
 611 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_CBO_SAD0 0x6ffc
 612 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_CBO_SAD1 0x6ffd
 613 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD0 0x6faa
 614 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD1 0x6fab
 615 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD2 0x6fac
 616 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD3 0x6fad
 617 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD0 0x6f6a
 618 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD1 0x6f6b
 619 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD2 0x6f6c
 620 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD3 0x6f6d
 621 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_DDRIO0 0x6faf
 622
 623 static const struct pci_id_descr pci_dev_descr_broadwell[] = {
 624         /* first item must be the HA */
 625         { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0, 0)           },
 626
 627         { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_CBO_SAD0, 0)      },
 628         { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_CBO_SAD1, 0)      },
 629
 630         { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1, 1)           },
 631
 632         { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TA, 0)        },
 633         { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_THERMAL, 0)   },
 634         { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD0, 0)      },
 635         { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD1, 0)      },
 636         { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD2, 1)      },
 637         { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD3, 1)      },
 638
 639         { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_DDRIO0, 1)        },
 640
 641         { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TA, 1)        },
 642         { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_THERMAL, 1)   },
 643         { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD0, 1)      },
 644         { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD1, 1)      },
 645         { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD2, 1)      },
 646         { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD3, 1)      },
 647 };
 648
 649 static const struct pci_id_table pci_dev_descr_broadwell_table[] = {
 650         PCI_ID_TABLE_ENTRY(pci_dev_descr_broadwell),
 651         {0,}                    /* 0 terminated list. */
 652 };
 653
 654
 655 /****************************************************************************
 656                         Ancillary status routines
 657  ****************************************************************************/
 658
 659 static inline int numrank(enum type type, u32 mtr)
 660 {
 661         int ranks = (1 << RANK_CNT_BITS(mtr));
 662         int max = 4;
 663
 664         if (type == HASWELL || type == BROADWELL || type == KNIGHTS_LANDING)
 665                 max = 8;
 666
 667         if (ranks > max) {
 668                 edac_dbg(0, "Invalid number of ranks: %d (max = %i) raw value = %x (%04x)\n",
 669                          ranks, max, (unsigned int)RANK_CNT_BITS(mtr), mtr);
 670                 return -EINVAL;
 671         }
 672
 673         return ranks;
 674 }
 675
 676 static inline int numrow(u32 mtr)
 677 {
 678         int rows = (RANK_WIDTH_BITS(mtr) + 12);
 679
 680         if (rows < 13 || rows > 18) {
 681                 edac_dbg(0, "Invalid number of rows: %d (should be between 14 and 17) raw value = %x (%04x)\n",
 682                          rows, (unsigned int)RANK_WIDTH_BITS(mtr), mtr);
 683                 return -EINVAL;
 684         }
 685
 686         return 1 << rows;
 687 }
 688
 689 static inline int numcol(u32 mtr)
 690 {
 691         int cols = (COL_WIDTH_BITS(mtr) + 10);
 692
 693         if (cols > 12) {
 694                 edac_dbg(0, "Invalid number of cols: %d (max = 4) raw value = %x (%04x)\n",
 695                          cols, (unsigned int)COL_WIDTH_BITS(mtr), mtr);
 696                 return -EINVAL;
 697         }
 698
 699         return 1 << cols;
 700 }
 701
 702 static struct sbridge_dev *get_sbridge_dev(u8 bus, int multi_bus)
 703 {
 704         struct sbridge_dev *sbridge_dev;
 705
 706         /*
 707          * If we have devices scattered across several busses that pertain
 708          * to the same memory controller, we'll lump them all together.
 709          */
 710         if (multi_bus) {
 711                 return list_first_entry_or_null(&sbridge_edac_list,
 712                                 struct sbridge_dev, list);
 713         }
 714
 715         list_for_each_entry(sbridge_dev, &sbridge_edac_list, list) {
 716                 if (sbridge_dev->bus == bus)
 717                         return sbridge_dev;
 718         }
 719
 720         return NULL;
 721 }
 722
 723 static struct sbridge_dev *alloc_sbridge_dev(u8 bus,
 724                                            const struct pci_id_table *table)
 725 {
 726         struct sbridge_dev *sbridge_dev;
 727
 728         sbridge_dev = kzalloc(sizeof(*sbridge_dev), GFP_KERNEL);
 729         if (!sbridge_dev)
 730                 return NULL;
 731
 732         sbridge_dev->pdev = kzalloc(sizeof(*sbridge_dev->pdev) * table->n_devs,
 733                                    GFP_KERNEL);
 734         if (!sbridge_dev->pdev) {
 735                 kfree(sbridge_dev);
 736                 return NULL;
 737         }
 738
 739         sbridge_dev->bus = bus;
 740         sbridge_dev->n_devs = table->n_devs;
 741         list_add_tail(&sbridge_dev->list, &sbridge_edac_list);
 742
 743         return sbridge_dev;
 744 }
 745
 746 static void free_sbridge_dev(struct sbridge_dev *sbridge_dev)
 747 {
 748         list_del(&sbridge_dev->list);
 749         kfree(sbridge_dev->pdev);
 750         kfree(sbridge_dev);
 751 }
 752
 753 static u64 sbridge_get_tolm(struct sbridge_pvt *pvt)
 754 {
 755         u32 reg;
 756
 757         /* Address range is 32:28 */
 758         pci_read_config_dword(pvt->pci_sad1, TOLM, &reg);
 759         return GET_TOLM(reg);
 760 }
 761
 762 static u64 sbridge_get_tohm(struct sbridge_pvt *pvt)
 763 {
 764         u32 reg;
 765
 766         pci_read_config_dword(pvt->pci_sad1, TOHM, &reg);
 767         return GET_TOHM(reg);
 768 }
 769
 770 static u64 ibridge_get_tolm(struct sbridge_pvt *pvt)
 771 {
 772         u32 reg;
 773
 774         pci_read_config_dword(pvt->pci_br1, TOLM, &reg);
 775
 776         return GET_TOLM(reg);
 777 }
 778
 779 static u64 ibridge_get_tohm(struct sbridge_pvt *pvt)
 780 {
 781         u32 reg;
 782
 783         pci_read_config_dword(pvt->pci_br1, TOHM, &reg);
 784
 785         return GET_TOHM(reg);
 786 }
 787
 788 static u64 rir_limit(u32 reg)
 789 {
 790         return ((u64)GET_BITFIELD(reg,  1, 10) << 29) | 0x1fffffff;
 791 }
 792
 793 static u64 sad_limit(u32 reg)
 794 {
 795         return (GET_BITFIELD(reg, 6, 25) << 26) | 0x3ffffff;
 796 }
 797
 798 static u32 interleave_mode(u32 reg)
 799 {
 800         return GET_BITFIELD(reg, 1, 1);
 801 }
 802
 803 char *show_interleave_mode(u32 reg)
 804 {
 805         return interleave_mode(reg) ? "8:6" : "[8:6]XOR[18:16]";
 806 }
 807
 808 static u32 dram_attr(u32 reg)
 809 {
 810         return GET_BITFIELD(reg, 2, 3);
 811 }
 812
 813 static u64 knl_sad_limit(u32 reg)
 814 {
 815         return (GET_BITFIELD(reg, 7, 26) << 26) | 0x3ffffff;
 816 }
 817
 818 static u32 knl_interleave_mode(u32 reg)
 819 {
 820         return GET_BITFIELD(reg, 1, 2);
 821 }
 822
 823 static char *knl_show_interleave_mode(u32 reg)
 824 {
 825         char *s;
 826
 827         switch (knl_interleave_mode(reg)) {
 828         case 0:
 829                 s = "use address bits [8:6]";
 830                 break;
 831         case 1:
 832                 s = "use address bits [10:8]";
 833                 break;
 834         case 2:
 835                 s = "use address bits [14:12]";
 836                 break;
 837         case 3:
 838                 s = "use address bits [32:30]";
 839                 break;
 840         default:
 841                 WARN_ON(1);
 842                 break;
 843         }
 844
 845         return s;
 846 }
 847
 848 static u32 dram_attr_knl(u32 reg)
 849 {
 850         return GET_BITFIELD(reg, 3, 4);
 851 }
 852
 853
 854 static enum mem_type get_memory_type(struct sbridge_pvt *pvt)
 855 {
 856         u32 reg;
 857         enum mem_type mtype;
 858
 859         if (pvt->pci_ddrio) {
 860                 pci_read_config_dword(pvt->pci_ddrio, pvt->info.rankcfgr,
 861                                       &reg);
 862                 if (GET_BITFIELD(reg, 11, 11))
 863                         /* FIXME: Can also be LRDIMM */
 864                         mtype = MEM_RDDR3;
 865                 else
 866                         mtype = MEM_DDR3;
 867         } else
 868                 mtype = MEM_UNKNOWN;
 869
 870         return mtype;
 871 }
 872
 873 static enum mem_type haswell_get_memory_type(struct sbridge_pvt *pvt)
 874 {
 875         u32 reg;
 876         bool registered = false;
 877         enum mem_type mtype = MEM_UNKNOWN;
 878
 879         if (!pvt->pci_ddrio)
 880                 goto out;
 881
 882         pci_read_config_dword(pvt->pci_ddrio,
 883                               HASWELL_DDRCRCLKCONTROLS, &reg);
 884         /* Is_Rdimm */
 885         if (GET_BITFIELD(reg, 16, 16))
 886                 registered = true;
 887
 888         pci_read_config_dword(pvt->pci_ta, MCMTR, &reg);
 889         if (GET_BITFIELD(reg, 14, 14)) {
 890                 if (registered)
 891                         mtype = MEM_RDDR4;
 892                 else
 893                         mtype = MEM_DDR4;
 894         } else {
 895                 if (registered)
 896                         mtype = MEM_RDDR3;
 897                 else
 898                         mtype = MEM_DDR3;
 899         }
 900
 901 out:
 902         return mtype;
 903 }
 904
 905 static enum dev_type knl_get_width(struct sbridge_pvt *pvt, u32 mtr)
 906 {
 907         /* for KNL value is fixed */
 908         return DEV_X16;
 909 }
 910
 911 static enum dev_type sbridge_get_width(struct sbridge_pvt *pvt, u32 mtr)
 912 {
 913         /* there's no way to figure out */
 914         return DEV_UNKNOWN;
 915 }
 916
 917 static enum dev_type __ibridge_get_width(u32 mtr)
 918 {
 919         enum dev_type type;
 920
 921         switch (mtr) {
 922         case 3:
 923                 type = DEV_UNKNOWN;
 924                 break;
 925         case 2:
 926                 type = DEV_X16;
 927                 break;
 928         case 1:
 929                 type = DEV_X8;
 930                 break;
 931         case 0:
 932                 type = DEV_X4;
 933                 break;
 934         }
 935
 936         return type;
 937 }
 938
 939 static enum dev_type ibridge_get_width(struct sbridge_pvt *pvt, u32 mtr)
 940 {
 941         /*
 942          * ddr3_width on the documentation but also valid for DDR4 on
 943          * Haswell
 944          */
 945         return __ibridge_get_width(GET_BITFIELD(mtr, 7, 8));
 946 }
 947
 948 static enum dev_type broadwell_get_width(struct sbridge_pvt *pvt, u32 mtr)
 949 {
 950         /* ddr3_width on the documentation but also valid for DDR4 */
 951         return __ibridge_get_width(GET_BITFIELD(mtr, 8, 9));
 952 }
 953
 954 static enum mem_type knl_get_memory_type(struct sbridge_pvt *pvt)
 955 {
 956         /* DDR4 RDIMMS and LRDIMMS are supported */
 957         return MEM_RDDR4;
 958 }
 959
 960 static u8 get_node_id(struct sbridge_pvt *pvt)
 961 {
 962         u32 reg;
 963         pci_read_config_dword(pvt->pci_br0, SAD_CONTROL, &reg);
 964         return GET_BITFIELD(reg, 0, 2);
 965 }
 966
 967 static u8 haswell_get_node_id(struct sbridge_pvt *pvt)
 968 {
 969         u32 reg;
 970
 971         pci_read_config_dword(pvt->pci_sad1, SAD_CONTROL, &reg);
 972         return GET_BITFIELD(reg, 0, 3);
 973 }
 974
 975 static u8 knl_get_node_id(struct sbridge_pvt *pvt)
 976 {
 977         u32 reg;
 978
 979         pci_read_config_dword(pvt->pci_sad1, SAD_CONTROL, &reg);
 980         return GET_BITFIELD(reg, 0, 2);
 981 }
 982
 983
 984 static u64 haswell_get_tolm(struct sbridge_pvt *pvt)
 985 {
 986         u32 reg;
 987
 988         pci_read_config_dword(pvt->info.pci_vtd, HASWELL_TOLM, &reg);
 989         return (GET_BITFIELD(reg, 26, 31) << 26) | 0x3ffffff;
 990 }
 991
 992 static u64 haswell_get_tohm(struct sbridge_pvt *pvt)
 993 {
 994         u64 rc;
 995         u32 reg;
 996
 997         pci_read_config_dword(pvt->info.pci_vtd, HASWELL_TOHM_0, &reg);
 998         rc = GET_BITFIELD(reg, 26, 31);
 999         pci_read_config_dword(pvt->info.pci_vtd, HASWELL_TOHM_1, &reg);
1000         rc = ((reg << 6) | rc) << 26;
1001
1002         return rc | 0x1ffffff;
1003 }
1004
1005 static u64 knl_get_tolm(struct sbridge_pvt *pvt)
1006 {
1007         u32 reg;
1008
1009         pci_read_config_dword(pvt->knl.pci_mc_info, KNL_TOLM, &reg);
1010         return (GET_BITFIELD(reg, 26, 31) << 26) | 0x3ffffff;
1011 }
1012
1013 static u64 knl_get_tohm(struct sbridge_pvt *pvt)
1014 {
1015         u64 rc;
1016         u32 reg_lo, reg_hi;
1017
1018         pci_read_config_dword(pvt->knl.pci_mc_info, KNL_TOHM_0, &reg_lo);
1019         pci_read_config_dword(pvt->knl.pci_mc_info, KNL_TOHM_1, &reg_hi);
1020         rc = ((u64)reg_hi << 32) | reg_lo;
1021         return rc | 0x3ffffff;
1022 }
1023
1024
1025 static u64 haswell_rir_limit(u32 reg)
1026 {
1027         return (((u64)GET_BITFIELD(reg,  1, 11) + 1) << 29) - 1;
1028 }
1029
1030 static inline u8 sad_pkg_socket(u8 pkg)
1031 {
1032         /* on Ivy Bridge, nodeID is SASS, where A is HA and S is node id */
1033         return ((pkg >> 3) << 2) | (pkg & 0x3);
1034 }
1035
1036 static inline u8 sad_pkg_ha(u8 pkg)
1037 {
1038         return (pkg >> 2) & 0x1;
1039 }
1040
1041 /****************************************************************************
1042                         Memory check routines
1043  ****************************************************************************/
1044 static struct pci_dev *get_pdev_same_bus(u8 bus, u32 id)
1045 {
1046         struct pci_dev *pdev = NULL;
1047
1048         do {
1049                 pdev = pci_get_device(PCI_VENDOR_ID_INTEL, id, pdev);
1050                 if (pdev && pdev->bus->number == bus)
1051                         break;
1052         } while (pdev);
1053
1054         return pdev;
1055 }
1056
1057 /**
1058  * check_if_ecc_is_active() - Checks if ECC is active
1059  * @bus:        Device bus
1060  * @type:       Memory controller type
1061  * returns: 0 in case ECC is active, -ENODEV if it can't be determined or
1062  *          disabled
1063  */
1064 static int check_if_ecc_is_active(const u8 bus, enum type type)
1065 {
1066         struct pci_dev *pdev = NULL;
1067         u32 mcmtr, id;
1068
1069         switch (type) {
1070         case IVY_BRIDGE:
1071                 id = PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TA;
1072                 break;
1073         case HASWELL:
1074                 id = PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TA;
1075                 break;
1076         case SANDY_BRIDGE:
1077                 id = PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TA;
1078                 break;
1079         case BROADWELL:
1080                 id = PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TA;
1081                 break;
1082         case KNIGHTS_LANDING:
1083                 /*
1084                  * KNL doesn't group things by bus the same way
1085                  * SB/IB/Haswell does.
1086                  */
1087                 id = PCI_DEVICE_ID_INTEL_KNL_IMC_TA;
1088                 break;
1089         default:
1090                 return -ENODEV;
1091         }
1092
1093         if (type != KNIGHTS_LANDING)
1094                 pdev = get_pdev_same_bus(bus, id);
1095         else
1096                 pdev = pci_get_device(PCI_VENDOR_ID_INTEL, id, 0);
1097
1098         if (!pdev) {
1099                 sbridge_printk(KERN_ERR, "Couldn't find PCI device "
1100                                         "%04x:%04x! on bus %02d\n",
1101                                         PCI_VENDOR_ID_INTEL, id, bus);
1102                 return -ENODEV;
1103         }
1104
1105         pci_read_config_dword(pdev,
1106                         type == KNIGHTS_LANDING ? KNL_MCMTR : MCMTR, &mcmtr);
1107         if (!IS_ECC_ENABLED(mcmtr)) {
1108                 sbridge_printk(KERN_ERR, "ECC is disabled. Aborting\n");
1109                 return -ENODEV;
1110         }
1111         return 0;
1112 }
1113
1114 /* Low bits of TAD limit, and some metadata. */
1115 static const u32 knl_tad_dram_limit_lo[] = {
1116         0x400, 0x500, 0x600, 0x700,
1117         0x800, 0x900, 0xa00, 0xb00,
1118 };
1119
1120 /* Low bits of TAD offset. */
1121 static const u32 knl_tad_dram_offset_lo[] = {
1122         0x404, 0x504, 0x604, 0x704,
1123         0x804, 0x904, 0xa04, 0xb04,
1124 };
1125
1126 /* High 16 bits of TAD limit and offset. */
1127 static const u32 knl_tad_dram_hi[] = {
1128         0x408, 0x508, 0x608, 0x708,
1129         0x808, 0x908, 0xa08, 0xb08,
1130 };
1131
1132 /* Number of ways a tad entry is interleaved. */
1133 static const u32 knl_tad_ways[] = {
1134         8, 6, 4, 3, 2, 1,
1135 };
1136
1137 /*
1138  * Retrieve the n'th Target Address Decode table entry
1139  * from the memory controller's TAD table.
1140  *
1141  * @pvt:        driver private data
1142  * @entry:      which entry you want to retrieve
1143  * @mc:         which memory controller (0 or 1)
1144  * @offset:     output tad range offset
1145  * @limit:      output address of first byte above tad range
1146  * @ways:       output number of interleave ways
1147  *
1148  * The offset value has curious semantics.  It's a sort of running total
1149  * of the sizes of all the memory regions that aren't mapped in this
1150  * tad table.
1151  */
1152 static int knl_get_tad(const struct sbridge_pvt *pvt,
1153                 const int entry,
1154                 const int mc,
1155                 u64 *offset,
1156                 u64 *limit,
1157                 int *ways)
1158 {
1159         u32 reg_limit_lo, reg_offset_lo, reg_hi;
1160         struct pci_dev *pci_mc;
1161         int way_id;
1162
1163         switch (mc) {
1164         case 0:
1165                 pci_mc = pvt->knl.pci_mc0;
1166                 break;
1167         case 1:
1168                 pci_mc = pvt->knl.pci_mc1;
1169                 break;
1170         default:
1171                 WARN_ON(1);
1172                 return -EINVAL;
1173         }
1174
1175         pci_read_config_dword(pci_mc,
1176                         knl_tad_dram_limit_lo[entry], &reg_limit_lo);
1177         pci_read_config_dword(pci_mc,
1178                         knl_tad_dram_offset_lo[entry], &reg_offset_lo);
1179         pci_read_config_dword(pci_mc,
1180                         knl_tad_dram_hi[entry], &reg_hi);
1181
1182         /* Is this TAD entry enabled? */
1183         if (!GET_BITFIELD(reg_limit_lo, 0, 0))
1184                 return -ENODEV;
1185
1186         way_id = GET_BITFIELD(reg_limit_lo, 3, 5);
1187
1188         if (way_id < ARRAY_SIZE(knl_tad_ways)) {
1189                 *ways = knl_tad_ways[way_id];
1190         } else {
1191                 *ways = 0;
1192                 sbridge_printk(KERN_ERR,
1193                                 "Unexpected value %d in mc_tad_limit_lo wayness field\n",
1194                                 way_id);
1195                 return -ENODEV;
1196         }
1197
1198         /*
1199          * The least significant 6 bits of base and limit are truncated.
1200          * For limit, we fill the missing bits with 1s.
1201          */
1202         *offset = ((u64) GET_BITFIELD(reg_offset_lo, 6, 31) << 6) |
1203                                 ((u64) GET_BITFIELD(reg_hi, 0,  15) << 32);
1204         *limit = ((u64) GET_BITFIELD(reg_limit_lo,  6, 31) << 6) | 63 |
1205                                 ((u64) GET_BITFIELD(reg_hi, 16, 31) << 32);
1206
1207         return 0;
1208 }
1209
1210 /* Determine which memory controller is responsible for a given channel. */
1211 static int knl_channel_mc(int channel)
1212 {
1213         WARN_ON(channel < 0 || channel >= 6);
1214
1215         return channel < 3 ? 1 : 0;
1216 }
1217
1218 /*
1219  * Get the Nth entry from EDC_ROUTE_TABLE register.
1220  * (This is the per-tile mapping of logical interleave targets to
1221  *  physical EDC modules.)
1222  *
1223  * entry 0: 0:2
1224  *       1: 3:5
1225  *       2: 6:8
1226  *       3: 9:11
1227  *       4: 12:14
1228  *       5: 15:17
1229  *       6: 18:20
1230  *       7: 21:23
1231  * reserved: 24:31
1232  */
1233 static u32 knl_get_edc_route(int entry, u32 reg)
1234 {
1235         WARN_ON(entry >= KNL_MAX_EDCS);
1236         return GET_BITFIELD(reg, entry*3, (entry*3)+2);
1237 }
1238
1239 /*
1240  * Get the Nth entry from MC_ROUTE_TABLE register.
1241  * (This is the per-tile mapping of logical interleave targets to
1242  *  physical DRAM channels modules.)
1243  *
1244  * entry 0: mc 0:2   channel 18:19
1245  *       1: mc 3:5   channel 20:21
1246  *       2: mc 6:8   channel 22:23
1247  *       3: mc 9:11  channel 24:25
1248  *       4: mc 12:14 channel 26:27
1249  *       5: mc 15:17 channel 28:29
1250  * reserved: 30:31
1251  *
1252  * Though we have 3 bits to identify the MC, we should only see
1253  * the values 0 or 1.
1254  */
1255
1256 static u32 knl_get_mc_route(int entry, u32 reg)
1257 {
1258         int mc, chan;
1259
1260         WARN_ON(entry >= KNL_MAX_CHANNELS);
1261
1262         mc = GET_BITFIELD(reg, entry*3, (entry*3)+2);
1263         chan = GET_BITFIELD(reg, (entry*2) + 18, (entry*2) + 18 + 1);
1264
1265         return knl_channel_remap(mc*3 + chan);
1266 }
1267
1268 /*
1269  * Render the EDC_ROUTE register in human-readable form.
1270  * Output string s should be at least KNL_MAX_EDCS*2 bytes.
1271  */
1272 static void knl_show_edc_route(u32 reg, char *s)
1273 {
1274         int i;
1275
1276         for (i = 0; i < KNL_MAX_EDCS; i++) {
1277                 s[i*2] = knl_get_edc_route(i, reg) + '0';
1278                 s[i*2+1] = '-';
1279         }
1280
1281         s[KNL_MAX_EDCS*2 - 1] = '\0';
1282 }
1283
1284 /*
1285  * Render the MC_ROUTE register in human-readable form.
1286  * Output string s should be at least KNL_MAX_CHANNELS*2 bytes.
1287  */
1288 static void knl_show_mc_route(u32 reg, char *s)
1289 {
1290         int i;
1291
1292         for (i = 0; i < KNL_MAX_CHANNELS; i++) {
1293                 s[i*2] = knl_get_mc_route(i, reg) + '0';
1294                 s[i*2+1] = '-';
1295         }
1296
1297         s[KNL_MAX_CHANNELS*2 - 1] = '\0';
1298 }
1299
1300 #define KNL_EDC_ROUTE 0xb8
1301 #define KNL_MC_ROUTE 0xb4
1302
1303 /* Is this dram rule backed by regular DRAM in flat mode? */
1304 #define KNL_EDRAM(reg) GET_BITFIELD(reg, 29, 29)
1305
1306 /* Is this dram rule cached? */
1307 #define KNL_CACHEABLE(reg) GET_BITFIELD(reg, 28, 28)
1308
1309 /* Is this rule backed by edc ? */
1310 #define KNL_EDRAM_ONLY(reg) GET_BITFIELD(reg, 29, 29)
1311
1312 /* Is this rule backed by DRAM, cacheable in EDRAM? */
1313 #define KNL_CACHEABLE(reg) GET_BITFIELD(reg, 28, 28)
1314
1315 /* Is this rule mod3? */
1316 #define KNL_MOD3(reg) GET_BITFIELD(reg, 27, 27)
1317
1318 /*
1319  * Figure out how big our RAM modules are.
1320  *
1321  * The DIMMMTR register in KNL doesn't tell us the size of the DIMMs, so we
1322  * have to figure this out from the SAD rules, interleave lists, route tables,
1323  * and TAD rules.
1324  *
1325  * SAD rules can have holes in them (e.g. the 3G-4G hole), so we have to
1326  * inspect the TAD rules to figure out how large the SAD regions really are.
1327  *
1328  * When we know the real size of a SAD region and how many ways it's
1329  * interleaved, we know the individual contribution of each channel to
1330  * TAD is size/ways.
1331  *
1332  * Finally, we have to check whether each channel participates in each SAD
1333  * region.
1334  *
1335  * Fortunately, KNL only supports one DIMM per channel, so once we know how
1336  * much memory the channel uses, we know the DIMM is at least that large.
1337  * (The BIOS might possibly choose not to map all available memory, in which
1338  * case we will underreport the size of the DIMM.)
1339  *
1340  * In theory, we could try to determine the EDC sizes as well, but that would
1341  * only work in flat mode, not in cache mode.
1342  *
1343  * @mc_sizes: Output sizes of channels (must have space for KNL_MAX_CHANNELS
1344  *            elements)
1345  */
1346 static int knl_get_dimm_capacity(struct sbridge_pvt *pvt, u64 *mc_sizes)
1347 {
1348         u64 sad_base, sad_size, sad_limit = 0;
1349         u64 tad_base, tad_size, tad_limit, tad_deadspace, tad_livespace;
1350         int sad_rule = 0;
1351         int tad_rule = 0;
1352         int intrlv_ways, tad_ways;
1353         u32 first_pkg, pkg;
1354         int i;
1355         u64 sad_actual_size[2]; /* sad size accounting for holes, per mc */
1356         u32 dram_rule, interleave_reg;
1357         u32 mc_route_reg[KNL_MAX_CHAS];
1358         u32 edc_route_reg[KNL_MAX_CHAS];
1359         int edram_only;
1360         char edc_route_string[KNL_MAX_EDCS*2];
1361         char mc_route_string[KNL_MAX_CHANNELS*2];
1362         int cur_reg_start;
1363         int mc;
1364         int channel;
1365         int way;
1366         int participants[KNL_MAX_CHANNELS];
1367         int participant_count = 0;
1368
1369         for (i = 0; i < KNL_MAX_CHANNELS; i++)
1370                 mc_sizes[i] = 0;
1371
1372         /* Read the EDC route table in each CHA. */
1373         cur_reg_start = 0;
1374         for (i = 0; i < KNL_MAX_CHAS; i++) {
1375                 pci_read_config_dword(pvt->knl.pci_cha[i],
1376                                 KNL_EDC_ROUTE, &edc_route_reg[i]);
1377
1378                 if (i > 0 && edc_route_reg[i] != edc_route_reg[i-1]) {
1379                         knl_show_edc_route(edc_route_reg[i-1],
1380                                         edc_route_string);
1381                         if (cur_reg_start == i-1)
1382                                 edac_dbg(0, "edc route table for CHA %d: %s\n",
1383                                         cur_reg_start, edc_route_string);
1384                         else
1385                                 edac_dbg(0, "edc route table for CHA %d-%d: %s\n",
1386                                         cur_reg_start, i-1, edc_route_string);
1387                         cur_reg_start = i;
1388                 }
1389         }
1390         knl_show_edc_route(edc_route_reg[i-1], edc_route_string);
1391         if (cur_reg_start == i-1)
1392                 edac_dbg(0, "edc route table for CHA %d: %s\n",
1393                         cur_reg_start, edc_route_string);
1394         else
1395                 edac_dbg(0, "edc route table for CHA %d-%d: %s\n",
1396                         cur_reg_start, i-1, edc_route_string);
1397
1398         /* Read the MC route table in each CHA. */
1399         cur_reg_start = 0;
1400         for (i = 0; i < KNL_MAX_CHAS; i++) {
1401                 pci_read_config_dword(pvt->knl.pci_cha[i],
1402                         KNL_MC_ROUTE, &mc_route_reg[i]);
1403
1404                 if (i > 0 && mc_route_reg[i] != mc_route_reg[i-1]) {
1405                         knl_show_mc_route(mc_route_reg[i-1], mc_route_string);
1406                         if (cur_reg_start == i-1)
1407                                 edac_dbg(0, "mc route table for CHA %d: %s\n",
1408                                         cur_reg_start, mc_route_string);
1409                         else
1410                                 edac_dbg(0, "mc route table for CHA %d-%d: %s\n",
1411                                         cur_reg_start, i-1, mc_route_string);
1412                         cur_reg_start = i;
1413                 }
1414         }
1415         knl_show_mc_route(mc_route_reg[i-1], mc_route_string);
1416         if (cur_reg_start == i-1)
1417                 edac_dbg(0, "mc route table for CHA %d: %s\n",
1418                         cur_reg_start, mc_route_string);
1419         else
1420                 edac_dbg(0, "mc route table for CHA %d-%d: %s\n",
1421                         cur_reg_start, i-1, mc_route_string);
1422
1423         /* Process DRAM rules */
1424         for (sad_rule = 0; sad_rule < pvt->info.max_sad; sad_rule++) {
1425                 /* previous limit becomes the new base */
1426                 sad_base = sad_limit;
1427
1428                 pci_read_config_dword(pvt->pci_sad0,
1429                         pvt->info.dram_rule[sad_rule], &dram_rule);
1430
1431                 if (!DRAM_RULE_ENABLE(dram_rule))
1432                         break;
1433
1434                 edram_only = KNL_EDRAM_ONLY(dram_rule);
1435
1436                 sad_limit = pvt->info.sad_limit(dram_rule)+1;
1437                 sad_size = sad_limit - sad_base;
1438
1439                 pci_read_config_dword(pvt->pci_sad0,
1440                         pvt->info.interleave_list[sad_rule], &interleave_reg);
1441
1442                 /*
1443                  * Find out how many ways this dram rule is interleaved.
1444                  * We stop when we see the first channel again.
1445                  */
1446                 first_pkg = sad_pkg(pvt->info.interleave_pkg,
1447                                                 interleave_reg, 0);
1448                 for (intrlv_ways = 1; intrlv_ways < 8; intrlv_ways++) {
1449                         pkg = sad_pkg(pvt->info.interleave_pkg,
1450                                                 interleave_reg, intrlv_ways);
1451
1452                         if ((pkg & 0x8) == 0) {
1453                                 /*
1454                                  * 0 bit means memory is non-local,
1455                                  * which KNL doesn't support
1456                                  */
1457                                 edac_dbg(0, "Unexpected interleave target %d\n",
1458                                         pkg);
1459                                 return -1;
1460                         }
1461
1462                         if (pkg == first_pkg)
1463                                 break;
1464                 }
1465                 if (KNL_MOD3(dram_rule))
1466                         intrlv_ways *= 3;
1467
1468                 edac_dbg(3, "dram rule %d (base 0x%llx, limit 0x%llx), %d way interleave%s\n",
1469                         sad_rule,
1470                         sad_base,
1471                         sad_limit,
1472                         intrlv_ways,
1473                         edram_only ? ", EDRAM" : "");
1474
1475                 /*
1476                  * Find out how big the SAD region really is by iterating
1477                  * over TAD tables (SAD regions may contain holes).
1478                  * Each memory controller might have a different TAD table, so
1479                  * we have to look at both.
1480                  *
1481                  * Livespace is the memory that's mapped in this TAD table,
1482                  * deadspace is the holes (this could be the MMIO hole, or it
1483                  * could be memory that's mapped by the other TAD table but
1484                  * not this one).
1485                  */
1486                 for (mc = 0; mc < 2; mc++) {
1487                         sad_actual_size[mc] = 0;
1488                         tad_livespace = 0;
1489                         for (tad_rule = 0;
1490                                         tad_rule < ARRAY_SIZE(
1491                                                 knl_tad_dram_limit_lo);
1492                                         tad_rule++) {
1493                                 if (knl_get_tad(pvt,
1494                                                 tad_rule,
1495                                                 mc,
1496                                                 &tad_deadspace,
1497                                                 &tad_limit,
1498                                                 &tad_ways))
1499                                         break;
1500
1501                                 tad_size = (tad_limit+1) -
1502                                         (tad_livespace + tad_deadspace);
1503                                 tad_livespace += tad_size;
1504                                 tad_base = (tad_limit+1) - tad_size;
1505
1506                                 if (tad_base < sad_base) {
1507                                         if (tad_limit > sad_base)
1508                                                 edac_dbg(0, "TAD region overlaps lower SAD boundary -- TAD tables may be configured incorrectly.\n");
1509                                 } else if (tad_base < sad_limit) {
1510                                         if (tad_limit+1 > sad_limit) {
1511                                                 edac_dbg(0, "TAD region overlaps upper SAD boundary -- TAD tables may be configured incorrectly.\n");
1512                                         } else {
1513                                                 /* TAD region is completely inside SAD region */
1514                                                 edac_dbg(3, "TAD region %d 0x%llx - 0x%llx (%lld bytes) table%d\n",
1515                                                         tad_rule, tad_base,
1516                                                         tad_limit, tad_size,
1517                                                         mc);
1518                                                 sad_actual_size[mc] += tad_size;
1519                                         }
1520                                 }
1521                                 tad_base = tad_limit+1;
1522                         }
1523                 }
1524
1525                 for (mc = 0; mc < 2; mc++) {
1526                         edac_dbg(3, " total TAD DRAM footprint in table%d : 0x%llx (%lld bytes)\n",
1527                                 mc, sad_actual_size[mc], sad_actual_size[mc]);
1528                 }
1529
1530                 /* Ignore EDRAM rule */
1531                 if (edram_only)
1532                         continue;
1533
1534                 /* Figure out which channels participate in interleave. */
1535                 for (channel = 0; channel < KNL_MAX_CHANNELS; channel++)
1536                         participants[channel] = 0;
1537
1538                 /* For each channel, does at least one CHA have
1539                  * this channel mapped to the given target?
1540                  */
1541                 for (channel = 0; channel < KNL_MAX_CHANNELS; channel++) {
1542                         for (way = 0; way < intrlv_ways; way++) {
1543                                 int target;
1544                                 int cha;
1545
1546                                 if (KNL_MOD3(dram_rule))
1547                                         target = way;
1548                                 else
1549                                         target = 0x7 & sad_pkg(
1550                                 pvt->info.interleave_pkg, interleave_reg, way);
1551
1552                                 for (cha = 0; cha < KNL_MAX_CHAS; cha++) {
1553                                         if (knl_get_mc_route(target,
1554                                                 mc_route_reg[cha]) == channel
1555                                                 && !participants[channel]) {
1556                                                 participant_count++;
1557                                                 participants[channel] = 1;
1558                                                 break;
1559                                         }
1560                                 }
1561                         }
1562                 }
1563
1564                 if (participant_count != intrlv_ways)
1565                         edac_dbg(0, "participant_count (%d) != interleave_ways (%d): DIMM size may be incorrect\n",
1566                                 participant_count, intrlv_ways);
1567
1568                 for (channel = 0; channel < KNL_MAX_CHANNELS; channel++) {
1569                         mc = knl_channel_mc(channel);
1570                         if (participants[channel]) {
1571                                 edac_dbg(4, "mc channel %d contributes %lld bytes via sad entry %d\n",
1572                                         channel,
1573                                         sad_actual_size[mc]/intrlv_ways,
1574                                         sad_rule);
1575                                 mc_sizes[channel] +=
1576                                         sad_actual_size[mc]/intrlv_ways;
1577                         }
1578                 }
1579         }
1580
1581         return 0;
1582 }
1583
1584 static int get_dimm_config(struct mem_ctl_info *mci)
1585 {
1586         struct sbridge_pvt *pvt = mci->pvt_info;
1587         struct dimm_info *dimm;
1588         unsigned i, j, banks, ranks, rows, cols, npages;
1589         u64 size;
1590         u32 reg;
1591         enum edac_type mode;
1592         enum mem_type mtype;
1593         int channels = pvt->info.type == KNIGHTS_LANDING ?
1594                 KNL_MAX_CHANNELS : NUM_CHANNELS;
1595         u64 knl_mc_sizes[KNL_MAX_CHANNELS];
1596
1597         if (pvt->info.type == HASWELL || pvt->info.type == BROADWELL ||
1598                         pvt->info.type == KNIGHTS_LANDING)
1599                 pci_read_config_dword(pvt->pci_sad1, SAD_TARGET, &reg);
1600         else
1601                 pci_read_config_dword(pvt->pci_br0, SAD_TARGET, &reg);
1602
1603         if (pvt->info.type == KNIGHTS_LANDING)
1604                 pvt->sbridge_dev->source_id = SOURCE_ID_KNL(reg);
1605         else
1606                 pvt->sbridge_dev->source_id = SOURCE_ID(reg);
1607
1608         pvt->sbridge_dev->node_id = pvt->info.get_node_id(pvt);
1609         edac_dbg(0, "mc#%d: Node ID: %d, source ID: %d\n",
1610                  pvt->sbridge_dev->mc,
1611                  pvt->sbridge_dev->node_id,
1612                  pvt->sbridge_dev->source_id);
1613
1614         /* KNL doesn't support mirroring or lockstep,
1615          * and is always closed page
1616          */
1617         if (pvt->info.type == KNIGHTS_LANDING) {
1618                 mode = EDAC_S4ECD4ED;
1619                 pvt->is_mirrored = false;
1620
1621                 if (knl_get_dimm_capacity(pvt, knl_mc_sizes) != 0)
1622                         return -1;
1623         } else {
1624                 pci_read_config_dword(pvt->pci_ras, RASENABLES, &reg);
1625                 if (IS_MIRROR_ENABLED(reg)) {
1626                         edac_dbg(0, "Memory mirror is enabled\n");
1627                         pvt->is_mirrored = true;
1628                 } else {
1629                         edac_dbg(0, "Memory mirror is disabled\n");
1630                         pvt->is_mirrored = false;
1631                 }
1632
1633                 pci_read_config_dword(pvt->pci_ta, MCMTR, &pvt->info.mcmtr);
1634                 if (IS_LOCKSTEP_ENABLED(pvt->info.mcmtr)) {
1635                         edac_dbg(0, "Lockstep is enabled\n");
1636                         mode = EDAC_S8ECD8ED;
1637                         pvt->is_lockstep = true;
1638                 } else {
1639                         edac_dbg(0, "Lockstep is disabled\n");
1640                         mode = EDAC_S4ECD4ED;
1641                         pvt->is_lockstep = false;
1642                 }
1643                 if (IS_CLOSE_PG(pvt->info.mcmtr)) {
1644                         edac_dbg(0, "address map is on closed page mode\n");
1645                         pvt->is_close_pg = true;
1646                 } else {
1647                         edac_dbg(0, "address map is on open page mode\n");
1648                         pvt->is_close_pg = false;
1649                 }
1650         }
1651
1652         mtype = pvt->info.get_memory_type(pvt);
1653         if (mtype == MEM_RDDR3 || mtype == MEM_RDDR4)
1654                 edac_dbg(0, "Memory is registered\n");
1655         else if (mtype == MEM_UNKNOWN)
1656                 edac_dbg(0, "Cannot determine memory type\n");
1657         else
1658                 edac_dbg(0, "Memory is unregistered\n");
1659
1660         if (mtype == MEM_DDR4 || mtype == MEM_RDDR4)
1661                 banks = 16;
1662         else
1663                 banks = 8;
1664
1665         for (i = 0; i < channels; i++) {
1666                 u32 mtr;
1667
1668                 int max_dimms_per_channel;
1669
1670                 if (pvt->info.type == KNIGHTS_LANDING) {
1671                         max_dimms_per_channel = 1;
1672                         if (!pvt->knl.pci_channel[i])
1673                                 continue;
1674                 } else {
1675                         max_dimms_per_channel = ARRAY_SIZE(mtr_regs);
1676                         if (!pvt->pci_tad[i])
1677                                 continue;
1678                 }
1679
1680                 for (j = 0; j < max_dimms_per_channel; j++) {
1681                         dimm = EDAC_DIMM_PTR(mci->layers, mci->dimms, mci->n_layers,
1682                                        i, j, 0);
1683                         if (pvt->info.type == KNIGHTS_LANDING) {
1684                                 pci_read_config_dword(pvt->knl.pci_channel[i],
1685                                         knl_mtr_reg, &mtr);
1686                         } else {
1687                                 pci_read_config_dword(pvt->pci_tad[i],
1688                                         mtr_regs[j], &mtr);
1689                         }
1690                         edac_dbg(4, "Channel #%d  MTR%d = %x\n", i, j, mtr);
1691                         if (IS_DIMM_PRESENT(mtr)) {
1692                                 pvt->channel[i].dimms++;
1693
1694                                 ranks = numrank(pvt->info.type, mtr);
1695
1696                                 if (pvt->info.type == KNIGHTS_LANDING) {
1697                                         /* For DDR4, this is fixed. */
1698                                         cols = 1 << 10;
1699                                         rows = knl_mc_sizes[i] /
1700                                                 ((u64) cols * ranks * banks * 8);
1701                                 } else {
1702                                         rows = numrow(mtr);
1703                                         cols = numcol(mtr);
1704                                 }
1705
1706                                 size = ((u64)rows * cols * banks * ranks) >> (20 - 3);
1707                                 npages = MiB_TO_PAGES(size);
1708
1709                                 edac_dbg(0, "mc#%d: ha %d channel %d, dimm %d, %lld Mb (%d pages) bank: %d, rank: %d, row: %#x, col: %#x\n",
1710                                          pvt->sbridge_dev->mc, i/4, i%4, j,
1711                                          size, npages,
1712                                          banks, ranks, rows, cols);
1713
1714                                 dimm->nr_pages = npages;
1715                                 dimm->grain = 32;
1716                                 dimm->dtype = pvt->info.get_width(pvt, mtr);
1717                                 dimm->mtype = mtype;
1718                                 dimm->edac_mode = mode;
1719                                 snprintf(dimm->label, sizeof(dimm->label),
1720                                          "CPU_SrcID#%u_Ha#%u_Chan#%u_DIMM#%u",
1721                                          pvt->sbridge_dev->source_id, i/4, i%4, j);
1722                         }
1723                 }
1724         }
1725
1726         return 0;
1727 }
1728
1729 static void get_memory_layout(const struct mem_ctl_info *mci)
1730 {
1731         struct sbridge_pvt *pvt = mci->pvt_info;
1732         int i, j, k, n_sads, n_tads, sad_interl;
1733         u32 reg;
1734         u64 limit, prv = 0;
1735         u64 tmp_mb;
1736         u32 gb, mb;
1737         u32 rir_way;
1738
1739         /*
1740          * Step 1) Get TOLM/TOHM ranges
1741          */
1742
1743         pvt->tolm = pvt->info.get_tolm(pvt);
1744         tmp_mb = (1 + pvt->tolm) >> 20;
1745
1746         gb = div_u64_rem(tmp_mb, 1024, &mb);
1747         edac_dbg(0, "TOLM: %u.%03u GB (0x%016Lx)\n",
1748                 gb, (mb*1000)/1024, (u64)pvt->tolm);
1749
1750         /* Address range is already 45:25 */
1751         pvt->tohm = pvt->info.get_tohm(pvt);
1752         tmp_mb = (1 + pvt->tohm) >> 20;
1753
1754         gb = div_u64_rem(tmp_mb, 1024, &mb);
1755         edac_dbg(0, "TOHM: %u.%03u GB (0x%016Lx)\n",
1756                 gb, (mb*1000)/1024, (u64)pvt->tohm);
1757
1758         /*
1759          * Step 2) Get SAD range and SAD Interleave list
1760          * TAD registers contain the interleave wayness. However, it
1761          * seems simpler to just discover it indirectly, with the
1762          * algorithm bellow.
1763          */
1764         prv = 0;
1765         for (n_sads = 0; n_sads < pvt->info.max_sad; n_sads++) {
1766                 /* SAD_LIMIT Address range is 45:26 */
1767                 pci_read_config_dword(pvt->pci_sad0, pvt->info.dram_rule[n_sads],
1768                                       &reg);
1769                 limit = pvt->info.sad_limit(reg);
1770
1771                 if (!DRAM_RULE_ENABLE(reg))
1772                         continue;
1773
1774                 if (limit <= prv)
1775                         break;
1776
1777                 tmp_mb = (limit + 1) >> 20;
1778                 gb = div_u64_rem(tmp_mb, 1024, &mb);
1779                 edac_dbg(0, "SAD#%d %s up to %u.%03u GB (0x%016Lx) Interleave: %s reg=0x%08x\n",
1780                          n_sads,
1781                          show_dram_attr(pvt->info.dram_attr(reg)),
1782                          gb, (mb*1000)/1024,
1783                          ((u64)tmp_mb) << 20L,
1784                          pvt->info.show_interleave_mode(reg),
1785                          reg);
1786                 prv = limit;
1787
1788                 pci_read_config_dword(pvt->pci_sad0, pvt->info.interleave_list[n_sads],
1789                                       &reg);
1790                 sad_interl = sad_pkg(pvt->info.interleave_pkg, reg, 0);
1791                 for (j = 0; j < 8; j++) {
1792                         u32 pkg = sad_pkg(pvt->info.interleave_pkg, reg, j);
1793                         if (j > 0 && sad_interl == pkg)
1794                                 break;
1795
1796                         edac_dbg(0, "SAD#%d, interleave #%d: %d\n",
1797                                  n_sads, j, pkg);
1798                 }
1799         }
1800
1801         if (pvt->info.type == KNIGHTS_LANDING)
1802                 return;
1803
1804         /*
1805          * Step 3) Get TAD range
1806          */
1807         prv = 0;
1808         for (n_tads = 0; n_tads < MAX_TAD; n_tads++) {
1809                 pci_read_config_dword(pvt->pci_ha0, tad_dram_rule[n_tads],
1810                                       &reg);
1811                 limit = TAD_LIMIT(reg);
1812                 if (limit <= prv)
1813                         break;
1814                 tmp_mb = (limit + 1) >> 20;
1815
1816                 gb = div_u64_rem(tmp_mb, 1024, &mb);
1817                 edac_dbg(0, "TAD#%d: up to %u.%03u GB (0x%016Lx), socket interleave %d, memory interleave %d, TGT: %d, %d, %d, %d, reg=0x%08x\n",
1818                          n_tads, gb, (mb*1000)/1024,
1819                          ((u64)tmp_mb) << 20L,
1820                          (u32)(1 << TAD_SOCK(reg)),
1821                          (u32)TAD_CH(reg) + 1,
1822                          (u32)TAD_TGT0(reg),
1823                          (u32)TAD_TGT1(reg),
1824                          (u32)TAD_TGT2(reg),
1825                          (u32)TAD_TGT3(reg),
1826                          reg);
1827                 prv = limit;
1828         }
1829
1830         /*
1831          * Step 4) Get TAD offsets, per each channel
1832          */
1833         for (i = 0; i < NUM_CHANNELS; i++) {
1834                 if (!pvt->channel[i].dimms)
1835                         continue;
1836                 for (j = 0; j < n_tads; j++) {
1837                         pci_read_config_dword(pvt->pci_tad[i],
1838                                               tad_ch_nilv_offset[j],
1839                                               &reg);
1840                         tmp_mb = TAD_OFFSET(reg) >> 20;
1841                         gb = div_u64_rem(tmp_mb, 1024, &mb);
1842                         edac_dbg(0, "TAD CH#%d, offset #%d: %u.%03u GB (0x%016Lx), reg=0x%08x\n",
1843                                  i, j,
1844                                  gb, (mb*1000)/1024,
1845                                  ((u64)tmp_mb) << 20L,
1846                                  reg);
1847                 }
1848         }
1849
1850         /*
1851          * Step 6) Get RIR Wayness/Limit, per each channel
1852          */
1853         for (i = 0; i < NUM_CHANNELS; i++) {
1854                 if (!pvt->channel[i].dimms)
1855                         continue;
1856                 for (j = 0; j < MAX_RIR_RANGES; j++) {
1857                         pci_read_config_dword(pvt->pci_tad[i],
1858                                               rir_way_limit[j],
1859                                               &reg);
1860
1861                         if (!IS_RIR_VALID(reg))
1862                                 continue;
1863
1864                         tmp_mb = pvt->info.rir_limit(reg) >> 20;
1865                         rir_way = 1 << RIR_WAY(reg);
1866                         gb = div_u64_rem(tmp_mb, 1024, &mb);
1867                         edac_dbg(0, "CH#%d RIR#%d, limit: %u.%03u GB (0x%016Lx), way: %d, reg=0x%08x\n",
1868                                  i, j,
1869                                  gb, (mb*1000)/1024,
1870                                  ((u64)tmp_mb) << 20L,
1871                                  rir_way,
1872                                  reg);
1873
1874                         for (k = 0; k < rir_way; k++) {
1875                                 pci_read_config_dword(pvt->pci_tad[i],
1876                                                       rir_offset[j][k],
1877                                                       &reg);
1878                                 tmp_mb = RIR_OFFSET(reg) << 6;
1879
1880                                 gb = div_u64_rem(tmp_mb, 1024, &mb);
1881                                 edac_dbg(0, "CH#%d RIR#%d INTL#%d, offset %u.%03u GB (0x%016Lx), tgt: %d, reg=0x%08x\n",
1882                                          i, j, k,
1883                                          gb, (mb*1000)/1024,
1884                                          ((u64)tmp_mb) << 20L,
1885                                          (u32)RIR_RNK_TGT(reg),
1886                                          reg);
1887                         }
1888                 }
1889         }
1890 }
1891
1892 static struct mem_ctl_info *get_mci_for_node_id(u8 node_id)
1893 {
1894         struct sbridge_dev *sbridge_dev;
1895
1896         list_for_each_entry(sbridge_dev, &sbridge_edac_list, list) {
1897                 if (sbridge_dev->node_id == node_id)
1898                         return sbridge_dev->mci;
1899         }
1900         return NULL;
1901 }
1902
1903 static int get_memory_error_data(struct mem_ctl_info *mci,
1904                                  u64 addr,
1905                                  u8 *socket, u8 *ha,
1906                                  long *channel_mask,
1907                                  u8 *rank,
1908                                  char **area_type, char *msg)
1909 {
1910         struct mem_ctl_info     *new_mci;
1911         struct sbridge_pvt *pvt = mci->pvt_info;
1912         struct pci_dev          *pci_ha;
1913         int                     n_rir, n_sads, n_tads, sad_way, sck_xch;
1914         int                     sad_interl, idx, base_ch;
1915         int                     interleave_mode, shiftup = 0;
1916         unsigned                sad_interleave[pvt->info.max_interleave];
1917         u32                     reg, dram_rule;
1918         u8                      ch_way, sck_way, pkg, sad_ha = 0, ch_add = 0;
1919         u32                     tad_offset;
1920         u32                     rir_way;
1921         u32                     mb, gb;
1922         u64                     ch_addr, offset, limit = 0, prv = 0;
1923
1924
1925         /*
1926          * Step 0) Check if the address is at special memory ranges
1927          * The check bellow is probably enough to fill all cases where
1928          * the error is not inside a memory, except for the legacy
1929          * range (e. g. VGA addresses). It is unlikely, however, that the
1930          * memory controller would generate an error on that range.
1931          */
1932         if ((addr > (u64) pvt->tolm) && (addr < (1LL << 32))) {
1933                 sprintf(msg, "Error at TOLM area, on addr 0x%08Lx", addr);
1934                 return -EINVAL;
1935         }
1936         if (addr >= (u64)pvt->tohm) {
1937                 sprintf(msg, "Error at MMIOH area, on addr 0x%016Lx", addr);
1938                 return -EINVAL;
1939         }
1940
1941         /*
1942          * Step 1) Get socket
1943          */
1944         for (n_sads = 0; n_sads < pvt->info.max_sad; n_sads++) {
1945                 pci_read_config_dword(pvt->pci_sad0, pvt->info.dram_rule[n_sads],
1946                                       &reg);
1947
1948                 if (!DRAM_RULE_ENABLE(reg))
1949                         continue;
1950
1951                 limit = pvt->info.sad_limit(reg);
1952                 if (limit <= prv) {
1953                         sprintf(msg, "Can't discover the memory socket");
1954                         return -EINVAL;
1955                 }
1956                 if  (addr <= limit)
1957                         break;
1958                 prv = limit;
1959         }
1960         if (n_sads == pvt->info.max_sad) {
1961                 sprintf(msg, "Can't discover the memory socket");
1962                 return -EINVAL;
1963         }
1964         dram_rule = reg;
1965         *area_type = show_dram_attr(pvt->info.dram_attr(dram_rule));
1966         interleave_mode = pvt->info.interleave_mode(dram_rule);
1967
1968         pci_read_config_dword(pvt->pci_sad0, pvt->info.interleave_list[n_sads],
1969                               &reg);
1970
1971         if (pvt->info.type == SANDY_BRIDGE) {
1972                 sad_interl = sad_pkg(pvt->info.interleave_pkg, reg, 0);
1973                 for (sad_way = 0; sad_way < 8; sad_way++) {
1974                         u32 pkg = sad_pkg(pvt->info.interleave_pkg, reg, sad_way);
1975                         if (sad_way > 0 && sad_interl == pkg)
1976                                 break;
1977                         sad_interleave[sad_way] = pkg;
1978                         edac_dbg(0, "SAD interleave #%d: %d\n",
1979                                  sad_way, sad_interleave[sad_way]);
1980                 }
1981                 edac_dbg(0, "mc#%d: Error detected on SAD#%d: address 0x%016Lx < 0x%016Lx, Interleave [%d:6]%s\n",
1982                          pvt->sbridge_dev->mc,
1983                          n_sads,
1984                          addr,
1985                          limit,
1986                          sad_way + 7,
1987                          !interleave_mode ? "" : "XOR[18:16]");
1988                 if (interleave_mode)
1989                         idx = ((addr >> 6) ^ (addr >> 16)) & 7;
1990                 else
1991                         idx = (addr >> 6) & 7;
1992                 switch (sad_way) {
1993                 case 1:
1994                         idx = 0;
1995                         break;
1996                 case 2:
1997                         idx = idx & 1;
1998                         break;
1999                 case 4:
2000                         idx = idx & 3;
2001                         break;
2002                 case 8:
2003                         break;
2004                 default:
2005                         sprintf(msg, "Can't discover socket interleave");
2006                         return -EINVAL;
2007                 }
2008                 *socket = sad_interleave[idx];
2009                 edac_dbg(0, "SAD interleave index: %d (wayness %d) = CPU socket %d\n",
2010                          idx, sad_way, *socket);
2011         } else if (pvt->info.type == HASWELL || pvt->info.type == BROADWELL) {
2012                 int bits, a7mode = A7MODE(dram_rule);
2013
2014                 if (a7mode) {
2015                         /* A7 mode swaps P9 with P6 */
2016                         bits = GET_BITFIELD(addr, 7, 8) << 1;
2017                         bits |= GET_BITFIELD(addr, 9, 9);
2018                 } else
2019                         bits = GET_BITFIELD(addr, 6, 8);
2020
2021                 if (interleave_mode == 0) {
2022                         /* interleave mode will XOR {8,7,6} with {18,17,16} */
2023                         idx = GET_BITFIELD(addr, 16, 18);
2024                         idx ^= bits;
2025                 } else
2026                         idx = bits;
2027
2028                 pkg = sad_pkg(pvt->info.interleave_pkg, reg, idx);
2029                 *socket = sad_pkg_socket(pkg);
2030                 sad_ha = sad_pkg_ha(pkg);
2031                 if (sad_ha)
2032                         ch_add = 4;
2033
2034                 if (a7mode) {
2035                         /* MCChanShiftUpEnable */
2036                         pci_read_config_dword(pvt->pci_ha0,
2037                                               HASWELL_HASYSDEFEATURE2, &reg);
2038                         shiftup = GET_BITFIELD(reg, 22, 22);
2039                 }
2040
2041                 edac_dbg(0, "SAD interleave package: %d = CPU socket %d, HA %i, shiftup: %i\n",
2042                          idx, *socket, sad_ha, shiftup);
2043         } else {
2044                 /* Ivy Bridge's SAD mode doesn't support XOR interleave mode */
2045                 idx = (addr >> 6) & 7;
2046                 pkg = sad_pkg(pvt->info.interleave_pkg, reg, idx);
2047                 *socket = sad_pkg_socket(pkg);
2048                 sad_ha = sad_pkg_ha(pkg);
2049                 if (sad_ha)
2050                         ch_add = 4;
2051                 edac_dbg(0, "SAD interleave package: %d = CPU socket %d, HA %d\n",
2052                          idx, *socket, sad_ha);
2053         }
2054
2055         *ha = sad_ha;
2056
2057         /*
2058          * Move to the proper node structure, in order to access the
2059          * right PCI registers
2060          */
2061         new_mci = get_mci_for_node_id(*socket);
2062         if (!new_mci) {
2063                 sprintf(msg, "Struct for socket #%u wasn't initialized",
2064                         *socket);
2065                 return -EINVAL;
2066         }
2067         mci = new_mci;
2068         pvt = mci->pvt_info;
2069
2070         /*
2071          * Step 2) Get memory channel
2072          */
2073         prv = 0;
2074         if (pvt->info.type == SANDY_BRIDGE)
2075                 pci_ha = pvt->pci_ha0;
2076         else {
2077                 if (sad_ha)
2078                         pci_ha = pvt->pci_ha1;
2079                 else
2080                         pci_ha = pvt->pci_ha0;
2081         }
2082         for (n_tads = 0; n_tads < MAX_TAD; n_tads++) {
2083                 pci_read_config_dword(pci_ha, tad_dram_rule[n_tads], &reg);
2084                 limit = TAD_LIMIT(reg);
2085                 if (limit <= prv) {
2086                         sprintf(msg, "Can't discover the memory channel");
2087                         return -EINVAL;
2088                 }
2089                 if  (addr <= limit)
2090                         break;
2091                 prv = limit;
2092         }
2093         if (n_tads == MAX_TAD) {
2094                 sprintf(msg, "Can't discover the memory channel");
2095                 return -EINVAL;
2096         }
2097
2098         ch_way = TAD_CH(reg) + 1;
2099         sck_way = 1 << TAD_SOCK(reg);
2100
2101         if (ch_way == 3)
2102                 idx = addr >> 6;
2103         else
2104                 idx = (addr >> (6 + sck_way + shiftup)) & 0x3;
2105         idx = idx % ch_way;
2106
2107         /*
2108          * FIXME: Shouldn't we use CHN_IDX_OFFSET() here, when ch_way == 3 ???
2109          */
2110         switch (idx) {
2111         case 0:
2112                 base_ch = TAD_TGT0(reg);
2113                 break;
2114         case 1:
2115                 base_ch = TAD_TGT1(reg);
2116                 break;
2117         case 2:
2118                 base_ch = TAD_TGT2(reg);
2119                 break;
2120         case 3:
2121                 base_ch = TAD_TGT3(reg);
2122                 break;
2123         default:
2124                 sprintf(msg, "Can't discover the TAD target");
2125                 return -EINVAL;
2126         }
2127         *channel_mask = 1 << base_ch;
2128
2129         pci_read_config_dword(pvt->pci_tad[ch_add + base_ch],
2130                                 tad_ch_nilv_offset[n_tads],
2131                                 &tad_offset);
2132
2133         if (pvt->is_mirrored) {
2134                 *channel_mask |= 1 << ((base_ch + 2) % 4);
2135                 switch(ch_way) {
2136                 case 2:
2137                 case 4:
2138                         sck_xch = 1 << sck_way * (ch_way >> 1);
2139                         break;
2140                 default:
2141                         sprintf(msg, "Invalid mirror set. Can't decode addr");
2142                         return -EINVAL;
2143                 }
2144         } else
2145                 sck_xch = (1 << sck_way) * ch_way;
2146
2147         if (pvt->is_lockstep)
2148                 *channel_mask |= 1 << ((base_ch + 1) % 4);
2149
2150         offset = TAD_OFFSET(tad_offset);
2151
2152         edac_dbg(0, "TAD#%d: address 0x%016Lx < 0x%016Lx, socket interleave %d, channel interleave %d (offset 0x%08Lx), index %d, base ch: %d, ch mask: 0x%02lx\n",
2153                  n_tads,
2154                  addr,
2155                  limit,
2156                  sck_way,
2157                  ch_way,
2158                  offset,
2159                  idx,
2160                  base_ch,
2161                  *channel_mask);
2162
2163         /* Calculate channel address */
2164         /* Remove the TAD offset */
2165
2166         if (offset > addr) {
2167                 sprintf(msg, "Can't calculate ch addr: TAD offset 0x%08Lx is too high for addr 0x%08Lx!",
2168                         offset, addr);
2169                 return -EINVAL;
2170         }
2171
2172         ch_addr = addr - offset;
2173         ch_addr >>= (6 + shiftup);
2174         ch_addr /= ch_way * sck_way;
2175         ch_addr <<= (6 + shiftup);
2176         ch_addr |= addr & ((1 << (6 + shiftup)) - 1);
2177
2178         /*
2179          * Step 3) Decode rank
2180          */
2181         for (n_rir = 0; n_rir < MAX_RIR_RANGES; n_rir++) {
2182                 pci_read_config_dword(pvt->pci_tad[ch_add + base_ch],
2183                                       rir_way_limit[n_rir],
2184                                       &reg);
2185
2186                 if (!IS_RIR_VALID(reg))
2187                         continue;
2188
2189                 limit = pvt->info.rir_limit(reg);
2190                 gb = div_u64_rem(limit >> 20, 1024, &mb);
2191                 edac_dbg(0, "RIR#%d, limit: %u.%03u GB (0x%016Lx), way: %d\n",
2192                          n_rir,
2193                          gb, (mb*1000)/1024,
2194                          limit,
2195                          1 << RIR_WAY(reg));
2196                 if  (ch_addr <= limit)
2197                         break;
2198         }
2199         if (n_rir == MAX_RIR_RANGES) {
2200                 sprintf(msg, "Can't discover the memory rank for ch addr 0x%08Lx",
2201                         ch_addr);
2202                 return -EINVAL;
2203         }
2204         rir_way = RIR_WAY(reg);
2205
2206         if (pvt->is_close_pg)
2207                 idx = (ch_addr >> 6);
2208         else
2209                 idx = (ch_addr >> 13);  /* FIXME: Datasheet says to shift by 15 */
2210         idx %= 1 << rir_way;
2211
2212         pci_read_config_dword(pvt->pci_tad[ch_add + base_ch],
2213                               rir_offset[n_rir][idx],
2214                               &reg);
2215         *rank = RIR_RNK_TGT(reg);
2216
2217         edac_dbg(0, "RIR#%d: channel address 0x%08Lx < 0x%08Lx, RIR interleave %d, index %d\n",
2218                  n_rir,
2219                  ch_addr,
2220                  limit,
2221                  rir_way,
2222                  idx);
2223
2224         return 0;
2225 }
2226
2227 /****************************************************************************
2228         Device initialization routines: put/get, init/exit
2229  ****************************************************************************/
2230
2231 /*
2232  *      sbridge_put_all_devices 'put' all the devices that we have
2233  *                              reserved via 'get'
2234  */
2235 static void sbridge_put_devices(struct sbridge_dev *sbridge_dev)
2236 {
2237         int i;
2238
2239         edac_dbg(0, "\n");
2240         for (i = 0; i < sbridge_dev->n_devs; i++) {
2241                 struct pci_dev *pdev = sbridge_dev->pdev[i];
2242                 if (!pdev)
2243                         continue;
2244                 edac_dbg(0, "Removing dev %02x:%02x.%d\n",
2245                          pdev->bus->number,
2246                          PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn));
2247                 pci_dev_put(pdev);
2248         }
2249 }
2250
2251 static void sbridge_put_all_devices(void)
2252 {
2253         struct sbridge_dev *sbridge_dev, *tmp;
2254
2255         list_for_each_entry_safe(sbridge_dev, tmp, &sbridge_edac_list, list) {
2256                 sbridge_put_devices(sbridge_dev);
2257                 free_sbridge_dev(sbridge_dev);
2258         }
2259 }
2260
2261 static int sbridge_get_onedevice(struct pci_dev **prev,
2262                                  u8 *num_mc,
2263                                  const struct pci_id_table *table,
2264                                  const unsigned devno,
2265                                  const int multi_bus)
2266 {
2267         struct sbridge_dev *sbridge_dev;
2268         const struct pci_id_descr *dev_descr = &table->descr[devno];
2269         struct pci_dev *pdev = NULL;
2270         u8 bus = 0;
2271
2272         sbridge_printk(KERN_DEBUG,
2273                 "Seeking for: PCI ID %04x:%04x\n",
2274                 PCI_VENDOR_ID_INTEL, dev_descr->dev_id);
2275
2276         pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
2277                               dev_descr->dev_id, *prev);
2278
2279         if (!pdev) {
2280                 if (*prev) {
2281                         *prev = pdev;
2282                         return 0;
2283                 }
2284
2285                 if (dev_descr->optional)
2286                         return 0;
2287
2288                 /* if the HA wasn't found */
2289                 if (devno == 0)
2290                         return -ENODEV;
2291
2292                 sbridge_printk(KERN_INFO,
2293                         "Device not found: %04x:%04x\n",
2294                         PCI_VENDOR_ID_INTEL, dev_descr->dev_id);
2295
2296                 /* End of list, leave */
2297                 return -ENODEV;
2298         }
2299         bus = pdev->bus->number;
2300
2301         sbridge_dev = get_sbridge_dev(bus, multi_bus);
2302         if (!sbridge_dev) {
2303                 sbridge_dev = alloc_sbridge_dev(bus, table);
2304                 if (!sbridge_dev) {
2305                         pci_dev_put(pdev);
2306                         return -ENOMEM;
2307                 }
2308                 (*num_mc)++;
2309         }
2310
2311         if (sbridge_dev->pdev[devno]) {
2312                 sbridge_printk(KERN_ERR,
2313                         "Duplicated device for %04x:%04x\n",
2314                         PCI_VENDOR_ID_INTEL, dev_descr->dev_id);
2315                 pci_dev_put(pdev);
2316                 return -ENODEV;
2317         }
2318
2319         sbridge_dev->pdev[devno] = pdev;
2320
2321         /* Be sure that the device is enabled */
2322         if (unlikely(pci_enable_device(pdev) < 0)) {
2323                 sbridge_printk(KERN_ERR,
2324                         "Couldn't enable %04x:%04x\n",
2325                         PCI_VENDOR_ID_INTEL, dev_descr->dev_id);
2326                 return -ENODEV;
2327         }
2328
2329         edac_dbg(0, "Detected %04x:%04x\n",
2330                  PCI_VENDOR_ID_INTEL, dev_descr->dev_id);
2331
2332         /*
2333          * As stated on drivers/pci/search.c, the reference count for
2334          * @from is always decremented if it is not %NULL. So, as we need
2335          * to get all devices up to null, we need to do a get for the device
2336          */
2337         pci_dev_get(pdev);
2338
2339         *prev = pdev;
2340
2341         return 0;
2342 }
2343
2344 /*
2345  * sbridge_get_all_devices - Find and perform 'get' operation on the MCH's
2346  *                           devices we want to reference for this driver.
2347  * @num_mc: pointer to the memory controllers count, to be incremented in case
2348  *          of success.
2349  * @table: model specific table
2350  * @allow_dups: allow for multiple devices to exist with the same device id
2351  *              (as implemented, this isn't expected to work correctly in the
2352  *              multi-socket case).
2353  * @multi_bus: don't assume devices on different buses belong to different
2354  *             memory controllers.
2355  *
2356  * returns 0 in case of success or error code
2357  */
2358 static int sbridge_get_all_devices_full(u8 *num_mc,
2359                                         const struct pci_id_table *table,
2360                                         int allow_dups,
2361                                         int multi_bus)
2362 {
2363         int i, rc;
2364         struct pci_dev *pdev = NULL;
2365
2366         while (table && table->descr) {
2367                 for (i = 0; i < table->n_devs; i++) {
2368                         if (!allow_dups || i == 0 ||
2369                                         table->descr[i].dev_id !=
2370                                                 table->descr[i-1].dev_id) {
2371                                 pdev = NULL;
2372                         }
2373                         do {
2374                                 rc = sbridge_get_onedevice(&pdev, num_mc,
2375                                                            table, i, multi_bus);
2376                                 if (rc < 0) {
2377                                         if (i == 0) {
2378                                                 i = table->n_devs;
2379                                                 break;
2380                                         }
2381                                         sbridge_put_all_devices();
2382                                         return -ENODEV;
2383                                 }
2384                         } while (pdev && !allow_dups);
2385                 }
2386                 table++;
2387         }
2388
2389         return 0;
2390 }
2391
2392 #define sbridge_get_all_devices(num_mc, table) \
2393                 sbridge_get_all_devices_full(num_mc, table, 0, 0)
2394 #define sbridge_get_all_devices_knl(num_mc, table) \
2395                 sbridge_get_all_devices_full(num_mc, table, 1, 1)
2396
2397 static int sbridge_mci_bind_devs(struct mem_ctl_info *mci,
2398                                  struct sbridge_dev *sbridge_dev)
2399 {
2400         struct sbridge_pvt *pvt = mci->pvt_info;
2401         struct pci_dev *pdev;
2402         u8 saw_chan_mask = 0;
2403         int i;
2404
2405         for (i = 0; i < sbridge_dev->n_devs; i++) {
2406                 pdev = sbridge_dev->pdev[i];
2407                 if (!pdev)
2408                         continue;
2409
2410                 switch (pdev->device) {
2411                 case PCI_DEVICE_ID_INTEL_SBRIDGE_SAD0:
2412                         pvt->pci_sad0 = pdev;
2413                         break;
2414                 case PCI_DEVICE_ID_INTEL_SBRIDGE_SAD1:
2415                         pvt->pci_sad1 = pdev;
2416                         break;
2417                 case PCI_DEVICE_ID_INTEL_SBRIDGE_BR:
2418                         pvt->pci_br0 = pdev;
2419                         break;
2420                 case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_HA0:
2421                         pvt->pci_ha0 = pdev;
2422                         break;
2423                 case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TA:
2424                         pvt->pci_ta = pdev;
2425                         break;
2426                 case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_RAS:
2427                         pvt->pci_ras = pdev;
2428                         break;
2429                 case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD0:
2430                 case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD1:
2431                 case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD2:
2432                 case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD3:
2433                 {
2434                         int id = pdev->device - PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD0;
2435                         pvt->pci_tad[id] = pdev;
2436                         saw_chan_mask |= 1 << id;
2437                 }
2438                         break;
2439                 case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_DDRIO:
2440                         pvt->pci_ddrio = pdev;
2441                         break;
2442                 default:
2443                         goto error;
2444                 }
2445
2446                 edac_dbg(0, "Associated PCI %02x:%02x, bus %d with dev = %p\n",
2447                          pdev->vendor, pdev->device,
2448                          sbridge_dev->bus,
2449                          pdev);
2450         }
2451
2452         /* Check if everything were registered */
2453         if (!pvt->pci_sad0 || !pvt->pci_sad1 || !pvt->pci_ha0 ||
2454             !pvt-> pci_tad || !pvt->pci_ras  || !pvt->pci_ta)
2455                 goto enodev;
2456
2457         if (saw_chan_mask != 0x0f)
2458                 goto enodev;
2459         return 0;
2460
2461 enodev:
2462         sbridge_printk(KERN_ERR, "Some needed devices are missing\n");
2463         return -ENODEV;
2464
2465 error:
2466         sbridge_printk(KERN_ERR, "Unexpected device %02x:%02x\n",
2467                        PCI_VENDOR_ID_INTEL, pdev->device);
2468         return -EINVAL;
2469 }
2470
2471 static int ibridge_mci_bind_devs(struct mem_ctl_info *mci,
2472                                  struct sbridge_dev *sbridge_dev)
2473 {
2474         struct sbridge_pvt *pvt = mci->pvt_info;
2475         struct pci_dev *pdev;
2476         u8 saw_chan_mask = 0;
2477         int i;
2478
2479         for (i = 0; i < sbridge_dev->n_devs; i++) {
2480                 pdev = sbridge_dev->pdev[i];
2481                 if (!pdev)
2482                         continue;
2483
2484                 switch (pdev->device) {
2485                 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0:
2486                         pvt->pci_ha0 = pdev;
2487                         break;
2488                 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TA:
2489                         pvt->pci_ta = pdev;
2490                 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_RAS:
2491                         pvt->pci_ras = pdev;
2492                         break;
2493                 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD0:
2494                 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD1:
2495                 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD2:
2496                 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD3:
2497                 {
2498                         int id = pdev->device - PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD0;
2499                         pvt->pci_tad[id] = pdev;
2500                         saw_chan_mask |= 1 << id;
2501                 }
2502                         break;
2503                 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_2HA_DDRIO0:
2504                         pvt->pci_ddrio = pdev;
2505                         break;
2506                 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_1HA_DDRIO0:
2507                         pvt->pci_ddrio = pdev;
2508                         break;
2509                 case PCI_DEVICE_ID_INTEL_IBRIDGE_SAD:
2510                         pvt->pci_sad0 = pdev;
2511                         break;
2512                 case PCI_DEVICE_ID_INTEL_IBRIDGE_BR0:
2513                         pvt->pci_br0 = pdev;
2514                         break;
2515                 case PCI_DEVICE_ID_INTEL_IBRIDGE_BR1:
2516                         pvt->pci_br1 = pdev;
2517                         break;
2518                 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1:
2519                         pvt->pci_ha1 = pdev;
2520                         break;
2521                 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD0:
2522                 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD1:
2523                 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD2:
2524                 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD3:
2525                 {
2526                         int id = pdev->device - PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD0 + 4;
2527                         pvt->pci_tad[id] = pdev;
2528                         saw_chan_mask |= 1 << id;
2529                 }
2530                         break;
2531                 default:
2532                         goto error;
2533                 }
2534
2535                 edac_dbg(0, "Associated PCI %02x.%02d.%d with dev = %p\n",
2536                          sbridge_dev->bus,
2537                          PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn),
2538                          pdev);
2539         }
2540
2541         /* Check if everything were registered */
2542         if (!pvt->pci_sad0 || !pvt->pci_ha0 || !pvt->pci_br0 ||
2543             !pvt->pci_br1 || !pvt->pci_tad || !pvt->pci_ras  ||
2544             !pvt->pci_ta)
2545                 goto enodev;
2546
2547         if (saw_chan_mask != 0x0f && /* -EN */
2548             saw_chan_mask != 0x33 && /* -EP */
2549             saw_chan_mask != 0xff)   /* -EX */
2550                 goto enodev;
2551         return 0;
2552
2553 enodev:
2554         sbridge_printk(KERN_ERR, "Some needed devices are missing\n");
2555         return -ENODEV;
2556
2557 error:
2558         sbridge_printk(KERN_ERR,
2559                        "Unexpected device %02x:%02x\n", PCI_VENDOR_ID_INTEL,
2560                         pdev->device);
2561         return -EINVAL;
2562 }
2563
2564 static int haswell_mci_bind_devs(struct mem_ctl_info *mci,
2565                                  struct sbridge_dev *sbridge_dev)
2566 {
2567         struct sbridge_pvt *pvt = mci->pvt_info;
2568         struct pci_dev *pdev;
2569         u8 saw_chan_mask = 0;
2570         int i;
2571
2572         /* there's only one device per system; not tied to any bus */
2573         if (pvt->info.pci_vtd == NULL)
2574                 /* result will be checked later */
2575                 pvt->info.pci_vtd = pci_get_device(PCI_VENDOR_ID_INTEL,
2576                                                    PCI_DEVICE_ID_INTEL_HASWELL_IMC_VTD_MISC,
2577                                                    NULL);
2578
2579         for (i = 0; i < sbridge_dev->n_devs; i++) {
2580                 pdev = sbridge_dev->pdev[i];
2581                 if (!pdev)
2582                         continue;
2583
2584                 switch (pdev->device) {
2585                 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_CBO_SAD0:
2586                         pvt->pci_sad0 = pdev;
2587                         break;
2588                 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_CBO_SAD1:
2589                         pvt->pci_sad1 = pdev;
2590                         break;
2591                 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0:
2592                         pvt->pci_ha0 = pdev;
2593                         break;
2594                 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TA:
2595                         pvt->pci_ta = pdev;
2596                         break;
2597                 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_THERMAL:
2598                         pvt->pci_ras = pdev;
2599                         break;
2600                 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD0:
2601                 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD1:
2602                 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD2:
2603                 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD3:
2604                 {
2605                         int id = pdev->device - PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD0;
2606
2607                         pvt->pci_tad[id] = pdev;
2608                         saw_chan_mask |= 1 << id;
2609                 }
2610                         break;
2611                 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD0:
2612                 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD1:
2613                 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD2:
2614                 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD3:
2615                 {
2616                         int id = pdev->device - PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD0 + 4;
2617
2618                         pvt->pci_tad[id] = pdev;
2619                         saw_chan_mask |= 1 << id;
2620                 }
2621                         break;
2622                 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO0:
2623                 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO1:
2624                 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO2:
2625                 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO3:
2626                         if (!pvt->pci_ddrio)
2627                                 pvt->pci_ddrio = pdev;
2628                         break;
2629                 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1:
2630                         pvt->pci_ha1 = pdev;
2631                         break;
2632                 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TA:
2633                         pvt->pci_ha1_ta = pdev;
2634                         break;
2635                 default:
2636                         break;
2637                 }
2638
2639                 edac_dbg(0, "Associated PCI %02x.%02d.%d with dev = %p\n",
2640                          sbridge_dev->bus,
2641                          PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn),
2642                          pdev);
2643         }
2644
2645         /* Check if everything were registered */
2646         if (!pvt->pci_sad0 || !pvt->pci_ha0 || !pvt->pci_sad1 ||
2647             !pvt->pci_ras  || !pvt->pci_ta || !pvt->info.pci_vtd)
2648                 goto enodev;
2649
2650         if (saw_chan_mask != 0x0f && /* -EN */
2651             saw_chan_mask != 0x33 && /* -EP */
2652             saw_chan_mask != 0xff)   /* -EX */
2653                 goto enodev;
2654         return 0;
2655
2656 enodev:
2657         sbridge_printk(KERN_ERR, "Some needed devices are missing\n");
2658         return -ENODEV;
2659 }
2660
2661 static int broadwell_mci_bind_devs(struct mem_ctl_info *mci,
2662                                  struct sbridge_dev *sbridge_dev)
2663 {
2664         struct sbridge_pvt *pvt = mci->pvt_info;
2665         struct pci_dev *pdev;
2666         u8 saw_chan_mask = 0;
2667         int i;
2668
2669         /* there's only one device per system; not tied to any bus */
2670         if (pvt->info.pci_vtd == NULL)
2671                 /* result will be checked later */
2672                 pvt->info.pci_vtd = pci_get_device(PCI_VENDOR_ID_INTEL,
2673                                                    PCI_DEVICE_ID_INTEL_BROADWELL_IMC_VTD_MISC,
2674                                                    NULL);
2675
2676         for (i = 0; i < sbridge_dev->n_devs; i++) {
2677                 pdev = sbridge_dev->pdev[i];
2678                 if (!pdev)
2679                         continue;
2680
2681                 switch (pdev->device) {
2682                 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_CBO_SAD0:
2683                         pvt->pci_sad0 = pdev;
2684                         break;
2685                 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_CBO_SAD1:
2686                         pvt->pci_sad1 = pdev;
2687                         break;
2688                 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0:
2689                         pvt->pci_ha0 = pdev;
2690                         break;
2691                 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TA:
2692                         pvt->pci_ta = pdev;
2693                         break;
2694                 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_THERMAL:
2695                         pvt->pci_ras = pdev;
2696                         break;
2697                 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD0:
2698                 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD1:
2699                 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD2:
2700                 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD3:
2701                 {
2702                         int id = pdev->device - PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD0;
2703                         pvt->pci_tad[id] = pdev;
2704                         saw_chan_mask |= 1 << id;
2705                 }
2706                         break;
2707                 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD0:
2708                 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD1:
2709                 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD2:
2710                 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD3:
2711                 {
2712                         int id = pdev->device - PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD0 + 4;
2713                         pvt->pci_tad[id] = pdev;
2714                         saw_chan_mask |= 1 << id;
2715                 }
2716                         break;
2717                 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_DDRIO0:
2718                         pvt->pci_ddrio = pdev;
2719                         break;
2720                 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1:
2721                         pvt->pci_ha1 = pdev;
2722                         break;
2723                 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TA:
2724                         pvt->pci_ha1_ta = pdev;
2725                         break;
2726                 default:
2727                         break;
2728                 }
2729
2730                 edac_dbg(0, "Associated PCI %02x.%02d.%d with dev = %p\n",
2731                          sbridge_dev->bus,
2732                          PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn),
2733                          pdev);
2734         }
2735
2736         /* Check if everything were registered */
2737         if (!pvt->pci_sad0 || !pvt->pci_ha0 || !pvt->pci_sad1 ||
2738             !pvt->pci_ras  || !pvt->pci_ta || !pvt->info.pci_vtd)
2739                 goto enodev;
2740
2741         if (saw_chan_mask != 0x0f && /* -EN */
2742             saw_chan_mask != 0x33 && /* -EP */
2743             saw_chan_mask != 0xff)   /* -EX */
2744                 goto enodev;
2745         return 0;
2746
2747 enodev:
2748         sbridge_printk(KERN_ERR, "Some needed devices are missing\n");
2749         return -ENODEV;
2750 }
2751
2752 static int knl_mci_bind_devs(struct mem_ctl_info *mci,
2753                         struct sbridge_dev *sbridge_dev)
2754 {
2755         struct sbridge_pvt *pvt = mci->pvt_info;
2756         struct pci_dev *pdev;
2757         int dev, func;
2758
2759         int i;
2760         int devidx;
2761
2762         for (i = 0; i < sbridge_dev->n_devs; i++) {
2763                 pdev = sbridge_dev->pdev[i];
2764                 if (!pdev)
2765                         continue;
2766
2767                 /* Extract PCI device and function. */
2768                 dev = (pdev->devfn >> 3) & 0x1f;
2769                 func = pdev->devfn & 0x7;
2770
2771                 switch (pdev->device) {
2772                 case PCI_DEVICE_ID_INTEL_KNL_IMC_MC:
2773                         if (dev == 8)
2774                                 pvt->knl.pci_mc0 = pdev;
2775                         else if (dev == 9)
2776                                 pvt->knl.pci_mc1 = pdev;
2777                         else {
2778                                 sbridge_printk(KERN_ERR,
2779                                         "Memory controller in unexpected place! (dev %d, fn %d)\n",
2780                                         dev, func);
2781                                 continue;
2782                         }
2783                         break;
2784
2785                 case PCI_DEVICE_ID_INTEL_KNL_IMC_SAD0:
2786                         pvt->pci_sad0 = pdev;
2787                         break;
2788
2789                 case PCI_DEVICE_ID_INTEL_KNL_IMC_SAD1:
2790                         pvt->pci_sad1 = pdev;
2791                         break;
2792
2793                 case PCI_DEVICE_ID_INTEL_KNL_IMC_CHA:
2794                         /* There are one of these per tile, and range from
2795                          * 1.14.0 to 1.18.5.
2796                          */
2797                         devidx = ((dev-14)*8)+func;
2798
2799                         if (devidx < 0 || devidx >= KNL_MAX_CHAS) {
2800                                 sbridge_printk(KERN_ERR,
2801                                         "Caching and Home Agent in unexpected place! (dev %d, fn %d)\n",
2802                                         dev, func);
2803                                 continue;
2804                         }
2805
2806                         WARN_ON(pvt->knl.pci_cha[devidx] != NULL);
2807
2808                         pvt->knl.pci_cha[devidx] = pdev;
2809                         break;
2810
2811                 case PCI_DEVICE_ID_INTEL_KNL_IMC_CHANNEL:
2812                         devidx = -1;
2813
2814                         /*
2815                          *  MC0 channels 0-2 are device 9 function 2-4,
2816                          *  MC1 channels 3-5 are device 8 function 2-4.
2817                          */
2818
2819                         if (dev == 9)
2820                                 devidx = func-2;
2821                         else if (dev == 8)
2822                                 devidx = 3 + (func-2);
2823
2824                         if (devidx < 0 || devidx >= KNL_MAX_CHANNELS) {
2825                                 sbridge_printk(KERN_ERR,
2826                                         "DRAM Channel Registers in unexpected place! (dev %d, fn %d)\n",
2827                                         dev, func);
2828                                 continue;
2829                         }
2830
2831                         WARN_ON(pvt->knl.pci_channel[devidx] != NULL);
2832                         pvt->knl.pci_channel[devidx] = pdev;
2833                         break;
2834
2835                 case PCI_DEVICE_ID_INTEL_KNL_IMC_TOLHM:
2836                         pvt->knl.pci_mc_info = pdev;
2837                         break;
2838
2839                 case PCI_DEVICE_ID_INTEL_KNL_IMC_TA:
2840                         pvt->pci_ta = pdev;
2841                         break;
2842
2843                 default:
2844                         sbridge_printk(KERN_ERR, "Unexpected device %d\n",
2845                                 pdev->device);
2846                         break;
2847                 }
2848         }
2849
2850         if (!pvt->knl.pci_mc0  || !pvt->knl.pci_mc1 ||
2851             !pvt->pci_sad0     || !pvt->pci_sad1    ||
2852             !pvt->pci_ta) {
2853                 goto enodev;
2854         }
2855
2856         for (i = 0; i < KNL_MAX_CHANNELS; i++) {
2857                 if (!pvt->knl.pci_channel[i]) {
2858                         sbridge_printk(KERN_ERR, "Missing channel %d\n", i);
2859                         goto enodev;
2860                 }
2861         }
2862
2863         for (i = 0; i < KNL_MAX_CHAS; i++) {
2864                 if (!pvt->knl.pci_cha[i]) {
2865                         sbridge_printk(KERN_ERR, "Missing CHA %d\n", i);
2866                         goto enodev;
2867                 }
2868         }
2869
2870         return 0;
2871
2872 enodev:
2873         sbridge_printk(KERN_ERR, "Some needed devices are missing\n");
2874         return -ENODEV;
2875 }
2876
2877 /****************************************************************************
2878                         Error check routines
2879  ****************************************************************************/
2880
2881 /*
2882  * While Sandy Bridge has error count registers, SMI BIOS read values from
2883  * and resets the counters. So, they are not reliable for the OS to read
2884  * from them. So, we have no option but to just trust on whatever MCE is
2885  * telling us about the errors.
2886  */
2887 static void sbridge_mce_output_error(struct mem_ctl_info *mci,
2888                                     const struct mce *m)
2889 {
2890         struct mem_ctl_info *new_mci;
2891         struct sbridge_pvt *pvt = mci->pvt_info;
2892         enum hw_event_mc_err_type tp_event;
2893         char *type, *optype, msg[256];
2894         bool ripv = GET_BITFIELD(m->mcgstatus, 0, 0);
2895         bool overflow = GET_BITFIELD(m->status, 62, 62);
2896         bool uncorrected_error = GET_BITFIELD(m->status, 61, 61);
2897         bool recoverable;
2898         u32 core_err_cnt = GET_BITFIELD(m->status, 38, 52);
2899         u32 mscod = GET_BITFIELD(m->status, 16, 31);
2900         u32 errcode = GET_BITFIELD(m->status, 0, 15);
2901         u32 channel = GET_BITFIELD(m->status, 0, 3);
2902         u32 optypenum = GET_BITFIELD(m->status, 4, 6);
2903         long channel_mask, first_channel;
2904         u8  rank, socket, ha;
2905         int rc, dimm;
2906         char *area_type = NULL;
2907
2908         if (pvt->info.type != SANDY_BRIDGE)
2909                 recoverable = true;
2910         else
2911                 recoverable = GET_BITFIELD(m->status, 56, 56);
2912
2913         if (uncorrected_error) {
2914                 if (ripv) {
2915                         type = "FATAL";
2916                         tp_event = HW_EVENT_ERR_FATAL;
2917                 } else {
2918                         type = "NON_FATAL";
2919                         tp_event = HW_EVENT_ERR_UNCORRECTED;
2920                 }
2921         } else {
2922                 type = "CORRECTED";
2923                 tp_event = HW_EVENT_ERR_CORRECTED;
2924         }
2925
2926         /*
2927          * According with Table 15-9 of the Intel Architecture spec vol 3A,
2928          * memory errors should fit in this mask:
2929          *      000f 0000 1mmm cccc (binary)
2930          * where:
2931          *      f = Correction Report Filtering Bit. If 1, subsequent errors
2932          *          won't be shown
2933          *      mmm = error type
2934          *      cccc = channel
2935          * If the mask doesn't match, report an error to the parsing logic
2936          */
2937         if (! ((errcode & 0xef80) == 0x80)) {
2938                 optype = "Can't parse: it is not a mem";
2939         } else {
2940                 switch (optypenum) {
2941                 case 0:
2942                         optype = "generic undef request error";
2943                         break;
2944                 case 1:
2945                         optype = "memory read error";
2946                         break;
2947                 case 2:
2948                         optype = "memory write error";
2949                         break;
2950                 case 3:
2951                         optype = "addr/cmd error";
2952                         break;
2953                 case 4:
2954                         optype = "memory scrubbing error";
2955                         break;
2956                 default:
2957                         optype = "reserved";
2958                         break;
2959                 }
2960         }
2961
2962         /* Only decode errors with an valid address (ADDRV) */
2963         if (!GET_BITFIELD(m->status, 58, 58))
2964                 return;
2965
2966         if (pvt->info.type == KNIGHTS_LANDING) {
2967                 if (channel == 14) {
2968                         edac_dbg(0, "%s%s err_code:%04x:%04x EDRAM bank %d\n",
2969                                 overflow ? " OVERFLOW" : "",
2970                                 (uncorrected_error && recoverable)
2971                                 ? " recoverable" : "",
2972                                 mscod, errcode,
2973                                 m->bank);
2974                 } else {
2975                         char A = *("A");
2976
2977                         channel = knl_channel_remap(channel);
2978                         channel_mask = 1 << channel;
2979                         snprintf(msg, sizeof(msg),
2980                                 "%s%s err_code:%04x:%04x channel:%d (DIMM_%c)",
2981                                 overflow ? " OVERFLOW" : "",
2982                                 (uncorrected_error && recoverable)
2983                                 ? " recoverable" : " ",
2984                                 mscod, errcode, channel, A + channel);
2985                         edac_mc_handle_error(tp_event, mci, core_err_cnt,
2986                                 m->addr >> PAGE_SHIFT, m->addr & ~PAGE_MASK, 0,
2987                                 channel, 0, -1,
2988                                 optype, msg);
2989                 }
2990                 return;
2991         } else {
2992                 rc = get_memory_error_data(mci, m->addr, &socket, &ha,
2993                                 &channel_mask, &rank, &area_type, msg);
2994         }
2995
2996         if (rc < 0)
2997                 goto err_parsing;
2998         new_mci = get_mci_for_node_id(socket);
2999         if (!new_mci) {
3000                 strcpy(msg, "Error: socket got corrupted!");
3001                 goto err_parsing;
3002         }
3003         mci = new_mci;
3004         pvt = mci->pvt_info;
3005
3006         first_channel = find_first_bit(&channel_mask, NUM_CHANNELS);
3007
3008         if (rank < 4)
3009                 dimm = 0;
3010         else if (rank < 8)
3011                 dimm = 1;
3012         else
3013                 dimm = 2;
3014
3015
3016         /*
3017          * FIXME: On some memory configurations (mirror, lockstep), the
3018          * Memory Controller can't point the error to a single DIMM. The
3019          * EDAC core should be handling the channel mask, in order to point
3020          * to the group of dimm's where the error may be happening.
3021          */
3022         if (!pvt->is_lockstep && !pvt->is_mirrored && !pvt->is_close_pg)
3023                 channel = first_channel;
3024
3025         snprintf(msg, sizeof(msg),
3026                  "%s%s area:%s err_code:%04x:%04x socket:%d ha:%d channel_mask:%ld rank:%d",
3027                  overflow ? " OVERFLOW" : "",
3028                  (uncorrected_error && recoverable) ? " recoverable" : "",
3029                  area_type,
3030                  mscod, errcode,
3031                  socket, ha,
3032                  channel_mask,
3033                  rank);
3034
3035         edac_dbg(0, "%s\n", msg);
3036
3037         /* FIXME: need support for channel mask */
3038
3039         if (channel == CHANNEL_UNSPECIFIED)
3040                 channel = -1;
3041
3042         /* Call the helper to output message */
3043         edac_mc_handle_error(tp_event, mci, core_err_cnt,
3044                              m->addr >> PAGE_SHIFT, m->addr & ~PAGE_MASK, 0,
3045                              4*ha+channel, dimm, -1,
3046                              optype, msg);
3047         return;
3048 err_parsing:
3049         edac_mc_handle_error(tp_event, mci, core_err_cnt, 0, 0, 0,
3050                              -1, -1, -1,
3051                              msg, "");
3052
3053 }
3054
3055 /*
3056  * Check that logging is enabled and that this is the right type
3057  * of error for us to handle.
3058  */
3059 static int sbridge_mce_check_error(struct notifier_block *nb, unsigned long val,
3060                                    void *data)
3061 {
3062         struct mce *mce = (struct mce *)data;
3063         struct mem_ctl_info *mci;
3064         struct sbridge_pvt *pvt;
3065         char *type;
3066
3067         if (get_edac_report_status() == EDAC_REPORTING_DISABLED)
3068                 return NOTIFY_DONE;
3069
3070         mci = get_mci_for_node_id(mce->socketid);
3071         if (!mci)
3072                 return NOTIFY_BAD;
3073         pvt = mci->pvt_info;
3074
3075         /*
3076          * Just let mcelog handle it if the error is
3077          * outside the memory controller. A memory error
3078          * is indicated by bit 7 = 1 and bits = 8-11,13-15 = 0.
3079          * bit 12 has an special meaning.
3080          */
3081         if ((mce->status & 0xefff) >> 7 != 1)
3082                 return NOTIFY_DONE;
3083
3084         if (mce->mcgstatus & MCG_STATUS_MCIP)
3085                 type = "Exception";
3086         else
3087                 type = "Event";
3088
3089         sbridge_mc_printk(mci, KERN_DEBUG, "HANDLING MCE MEMORY ERROR\n");
3090
3091         sbridge_mc_printk(mci, KERN_DEBUG, "CPU %d: Machine Check %s: %Lx "
3092                           "Bank %d: %016Lx\n", mce->extcpu, type,
3093                           mce->mcgstatus, mce->bank, mce->status);
3094         sbridge_mc_printk(mci, KERN_DEBUG, "TSC %llx ", mce->tsc);
3095         sbridge_mc_printk(mci, KERN_DEBUG, "ADDR %llx ", mce->addr);
3096         sbridge_mc_printk(mci, KERN_DEBUG, "MISC %llx ", mce->misc);
3097
3098         sbridge_mc_printk(mci, KERN_DEBUG, "PROCESSOR %u:%x TIME %llu SOCKET "
3099                           "%u APIC %x\n", mce->cpuvendor, mce->cpuid,
3100                           mce->time, mce->socketid, mce->apicid);
3101
3102         sbridge_mce_output_error(mci, mce);
3103
3104         /* Advice mcelog that the error were handled */
3105         return NOTIFY_STOP;
3106 }
3107
3108 static struct notifier_block sbridge_mce_dec = {
3109         .notifier_call      = sbridge_mce_check_error,
3110 };
3111
3112 /****************************************************************************
3113                         EDAC register/unregister logic
3114  ****************************************************************************/
3115
3116 static void sbridge_unregister_mci(struct sbridge_dev *sbridge_dev)
3117 {
3118         struct mem_ctl_info *mci = sbridge_dev->mci;
3119         struct sbridge_pvt *pvt;
3120
3121         if (unlikely(!mci || !mci->pvt_info)) {
3122                 edac_dbg(0, "MC: dev = %p\n", &sbridge_dev->pdev[0]->dev);
3123
3124                 sbridge_printk(KERN_ERR, "Couldn't find mci handler\n");
3125                 return;
3126         }
3127
3128         pvt = mci->pvt_info;
3129
3130         edac_dbg(0, "MC: mci = %p, dev = %p\n",
3131                  mci, &sbridge_dev->pdev[0]->dev);
3132
3133         /* Remove MC sysfs nodes */
3134         edac_mc_del_mc(mci->pdev);
3135
3136         edac_dbg(1, "%s: free mci struct\n", mci->ctl_name);
3137         kfree(mci->ctl_name);
3138         edac_mc_free(mci);
3139         sbridge_dev->mci = NULL;
3140 }
3141
3142 static int sbridge_register_mci(struct sbridge_dev *sbridge_dev, enum type type)
3143 {
3144         struct mem_ctl_info *mci;
3145         struct edac_mc_layer layers[2];
3146         struct sbridge_pvt *pvt;
3147         struct pci_dev *pdev = sbridge_dev->pdev[0];
3148         int rc;
3149
3150         /* Check the number of active and not disabled channels */
3151         rc = check_if_ecc_is_active(sbridge_dev->bus, type);
3152         if (unlikely(rc < 0))
3153                 return rc;
3154
3155         /* allocate a new MC control structure */
3156         layers[0].type = EDAC_MC_LAYER_CHANNEL;
3157         layers[0].size = type == KNIGHTS_LANDING ?
3158                 KNL_MAX_CHANNELS : NUM_CHANNELS;
3159         layers[0].is_virt_csrow = false;
3160         layers[1].type = EDAC_MC_LAYER_SLOT;
3161         layers[1].size = type == KNIGHTS_LANDING ? 1 : MAX_DIMMS;
3162         layers[1].is_virt_csrow = true;
3163         mci = edac_mc_alloc(sbridge_dev->mc, ARRAY_SIZE(layers), layers,
3164                             sizeof(*pvt));
3165
3166         if (unlikely(!mci))
3167                 return -ENOMEM;
3168
3169         edac_dbg(0, "MC: mci = %p, dev = %p\n",
3170                  mci, &pdev->dev);
3171
3172         pvt = mci->pvt_info;
3173         memset(pvt, 0, sizeof(*pvt));
3174
3175         /* Associate sbridge_dev and mci for future usage */
3176         pvt->sbridge_dev = sbridge_dev;
3177         sbridge_dev->mci = mci;
3178
3179         mci->mtype_cap = type == KNIGHTS_LANDING ?
3180                 MEM_FLAG_DDR4 : MEM_FLAG_DDR3;
3181         mci->edac_ctl_cap = EDAC_FLAG_NONE;
3182         mci->edac_cap = EDAC_FLAG_NONE;
3183         mci->mod_name = "sbridge_edac.c";
3184         mci->mod_ver = SBRIDGE_REVISION;
3185         mci->dev_name = pci_name(pdev);
3186         mci->ctl_page_to_phys = NULL;
3187
3188         pvt->info.type = type;
3189         switch (type) {
3190         case IVY_BRIDGE:
3191                 pvt->info.rankcfgr = IB_RANK_CFG_A;
3192                 pvt->info.get_tolm = ibridge_get_tolm;
3193                 pvt->info.get_tohm = ibridge_get_tohm;
3194                 pvt->info.dram_rule = ibridge_dram_rule;
3195                 pvt->info.get_memory_type = get_memory_type;
3196                 pvt->info.get_node_id = get_node_id;
3197                 pvt->info.rir_limit = rir_limit;
3198                 pvt->info.sad_limit = sad_limit;
3199                 pvt->info.interleave_mode = interleave_mode;
3200                 pvt->info.show_interleave_mode = show_interleave_mode;
3201                 pvt->info.dram_attr = dram_attr;
3202                 pvt->info.max_sad = ARRAY_SIZE(ibridge_dram_rule);
3203                 pvt->info.interleave_list = ibridge_interleave_list;
3204                 pvt->info.max_interleave = ARRAY_SIZE(ibridge_interleave_list);
3205                 pvt->info.interleave_pkg = ibridge_interleave_pkg;
3206                 pvt->info.get_width = ibridge_get_width;
3207                 mci->ctl_name = kasprintf(GFP_KERNEL, "Ivy Bridge Socket#%d", mci->mc_idx);
3208
3209                 /* Store pci devices at mci for faster access */
3210                 rc = ibridge_mci_bind_devs(mci, sbridge_dev);
3211                 if (unlikely(rc < 0))
3212                         goto fail0;
3213                 break;
3214         case SANDY_BRIDGE:
3215                 pvt->info.rankcfgr = SB_RANK_CFG_A;
3216                 pvt->info.get_tolm = sbridge_get_tolm;
3217                 pvt->info.get_tohm = sbridge_get_tohm;
3218                 pvt->info.dram_rule = sbridge_dram_rule;
3219                 pvt->info.get_memory_type = get_memory_type;
3220                 pvt->info.get_node_id = get_node_id;
3221                 pvt->info.rir_limit = rir_limit;
3222                 pvt->info.sad_limit = sad_limit;
3223                 pvt->info.interleave_mode = interleave_mode;
3224                 pvt->info.show_interleave_mode = show_interleave_mode;
3225                 pvt->info.dram_attr = dram_attr;
3226                 pvt->info.max_sad = ARRAY_SIZE(sbridge_dram_rule);
3227                 pvt->info.interleave_list = sbridge_interleave_list;
3228                 pvt->info.max_interleave = ARRAY_SIZE(sbridge_interleave_list);
3229                 pvt->info.interleave_pkg = sbridge_interleave_pkg;
3230                 pvt->info.get_width = sbridge_get_width;
3231                 mci->ctl_name = kasprintf(GFP_KERNEL, "Sandy Bridge Socket#%d", mci->mc_idx);
3232
3233                 /* Store pci devices at mci for faster access */
3234                 rc = sbridge_mci_bind_devs(mci, sbridge_dev);
3235                 if (unlikely(rc < 0))
3236                         goto fail0;
3237                 break;
3238         case HASWELL:
3239                 /* rankcfgr isn't used */
3240                 pvt->info.get_tolm = haswell_get_tolm;
3241                 pvt->info.get_tohm = haswell_get_tohm;
3242                 pvt->info.dram_rule = ibridge_dram_rule;
3243                 pvt->info.get_memory_type = haswell_get_memory_type;
3244                 pvt->info.get_node_id = haswell_get_node_id;
3245                 pvt->info.rir_limit = haswell_rir_limit;
3246                 pvt->info.sad_limit = sad_limit;
3247                 pvt->info.interleave_mode = interleave_mode;
3248                 pvt->info.show_interleave_mode = show_interleave_mode;
3249                 pvt->info.dram_attr = dram_attr;
3250                 pvt->info.max_sad = ARRAY_SIZE(ibridge_dram_rule);
3251                 pvt->info.interleave_list = ibridge_interleave_list;
3252                 pvt->info.max_interleave = ARRAY_SIZE(ibridge_interleave_list);
3253                 pvt->info.interleave_pkg = ibridge_interleave_pkg;
3254                 pvt->info.get_width = ibridge_get_width;
3255                 mci->ctl_name = kasprintf(GFP_KERNEL, "Haswell Socket#%d", mci->mc_idx);
3256
3257                 /* Store pci devices at mci for faster access */
3258                 rc = haswell_mci_bind_devs(mci, sbridge_dev);
3259                 if (unlikely(rc < 0))
3260                         goto fail0;
3261                 break;
3262         case BROADWELL:
3263                 /* rankcfgr isn't used */
3264                 pvt->info.get_tolm = haswell_get_tolm;
3265                 pvt->info.get_tohm = haswell_get_tohm;
3266                 pvt->info.dram_rule = ibridge_dram_rule;
3267                 pvt->info.get_memory_type = haswell_get_memory_type;
3268                 pvt->info.get_node_id = haswell_get_node_id;
3269                 pvt->info.rir_limit = haswell_rir_limit;
3270                 pvt->info.sad_limit = sad_limit;
3271                 pvt->info.interleave_mode = interleave_mode;
3272                 pvt->info.show_interleave_mode = show_interleave_mode;
3273                 pvt->info.dram_attr = dram_attr;
3274                 pvt->info.max_sad = ARRAY_SIZE(ibridge_dram_rule);
3275                 pvt->info.interleave_list = ibridge_interleave_list;
3276                 pvt->info.max_interleave = ARRAY_SIZE(ibridge_interleave_list);
3277                 pvt->info.interleave_pkg = ibridge_interleave_pkg;
3278                 pvt->info.get_width = broadwell_get_width;
3279                 mci->ctl_name = kasprintf(GFP_KERNEL, "Broadwell Socket#%d", mci->mc_idx);
3280
3281                 /* Store pci devices at mci for faster access */
3282                 rc = broadwell_mci_bind_devs(mci, sbridge_dev);
3283                 if (unlikely(rc < 0))
3284                         goto fail0;
3285                 break;
3286         case KNIGHTS_LANDING:
3287                 /* pvt->info.rankcfgr == ??? */
3288                 pvt->info.get_tolm = knl_get_tolm;
3289                 pvt->info.get_tohm = knl_get_tohm;
3290                 pvt->info.dram_rule = knl_dram_rule;
3291                 pvt->info.get_memory_type = knl_get_memory_type;
3292                 pvt->info.get_node_id = knl_get_node_id;
3293                 pvt->info.rir_limit = NULL;
3294                 pvt->info.sad_limit = knl_sad_limit;
3295                 pvt->info.interleave_mode = knl_interleave_mode;
3296                 pvt->info.show_interleave_mode = knl_show_interleave_mode;
3297                 pvt->info.dram_attr = dram_attr_knl;
3298                 pvt->info.max_sad = ARRAY_SIZE(knl_dram_rule);
3299                 pvt->info.interleave_list = knl_interleave_list;
3300                 pvt->info.max_interleave = ARRAY_SIZE(knl_interleave_list);
3301                 pvt->info.interleave_pkg = ibridge_interleave_pkg;
3302                 pvt->info.get_width = knl_get_width;
3303                 mci->ctl_name = kasprintf(GFP_KERNEL,
3304                         "Knights Landing Socket#%d", mci->mc_idx);
3305
3306                 rc = knl_mci_bind_devs(mci, sbridge_dev);
3307                 if (unlikely(rc < 0))
3308                         goto fail0;
3309                 break;
3310         }
3311
3312         /* Get dimm basic config and the memory layout */
3313         get_dimm_config(mci);
3314         get_memory_layout(mci);
3315
3316         /* record ptr to the generic device */
3317         mci->pdev = &pdev->dev;
3318
3319         /* add this new MC control structure to EDAC's list of MCs */
3320         if (unlikely(edac_mc_add_mc(mci))) {
3321                 edac_dbg(0, "MC: failed edac_mc_add_mc()\n");
3322                 rc = -EINVAL;
3323                 goto fail0;
3324         }
3325
3326         return 0;
3327
3328 fail0:
3329         kfree(mci->ctl_name);
3330         edac_mc_free(mci);
3331         sbridge_dev->mci = NULL;
3332         return rc;
3333 }
3334
3335 #define ICPU(model, table) \
3336         { X86_VENDOR_INTEL, 6, model, 0, (unsigned long)&table }
3337
3338 /* Order here must match "enum type" */
3339 static const struct x86_cpu_id sbridge_cpuids[] = {
3340         ICPU(0x2d, pci_dev_descr_sbridge_table),        /* SANDY_BRIDGE */
3341         ICPU(0x3e, pci_dev_descr_ibridge_table),        /* IVY_BRIDGE */
3342         ICPU(0x3f, pci_dev_descr_haswell_table),        /* HASWELL */
3343         ICPU(0x4f, pci_dev_descr_broadwell_table),      /* BROADWELL */
3344         ICPU(0x57, pci_dev_descr_knl_table),            /* KNIGHTS_LANDING */
3345         { }
3346 };
3347 MODULE_DEVICE_TABLE(x86cpu, sbridge_cpuids);
3348
3349 /*
3350  *      sbridge_probe   Get all devices and register memory controllers
3351  *                      present.
3352  *      return:
3353  *              0 for FOUND a device
3354  *              < 0 for error code
3355  */
3356
3357 static int sbridge_probe(const struct x86_cpu_id *id)
3358 {
3359         int rc = -ENODEV;
3360         u8 mc, num_mc = 0;
3361         struct sbridge_dev *sbridge_dev;
3362         struct pci_id_table *ptable = (struct pci_id_table *)id->driver_data;
3363
3364         /* get the pci devices we want to reserve for our use */
3365         rc = sbridge_get_all_devices(&num_mc, ptable);
3366
3367         if (unlikely(rc < 0)) {
3368                 edac_dbg(0, "couldn't get all devices\n");
3369                 goto fail0;
3370         }
3371
3372         mc = 0;
3373
3374         list_for_each_entry(sbridge_dev, &sbridge_edac_list, list) {
3375                 edac_dbg(0, "Registering MC#%d (%d of %d)\n",
3376                          mc, mc + 1, num_mc);
3377
3378                 sbridge_dev->mc = mc++;
3379                 rc = sbridge_register_mci(sbridge_dev, id - sbridge_cpuids);
3380                 if (unlikely(rc < 0))
3381                         goto fail1;
3382         }
3383
3384         sbridge_printk(KERN_INFO, "%s\n", SBRIDGE_REVISION);
3385
3386         return 0;
3387
3388 fail1:
3389         list_for_each_entry(sbridge_dev, &sbridge_edac_list, list)
3390                 sbridge_unregister_mci(sbridge_dev);
3391
3392         sbridge_put_all_devices();
3393 fail0:
3394         return rc;
3395 }
3396
3397 /*
3398  *      sbridge_remove  cleanup
3399  *
3400  */
3401 static void sbridge_remove(void)
3402 {
3403         struct sbridge_dev *sbridge_dev;
3404
3405         edac_dbg(0, "\n");
3406
3407         list_for_each_entry(sbridge_dev, &sbridge_edac_list, list)
3408                 sbridge_unregister_mci(sbridge_dev);
3409
3410         /* Release PCI resources */
3411         sbridge_put_all_devices();
3412 }
3413
3414 /*
3415  *      sbridge_init            Module entry function
3416  *                      Try to initialize this module for its devices
3417  */
3418 static int __init sbridge_init(void)
3419 {
3420         const struct x86_cpu_id *id;
3421         int rc;
3422
3423         edac_dbg(2, "\n");
3424
3425         id = x86_match_cpu(sbridge_cpuids);
3426         if (!id)
3427                 return -ENODEV;
3428
3429         /* Ensure that the OPSTATE is set correctly for POLL or NMI */
3430         opstate_init();
3431
3432         rc = sbridge_probe(id);
3433
3434         if (rc >= 0) {
3435                 mce_register_decode_chain(&sbridge_mce_dec);
3436                 if (get_edac_report_status() == EDAC_REPORTING_DISABLED)
3437                         sbridge_printk(KERN_WARNING, "Loading driver, error reporting disabled.\n");
3438                 return 0;
3439         }
3440
3441         sbridge_printk(KERN_ERR, "Failed to register device with error %d.\n",
3442                       rc);
3443
3444         return rc;
3445 }
3446
3447 /*
3448  *      sbridge_exit()  Module exit function
3449  *                      Unregister the driver
3450  */
3451 static void __exit sbridge_exit(void)
3452 {
3453         edac_dbg(2, "\n");
3454         sbridge_remove();
3455         mce_unregister_decode_chain(&sbridge_mce_dec);
3456 }
3457
3458 module_init(sbridge_init);
3459 module_exit(sbridge_exit);
3460
3461 module_param(edac_op_state, int, 0444);
3462 MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");
3463
3464 MODULE_LICENSE("GPL");
3465 MODULE_AUTHOR("Mauro Carvalho Chehab");
3466 MODULE_AUTHOR("Red Hat Inc. (http://www.redhat.com)");
3467 MODULE_DESCRIPTION("MC Driver for Intel Sandy Bridge and Ivy Bridge memory controllers - "
3468                    SBRIDGE_REVISION);