2 * AMD 76x Memory Controller kernel module
3 * (C) 2003 Linux Networx (http://lnxi.com)
4 * This file may be distributed under the terms of the
5 * GNU General Public License.
7 * Written by Thayne Harbaugh
8 * Based on work by Dan Hollis <goemon at anime dot net> and others.
9 * http://www.anime.net/~goemon/linux-ecc/
11 * $Id: edac_amd76x.c,v 1.4.2.5 2005/10/05 00:43:44 dsp_llnl Exp $
15 #include <linux/config.h>
16 #include <linux/module.h>
17 #include <linux/init.h>
18 #include <linux/pci.h>
19 #include <linux/pci_ids.h>
20 #include <linux/slab.h>
23 #define AMD76X_REVISION " Ver: 2.0.0 " __DATE__
26 #define amd76x_printk(level, fmt, arg...) \
27 edac_printk(level, "amd76x", fmt, ##arg)
29 #define amd76x_mc_printk(mci, level, fmt, arg...) \
30 edac_mc_chipset_printk(mci, level, "amd76x", fmt, ##arg)
32 #define AMD76X_NR_CSROWS 8
33 #define AMD76X_NR_CHANS 1
34 #define AMD76X_NR_DIMMS 4
36 /* AMD 76x register addresses - device 0 function 0 - PCI bridge */
38 #define AMD76X_ECC_MODE_STATUS 0x48 /* Mode and status of ECC (32b)
41 * 15:14 SERR enabled: x1=ue 1x=ce
43 * 12 diag: disabled, enabled
44 * 11:10 mode: dis, EC, ECC, ECC+scrub
45 * 9:8 status: x1=ue 1x=ce
50 #define AMD76X_DRAM_MODE_STATUS 0x58 /* DRAM Mode and status (32b)
52 * 31:26 clock disable 5 - 0
55 * 23 mode register service
56 * 22:21 suspend to RAM
57 * 20 burst refresh enable
60 * 17:16 cycles-per-refresh
62 * 7:0 x4 mode enable 7 - 0
65 #define AMD76X_MEM_BASE_ADDR 0xC0 /* Memory base address (8 x 32b)
67 * 31:23 chip-select base
69 * 15:7 chip-select mask
72 * 0 chip-select enable
75 struct amd76x_error_info {
84 struct amd76x_dev_info {
88 static const struct amd76x_dev_info amd76x_devs[] = {
98 * amd76x_get_error_info - fetch error information
99 * @mci: Memory controller
100 * @info: Info to fill in
102 * Fetch and store the AMD76x ECC status. Clear pending status
103 * on the chip so that further errors will be reported
105 static void amd76x_get_error_info(struct mem_ctl_info *mci,
106 struct amd76x_error_info *info)
108 struct pci_dev *pdev;
110 pdev = to_pci_dev(mci->dev);
111 pci_read_config_dword(pdev, AMD76X_ECC_MODE_STATUS,
112 &info->ecc_mode_status);
114 if (info->ecc_mode_status & BIT(8))
115 pci_write_bits32(pdev, AMD76X_ECC_MODE_STATUS,
116 (u32) BIT(8), (u32) BIT(8));
118 if (info->ecc_mode_status & BIT(9))
119 pci_write_bits32(pdev, AMD76X_ECC_MODE_STATUS,
120 (u32) BIT(9), (u32) BIT(9));
124 * amd76x_process_error_info - Error check
125 * @mci: Memory controller
126 * @info: Previously fetched information from chip
127 * @handle_errors: 1 if we should do recovery
129 * Process the chip state and decide if an error has occurred.
130 * A return of 1 indicates an error. Also if handle_errors is true
131 * then attempt to handle and clean up after the error
133 static int amd76x_process_error_info(struct mem_ctl_info *mci,
134 struct amd76x_error_info *info, int handle_errors)
142 * Check for an uncorrectable error
144 if (info->ecc_mode_status & BIT(8)) {
148 row = (info->ecc_mode_status >> 4) & 0xf;
149 edac_mc_handle_ue(mci, mci->csrows[row].first_page, 0,
155 * Check for a correctable error
157 if (info->ecc_mode_status & BIT(9)) {
161 row = info->ecc_mode_status & 0xf;
162 edac_mc_handle_ce(mci, mci->csrows[row].first_page, 0,
163 0, row, 0, mci->ctl_name);
171 * amd76x_check - Poll the controller
172 * @mci: Memory controller
174 * Called by the poll handlers this function reads the status
175 * from the controller and checks for errors.
177 static void amd76x_check(struct mem_ctl_info *mci)
179 struct amd76x_error_info info;
180 debugf3("%s()\n", __func__);
181 amd76x_get_error_info(mci, &info);
182 amd76x_process_error_info(mci, &info, 1);
185 static void amd76x_init_csrows(struct mem_ctl_info *mci, struct pci_dev *pdev,
186 enum edac_type edac_mode)
188 struct csrow_info *csrow;
189 u32 mba, mba_base, mba_mask, dms;
192 for (index = 0; index < mci->nr_csrows; index++) {
193 csrow = &mci->csrows[index];
195 /* find the DRAM Chip Select Base address and mask */
196 pci_read_config_dword(pdev,
197 AMD76X_MEM_BASE_ADDR + (index * 4),
203 mba_base = mba & 0xff800000UL;
204 mba_mask = ((mba & 0xff80) << 16) | 0x7fffffUL;
205 pci_read_config_dword(pdev, AMD76X_DRAM_MODE_STATUS, &dms);
206 csrow->first_page = mba_base >> PAGE_SHIFT;
207 csrow->nr_pages = (mba_mask + 1) >> PAGE_SHIFT;
208 csrow->last_page = csrow->first_page + csrow->nr_pages - 1;
209 csrow->page_mask = mba_mask >> PAGE_SHIFT;
210 csrow->grain = csrow->nr_pages << PAGE_SHIFT;
211 csrow->mtype = MEM_RDDR;
212 csrow->dtype = ((dms >> index) & 0x1) ? DEV_X4 : DEV_UNKNOWN;
213 csrow->edac_mode = edac_mode;
218 * amd76x_probe1 - Perform set up for detected device
219 * @pdev; PCI device detected
220 * @dev_idx: Device type index
222 * We have found an AMD76x and now need to set up the memory
223 * controller status reporting. We configure and set up the
224 * memory controller reporting and claim the device.
226 static int amd76x_probe1(struct pci_dev *pdev, int dev_idx)
228 static const enum edac_type ems_modes[] = {
234 struct mem_ctl_info *mci = NULL;
237 struct amd76x_error_info discard;
239 debugf0("%s()\n", __func__);
240 pci_read_config_dword(pdev, AMD76X_ECC_MODE_STATUS, &ems);
241 ems_mode = (ems >> 10) & 0x3;
242 mci = edac_mc_alloc(0, AMD76X_NR_CSROWS, AMD76X_NR_CHANS);
248 debugf0("%s(): mci = %p\n", __func__, mci);
249 mci->dev = &pdev->dev;
250 mci->mtype_cap = MEM_FLAG_RDDR;
251 mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_EC | EDAC_FLAG_SECDED;
252 mci->edac_cap = ems_mode ?
253 (EDAC_FLAG_EC | EDAC_FLAG_SECDED) : EDAC_FLAG_NONE;
254 mci->mod_name = EDAC_MOD_STR;
255 mci->mod_ver = AMD76X_REVISION;
256 mci->ctl_name = amd76x_devs[dev_idx].ctl_name;
257 mci->edac_check = amd76x_check;
258 mci->ctl_page_to_phys = NULL;
260 amd76x_init_csrows(mci, pdev, ems_modes[ems_mode]);
261 amd76x_get_error_info(mci, &discard); /* clear counters */
263 /* Here we assume that we will never see multiple instances of this
264 * type of memory controller. The ID is therefore hardcoded to 0.
266 if (edac_mc_add_mc(mci,0)) {
267 debugf3("%s(): failed edac_mc_add_mc()\n", __func__);
271 /* get this far and it's successful */
272 debugf3("%s(): success\n", __func__);
280 /* returns count (>= 0), or negative on error */
281 static int __devinit amd76x_init_one(struct pci_dev *pdev,
282 const struct pci_device_id *ent)
284 debugf0("%s()\n", __func__);
286 /* don't need to call pci_device_enable() */
287 return amd76x_probe1(pdev, ent->driver_data);
291 * amd76x_remove_one - driver shutdown
292 * @pdev: PCI device being handed back
294 * Called when the driver is unloaded. Find the matching mci
295 * structure for the device then delete the mci and free the
298 static void __devexit amd76x_remove_one(struct pci_dev *pdev)
300 struct mem_ctl_info *mci;
302 debugf0("%s()\n", __func__);
304 if ((mci = edac_mc_del_mc(&pdev->dev)) == NULL)
310 static const struct pci_device_id amd76x_pci_tbl[] __devinitdata = {
312 PCI_VEND_DEV(AMD, FE_GATE_700C), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
316 PCI_VEND_DEV(AMD, FE_GATE_700E), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
321 } /* 0 terminated list. */
324 MODULE_DEVICE_TABLE(pci, amd76x_pci_tbl);
326 static struct pci_driver amd76x_driver = {
327 .name = EDAC_MOD_STR,
328 .probe = amd76x_init_one,
329 .remove = __devexit_p(amd76x_remove_one),
330 .id_table = amd76x_pci_tbl,
333 static int __init amd76x_init(void)
335 return pci_register_driver(&amd76x_driver);
338 static void __exit amd76x_exit(void)
340 pci_unregister_driver(&amd76x_driver);
343 module_init(amd76x_init);
344 module_exit(amd76x_exit);
346 MODULE_LICENSE("GPL");
347 MODULE_AUTHOR("Linux Networx (http://lnxi.com) Thayne Harbaugh");
348 MODULE_DESCRIPTION("MC support for AMD 76x memory controllers");