drivers/edac/altera_edac.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  *  Copyright (C) 2017-2018, Intel Corporation. All rights reserved
   4  *  Copyright Altera Corporation (C) 2014-2016. All rights reserved.
   5  *  Copyright 2011-2012 Calxeda, Inc.
   6  */
   7
   8 #include <asm/cacheflush.h>
   9 #include <linux/ctype.h>
  10 #include <linux/delay.h>
  11 #include <linux/edac.h>
  12 #include <linux/genalloc.h>
  13 #include <linux/interrupt.h>
  14 #include <linux/irqchip/chained_irq.h>
  15 #include <linux/kernel.h>
  16 #include <linux/mfd/syscon.h>
  17 #include <linux/notifier.h>
  18 #include <linux/of_address.h>
  19 #include <linux/of_irq.h>
  20 #include <linux/of_platform.h>
  21 #include <linux/platform_device.h>
  22 #include <linux/regmap.h>
  23 #include <linux/types.h>
  24 #include <linux/uaccess.h>
  25
  26 #include "altera_edac.h"
  27 #include "edac_module.h"
  28
  29 #define EDAC_MOD_STR            "altera_edac"
  30 #define EDAC_DEVICE             "Altera"
  31
  32 static const struct altr_sdram_prv_data c5_data = {
  33         .ecc_ctrl_offset    = CV_CTLCFG_OFST,
  34         .ecc_ctl_en_mask    = CV_CTLCFG_ECC_AUTO_EN,
  35         .ecc_stat_offset    = CV_DRAMSTS_OFST,
  36         .ecc_stat_ce_mask   = CV_DRAMSTS_SBEERR,
  37         .ecc_stat_ue_mask   = CV_DRAMSTS_DBEERR,
  38         .ecc_saddr_offset   = CV_ERRADDR_OFST,
  39         .ecc_daddr_offset   = CV_ERRADDR_OFST,
  40         .ecc_cecnt_offset   = CV_SBECOUNT_OFST,
  41         .ecc_uecnt_offset   = CV_DBECOUNT_OFST,
  42         .ecc_irq_en_offset  = CV_DRAMINTR_OFST,
  43         .ecc_irq_en_mask    = CV_DRAMINTR_INTREN,
  44         .ecc_irq_clr_offset = CV_DRAMINTR_OFST,
  45         .ecc_irq_clr_mask   = (CV_DRAMINTR_INTRCLR | CV_DRAMINTR_INTREN),
  46         .ecc_cnt_rst_offset = CV_DRAMINTR_OFST,
  47         .ecc_cnt_rst_mask   = CV_DRAMINTR_INTRCLR,
  48         .ce_ue_trgr_offset  = CV_CTLCFG_OFST,
  49         .ce_set_mask        = CV_CTLCFG_GEN_SB_ERR,
  50         .ue_set_mask        = CV_CTLCFG_GEN_DB_ERR,
  51 };
  52
  53 static const struct altr_sdram_prv_data a10_data = {
  54         .ecc_ctrl_offset    = A10_ECCCTRL1_OFST,
  55         .ecc_ctl_en_mask    = A10_ECCCTRL1_ECC_EN,
  56         .ecc_stat_offset    = A10_INTSTAT_OFST,
  57         .ecc_stat_ce_mask   = A10_INTSTAT_SBEERR,
  58         .ecc_stat_ue_mask   = A10_INTSTAT_DBEERR,
  59         .ecc_saddr_offset   = A10_SERRADDR_OFST,
  60         .ecc_daddr_offset   = A10_DERRADDR_OFST,
  61         .ecc_irq_en_offset  = A10_ERRINTEN_OFST,
  62         .ecc_irq_en_mask    = A10_ECC_IRQ_EN_MASK,
  63         .ecc_irq_clr_offset = A10_INTSTAT_OFST,
  64         .ecc_irq_clr_mask   = (A10_INTSTAT_SBEERR | A10_INTSTAT_DBEERR),
  65         .ecc_cnt_rst_offset = A10_ECCCTRL1_OFST,
  66         .ecc_cnt_rst_mask   = A10_ECC_CNT_RESET_MASK,
  67         .ce_ue_trgr_offset  = A10_DIAGINTTEST_OFST,
  68         .ce_set_mask        = A10_DIAGINT_TSERRA_MASK,
  69         .ue_set_mask        = A10_DIAGINT_TDERRA_MASK,
  70 };
  71
  72 /*********************** EDAC Memory Controller Functions ****************/
  73
  74 /* The SDRAM controller uses the EDAC Memory Controller framework.       */
  75
  76 static irqreturn_t altr_sdram_mc_err_handler(int irq, void *dev_id)
  77 {
  78         struct mem_ctl_info *mci = dev_id;
  79         struct altr_sdram_mc_data *drvdata = mci->pvt_info;
  80         const struct altr_sdram_prv_data *priv = drvdata->data;
  81         u32 status, err_count = 1, err_addr;
  82
  83         regmap_read(drvdata->mc_vbase, priv->ecc_stat_offset, &status);
  84
  85         if (status & priv->ecc_stat_ue_mask) {
  86                 regmap_read(drvdata->mc_vbase, priv->ecc_daddr_offset,
  87                             &err_addr);
  88                 if (priv->ecc_uecnt_offset)
  89                         regmap_read(drvdata->mc_vbase, priv->ecc_uecnt_offset,
  90                                     &err_count);
  91                 panic("\nEDAC: [%d Uncorrectable errors @ 0x%08X]\n",
  92                       err_count, err_addr);
  93         }
  94         if (status & priv->ecc_stat_ce_mask) {
  95                 regmap_read(drvdata->mc_vbase, priv->ecc_saddr_offset,
  96                             &err_addr);
  97                 if (priv->ecc_uecnt_offset)
  98                         regmap_read(drvdata->mc_vbase,  priv->ecc_cecnt_offset,
  99                                     &err_count);
 100                 edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, err_count,
 101                                      err_addr >> PAGE_SHIFT,
 102                                      err_addr & ~PAGE_MASK, 0,
 103                                      0, 0, -1, mci->ctl_name, "");
 104                 /* Clear IRQ to resume */
 105                 regmap_write(drvdata->mc_vbase, priv->ecc_irq_clr_offset,
 106                              priv->ecc_irq_clr_mask);
 107
 108                 return IRQ_HANDLED;
 109         }
 110         return IRQ_NONE;
 111 }
 112
 113 static ssize_t altr_sdr_mc_err_inject_write(struct file *file,
 114                                             const char __user *data,
 115                                             size_t count, loff_t *ppos)
 116 {
 117         struct mem_ctl_info *mci = file->private_data;
 118         struct altr_sdram_mc_data *drvdata = mci->pvt_info;
 119         const struct altr_sdram_prv_data *priv = drvdata->data;
 120         u32 *ptemp;
 121         dma_addr_t dma_handle;
 122         u32 reg, read_reg;
 123
 124         ptemp = dma_alloc_coherent(mci->pdev, 16, &dma_handle, GFP_KERNEL);
 125         if (!ptemp) {
 126                 dma_free_coherent(mci->pdev, 16, ptemp, dma_handle);
 127                 edac_printk(KERN_ERR, EDAC_MC,
 128                             "Inject: Buffer Allocation error\n");
 129                 return -ENOMEM;
 130         }
 131
 132         regmap_read(drvdata->mc_vbase, priv->ce_ue_trgr_offset,
 133                     &read_reg);
 134         read_reg &= ~(priv->ce_set_mask | priv->ue_set_mask);
 135
 136         /* Error are injected by writing a word while the SBE or DBE
 137          * bit in the CTLCFG register is set. Reading the word will
 138          * trigger the SBE or DBE error and the corresponding IRQ.
 139          */
 140         if (count == 3) {
 141                 edac_printk(KERN_ALERT, EDAC_MC,
 142                             "Inject Double bit error\n");
 143                 local_irq_disable();
 144                 regmap_write(drvdata->mc_vbase, priv->ce_ue_trgr_offset,
 145                              (read_reg | priv->ue_set_mask));
 146                 local_irq_enable();
 147         } else {
 148                 edac_printk(KERN_ALERT, EDAC_MC,
 149                             "Inject Single bit error\n");
 150                 local_irq_disable();
 151                 regmap_write(drvdata->mc_vbase, priv->ce_ue_trgr_offset,
 152                              (read_reg | priv->ce_set_mask));
 153                 local_irq_enable();
 154         }
 155
 156         ptemp[0] = 0x5A5A5A5A;
 157         ptemp[1] = 0xA5A5A5A5;
 158
 159         /* Clear the error injection bits */
 160         regmap_write(drvdata->mc_vbase, priv->ce_ue_trgr_offset, read_reg);
 161         /* Ensure it has been written out */
 162         wmb();
 163
 164         /*
 165          * To trigger the error, we need to read the data back
 166          * (the data was written with errors above).
 167          * The READ_ONCE macros and printk are used to prevent the
 168          * the compiler optimizing these reads out.
 169          */
 170         reg = READ_ONCE(ptemp[0]);
 171         read_reg = READ_ONCE(ptemp[1]);
 172         /* Force Read */
 173         rmb();
 174
 175         edac_printk(KERN_ALERT, EDAC_MC, "Read Data [0x%X, 0x%X]\n",
 176                     reg, read_reg);
 177
 178         dma_free_coherent(mci->pdev, 16, ptemp, dma_handle);
 179
 180         return count;
 181 }
 182
 183 static const struct file_operations altr_sdr_mc_debug_inject_fops = {
 184         .open = simple_open,
 185         .write = altr_sdr_mc_err_inject_write,
 186         .llseek = generic_file_llseek,
 187 };
 188
 189 static void altr_sdr_mc_create_debugfs_nodes(struct mem_ctl_info *mci)
 190 {
 191         if (!IS_ENABLED(CONFIG_EDAC_DEBUG))
 192                 return;
 193
 194         if (!mci->debugfs)
 195                 return;
 196
 197         edac_debugfs_create_file("altr_trigger", S_IWUSR, mci->debugfs, mci,
 198                                  &altr_sdr_mc_debug_inject_fops);
 199 }
 200
 201 /* Get total memory size from Open Firmware DTB */
 202 static unsigned long get_total_mem(void)
 203 {
 204         struct device_node *np = NULL;
 205         struct resource res;
 206         int ret;
 207         unsigned long total_mem = 0;
 208
 209         for_each_node_by_type(np, "memory") {
 210                 ret = of_address_to_resource(np, 0, &res);
 211                 if (ret)
 212                         continue;
 213
 214                 total_mem += resource_size(&res);
 215         }
 216         edac_dbg(0, "total_mem 0x%lx\n", total_mem);
 217         return total_mem;
 218 }
 219
 220 static const struct of_device_id altr_sdram_ctrl_of_match[] = {
 221         { .compatible = "altr,sdram-edac", .data = &c5_data},
 222         { .compatible = "altr,sdram-edac-a10", .data = &a10_data},
 223         { .compatible = "altr,sdram-edac-s10", .data = &a10_data},
 224         {},
 225 };
 226 MODULE_DEVICE_TABLE(of, altr_sdram_ctrl_of_match);
 227
 228 static int a10_init(struct regmap *mc_vbase)
 229 {
 230         if (regmap_update_bits(mc_vbase, A10_INTMODE_OFST,
 231                                A10_INTMODE_SB_INT, A10_INTMODE_SB_INT)) {
 232                 edac_printk(KERN_ERR, EDAC_MC,
 233                             "Error setting SB IRQ mode\n");
 234                 return -ENODEV;
 235         }
 236
 237         if (regmap_write(mc_vbase, A10_SERRCNTREG_OFST, 1)) {
 238                 edac_printk(KERN_ERR, EDAC_MC,
 239                             "Error setting trigger count\n");
 240                 return -ENODEV;
 241         }
 242
 243         return 0;
 244 }
 245
 246 static int a10_unmask_irq(struct platform_device *pdev, u32 mask)
 247 {
 248         void __iomem  *sm_base;
 249         int  ret = 0;
 250
 251         if (!request_mem_region(A10_SYMAN_INTMASK_CLR, sizeof(u32),
 252                                 dev_name(&pdev->dev))) {
 253                 edac_printk(KERN_ERR, EDAC_MC,
 254                             "Unable to request mem region\n");
 255                 return -EBUSY;
 256         }
 257
 258         sm_base = ioremap(A10_SYMAN_INTMASK_CLR, sizeof(u32));
 259         if (!sm_base) {
 260                 edac_printk(KERN_ERR, EDAC_MC,
 261                             "Unable to ioremap device\n");
 262
 263                 ret = -ENOMEM;
 264                 goto release;
 265         }
 266
 267         iowrite32(mask, sm_base);
 268
 269         iounmap(sm_base);
 270
 271 release:
 272         release_mem_region(A10_SYMAN_INTMASK_CLR, sizeof(u32));
 273
 274         return ret;
 275 }
 276
 277 static int socfpga_is_a10(void);
 278 static int altr_sdram_probe(struct platform_device *pdev)
 279 {
 280         const struct of_device_id *id;
 281         struct edac_mc_layer layers[2];
 282         struct mem_ctl_info *mci;
 283         struct altr_sdram_mc_data *drvdata;
 284         const struct altr_sdram_prv_data *priv;
 285         struct regmap *mc_vbase;
 286         struct dimm_info *dimm;
 287         u32 read_reg;
 288         int irq, irq2, res = 0;
 289         unsigned long mem_size, irqflags = 0;
 290
 291         id = of_match_device(altr_sdram_ctrl_of_match, &pdev->dev);
 292         if (!id)
 293                 return -ENODEV;
 294
 295         /* Grab the register range from the sdr controller in device tree */
 296         mc_vbase = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
 297                                                    "altr,sdr-syscon");
 298         if (IS_ERR(mc_vbase)) {
 299                 edac_printk(KERN_ERR, EDAC_MC,
 300                             "regmap for altr,sdr-syscon lookup failed.\n");
 301                 return -ENODEV;
 302         }
 303
 304         /* Check specific dependencies for the module */
 305         priv = of_match_node(altr_sdram_ctrl_of_match,
 306                              pdev->dev.of_node)->data;
 307
 308         /* Validate the SDRAM controller has ECC enabled */
 309         if (regmap_read(mc_vbase, priv->ecc_ctrl_offset, &read_reg) ||
 310             ((read_reg & priv->ecc_ctl_en_mask) != priv->ecc_ctl_en_mask)) {
 311                 edac_printk(KERN_ERR, EDAC_MC,
 312                             "No ECC/ECC disabled [0x%08X]\n", read_reg);
 313                 return -ENODEV;
 314         }
 315
 316         /* Grab memory size from device tree. */
 317         mem_size = get_total_mem();
 318         if (!mem_size) {
 319                 edac_printk(KERN_ERR, EDAC_MC, "Unable to calculate memory size\n");
 320                 return -ENODEV;
 321         }
 322
 323         /* Ensure the SDRAM Interrupt is disabled */
 324         if (regmap_update_bits(mc_vbase, priv->ecc_irq_en_offset,
 325                                priv->ecc_irq_en_mask, 0)) {
 326                 edac_printk(KERN_ERR, EDAC_MC,
 327                             "Error disabling SDRAM ECC IRQ\n");
 328                 return -ENODEV;
 329         }
 330
 331         /* Toggle to clear the SDRAM Error count */
 332         if (regmap_update_bits(mc_vbase, priv->ecc_cnt_rst_offset,
 333                                priv->ecc_cnt_rst_mask,
 334                                priv->ecc_cnt_rst_mask)) {
 335                 edac_printk(KERN_ERR, EDAC_MC,
 336                             "Error clearing SDRAM ECC count\n");
 337                 return -ENODEV;
 338         }
 339
 340         if (regmap_update_bits(mc_vbase, priv->ecc_cnt_rst_offset,
 341                                priv->ecc_cnt_rst_mask, 0)) {
 342                 edac_printk(KERN_ERR, EDAC_MC,
 343                             "Error clearing SDRAM ECC count\n");
 344                 return -ENODEV;
 345         }
 346
 347         irq = platform_get_irq(pdev, 0);
 348         if (irq < 0) {
 349                 edac_printk(KERN_ERR, EDAC_MC,
 350                             "No irq %d in DT\n", irq);
 351                 return -ENODEV;
 352         }
 353
 354         /* Arria10 has a 2nd IRQ */
 355         irq2 = platform_get_irq(pdev, 1);
 356
 357         layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
 358         layers[0].size = 1;
 359         layers[0].is_virt_csrow = true;
 360         layers[1].type = EDAC_MC_LAYER_CHANNEL;
 361         layers[1].size = 1;
 362         layers[1].is_virt_csrow = false;
 363         mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers,
 364                             sizeof(struct altr_sdram_mc_data));
 365         if (!mci)
 366                 return -ENOMEM;
 367
 368         mci->pdev = &pdev->dev;
 369         drvdata = mci->pvt_info;
 370         drvdata->mc_vbase = mc_vbase;
 371         drvdata->data = priv;
 372         platform_set_drvdata(pdev, mci);
 373
 374         if (!devres_open_group(&pdev->dev, NULL, GFP_KERNEL)) {
 375                 edac_printk(KERN_ERR, EDAC_MC,
 376                             "Unable to get managed device resource\n");
 377                 res = -ENOMEM;
 378                 goto free;
 379         }
 380
 381         mci->mtype_cap = MEM_FLAG_DDR3;
 382         mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED;
 383         mci->edac_cap = EDAC_FLAG_SECDED;
 384         mci->mod_name = EDAC_MOD_STR;
 385         mci->ctl_name = dev_name(&pdev->dev);
 386         mci->scrub_mode = SCRUB_SW_SRC;
 387         mci->dev_name = dev_name(&pdev->dev);
 388
 389         dimm = *mci->dimms;
 390         dimm->nr_pages = ((mem_size - 1) >> PAGE_SHIFT) + 1;
 391         dimm->grain = 8;
 392         dimm->dtype = DEV_X8;
 393         dimm->mtype = MEM_DDR3;
 394         dimm->edac_mode = EDAC_SECDED;
 395
 396         res = edac_mc_add_mc(mci);
 397         if (res < 0)
 398                 goto err;
 399
 400         /* Only the Arria10 has separate IRQs */
 401         if (socfpga_is_a10()) {
 402                 /* Arria10 specific initialization */
 403                 res = a10_init(mc_vbase);
 404                 if (res < 0)
 405                         goto err2;
 406
 407                 res = devm_request_irq(&pdev->dev, irq2,
 408                                        altr_sdram_mc_err_handler,
 409                                        IRQF_SHARED, dev_name(&pdev->dev), mci);
 410                 if (res < 0) {
 411                         edac_mc_printk(mci, KERN_ERR,
 412                                        "Unable to request irq %d\n", irq2);
 413                         res = -ENODEV;
 414                         goto err2;
 415                 }
 416
 417                 res = a10_unmask_irq(pdev, A10_DDR0_IRQ_MASK);
 418                 if (res < 0)
 419                         goto err2;
 420
 421                 irqflags = IRQF_SHARED;
 422         }
 423
 424         res = devm_request_irq(&pdev->dev, irq, altr_sdram_mc_err_handler,
 425                                irqflags, dev_name(&pdev->dev), mci);
 426         if (res < 0) {
 427                 edac_mc_printk(mci, KERN_ERR,
 428                                "Unable to request irq %d\n", irq);
 429                 res = -ENODEV;
 430                 goto err2;
 431         }
 432
 433         /* Infrastructure ready - enable the IRQ */
 434         if (regmap_update_bits(drvdata->mc_vbase, priv->ecc_irq_en_offset,
 435                                priv->ecc_irq_en_mask, priv->ecc_irq_en_mask)) {
 436                 edac_mc_printk(mci, KERN_ERR,
 437                                "Error enabling SDRAM ECC IRQ\n");
 438                 res = -ENODEV;
 439                 goto err2;
 440         }
 441
 442         altr_sdr_mc_create_debugfs_nodes(mci);
 443
 444         devres_close_group(&pdev->dev, NULL);
 445
 446         return 0;
 447
 448 err2:
 449         edac_mc_del_mc(&pdev->dev);
 450 err:
 451         devres_release_group(&pdev->dev, NULL);
 452 free:
 453         edac_mc_free(mci);
 454         edac_printk(KERN_ERR, EDAC_MC,
 455                     "EDAC Probe Failed; Error %d\n", res);
 456
 457         return res;
 458 }
 459
 460 static int altr_sdram_remove(struct platform_device *pdev)
 461 {
 462         struct mem_ctl_info *mci = platform_get_drvdata(pdev);
 463
 464         edac_mc_del_mc(&pdev->dev);
 465         edac_mc_free(mci);
 466         platform_set_drvdata(pdev, NULL);
 467
 468         return 0;
 469 }
 470
 471 /**************** Stratix 10 EDAC Memory Controller Functions ************/
 472
 473 /**
 474  * s10_protected_reg_write
 475  * Write to a protected SMC register.
 476  * @context: Not used.
 477  * @reg: Address of register
 478  * @value: Value to write
 479  * Return: INTEL_SIP_SMC_STATUS_OK (0) on success
 480  *         INTEL_SIP_SMC_REG_ERROR on error
 481  *         INTEL_SIP_SMC_RETURN_UNKNOWN_FUNCTION if not supported
 482  */
 483 static int s10_protected_reg_write(void *context, unsigned int reg,
 484                                    unsigned int val)
 485 {
 486         struct arm_smccc_res result;
 487         unsigned long offset = (unsigned long)context;
 488
 489         arm_smccc_smc(INTEL_SIP_SMC_REG_WRITE, offset + reg, val, 0, 0,
 490                       0, 0, 0, &result);
 491
 492         return (int)result.a0;
 493 }
 494
 495 /**
 496  * s10_protected_reg_read
 497  * Read the status of a protected SMC register
 498  * @context: Not used.
 499  * @reg: Address of register
 500  * @value: Value read.
 501  * Return: INTEL_SIP_SMC_STATUS_OK (0) on success
 502  *         INTEL_SIP_SMC_REG_ERROR on error
 503  *         INTEL_SIP_SMC_RETURN_UNKNOWN_FUNCTION if not supported
 504  */
 505 static int s10_protected_reg_read(void *context, unsigned int reg,
 506                                   unsigned int *val)
 507 {
 508         struct arm_smccc_res result;
 509         unsigned long offset = (unsigned long)context;
 510
 511         arm_smccc_smc(INTEL_SIP_SMC_REG_READ, offset + reg, 0, 0, 0,
 512                       0, 0, 0, &result);
 513
 514         *val = (unsigned int)result.a1;
 515
 516         return (int)result.a0;
 517 }
 518
 519 static const struct regmap_config s10_sdram_regmap_cfg = {
 520         .name = "s10_ddr",
 521         .reg_bits = 32,
 522         .reg_stride = 4,
 523         .val_bits = 32,
 524         .max_register = 0xffd12228,
 525         .reg_read = s10_protected_reg_read,
 526         .reg_write = s10_protected_reg_write,
 527         .use_single_rw = true,
 528 };
 529
 530 /************** </Stratix10 EDAC Memory Controller Functions> ***********/
 531
 532 /*
 533  * If you want to suspend, need to disable EDAC by removing it
 534  * from the device tree or defconfig.
 535  */
 536 #ifdef CONFIG_PM
 537 static int altr_sdram_prepare(struct device *dev)
 538 {
 539         pr_err("Suspend not allowed when EDAC is enabled.\n");
 540
 541         return -EPERM;
 542 }
 543
 544 static const struct dev_pm_ops altr_sdram_pm_ops = {
 545         .prepare = altr_sdram_prepare,
 546 };
 547 #endif
 548
 549 static struct platform_driver altr_sdram_edac_driver = {
 550         .probe = altr_sdram_probe,
 551         .remove = altr_sdram_remove,
 552         .driver = {
 553                 .name = "altr_sdram_edac",
 554 #ifdef CONFIG_PM
 555                 .pm = &altr_sdram_pm_ops,
 556 #endif
 557                 .of_match_table = altr_sdram_ctrl_of_match,
 558         },
 559 };
 560
 561 module_platform_driver(altr_sdram_edac_driver);
 562
 563 /************************* EDAC Parent Probe *************************/
 564
 565 static const struct of_device_id altr_edac_device_of_match[];
 566
 567 static const struct of_device_id altr_edac_of_match[] = {
 568         { .compatible = "altr,socfpga-ecc-manager" },
 569         {},
 570 };
 571 MODULE_DEVICE_TABLE(of, altr_edac_of_match);
 572
 573 static int altr_edac_probe(struct platform_device *pdev)
 574 {
 575         of_platform_populate(pdev->dev.of_node, altr_edac_device_of_match,
 576                              NULL, &pdev->dev);
 577         return 0;
 578 }
 579
 580 static struct platform_driver altr_edac_driver = {
 581         .probe =  altr_edac_probe,
 582         .driver = {
 583                 .name = "socfpga_ecc_manager",
 584                 .of_match_table = altr_edac_of_match,
 585         },
 586 };
 587 module_platform_driver(altr_edac_driver);
 588
 589 /************************* EDAC Device Functions *************************/
 590
 591 /*
 592  * EDAC Device Functions (shared between various IPs).
 593  * The discrete memories use the EDAC Device framework. The probe
 594  * and error handling functions are very similar between memories
 595  * so they are shared. The memory allocation and freeing for EDAC
 596  * trigger testing are different for each memory.
 597  */
 598
 599 static const struct edac_device_prv_data ocramecc_data;
 600 static const struct edac_device_prv_data l2ecc_data;
 601 static const struct edac_device_prv_data a10_ocramecc_data;
 602 static const struct edac_device_prv_data a10_l2ecc_data;
 603
 604 static irqreturn_t altr_edac_device_handler(int irq, void *dev_id)
 605 {
 606         irqreturn_t ret_value = IRQ_NONE;
 607         struct edac_device_ctl_info *dci = dev_id;
 608         struct altr_edac_device_dev *drvdata = dci->pvt_info;
 609         const struct edac_device_prv_data *priv = drvdata->data;
 610
 611         if (irq == drvdata->sb_irq) {
 612                 if (priv->ce_clear_mask)
 613                         writel(priv->ce_clear_mask, drvdata->base);
 614                 edac_device_handle_ce(dci, 0, 0, drvdata->edac_dev_name);
 615                 ret_value = IRQ_HANDLED;
 616         } else if (irq == drvdata->db_irq) {
 617                 if (priv->ue_clear_mask)
 618                         writel(priv->ue_clear_mask, drvdata->base);
 619                 edac_device_handle_ue(dci, 0, 0, drvdata->edac_dev_name);
 620                 panic("\nEDAC:ECC_DEVICE[Uncorrectable errors]\n");
 621                 ret_value = IRQ_HANDLED;
 622         } else {
 623                 WARN_ON(1);
 624         }
 625
 626         return ret_value;
 627 }
 628
 629 static ssize_t altr_edac_device_trig(struct file *file,
 630                                      const char __user *user_buf,
 631                                      size_t count, loff_t *ppos)
 632
 633 {
 634         u32 *ptemp, i, error_mask;
 635         int result = 0;
 636         u8 trig_type;
 637         unsigned long flags;
 638         struct edac_device_ctl_info *edac_dci = file->private_data;
 639         struct altr_edac_device_dev *drvdata = edac_dci->pvt_info;
 640         const struct edac_device_prv_data *priv = drvdata->data;
 641         void *generic_ptr = edac_dci->dev;
 642
 643         if (!user_buf || get_user(trig_type, user_buf))
 644                 return -EFAULT;
 645
 646         if (!priv->alloc_mem)
 647                 return -ENOMEM;
 648
 649         /*
 650          * Note that generic_ptr is initialized to the device * but in
 651          * some alloc_functions, this is overridden and returns data.
 652          */
 653         ptemp = priv->alloc_mem(priv->trig_alloc_sz, &generic_ptr);
 654         if (!ptemp) {
 655                 edac_printk(KERN_ERR, EDAC_DEVICE,
 656                             "Inject: Buffer Allocation error\n");
 657                 return -ENOMEM;
 658         }
 659
 660         if (trig_type == ALTR_UE_TRIGGER_CHAR)
 661                 error_mask = priv->ue_set_mask;
 662         else
 663                 error_mask = priv->ce_set_mask;
 664
 665         edac_printk(KERN_ALERT, EDAC_DEVICE,
 666                     "Trigger Error Mask (0x%X)\n", error_mask);
 667
 668         local_irq_save(flags);
 669         /* write ECC corrupted data out. */
 670         for (i = 0; i < (priv->trig_alloc_sz / sizeof(*ptemp)); i++) {
 671                 /* Read data so we're in the correct state */
 672                 rmb();
 673                 if (READ_ONCE(ptemp[i]))
 674                         result = -1;
 675                 /* Toggle Error bit (it is latched), leave ECC enabled */
 676                 writel(error_mask, (drvdata->base + priv->set_err_ofst));
 677                 writel(priv->ecc_enable_mask, (drvdata->base +
 678                                                priv->set_err_ofst));
 679                 ptemp[i] = i;
 680         }
 681         /* Ensure it has been written out */
 682         wmb();
 683         local_irq_restore(flags);
 684
 685         if (result)
 686                 edac_printk(KERN_ERR, EDAC_DEVICE, "Mem Not Cleared\n");
 687
 688         /* Read out written data. ECC error caused here */
 689         for (i = 0; i < ALTR_TRIGGER_READ_WRD_CNT; i++)
 690                 if (READ_ONCE(ptemp[i]) != i)
 691                         edac_printk(KERN_ERR, EDAC_DEVICE,
 692                                     "Read doesn't match written data\n");
 693
 694         if (priv->free_mem)
 695                 priv->free_mem(ptemp, priv->trig_alloc_sz, generic_ptr);
 696
 697         return count;
 698 }
 699
 700 static const struct file_operations altr_edac_device_inject_fops = {
 701         .open = simple_open,
 702         .write = altr_edac_device_trig,
 703         .llseek = generic_file_llseek,
 704 };
 705
 706 static ssize_t altr_edac_a10_device_trig(struct file *file,
 707                                          const char __user *user_buf,
 708                                          size_t count, loff_t *ppos);
 709
 710 static const struct file_operations altr_edac_a10_device_inject_fops = {
 711         .open = simple_open,
 712         .write = altr_edac_a10_device_trig,
 713         .llseek = generic_file_llseek,
 714 };
 715
 716 static ssize_t altr_edac_a10_device_trig2(struct file *file,
 717                                           const char __user *user_buf,
 718                                           size_t count, loff_t *ppos);
 719
 720 static const struct file_operations altr_edac_a10_device_inject2_fops = {
 721         .open = simple_open,
 722         .write = altr_edac_a10_device_trig2,
 723         .llseek = generic_file_llseek,
 724 };
 725
 726 static void altr_create_edacdev_dbgfs(struct edac_device_ctl_info *edac_dci,
 727                                       const struct edac_device_prv_data *priv)
 728 {
 729         struct altr_edac_device_dev *drvdata = edac_dci->pvt_info;
 730
 731         if (!IS_ENABLED(CONFIG_EDAC_DEBUG))
 732                 return;
 733
 734         drvdata->debugfs_dir = edac_debugfs_create_dir(drvdata->edac_dev_name);
 735         if (!drvdata->debugfs_dir)
 736                 return;
 737
 738         if (!edac_debugfs_create_file("altr_trigger", S_IWUSR,
 739                                       drvdata->debugfs_dir, edac_dci,
 740                                       priv->inject_fops))
 741                 debugfs_remove_recursive(drvdata->debugfs_dir);
 742 }
 743
 744 static const struct of_device_id altr_edac_device_of_match[] = {
 745 #ifdef CONFIG_EDAC_ALTERA_L2C
 746         { .compatible = "altr,socfpga-l2-ecc", .data = &l2ecc_data },
 747 #endif
 748 #ifdef CONFIG_EDAC_ALTERA_OCRAM
 749         { .compatible = "altr,socfpga-ocram-ecc", .data = &ocramecc_data },
 750 #endif
 751         {},
 752 };
 753 MODULE_DEVICE_TABLE(of, altr_edac_device_of_match);
 754
 755 /*
 756  * altr_edac_device_probe()
 757  *      This is a generic EDAC device driver that will support
 758  *      various Altera memory devices such as the L2 cache ECC and
 759  *      OCRAM ECC as well as the memories for other peripherals.
 760  *      Module specific initialization is done by passing the
 761  *      function index in the device tree.
 762  */
 763 static int altr_edac_device_probe(struct platform_device *pdev)
 764 {
 765         struct edac_device_ctl_info *dci;
 766         struct altr_edac_device_dev *drvdata;
 767         struct resource *r;
 768         int res = 0;
 769         struct device_node *np = pdev->dev.of_node;
 770         char *ecc_name = (char *)np->name;
 771         static int dev_instance;
 772
 773         if (!devres_open_group(&pdev->dev, NULL, GFP_KERNEL)) {
 774                 edac_printk(KERN_ERR, EDAC_DEVICE,
 775                             "Unable to open devm\n");
 776                 return -ENOMEM;
 777         }
 778
 779         r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 780         if (!r) {
 781                 edac_printk(KERN_ERR, EDAC_DEVICE,
 782                             "Unable to get mem resource\n");
 783                 res = -ENODEV;
 784                 goto fail;
 785         }
 786
 787         if (!devm_request_mem_region(&pdev->dev, r->start, resource_size(r),
 788                                      dev_name(&pdev->dev))) {
 789                 edac_printk(KERN_ERR, EDAC_DEVICE,
 790                             "%s:Error requesting mem region\n", ecc_name);
 791                 res = -EBUSY;
 792                 goto fail;
 793         }
 794
 795         dci = edac_device_alloc_ctl_info(sizeof(*drvdata), ecc_name,
 796                                          1, ecc_name, 1, 0, NULL, 0,
 797                                          dev_instance++);
 798
 799         if (!dci) {
 800                 edac_printk(KERN_ERR, EDAC_DEVICE,
 801                             "%s: Unable to allocate EDAC device\n", ecc_name);
 802                 res = -ENOMEM;
 803                 goto fail;
 804         }
 805
 806         drvdata = dci->pvt_info;
 807         dci->dev = &pdev->dev;
 808         platform_set_drvdata(pdev, dci);
 809         drvdata->edac_dev_name = ecc_name;
 810
 811         drvdata->base = devm_ioremap(&pdev->dev, r->start, resource_size(r));
 812         if (!drvdata->base) {
 813                 res = -ENOMEM;
 814                 goto fail1;
 815         }
 816
 817         /* Get driver specific data for this EDAC device */
 818         drvdata->data = of_match_node(altr_edac_device_of_match, np)->data;
 819
 820         /* Check specific dependencies for the module */
 821         if (drvdata->data->setup) {
 822                 res = drvdata->data->setup(drvdata);
 823                 if (res)
 824                         goto fail1;
 825         }
 826
 827         drvdata->sb_irq = platform_get_irq(pdev, 0);
 828         res = devm_request_irq(&pdev->dev, drvdata->sb_irq,
 829                                altr_edac_device_handler,
 830                                0, dev_name(&pdev->dev), dci);
 831         if (res)
 832                 goto fail1;
 833
 834         drvdata->db_irq = platform_get_irq(pdev, 1);
 835         res = devm_request_irq(&pdev->dev, drvdata->db_irq,
 836                                altr_edac_device_handler,
 837                                0, dev_name(&pdev->dev), dci);
 838         if (res)
 839                 goto fail1;
 840
 841         dci->mod_name = "Altera ECC Manager";
 842         dci->dev_name = drvdata->edac_dev_name;
 843
 844         res = edac_device_add_device(dci);
 845         if (res)
 846                 goto fail1;
 847
 848         altr_create_edacdev_dbgfs(dci, drvdata->data);
 849
 850         devres_close_group(&pdev->dev, NULL);
 851
 852         return 0;
 853
 854 fail1:
 855         edac_device_free_ctl_info(dci);
 856 fail:
 857         devres_release_group(&pdev->dev, NULL);
 858         edac_printk(KERN_ERR, EDAC_DEVICE,
 859                     "%s:Error setting up EDAC device: %d\n", ecc_name, res);
 860
 861         return res;
 862 }
 863
 864 static int altr_edac_device_remove(struct platform_device *pdev)
 865 {
 866         struct edac_device_ctl_info *dci = platform_get_drvdata(pdev);
 867         struct altr_edac_device_dev *drvdata = dci->pvt_info;
 868
 869         debugfs_remove_recursive(drvdata->debugfs_dir);
 870         edac_device_del_device(&pdev->dev);
 871         edac_device_free_ctl_info(dci);
 872
 873         return 0;
 874 }
 875
 876 static struct platform_driver altr_edac_device_driver = {
 877         .probe =  altr_edac_device_probe,
 878         .remove = altr_edac_device_remove,
 879         .driver = {
 880                 .name = "altr_edac_device",
 881                 .of_match_table = altr_edac_device_of_match,
 882         },
 883 };
 884 module_platform_driver(altr_edac_device_driver);
 885
 886 /******************* Arria10 Device ECC Shared Functions *****************/
 887
 888 /*
 889  *  Test for memory's ECC dependencies upon entry because platform specific
 890  *  startup should have initialized the memory and enabled the ECC.
 891  *  Can't turn on ECC here because accessing un-initialized memory will
 892  *  cause CE/UE errors possibly causing an ABORT.
 893  */
 894 static int __maybe_unused
 895 altr_check_ecc_deps(struct altr_edac_device_dev *device)
 896 {
 897         void __iomem  *base = device->base;
 898         const struct edac_device_prv_data *prv = device->data;
 899
 900         if (readl(base + prv->ecc_en_ofst) & prv->ecc_enable_mask)
 901                 return 0;
 902
 903         edac_printk(KERN_ERR, EDAC_DEVICE,
 904                     "%s: No ECC present or ECC disabled.\n",
 905                     device->edac_dev_name);
 906         return -ENODEV;
 907 }
 908
 909 static irqreturn_t __maybe_unused altr_edac_a10_ecc_irq(int irq, void *dev_id)
 910 {
 911         struct altr_edac_device_dev *dci = dev_id;
 912         void __iomem  *base = dci->base;
 913
 914         if (irq == dci->sb_irq) {
 915                 writel(ALTR_A10_ECC_SERRPENA,
 916                        base + ALTR_A10_ECC_INTSTAT_OFST);
 917                 edac_device_handle_ce(dci->edac_dev, 0, 0, dci->edac_dev_name);
 918
 919                 return IRQ_HANDLED;
 920         } else if (irq == dci->db_irq) {
 921                 writel(ALTR_A10_ECC_DERRPENA,
 922                        base + ALTR_A10_ECC_INTSTAT_OFST);
 923                 edac_device_handle_ue(dci->edac_dev, 0, 0, dci->edac_dev_name);
 924                 if (dci->data->panic)
 925                         panic("\nEDAC:ECC_DEVICE[Uncorrectable errors]\n");
 926
 927                 return IRQ_HANDLED;
 928         }
 929
 930         WARN_ON(1);
 931
 932         return IRQ_NONE;
 933 }
 934
 935 /******************* Arria10 Memory Buffer Functions *********************/
 936
 937 static inline int a10_get_irq_mask(struct device_node *np)
 938 {
 939         int irq;
 940         const u32 *handle = of_get_property(np, "interrupts", NULL);
 941
 942         if (!handle)
 943                 return -ENODEV;
 944         irq = be32_to_cpup(handle);
 945         return irq;
 946 }
 947
 948 static inline void ecc_set_bits(u32 bit_mask, void __iomem *ioaddr)
 949 {
 950         u32 value = readl(ioaddr);
 951
 952         value |= bit_mask;
 953         writel(value, ioaddr);
 954 }
 955
 956 static inline void ecc_clear_bits(u32 bit_mask, void __iomem *ioaddr)
 957 {
 958         u32 value = readl(ioaddr);
 959
 960         value &= ~bit_mask;
 961         writel(value, ioaddr);
 962 }
 963
 964 static inline int ecc_test_bits(u32 bit_mask, void __iomem *ioaddr)
 965 {
 966         u32 value = readl(ioaddr);
 967
 968         return (value & bit_mask) ? 1 : 0;
 969 }
 970
 971 /*
 972  * This function uses the memory initialization block in the Arria10 ECC
 973  * controller to initialize/clear the entire memory data and ECC data.
 974  */
 975 static int __maybe_unused altr_init_memory_port(void __iomem *ioaddr, int port)
 976 {
 977         int limit = ALTR_A10_ECC_INIT_WATCHDOG_10US;
 978         u32 init_mask, stat_mask, clear_mask;
 979         int ret = 0;
 980
 981         if (port) {
 982                 init_mask = ALTR_A10_ECC_INITB;
 983                 stat_mask = ALTR_A10_ECC_INITCOMPLETEB;
 984                 clear_mask = ALTR_A10_ECC_ERRPENB_MASK;
 985         } else {
 986                 init_mask = ALTR_A10_ECC_INITA;
 987                 stat_mask = ALTR_A10_ECC_INITCOMPLETEA;
 988                 clear_mask = ALTR_A10_ECC_ERRPENA_MASK;
 989         }
 990
 991         ecc_set_bits(init_mask, (ioaddr + ALTR_A10_ECC_CTRL_OFST));
 992         while (limit--) {
 993                 if (ecc_test_bits(stat_mask,
 994                                   (ioaddr + ALTR_A10_ECC_INITSTAT_OFST)))
 995                         break;
 996                 udelay(1);
 997         }
 998         if (limit < 0)
 999                 ret = -EBUSY;
1000
1001         /* Clear any pending ECC interrupts */
1002         writel(clear_mask, (ioaddr + ALTR_A10_ECC_INTSTAT_OFST));
1003
1004         return ret;
1005 }
1006
1007 static int socfpga_is_a10(void)
1008 {
1009         return of_machine_is_compatible("altr,socfpga-arria10");
1010 }
1011
1012 static int socfpga_is_s10(void)
1013 {
1014         return of_machine_is_compatible("altr,socfpga-stratix10");
1015 }
1016
1017 static __init int __maybe_unused
1018 altr_init_a10_ecc_block(struct device_node *np, u32 irq_mask,
1019                         u32 ecc_ctrl_en_mask, bool dual_port)
1020 {
1021         int ret = 0;
1022         void __iomem *ecc_block_base;
1023         struct regmap *ecc_mgr_map;
1024         char *ecc_name;
1025         struct device_node *np_eccmgr;
1026
1027         ecc_name = (char *)np->name;
1028
1029         /* Get the ECC Manager - parent of the device EDACs */
1030         np_eccmgr = of_get_parent(np);
1031
1032         if (socfpga_is_a10()) {
1033                 ecc_mgr_map = syscon_regmap_lookup_by_phandle(np_eccmgr,
1034                                                               "altr,sysmgr-syscon");
1035         } else {
1036                 struct device_node *sysmgr_np;
1037                 struct resource res;
1038                 uintptr_t base;
1039
1040                 sysmgr_np = of_parse_phandle(np_eccmgr,
1041                                              "altr,sysmgr-syscon", 0);
1042                 if (!sysmgr_np) {
1043                         edac_printk(KERN_ERR, EDAC_DEVICE,
1044                                     "Unable to find altr,sysmgr-syscon\n");
1045                         return -ENODEV;
1046                 }
1047
1048                 if (of_address_to_resource(sysmgr_np, 0, &res))
1049                         return -ENOMEM;
1050
1051                 /* Need physical address for SMCC call */
1052                 base = res.start;
1053
1054                 ecc_mgr_map = regmap_init(NULL, NULL, (void *)base,
1055                                           &s10_sdram_regmap_cfg);
1056         }
1057         of_node_put(np_eccmgr);
1058         if (IS_ERR(ecc_mgr_map)) {
1059                 edac_printk(KERN_ERR, EDAC_DEVICE,
1060                             "Unable to get syscon altr,sysmgr-syscon\n");
1061                 return -ENODEV;
1062         }
1063
1064         /* Map the ECC Block */
1065         ecc_block_base = of_iomap(np, 0);
1066         if (!ecc_block_base) {
1067                 edac_printk(KERN_ERR, EDAC_DEVICE,
1068                             "Unable to map %s ECC block\n", ecc_name);
1069                 return -ENODEV;
1070         }
1071
1072         /* Disable ECC */
1073         regmap_write(ecc_mgr_map, A10_SYSMGR_ECC_INTMASK_SET_OFST, irq_mask);
1074         writel(ALTR_A10_ECC_SERRINTEN,
1075                (ecc_block_base + ALTR_A10_ECC_ERRINTENR_OFST));
1076         ecc_clear_bits(ecc_ctrl_en_mask,
1077                        (ecc_block_base + ALTR_A10_ECC_CTRL_OFST));
1078         /* Ensure all writes complete */
1079         wmb();
1080         /* Use HW initialization block to initialize memory for ECC */
1081         ret = altr_init_memory_port(ecc_block_base, 0);
1082         if (ret) {
1083                 edac_printk(KERN_ERR, EDAC_DEVICE,
1084                             "ECC: cannot init %s PORTA memory\n", ecc_name);
1085                 goto out;
1086         }
1087
1088         if (dual_port) {
1089                 ret = altr_init_memory_port(ecc_block_base, 1);
1090                 if (ret) {
1091                         edac_printk(KERN_ERR, EDAC_DEVICE,
1092                                     "ECC: cannot init %s PORTB memory\n",
1093                                     ecc_name);
1094                         goto out;
1095                 }
1096         }
1097
1098         /* Interrupt mode set to every SBERR */
1099         regmap_write(ecc_mgr_map, ALTR_A10_ECC_INTMODE_OFST,
1100                      ALTR_A10_ECC_INTMODE);
1101         /* Enable ECC */
1102         ecc_set_bits(ecc_ctrl_en_mask, (ecc_block_base +
1103                                         ALTR_A10_ECC_CTRL_OFST));
1104         writel(ALTR_A10_ECC_SERRINTEN,
1105                (ecc_block_base + ALTR_A10_ECC_ERRINTENS_OFST));
1106         regmap_write(ecc_mgr_map, A10_SYSMGR_ECC_INTMASK_CLR_OFST, irq_mask);
1107         /* Ensure all writes complete */
1108         wmb();
1109 out:
1110         iounmap(ecc_block_base);
1111         return ret;
1112 }
1113
1114 static int validate_parent_available(struct device_node *np);
1115 static const struct of_device_id altr_edac_a10_device_of_match[];
1116 static int __init __maybe_unused altr_init_a10_ecc_device_type(char *compat)
1117 {
1118         int irq;
1119         struct device_node *child, *np;
1120
1121         if (!socfpga_is_a10() && !socfpga_is_s10())
1122                 return -ENODEV;
1123
1124         np = of_find_compatible_node(NULL, NULL,
1125                                      "altr,socfpga-a10-ecc-manager");
1126         if (!np) {
1127                 edac_printk(KERN_ERR, EDAC_DEVICE, "ECC Manager not found\n");
1128                 return -ENODEV;
1129         }
1130
1131         for_each_child_of_node(np, child) {
1132                 const struct of_device_id *pdev_id;
1133                 const struct edac_device_prv_data *prv;
1134
1135                 if (!of_device_is_available(child))
1136                         continue;
1137                 if (!of_device_is_compatible(child, compat))
1138                         continue;
1139
1140                 if (validate_parent_available(child))
1141                         continue;
1142
1143                 irq = a10_get_irq_mask(child);
1144                 if (irq < 0)
1145                         continue;
1146
1147                 /* Get matching node and check for valid result */
1148                 pdev_id = of_match_node(altr_edac_a10_device_of_match, child);
1149                 if (IS_ERR_OR_NULL(pdev_id))
1150                         continue;
1151
1152                 /* Validate private data pointer before dereferencing */
1153                 prv = pdev_id->data;
1154                 if (!prv)
1155                         continue;
1156
1157                 altr_init_a10_ecc_block(child, BIT(irq),
1158                                         prv->ecc_enable_mask, 0);
1159         }
1160
1161         of_node_put(np);
1162         return 0;
1163 }
1164
1165 /*********************** OCRAM EDAC Device Functions *********************/
1166
1167 #ifdef CONFIG_EDAC_ALTERA_OCRAM
1168
1169 static void *ocram_alloc_mem(size_t size, void **other)
1170 {
1171         struct device_node *np;
1172         struct gen_pool *gp;
1173         void *sram_addr;
1174
1175         np = of_find_compatible_node(NULL, NULL, "altr,socfpga-ocram-ecc");
1176         if (!np)
1177                 return NULL;
1178
1179         gp = of_gen_pool_get(np, "iram", 0);
1180         of_node_put(np);
1181         if (!gp)
1182                 return NULL;
1183
1184         sram_addr = (void *)gen_pool_alloc(gp, size);
1185         if (!sram_addr)
1186                 return NULL;
1187
1188         memset(sram_addr, 0, size);
1189         /* Ensure data is written out */
1190         wmb();
1191
1192         /* Remember this handle for freeing  later */
1193         *other = gp;
1194
1195         return sram_addr;
1196 }
1197
1198 static void ocram_free_mem(void *p, size_t size, void *other)
1199 {
1200         gen_pool_free((struct gen_pool *)other, (unsigned long)p, size);
1201 }
1202
1203 static const struct edac_device_prv_data ocramecc_data = {
1204         .setup = altr_check_ecc_deps,
1205         .ce_clear_mask = (ALTR_OCR_ECC_EN | ALTR_OCR_ECC_SERR),
1206         .ue_clear_mask = (ALTR_OCR_ECC_EN | ALTR_OCR_ECC_DERR),
1207         .alloc_mem = ocram_alloc_mem,
1208         .free_mem = ocram_free_mem,
1209         .ecc_enable_mask = ALTR_OCR_ECC_EN,
1210         .ecc_en_ofst = ALTR_OCR_ECC_REG_OFFSET,
1211         .ce_set_mask = (ALTR_OCR_ECC_EN | ALTR_OCR_ECC_INJS),
1212         .ue_set_mask = (ALTR_OCR_ECC_EN | ALTR_OCR_ECC_INJD),
1213         .set_err_ofst = ALTR_OCR_ECC_REG_OFFSET,
1214         .trig_alloc_sz = ALTR_TRIG_OCRAM_BYTE_SIZE,
1215         .inject_fops = &altr_edac_device_inject_fops,
1216 };
1217
1218 static const struct edac_device_prv_data a10_ocramecc_data = {
1219         .setup = altr_check_ecc_deps,
1220         .ce_clear_mask = ALTR_A10_ECC_SERRPENA,
1221         .ue_clear_mask = ALTR_A10_ECC_DERRPENA,
1222         .irq_status_mask = A10_SYSMGR_ECC_INTSTAT_OCRAM,
1223         .ecc_enable_mask = ALTR_A10_OCRAM_ECC_EN_CTL,
1224         .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST,
1225         .ce_set_mask = ALTR_A10_ECC_TSERRA,
1226         .ue_set_mask = ALTR_A10_ECC_TDERRA,
1227         .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST,
1228         .ecc_irq_handler = altr_edac_a10_ecc_irq,
1229         .inject_fops = &altr_edac_a10_device_inject_fops,
1230         /*
1231          * OCRAM panic on uncorrectable error because sleep/resume
1232          * functions and FPGA contents are stored in OCRAM. Prefer
1233          * a kernel panic over executing/loading corrupted data.
1234          */
1235         .panic = true,
1236 };
1237
1238 #endif  /* CONFIG_EDAC_ALTERA_OCRAM */
1239
1240 /********************* L2 Cache EDAC Device Functions ********************/
1241
1242 #ifdef CONFIG_EDAC_ALTERA_L2C
1243
1244 static void *l2_alloc_mem(size_t size, void **other)
1245 {
1246         struct device *dev = *other;
1247         void *ptemp = devm_kzalloc(dev, size, GFP_KERNEL);
1248
1249         if (!ptemp)
1250                 return NULL;
1251
1252         /* Make sure everything is written out */
1253         wmb();
1254
1255         /*
1256          * Clean all cache levels up to LoC (includes L2)
1257          * This ensures the corrupted data is written into
1258          * L2 cache for readback test (which causes ECC error).
1259          */
1260         flush_cache_all();
1261
1262         return ptemp;
1263 }
1264
1265 static void l2_free_mem(void *p, size_t size, void *other)
1266 {
1267         struct device *dev = other;
1268
1269         if (dev && p)
1270                 devm_kfree(dev, p);
1271 }
1272
1273 /*
1274  * altr_l2_check_deps()
1275  *      Test for L2 cache ECC dependencies upon entry because
1276  *      platform specific startup should have initialized the L2
1277  *      memory and enabled the ECC.
1278  *      Bail if ECC is not enabled.
1279  *      Note that L2 Cache Enable is forced at build time.
1280  */
1281 static int altr_l2_check_deps(struct altr_edac_device_dev *device)
1282 {
1283         void __iomem *base = device->base;
1284         const struct edac_device_prv_data *prv = device->data;
1285
1286         if ((readl(base) & prv->ecc_enable_mask) ==
1287              prv->ecc_enable_mask)
1288                 return 0;
1289
1290         edac_printk(KERN_ERR, EDAC_DEVICE,
1291                     "L2: No ECC present, or ECC disabled\n");
1292         return -ENODEV;
1293 }
1294
1295 static irqreturn_t altr_edac_a10_l2_irq(int irq, void *dev_id)
1296 {
1297         struct altr_edac_device_dev *dci = dev_id;
1298
1299         if (irq == dci->sb_irq) {
1300                 regmap_write(dci->edac->ecc_mgr_map,
1301                              A10_SYSGMR_MPU_CLEAR_L2_ECC_OFST,
1302                              A10_SYSGMR_MPU_CLEAR_L2_ECC_SB);
1303                 edac_device_handle_ce(dci->edac_dev, 0, 0, dci->edac_dev_name);
1304
1305                 return IRQ_HANDLED;
1306         } else if (irq == dci->db_irq) {
1307                 regmap_write(dci->edac->ecc_mgr_map,
1308                              A10_SYSGMR_MPU_CLEAR_L2_ECC_OFST,
1309                              A10_SYSGMR_MPU_CLEAR_L2_ECC_MB);
1310                 edac_device_handle_ue(dci->edac_dev, 0, 0, dci->edac_dev_name);
1311                 panic("\nEDAC:ECC_DEVICE[Uncorrectable errors]\n");
1312
1313                 return IRQ_HANDLED;
1314         }
1315
1316         WARN_ON(1);
1317
1318         return IRQ_NONE;
1319 }
1320
1321 static const struct edac_device_prv_data l2ecc_data = {
1322         .setup = altr_l2_check_deps,
1323         .ce_clear_mask = 0,
1324         .ue_clear_mask = 0,
1325         .alloc_mem = l2_alloc_mem,
1326         .free_mem = l2_free_mem,
1327         .ecc_enable_mask = ALTR_L2_ECC_EN,
1328         .ce_set_mask = (ALTR_L2_ECC_EN | ALTR_L2_ECC_INJS),
1329         .ue_set_mask = (ALTR_L2_ECC_EN | ALTR_L2_ECC_INJD),
1330         .set_err_ofst = ALTR_L2_ECC_REG_OFFSET,
1331         .trig_alloc_sz = ALTR_TRIG_L2C_BYTE_SIZE,
1332         .inject_fops = &altr_edac_device_inject_fops,
1333 };
1334
1335 static const struct edac_device_prv_data a10_l2ecc_data = {
1336         .setup = altr_l2_check_deps,
1337         .ce_clear_mask = ALTR_A10_L2_ECC_SERR_CLR,
1338         .ue_clear_mask = ALTR_A10_L2_ECC_MERR_CLR,
1339         .irq_status_mask = A10_SYSMGR_ECC_INTSTAT_L2,
1340         .alloc_mem = l2_alloc_mem,
1341         .free_mem = l2_free_mem,
1342         .ecc_enable_mask = ALTR_A10_L2_ECC_EN_CTL,
1343         .ce_set_mask = ALTR_A10_L2_ECC_CE_INJ_MASK,
1344         .ue_set_mask = ALTR_A10_L2_ECC_UE_INJ_MASK,
1345         .set_err_ofst = ALTR_A10_L2_ECC_INJ_OFST,
1346         .ecc_irq_handler = altr_edac_a10_l2_irq,
1347         .trig_alloc_sz = ALTR_TRIG_L2C_BYTE_SIZE,
1348         .inject_fops = &altr_edac_device_inject_fops,
1349 };
1350
1351 #endif  /* CONFIG_EDAC_ALTERA_L2C */
1352
1353 /********************* Ethernet Device Functions ********************/
1354
1355 #ifdef CONFIG_EDAC_ALTERA_ETHERNET
1356
1357 static const struct edac_device_prv_data a10_enetecc_data = {
1358         .setup = altr_check_ecc_deps,
1359         .ce_clear_mask = ALTR_A10_ECC_SERRPENA,
1360         .ue_clear_mask = ALTR_A10_ECC_DERRPENA,
1361         .ecc_enable_mask = ALTR_A10_COMMON_ECC_EN_CTL,
1362         .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST,
1363         .ce_set_mask = ALTR_A10_ECC_TSERRA,
1364         .ue_set_mask = ALTR_A10_ECC_TDERRA,
1365         .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST,
1366         .ecc_irq_handler = altr_edac_a10_ecc_irq,
1367         .inject_fops = &altr_edac_a10_device_inject2_fops,
1368 };
1369
1370 static int __init socfpga_init_ethernet_ecc(void)
1371 {
1372         return altr_init_a10_ecc_device_type("altr,socfpga-eth-mac-ecc");
1373 }
1374
1375 early_initcall(socfpga_init_ethernet_ecc);
1376
1377 #endif  /* CONFIG_EDAC_ALTERA_ETHERNET */
1378
1379 /********************** NAND Device Functions **********************/
1380
1381 #ifdef CONFIG_EDAC_ALTERA_NAND
1382
1383 static const struct edac_device_prv_data a10_nandecc_data = {
1384         .setup = altr_check_ecc_deps,
1385         .ce_clear_mask = ALTR_A10_ECC_SERRPENA,
1386         .ue_clear_mask = ALTR_A10_ECC_DERRPENA,
1387         .ecc_enable_mask = ALTR_A10_COMMON_ECC_EN_CTL,
1388         .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST,
1389         .ce_set_mask = ALTR_A10_ECC_TSERRA,
1390         .ue_set_mask = ALTR_A10_ECC_TDERRA,
1391         .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST,
1392         .ecc_irq_handler = altr_edac_a10_ecc_irq,
1393         .inject_fops = &altr_edac_a10_device_inject_fops,
1394 };
1395
1396 static int __init socfpga_init_nand_ecc(void)
1397 {
1398         return altr_init_a10_ecc_device_type("altr,socfpga-nand-ecc");
1399 }
1400
1401 early_initcall(socfpga_init_nand_ecc);
1402
1403 #endif  /* CONFIG_EDAC_ALTERA_NAND */
1404
1405 /********************** DMA Device Functions **********************/
1406
1407 #ifdef CONFIG_EDAC_ALTERA_DMA
1408
1409 static const struct edac_device_prv_data a10_dmaecc_data = {
1410         .setup = altr_check_ecc_deps,
1411         .ce_clear_mask = ALTR_A10_ECC_SERRPENA,
1412         .ue_clear_mask = ALTR_A10_ECC_DERRPENA,
1413         .ecc_enable_mask = ALTR_A10_COMMON_ECC_EN_CTL,
1414         .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST,
1415         .ce_set_mask = ALTR_A10_ECC_TSERRA,
1416         .ue_set_mask = ALTR_A10_ECC_TDERRA,
1417         .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST,
1418         .ecc_irq_handler = altr_edac_a10_ecc_irq,
1419         .inject_fops = &altr_edac_a10_device_inject_fops,
1420 };
1421
1422 static int __init socfpga_init_dma_ecc(void)
1423 {
1424         return altr_init_a10_ecc_device_type("altr,socfpga-dma-ecc");
1425 }
1426
1427 early_initcall(socfpga_init_dma_ecc);
1428
1429 #endif  /* CONFIG_EDAC_ALTERA_DMA */
1430
1431 /********************** USB Device Functions **********************/
1432
1433 #ifdef CONFIG_EDAC_ALTERA_USB
1434
1435 static const struct edac_device_prv_data a10_usbecc_data = {
1436         .setup = altr_check_ecc_deps,
1437         .ce_clear_mask = ALTR_A10_ECC_SERRPENA,
1438         .ue_clear_mask = ALTR_A10_ECC_DERRPENA,
1439         .ecc_enable_mask = ALTR_A10_COMMON_ECC_EN_CTL,
1440         .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST,
1441         .ce_set_mask = ALTR_A10_ECC_TSERRA,
1442         .ue_set_mask = ALTR_A10_ECC_TDERRA,
1443         .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST,
1444         .ecc_irq_handler = altr_edac_a10_ecc_irq,
1445         .inject_fops = &altr_edac_a10_device_inject2_fops,
1446 };
1447
1448 static int __init socfpga_init_usb_ecc(void)
1449 {
1450         return altr_init_a10_ecc_device_type("altr,socfpga-usb-ecc");
1451 }
1452
1453 early_initcall(socfpga_init_usb_ecc);
1454
1455 #endif  /* CONFIG_EDAC_ALTERA_USB */
1456
1457 /********************** QSPI Device Functions **********************/
1458
1459 #ifdef CONFIG_EDAC_ALTERA_QSPI
1460
1461 static const struct edac_device_prv_data a10_qspiecc_data = {
1462         .setup = altr_check_ecc_deps,
1463         .ce_clear_mask = ALTR_A10_ECC_SERRPENA,
1464         .ue_clear_mask = ALTR_A10_ECC_DERRPENA,
1465         .ecc_enable_mask = ALTR_A10_COMMON_ECC_EN_CTL,
1466         .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST,
1467         .ce_set_mask = ALTR_A10_ECC_TSERRA,
1468         .ue_set_mask = ALTR_A10_ECC_TDERRA,
1469         .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST,
1470         .ecc_irq_handler = altr_edac_a10_ecc_irq,
1471         .inject_fops = &altr_edac_a10_device_inject_fops,
1472 };
1473
1474 static int __init socfpga_init_qspi_ecc(void)
1475 {
1476         return altr_init_a10_ecc_device_type("altr,socfpga-qspi-ecc");
1477 }
1478
1479 early_initcall(socfpga_init_qspi_ecc);
1480
1481 #endif  /* CONFIG_EDAC_ALTERA_QSPI */
1482
1483 /********************* SDMMC Device Functions **********************/
1484
1485 #ifdef CONFIG_EDAC_ALTERA_SDMMC
1486
1487 static const struct edac_device_prv_data a10_sdmmceccb_data;
1488 static int altr_portb_setup(struct altr_edac_device_dev *device)
1489 {
1490         struct edac_device_ctl_info *dci;
1491         struct altr_edac_device_dev *altdev;
1492         char *ecc_name = "sdmmcb-ecc";
1493         int edac_idx, rc;
1494         struct device_node *np;
1495         const struct edac_device_prv_data *prv = &a10_sdmmceccb_data;
1496
1497         rc = altr_check_ecc_deps(device);
1498         if (rc)
1499                 return rc;
1500
1501         np = of_find_compatible_node(NULL, NULL, "altr,socfpga-sdmmc-ecc");
1502         if (!np) {
1503                 edac_printk(KERN_WARNING, EDAC_DEVICE, "SDMMC node not found\n");
1504                 return -ENODEV;
1505         }
1506
1507         /* Create the PortB EDAC device */
1508         edac_idx = edac_device_alloc_index();
1509         dci = edac_device_alloc_ctl_info(sizeof(*altdev), ecc_name, 1,
1510                                          ecc_name, 1, 0, NULL, 0, edac_idx);
1511         if (!dci) {
1512                 edac_printk(KERN_ERR, EDAC_DEVICE,
1513                             "%s: Unable to allocate PortB EDAC device\n",
1514                             ecc_name);
1515                 return -ENOMEM;
1516         }
1517
1518         /* Initialize the PortB EDAC device structure from PortA structure */
1519         altdev = dci->pvt_info;
1520         *altdev = *device;
1521
1522         if (!devres_open_group(&altdev->ddev, altr_portb_setup, GFP_KERNEL))
1523                 return -ENOMEM;
1524
1525         /* Update PortB specific values */
1526         altdev->edac_dev_name = ecc_name;
1527         altdev->edac_idx = edac_idx;
1528         altdev->edac_dev = dci;
1529         altdev->data = prv;
1530         dci->dev = &altdev->ddev;
1531         dci->ctl_name = "Altera ECC Manager";
1532         dci->mod_name = ecc_name;
1533         dci->dev_name = ecc_name;
1534
1535         /* Update the IRQs for PortB */
1536         altdev->sb_irq = irq_of_parse_and_map(np, 2);
1537         if (!altdev->sb_irq) {
1538                 edac_printk(KERN_ERR, EDAC_DEVICE, "Error PortB SBIRQ alloc\n");
1539                 rc = -ENODEV;
1540                 goto err_release_group_1;
1541         }
1542         rc = devm_request_irq(&altdev->ddev, altdev->sb_irq,
1543                               prv->ecc_irq_handler,
1544                               IRQF_ONESHOT | IRQF_TRIGGER_HIGH,
1545                               ecc_name, altdev);
1546         if (rc) {
1547                 edac_printk(KERN_ERR, EDAC_DEVICE, "PortB SBERR IRQ error\n");
1548                 goto err_release_group_1;
1549         }
1550
1551         altdev->db_irq = irq_of_parse_and_map(np, 3);
1552         if (!altdev->db_irq) {
1553                 edac_printk(KERN_ERR, EDAC_DEVICE, "Error PortB DBIRQ alloc\n");
1554                 rc = -ENODEV;
1555                 goto err_release_group_1;
1556         }
1557         rc = devm_request_irq(&altdev->ddev, altdev->db_irq,
1558                               prv->ecc_irq_handler,
1559                               IRQF_ONESHOT | IRQF_TRIGGER_HIGH,
1560                               ecc_name, altdev);
1561         if (rc) {
1562                 edac_printk(KERN_ERR, EDAC_DEVICE, "PortB DBERR IRQ error\n");
1563                 goto err_release_group_1;
1564         }
1565
1566         rc = edac_device_add_device(dci);
1567         if (rc) {
1568                 edac_printk(KERN_ERR, EDAC_DEVICE,
1569                             "edac_device_add_device portB failed\n");
1570                 rc = -ENOMEM;
1571                 goto err_release_group_1;
1572         }
1573         altr_create_edacdev_dbgfs(dci, prv);
1574
1575         list_add(&altdev->next, &altdev->edac->a10_ecc_devices);
1576
1577         devres_remove_group(&altdev->ddev, altr_portb_setup);
1578
1579         return 0;
1580
1581 err_release_group_1:
1582         edac_device_free_ctl_info(dci);
1583         devres_release_group(&altdev->ddev, altr_portb_setup);
1584         edac_printk(KERN_ERR, EDAC_DEVICE,
1585                     "%s:Error setting up EDAC device: %d\n", ecc_name, rc);
1586         return rc;
1587 }
1588
1589 static irqreturn_t altr_edac_a10_ecc_irq_portb(int irq, void *dev_id)
1590 {
1591         struct altr_edac_device_dev *ad = dev_id;
1592         void __iomem  *base = ad->base;
1593         const struct edac_device_prv_data *priv = ad->data;
1594
1595         if (irq == ad->sb_irq) {
1596                 writel(priv->ce_clear_mask,
1597                        base + ALTR_A10_ECC_INTSTAT_OFST);
1598                 edac_device_handle_ce(ad->edac_dev, 0, 0, ad->edac_dev_name);
1599                 return IRQ_HANDLED;
1600         } else if (irq == ad->db_irq) {
1601                 writel(priv->ue_clear_mask,
1602                        base + ALTR_A10_ECC_INTSTAT_OFST);
1603                 edac_device_handle_ue(ad->edac_dev, 0, 0, ad->edac_dev_name);
1604                 return IRQ_HANDLED;
1605         }
1606
1607         WARN_ONCE(1, "Unhandled IRQ%d on Port B.", irq);
1608
1609         return IRQ_NONE;
1610 }
1611
1612 static const struct edac_device_prv_data a10_sdmmcecca_data = {
1613         .setup = altr_portb_setup,
1614         .ce_clear_mask = ALTR_A10_ECC_SERRPENA,
1615         .ue_clear_mask = ALTR_A10_ECC_DERRPENA,
1616         .ecc_enable_mask = ALTR_A10_COMMON_ECC_EN_CTL,
1617         .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST,
1618         .ce_set_mask = ALTR_A10_ECC_SERRPENA,
1619         .ue_set_mask = ALTR_A10_ECC_DERRPENA,
1620         .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST,
1621         .ecc_irq_handler = altr_edac_a10_ecc_irq,
1622         .inject_fops = &altr_edac_a10_device_inject_fops,
1623 };
1624
1625 static const struct edac_device_prv_data a10_sdmmceccb_data = {
1626         .setup = altr_portb_setup,
1627         .ce_clear_mask = ALTR_A10_ECC_SERRPENB,
1628         .ue_clear_mask = ALTR_A10_ECC_DERRPENB,
1629         .ecc_enable_mask = ALTR_A10_COMMON_ECC_EN_CTL,
1630         .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST,
1631         .ce_set_mask = ALTR_A10_ECC_TSERRB,
1632         .ue_set_mask = ALTR_A10_ECC_TDERRB,
1633         .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST,
1634         .ecc_irq_handler = altr_edac_a10_ecc_irq_portb,
1635         .inject_fops = &altr_edac_a10_device_inject_fops,
1636 };
1637
1638 static int __init socfpga_init_sdmmc_ecc(void)
1639 {
1640         int rc = -ENODEV;
1641         struct device_node *child;
1642
1643         if (!socfpga_is_a10() && !socfpga_is_s10())
1644                 return -ENODEV;
1645
1646         child = of_find_compatible_node(NULL, NULL, "altr,socfpga-sdmmc-ecc");
1647         if (!child) {
1648                 edac_printk(KERN_WARNING, EDAC_DEVICE, "SDMMC node not found\n");
1649                 return -ENODEV;
1650         }
1651
1652         if (!of_device_is_available(child))
1653                 goto exit;
1654
1655         if (validate_parent_available(child))
1656                 goto exit;
1657
1658         rc = altr_init_a10_ecc_block(child, ALTR_A10_SDMMC_IRQ_MASK,
1659                                      a10_sdmmcecca_data.ecc_enable_mask, 1);
1660 exit:
1661         of_node_put(child);
1662         return rc;
1663 }
1664
1665 early_initcall(socfpga_init_sdmmc_ecc);
1666
1667 #endif  /* CONFIG_EDAC_ALTERA_SDMMC */
1668
1669 /********************* Arria10 EDAC Device Functions *************************/
1670 static const struct of_device_id altr_edac_a10_device_of_match[] = {
1671 #ifdef CONFIG_EDAC_ALTERA_L2C
1672         { .compatible = "altr,socfpga-a10-l2-ecc", .data = &a10_l2ecc_data },
1673 #endif
1674 #ifdef CONFIG_EDAC_ALTERA_OCRAM
1675         { .compatible = "altr,socfpga-a10-ocram-ecc",
1676           .data = &a10_ocramecc_data },
1677 #endif
1678 #ifdef CONFIG_EDAC_ALTERA_ETHERNET
1679         { .compatible = "altr,socfpga-eth-mac-ecc",
1680           .data = &a10_enetecc_data },
1681 #endif
1682 #ifdef CONFIG_EDAC_ALTERA_NAND
1683         { .compatible = "altr,socfpga-nand-ecc", .data = &a10_nandecc_data },
1684 #endif
1685 #ifdef CONFIG_EDAC_ALTERA_DMA
1686         { .compatible = "altr,socfpga-dma-ecc", .data = &a10_dmaecc_data },
1687 #endif
1688 #ifdef CONFIG_EDAC_ALTERA_USB
1689         { .compatible = "altr,socfpga-usb-ecc", .data = &a10_usbecc_data },
1690 #endif
1691 #ifdef CONFIG_EDAC_ALTERA_QSPI
1692         { .compatible = "altr,socfpga-qspi-ecc", .data = &a10_qspiecc_data },
1693 #endif
1694 #ifdef CONFIG_EDAC_ALTERA_SDMMC
1695         { .compatible = "altr,socfpga-sdmmc-ecc", .data = &a10_sdmmcecca_data },
1696 #endif
1697         {},
1698 };
1699 MODULE_DEVICE_TABLE(of, altr_edac_a10_device_of_match);
1700
1701 /*
1702  * The Arria10 EDAC Device Functions differ from the Cyclone5/Arria5
1703  * because 2 IRQs are shared among the all ECC peripherals. The ECC
1704  * manager manages the IRQs and the children.
1705  * Based on xgene_edac.c peripheral code.
1706  */
1707
1708 static ssize_t altr_edac_a10_device_trig(struct file *file,
1709                                          const char __user *user_buf,
1710                                          size_t count, loff_t *ppos)
1711 {
1712         struct edac_device_ctl_info *edac_dci = file->private_data;
1713         struct altr_edac_device_dev *drvdata = edac_dci->pvt_info;
1714         const struct edac_device_prv_data *priv = drvdata->data;
1715         void __iomem *set_addr = (drvdata->base + priv->set_err_ofst);
1716         unsigned long flags;
1717         u8 trig_type;
1718
1719         if (!user_buf || get_user(trig_type, user_buf))
1720                 return -EFAULT;
1721
1722         local_irq_save(flags);
1723         if (trig_type == ALTR_UE_TRIGGER_CHAR)
1724                 writel(priv->ue_set_mask, set_addr);
1725         else
1726                 writel(priv->ce_set_mask, set_addr);
1727
1728         /* Ensure the interrupt test bits are set */
1729         wmb();
1730         local_irq_restore(flags);
1731
1732         return count;
1733 }
1734
1735 /*
1736  * The Stratix10 EDAC Error Injection Functions differ from Arria10
1737  * slightly. A few Arria10 peripherals can use this injection function.
1738  * Inject the error into the memory and then readback to trigger the IRQ.
1739  */
1740 static ssize_t altr_edac_a10_device_trig2(struct file *file,
1741                                           const char __user *user_buf,
1742                                           size_t count, loff_t *ppos)
1743 {
1744         struct edac_device_ctl_info *edac_dci = file->private_data;
1745         struct altr_edac_device_dev *drvdata = edac_dci->pvt_info;
1746         const struct edac_device_prv_data *priv = drvdata->data;
1747         void __iomem *set_addr = (drvdata->base + priv->set_err_ofst);
1748         unsigned long flags;
1749         u8 trig_type;
1750
1751         if (!user_buf || get_user(trig_type, user_buf))
1752                 return -EFAULT;
1753
1754         local_irq_save(flags);
1755         if (trig_type == ALTR_UE_TRIGGER_CHAR) {
1756                 writel(priv->ue_set_mask, set_addr);
1757         } else {
1758                 /* Setup write of 0 to first 4 bytes */
1759                 writel(0x0, drvdata->base + ECC_BLK_WDATA0_OFST);
1760                 writel(0x0, drvdata->base + ECC_BLK_WDATA1_OFST);
1761                 writel(0x0, drvdata->base + ECC_BLK_WDATA2_OFST);
1762                 writel(0x0, drvdata->base + ECC_BLK_WDATA3_OFST);
1763                 /* Setup write of 4 bytes */
1764                 writel(ECC_WORD_WRITE, drvdata->base + ECC_BLK_DBYTECTRL_OFST);
1765                 /* Setup Address to 0 */
1766                 writel(0x0, drvdata->base + ECC_BLK_ADDRESS_OFST);
1767                 /* Setup accctrl to write & data override */
1768                 writel(ECC_WRITE_DOVR, drvdata->base + ECC_BLK_ACCCTRL_OFST);
1769                 /* Kick it. */
1770                 writel(ECC_XACT_KICK, drvdata->base + ECC_BLK_STARTACC_OFST);
1771                 /* Setup accctrl to read & ecc override */
1772                 writel(ECC_READ_EOVR, drvdata->base + ECC_BLK_ACCCTRL_OFST);
1773                 /* Kick it. */
1774                 writel(ECC_XACT_KICK, drvdata->base + ECC_BLK_STARTACC_OFST);
1775                 /* Setup write for single bit change */
1776                 writel(0x1, drvdata->base + ECC_BLK_WDATA0_OFST);
1777                 writel(0x0, drvdata->base + ECC_BLK_WDATA1_OFST);
1778                 writel(0x0, drvdata->base + ECC_BLK_WDATA2_OFST);
1779                 writel(0x0, drvdata->base + ECC_BLK_WDATA3_OFST);
1780                 /* Copy Read ECC to Write ECC */
1781                 writel(readl(drvdata->base + ECC_BLK_RECC0_OFST),
1782                        drvdata->base + ECC_BLK_WECC0_OFST);
1783                 writel(readl(drvdata->base + ECC_BLK_RECC1_OFST),
1784                        drvdata->base + ECC_BLK_WECC1_OFST);
1785                 /* Setup accctrl to write & ecc override & data override */
1786                 writel(ECC_WRITE_EDOVR, drvdata->base + ECC_BLK_ACCCTRL_OFST);
1787                 /* Kick it. */
1788                 writel(ECC_XACT_KICK, drvdata->base + ECC_BLK_STARTACC_OFST);
1789                 /* Setup accctrl to read & ecc overwrite & data overwrite */
1790                 writel(ECC_READ_EDOVR, drvdata->base + ECC_BLK_ACCCTRL_OFST);
1791                 /* Kick it. */
1792                 writel(ECC_XACT_KICK, drvdata->base + ECC_BLK_STARTACC_OFST);
1793         }
1794
1795         /* Ensure the interrupt test bits are set */
1796         wmb();
1797         local_irq_restore(flags);
1798
1799         return count;
1800 }
1801
1802 static void altr_edac_a10_irq_handler(struct irq_desc *desc)
1803 {
1804         int dberr, bit, sm_offset, irq_status;
1805         struct altr_arria10_edac *edac = irq_desc_get_handler_data(desc);
1806         struct irq_chip *chip = irq_desc_get_chip(desc);
1807         int irq = irq_desc_get_irq(desc);
1808
1809         dberr = (irq == edac->db_irq) ? 1 : 0;
1810         sm_offset = dberr ? A10_SYSMGR_ECC_INTSTAT_DERR_OFST :
1811                             A10_SYSMGR_ECC_INTSTAT_SERR_OFST;
1812
1813         chained_irq_enter(chip, desc);
1814
1815         regmap_read(edac->ecc_mgr_map, sm_offset, &irq_status);
1816
1817         for_each_set_bit(bit, (unsigned long *)&irq_status, 32) {
1818                 irq = irq_linear_revmap(edac->domain, dberr * 32 + bit);
1819                 if (irq)
1820                         generic_handle_irq(irq);
1821         }
1822
1823         chained_irq_exit(chip, desc);
1824 }
1825
1826 static int validate_parent_available(struct device_node *np)
1827 {
1828         struct device_node *parent;
1829         int ret = 0;
1830
1831         /* Ensure parent device is enabled if parent node exists */
1832         parent = of_parse_phandle(np, "altr,ecc-parent", 0);
1833         if (parent && !of_device_is_available(parent))
1834                 ret = -ENODEV;
1835
1836         of_node_put(parent);
1837         return ret;
1838 }
1839
1840 static int altr_edac_a10_device_add(struct altr_arria10_edac *edac,
1841                                     struct device_node *np)
1842 {
1843         struct edac_device_ctl_info *dci;
1844         struct altr_edac_device_dev *altdev;
1845         char *ecc_name = (char *)np->name;
1846         struct resource res;
1847         int edac_idx;
1848         int rc = 0;
1849         const struct edac_device_prv_data *prv;
1850         /* Get matching node and check for valid result */
1851         const struct of_device_id *pdev_id =
1852                 of_match_node(altr_edac_a10_device_of_match, np);
1853         if (IS_ERR_OR_NULL(pdev_id))
1854                 return -ENODEV;
1855
1856         /* Get driver specific data for this EDAC device */
1857         prv = pdev_id->data;
1858         if (IS_ERR_OR_NULL(prv))
1859                 return -ENODEV;
1860
1861         if (validate_parent_available(np))
1862                 return -ENODEV;
1863
1864         if (!devres_open_group(edac->dev, altr_edac_a10_device_add, GFP_KERNEL))
1865                 return -ENOMEM;
1866
1867         rc = of_address_to_resource(np, 0, &res);
1868         if (rc < 0) {
1869                 edac_printk(KERN_ERR, EDAC_DEVICE,
1870                             "%s: no resource address\n", ecc_name);
1871                 goto err_release_group;
1872         }
1873
1874         edac_idx = edac_device_alloc_index();
1875         dci = edac_device_alloc_ctl_info(sizeof(*altdev), ecc_name,
1876                                          1, ecc_name, 1, 0, NULL, 0,
1877                                          edac_idx);
1878
1879         if (!dci) {
1880                 edac_printk(KERN_ERR, EDAC_DEVICE,
1881                             "%s: Unable to allocate EDAC device\n", ecc_name);
1882                 rc = -ENOMEM;
1883                 goto err_release_group;
1884         }
1885
1886         altdev = dci->pvt_info;
1887         dci->dev = edac->dev;
1888         altdev->edac_dev_name = ecc_name;
1889         altdev->edac_idx = edac_idx;
1890         altdev->edac = edac;
1891         altdev->edac_dev = dci;
1892         altdev->data = prv;
1893         altdev->ddev = *edac->dev;
1894         dci->dev = &altdev->ddev;
1895         dci->ctl_name = "Altera ECC Manager";
1896         dci->mod_name = ecc_name;
1897         dci->dev_name = ecc_name;
1898
1899         altdev->base = devm_ioremap_resource(edac->dev, &res);
1900         if (IS_ERR(altdev->base)) {
1901                 rc = PTR_ERR(altdev->base);
1902                 goto err_release_group1;
1903         }
1904
1905         /* Check specific dependencies for the module */
1906         if (altdev->data->setup) {
1907                 rc = altdev->data->setup(altdev);
1908                 if (rc)
1909                         goto err_release_group1;
1910         }
1911
1912         altdev->sb_irq = irq_of_parse_and_map(np, 0);
1913         if (!altdev->sb_irq) {
1914                 edac_printk(KERN_ERR, EDAC_DEVICE, "Error allocating SBIRQ\n");
1915                 rc = -ENODEV;
1916                 goto err_release_group1;
1917         }
1918         rc = devm_request_irq(edac->dev, altdev->sb_irq, prv->ecc_irq_handler,
1919                               IRQF_ONESHOT | IRQF_TRIGGER_HIGH,
1920                               ecc_name, altdev);
1921         if (rc) {
1922                 edac_printk(KERN_ERR, EDAC_DEVICE, "No SBERR IRQ resource\n");
1923                 goto err_release_group1;
1924         }
1925
1926         altdev->db_irq = irq_of_parse_and_map(np, 1);
1927         if (!altdev->db_irq) {
1928                 edac_printk(KERN_ERR, EDAC_DEVICE, "Error allocating DBIRQ\n");
1929                 rc = -ENODEV;
1930                 goto err_release_group1;
1931         }
1932         rc = devm_request_irq(edac->dev, altdev->db_irq, prv->ecc_irq_handler,
1933                               IRQF_ONESHOT | IRQF_TRIGGER_HIGH,
1934                               ecc_name, altdev);
1935         if (rc) {
1936                 edac_printk(KERN_ERR, EDAC_DEVICE, "No DBERR IRQ resource\n");
1937                 goto err_release_group1;
1938         }
1939
1940         rc = edac_device_add_device(dci);
1941         if (rc) {
1942                 dev_err(edac->dev, "edac_device_add_device failed\n");
1943                 rc = -ENOMEM;
1944                 goto err_release_group1;
1945         }
1946
1947         altr_create_edacdev_dbgfs(dci, prv);
1948
1949         list_add(&altdev->next, &edac->a10_ecc_devices);
1950
1951         devres_remove_group(edac->dev, altr_edac_a10_device_add);
1952
1953         return 0;
1954
1955 err_release_group1:
1956         edac_device_free_ctl_info(dci);
1957 err_release_group:
1958         devres_release_group(edac->dev, NULL);
1959         edac_printk(KERN_ERR, EDAC_DEVICE,
1960                     "%s:Error setting up EDAC device: %d\n", ecc_name, rc);
1961
1962         return rc;
1963 }
1964
1965 static void a10_eccmgr_irq_mask(struct irq_data *d)
1966 {
1967         struct altr_arria10_edac *edac = irq_data_get_irq_chip_data(d);
1968
1969         regmap_write(edac->ecc_mgr_map, A10_SYSMGR_ECC_INTMASK_SET_OFST,
1970                      BIT(d->hwirq));
1971 }
1972
1973 static void a10_eccmgr_irq_unmask(struct irq_data *d)
1974 {
1975         struct altr_arria10_edac *edac = irq_data_get_irq_chip_data(d);
1976
1977         regmap_write(edac->ecc_mgr_map, A10_SYSMGR_ECC_INTMASK_CLR_OFST,
1978                      BIT(d->hwirq));
1979 }
1980
1981 static int a10_eccmgr_irqdomain_map(struct irq_domain *d, unsigned int irq,
1982                                     irq_hw_number_t hwirq)
1983 {
1984         struct altr_arria10_edac *edac = d->host_data;
1985
1986         irq_set_chip_and_handler(irq, &edac->irq_chip, handle_simple_irq);
1987         irq_set_chip_data(irq, edac);
1988         irq_set_noprobe(irq);
1989
1990         return 0;
1991 }
1992
1993 static const struct irq_domain_ops a10_eccmgr_ic_ops = {
1994         .map = a10_eccmgr_irqdomain_map,
1995         .xlate = irq_domain_xlate_twocell,
1996 };
1997
1998 /************** Stratix 10 EDAC Double Bit Error Handler ************/
1999 #define to_a10edac(p, m) container_of(p, struct altr_arria10_edac, m)
2000
2001 /*
2002  * The double bit error is handled through SError which is fatal. This is
2003  * called as a panic notifier to printout ECC error info as part of the panic.
2004  */
2005 static int s10_edac_dberr_handler(struct notifier_block *this,
2006                                   unsigned long event, void *ptr)
2007 {
2008         struct altr_arria10_edac *edac = to_a10edac(this, panic_notifier);
2009         int err_addr, dberror;
2010
2011         regmap_read(edac->ecc_mgr_map, S10_SYSMGR_ECC_INTSTAT_DERR_OFST,
2012                     &dberror);
2013         regmap_write(edac->ecc_mgr_map, S10_SYSMGR_UE_VAL_OFST, dberror);
2014         if (dberror & S10_DDR0_IRQ_MASK) {
2015                 regmap_read(edac->ecc_mgr_map, A10_DERRADDR_OFST, &err_addr);
2016                 regmap_write(edac->ecc_mgr_map, S10_SYSMGR_UE_ADDR_OFST,
2017                              err_addr);
2018                 edac_printk(KERN_ERR, EDAC_MC,
2019                             "EDAC: [Uncorrectable errors @ 0x%08X]\n\n",
2020                             err_addr);
2021         }
2022
2023         return NOTIFY_DONE;
2024 }
2025
2026 /****************** Arria 10 EDAC Probe Function *********************/
2027 static int altr_edac_a10_probe(struct platform_device *pdev)
2028 {
2029         struct altr_arria10_edac *edac;
2030         struct device_node *child;
2031
2032         edac = devm_kzalloc(&pdev->dev, sizeof(*edac), GFP_KERNEL);
2033         if (!edac)
2034                 return -ENOMEM;
2035
2036         edac->dev = &pdev->dev;
2037         platform_set_drvdata(pdev, edac);
2038         INIT_LIST_HEAD(&edac->a10_ecc_devices);
2039
2040         if (socfpga_is_a10()) {
2041                 edac->ecc_mgr_map =
2042                         syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
2043                                                         "altr,sysmgr-syscon");
2044         } else {
2045                 struct device_node *sysmgr_np;
2046                 struct resource res;
2047                 uintptr_t base;
2048
2049                 sysmgr_np = of_parse_phandle(pdev->dev.of_node,
2050                                              "altr,sysmgr-syscon", 0);
2051                 if (!sysmgr_np) {
2052                         edac_printk(KERN_ERR, EDAC_DEVICE,
2053                                     "Unable to find altr,sysmgr-syscon\n");
2054                         return -ENODEV;
2055                 }
2056
2057                 if (of_address_to_resource(sysmgr_np, 0, &res))
2058                         return -ENOMEM;
2059
2060                 /* Need physical address for SMCC call */
2061                 base = res.start;
2062
2063                 edac->ecc_mgr_map = devm_regmap_init(&pdev->dev, NULL,
2064                                                      (void *)base,
2065                                                      &s10_sdram_regmap_cfg);
2066         }
2067
2068         if (IS_ERR(edac->ecc_mgr_map)) {
2069                 edac_printk(KERN_ERR, EDAC_DEVICE,
2070                             "Unable to get syscon altr,sysmgr-syscon\n");
2071                 return PTR_ERR(edac->ecc_mgr_map);
2072         }
2073
2074         edac->irq_chip.name = pdev->dev.of_node->name;
2075         edac->irq_chip.irq_mask = a10_eccmgr_irq_mask;
2076         edac->irq_chip.irq_unmask = a10_eccmgr_irq_unmask;
2077         edac->domain = irq_domain_add_linear(pdev->dev.of_node, 64,
2078                                              &a10_eccmgr_ic_ops, edac);
2079         if (!edac->domain) {
2080                 dev_err(&pdev->dev, "Error adding IRQ domain\n");
2081                 return -ENOMEM;
2082         }
2083
2084         edac->sb_irq = platform_get_irq(pdev, 0);
2085         if (edac->sb_irq < 0) {
2086                 dev_err(&pdev->dev, "No SBERR IRQ resource\n");
2087                 return edac->sb_irq;
2088         }
2089
2090         irq_set_chained_handler_and_data(edac->sb_irq,
2091                                          altr_edac_a10_irq_handler,
2092                                          edac);
2093
2094         if (socfpga_is_a10()) {
2095                 edac->db_irq = platform_get_irq(pdev, 1);
2096                 if (edac->db_irq < 0) {
2097                         dev_err(&pdev->dev, "No DBERR IRQ resource\n");
2098                         return edac->db_irq;
2099                 }
2100                 irq_set_chained_handler_and_data(edac->db_irq,
2101                                                  altr_edac_a10_irq_handler,
2102                                                  edac);
2103         } else {
2104                 int dberror, err_addr;
2105
2106                 edac->panic_notifier.notifier_call = s10_edac_dberr_handler;
2107                 atomic_notifier_chain_register(&panic_notifier_list,
2108                                                &edac->panic_notifier);
2109
2110                 /* Printout a message if uncorrectable error previously. */
2111                 regmap_read(edac->ecc_mgr_map, S10_SYSMGR_UE_VAL_OFST,
2112                             &dberror);
2113                 if (dberror) {
2114                         regmap_read(edac->ecc_mgr_map, S10_SYSMGR_UE_ADDR_OFST,
2115                                     &err_addr);
2116                         edac_printk(KERN_ERR, EDAC_DEVICE,
2117                                     "Previous Boot UE detected[0x%X] @ 0x%X\n",
2118                                     dberror, err_addr);
2119                         /* Reset the sticky registers */
2120                         regmap_write(edac->ecc_mgr_map,
2121                                      S10_SYSMGR_UE_VAL_OFST, 0);
2122                         regmap_write(edac->ecc_mgr_map,
2123                                      S10_SYSMGR_UE_ADDR_OFST, 0);
2124                 }
2125         }
2126
2127         for_each_child_of_node(pdev->dev.of_node, child) {
2128                 if (!of_device_is_available(child))
2129                         continue;
2130
2131                 if (of_device_is_compatible(child, "altr,socfpga-a10-l2-ecc") ||
2132                     of_device_is_compatible(child, "altr,socfpga-a10-ocram-ecc") ||
2133                     of_device_is_compatible(child, "altr,socfpga-eth-mac-ecc") ||
2134                     of_device_is_compatible(child, "altr,socfpga-nand-ecc") ||
2135                     of_device_is_compatible(child, "altr,socfpga-dma-ecc") ||
2136                     of_device_is_compatible(child, "altr,socfpga-usb-ecc") ||
2137                     of_device_is_compatible(child, "altr,socfpga-qspi-ecc") ||
2138                     of_device_is_compatible(child, "altr,socfpga-sdmmc-ecc"))
2139
2140                         altr_edac_a10_device_add(edac, child);
2141
2142                 else if ((of_device_is_compatible(child, "altr,sdram-edac-a10")) ||
2143                          (of_device_is_compatible(child, "altr,sdram-edac-s10")))
2144                         of_platform_populate(pdev->dev.of_node,
2145                                              altr_sdram_ctrl_of_match,
2146                                              NULL, &pdev->dev);
2147         }
2148
2149         return 0;
2150 }
2151
2152 static const struct of_device_id altr_edac_a10_of_match[] = {
2153         { .compatible = "altr,socfpga-a10-ecc-manager" },
2154         { .compatible = "altr,socfpga-s10-ecc-manager" },
2155         {},
2156 };
2157 MODULE_DEVICE_TABLE(of, altr_edac_a10_of_match);
2158
2159 static struct platform_driver altr_edac_a10_driver = {
2160         .probe =  altr_edac_a10_probe,
2161         .driver = {
2162                 .name = "socfpga_a10_ecc_manager",
2163                 .of_match_table = altr_edac_a10_of_match,
2164         },
2165 };
2166 module_platform_driver(altr_edac_a10_driver);
2167
2168 MODULE_LICENSE("GPL v2");
2169 MODULE_AUTHOR("Thor Thayer");
2170 MODULE_DESCRIPTION("EDAC Driver for Altera Memories");