3 # Copyright (c) 2008 Doug Thompson www.softwarebitmaker.com
4 # Licensed and distributed under the GPL
6 config EDAC_ATOMIC_SCRUB
13 tristate "EDAC (Error Detection And Correction) reporting"
14 depends on HAS_IOMEM && EDAC_SUPPORT && RAS
16 EDAC is a subsystem along with hardware-specific drivers designed to
17 report hardware errors. These are low-level errors that are reported
18 in the CPU or supporting chipset or other subsystems:
19 memory errors, cache errors, PCI errors, thermal throttling, etc..
20 If unsure, select 'Y'.
22 The mailing list for the EDAC project is linux-edac@vger.kernel.org.
26 config EDAC_LEGACY_SYSFS
27 bool "EDAC legacy sysfs"
30 Enable the compatibility sysfs nodes.
31 Use 'Y' if your edac utilities aren't ported to work with the newer
38 This turns on debugging information for the entire EDAC subsystem.
39 You do so by inserting edac_module with "edac_debug_level=x." Valid
40 levels are 0-4 (from low to high) and by default it is set to 2.
41 Usually you should select 'N' here.
43 config EDAC_DECODE_MCE
44 tristate "Decode MCEs in human-readable form (only on AMD for now)"
45 depends on CPU_SUP_AMD && X86_MCE_AMD
48 Enable this option if you want to decode Machine Check Exceptions
49 occurring on your machine in human-readable form.
51 You should definitely say Y here in case you want to decode MCEs
52 which occur really early upon boot, before the module infrastructure
56 tristate "Output ACPI APEI/GHES BIOS detected errors via EDAC"
57 depends on ACPI_APEI_GHES
60 Not all machines support hardware-driven error report. Some of those
61 provide a BIOS-driven error report mechanism via ACPI, using the
62 APEI/GHES driver. By enabling this option, the error reports provided
63 by GHES are sent to userspace via the EDAC API.
65 When this option is enabled, it will disable the hardware-driven
66 mechanisms, if a GHES BIOS is detected, entering into the
67 "Firmware First" mode.
69 It should be noticed that keeping both GHES and a hardware-driven
70 error mechanism won't work well, as BIOS will race with OS, while
71 reading the error registers. So, if you want to not use "Firmware
72 first" GHES error mechanism, you should disable GHES either at
73 compilation time or by passing "ghes.disable=1" Kernel parameter
79 tristate "AMD64 (Opteron, Athlon64)"
80 depends on AMD_NB && EDAC_DECODE_MCE
82 Support for error detection and correction of DRAM ECC errors on
83 the AMD64 families (>= K8) of memory controllers.
85 When EDAC_DEBUG is enabled, hardware error injection facilities
86 through sysfs are available:
88 AMD CPUs up to and excluding family 0x17 provide for Memory
89 Error Injection into the ECC detection circuits. The amd64_edac
90 module allows the operator/user to inject Uncorrectable and
91 Correctable errors into DRAM.
93 When enabled, in each of the respective memory controller directories
94 (/sys/devices/system/edac/mc/mcX), there are 3 input files:
96 - inject_section (0..3, 16-byte section of 64-byte cacheline),
97 - inject_word (0..8, 16-bit word of 16-byte section),
98 - inject_ecc_vector (hex ecc vector: select bits of inject word)
100 In addition, there are two control files, inject_read and inject_write,
101 which trigger the DRAM ECC Read and Write respectively.
104 tristate "Amazon's Annapurna Lab Memory Controller"
105 depends on (ARCH_ALPINE || COMPILE_TEST)
107 Support for error detection and correction for Amazon's Annapurna
108 Labs Alpine chips which allow 1 bit correction and 2 bits detection.
111 tristate "AMD 76x (760, 762, 768)"
112 depends on PCI && X86_32
114 Support for error detection and correction on the AMD 76x
115 series of chipsets used with the Athlon processor.
118 tristate "Intel e7xxx (e7205, e7500, e7501, e7505)"
119 depends on PCI && X86_32
121 Support for error detection and correction on the Intel
122 E7205, E7500, E7501 and E7505 server chipsets.
125 tristate "Intel e752x (e7520, e7525, e7320) and 3100"
126 depends on PCI && X86
128 Support for error detection and correction on the Intel
129 E7520, E7525, E7320 server chipsets.
131 config EDAC_I82443BXGX
132 tristate "Intel 82443BX/GX (440BX/GX)"
133 depends on PCI && X86_32
136 Support for error detection and correction on the Intel
137 82443BX/GX memory controllers (440BX/GX chipsets).
140 tristate "Intel 82875p (D82875P, E7210)"
141 depends on PCI && X86_32
143 Support for error detection and correction on the Intel
144 DP82785P and E7210 server chipsets.
147 tristate "Intel 82975x (D82975x)"
148 depends on PCI && X86
150 Support for error detection and correction on the Intel
151 DP82975x server chipsets.
154 tristate "Intel 3000/3010"
155 depends on PCI && X86
157 Support for error detection and correction on the Intel
158 3000 and 3010 server chipsets.
161 tristate "Intel 3200"
162 depends on PCI && X86
164 Support for error detection and correction on the Intel
165 3200 and 3210 server chipsets.
168 tristate "Intel e312xx"
169 depends on PCI && X86
171 Support for error detection and correction on the Intel
172 E3-1200 based DRAM controllers.
176 depends on PCI && X86
178 Support for error detection and correction on the Intel
182 tristate "Intel 5400 (Seaburg) chipsets"
183 depends on PCI && X86
185 Support for error detection and correction the Intel
186 i5400 MCH chipset (Seaburg).
189 tristate "Intel i7 Core (Nehalem) processors"
190 depends on PCI && X86 && X86_MCE_INTEL
192 Support for error detection and correction the Intel
193 i7 Core (Nehalem) Integrated Memory Controller that exists on
194 newer processors like i7 Core, i7 Core Extreme, Xeon 35xx
195 and Xeon 55xx processors.
198 tristate "Intel 82860"
199 depends on PCI && X86_32
201 Support for error detection and correction on the Intel
205 tristate "Radisys 82600 embedded chipset"
206 depends on PCI && X86_32
208 Support for error detection and correction on the Radisys
209 82600 embedded chipset.
212 tristate "Intel Greencreek/Blackford chipset"
213 depends on X86 && PCI
216 Support for error detection and correction the Intel
217 Greekcreek/Blackford chipsets.
220 tristate "Intel San Clemente MCH"
221 depends on X86 && PCI
223 Support for error detection and correction the Intel
227 tristate "Intel Clarksboro MCH"
228 depends on X86 && PCI
230 Support for error detection and correction the Intel
231 Clarksboro MCH (Intel 7300 chipset).
234 tristate "Intel Sandy-Bridge/Ivy-Bridge/Haswell Integrated MC"
235 depends on PCI && X86_64 && X86_MCE_INTEL && PCI_MMCONFIG
237 Support for error detection and correction the Intel
238 Sandy Bridge, Ivy Bridge and Haswell Integrated Memory Controllers.
241 tristate "Intel Skylake server Integrated MC"
242 depends on PCI && X86_64 && X86_MCE_INTEL && PCI_MMCONFIG && ACPI
243 depends on ACPI_NFIT || !ACPI_NFIT # if ACPI_NFIT=m, EDAC_SKX can't be y
247 Support for error detection and correction the Intel
248 Skylake server Integrated Memory Controllers. If your
249 system has non-volatile DIMMs you should also manually
250 select CONFIG_ACPI_NFIT.
253 tristate "Intel 10nm server Integrated MC"
254 depends on PCI && X86_64 && X86_MCE_INTEL && PCI_MMCONFIG && ACPI
255 depends on ACPI_NFIT || !ACPI_NFIT # if ACPI_NFIT=m, EDAC_I10NM can't be y
259 Support for error detection and correction the Intel
260 10nm server Integrated Memory Controllers. If your
261 system has non-volatile DIMMs you should also manually
262 select CONFIG_ACPI_NFIT.
265 tristate "Intel Pondicherry2"
266 depends on PCI && X86_64 && X86_MCE_INTEL
269 Support for error detection and correction on the Intel
270 Pondicherry2 Integrated Memory Controller. This SoC IP is
271 first used on the Apollo Lake platform and Denverton
272 micro-server but may appear on others in the future.
275 tristate "Intel client SoC Integrated MC"
276 depends on PCI && PCI_MMCONFIG && ARCH_HAVE_NMI_SAFE_CMPXCHG
277 depends on X86_64 && X86_MCE_INTEL
279 Support for error detection and correction on the Intel
280 client SoC Integrated Memory Controller using In-Band ECC IP.
281 This In-Band ECC is first used on the Elkhart Lake SoC but
282 may appear on others in the future.
285 bool "Freescale MPC83xx / MPC85xx"
286 depends on FSL_SOC && EDAC=y
288 Support for error detection and correction on the Freescale
289 MPC8349, MPC8560, MPC8540, MPC8548, T4240
291 config EDAC_LAYERSCAPE
292 tristate "Freescale Layerscape DDR"
293 depends on ARCH_LAYERSCAPE || SOC_LS1021A
295 Support for error detection and correction on Freescale memory
296 controllers on Layerscape SoCs.
299 tristate "PA Semi PWRficient"
300 depends on PPC_PASEMI && PCI
302 Support for error detection and correction on PA Semi
306 tristate "Cell Broadband Engine memory controller"
307 depends on PPC_CELL_COMMON
309 Support for error detection and correction on the
310 Cell Broadband Engine internal memory controller
311 on platform without a hypervisor
314 tristate "PPC4xx IBM DDR2 Memory Controller"
317 This enables support for EDAC on the ECC memory used
318 with the IBM DDR2 memory controller found in various
319 PowerPC 4xx embedded processors such as the 405EX[r],
320 440SP, 440SPe, 460EX, 460GT and 460SX.
323 tristate "AMD8131 HyperTransport PCI-X Tunnel"
324 depends on PCI && PPC_MAPLE
326 Support for error detection and correction on the
327 AMD8131 HyperTransport PCI-X Tunnel chip.
328 Note, add more Kconfig dependency if it's adopted
329 on some machine other than Maple.
332 tristate "AMD8111 HyperTransport I/O Hub"
333 depends on PCI && PPC_MAPLE
335 Support for error detection and correction on the
336 AMD8111 HyperTransport I/O Hub chip.
337 Note, add more Kconfig dependency if it's adopted
338 on some machine other than Maple.
341 tristate "IBM CPC925 Memory Controller (PPC970FX)"
344 Support for error detection and correction on the
345 IBM CPC925 Bridge and Memory Controller, which is
346 a companion chip to the PowerPC 970 family of
349 config EDAC_HIGHBANK_MC
350 tristate "Highbank Memory Controller"
351 depends on ARCH_HIGHBANK
353 Support for error detection and correction on the
354 Calxeda Highbank memory controller.
356 config EDAC_HIGHBANK_L2
357 tristate "Highbank L2 Cache"
358 depends on ARCH_HIGHBANK
360 Support for error detection and correction on the
361 Calxeda Highbank memory controller.
363 config EDAC_OCTEON_PC
364 tristate "Cavium Octeon Primary Caches"
365 depends on CPU_CAVIUM_OCTEON
367 Support for error detection and correction on the primary caches of
368 the cnMIPS cores of Cavium Octeon family SOCs.
370 config EDAC_OCTEON_L2C
371 tristate "Cavium Octeon Secondary Caches (L2C)"
372 depends on CAVIUM_OCTEON_SOC
374 Support for error detection and correction on the
375 Cavium Octeon family of SOCs.
377 config EDAC_OCTEON_LMC
378 tristate "Cavium Octeon DRAM Memory Controller (LMC)"
379 depends on CAVIUM_OCTEON_SOC
381 Support for error detection and correction on the
382 Cavium Octeon family of SOCs.
384 config EDAC_OCTEON_PCI
385 tristate "Cavium Octeon PCI Controller"
386 depends on PCI && CAVIUM_OCTEON_SOC
388 Support for error detection and correction on the
389 Cavium Octeon family of SOCs.
392 tristate "Cavium ThunderX EDAC"
396 Support for error detection and correction on the
397 Cavium ThunderX memory controllers (LMC), Cache
398 Coherent Processor Interconnect (CCPI) and L2 cache
399 blocks (TAD, CBC, MCI).
402 bool "Altera SOCFPGA ECC"
403 depends on EDAC=y && ARCH_INTEL_SOCFPGA
405 Support for error detection and correction on the
406 Altera SOCs. This is the global enable for the
407 various Altera peripherals.
409 config EDAC_ALTERA_SDRAM
410 bool "Altera SDRAM ECC"
411 depends on EDAC_ALTERA=y
413 Support for error detection and correction on the
414 Altera SDRAM Memory for Altera SoCs. Note that the
415 preloader must initialize the SDRAM before loading
418 config EDAC_ALTERA_L2C
419 bool "Altera L2 Cache ECC"
420 depends on EDAC_ALTERA=y && CACHE_L2X0
422 Support for error detection and correction on the
423 Altera L2 cache Memory for Altera SoCs. This option
426 config EDAC_ALTERA_OCRAM
427 bool "Altera On-Chip RAM ECC"
428 depends on EDAC_ALTERA=y && SRAM && GENERIC_ALLOCATOR
430 Support for error detection and correction on the
431 Altera On-Chip RAM Memory for Altera SoCs.
433 config EDAC_ALTERA_ETHERNET
434 bool "Altera Ethernet FIFO ECC"
435 depends on EDAC_ALTERA=y
437 Support for error detection and correction on the
438 Altera Ethernet FIFO Memory for Altera SoCs.
440 config EDAC_ALTERA_NAND
441 bool "Altera NAND FIFO ECC"
442 depends on EDAC_ALTERA=y && MTD_NAND_DENALI
444 Support for error detection and correction on the
445 Altera NAND FIFO Memory for Altera SoCs.
447 config EDAC_ALTERA_DMA
448 bool "Altera DMA FIFO ECC"
449 depends on EDAC_ALTERA=y && PL330_DMA=y
451 Support for error detection and correction on the
452 Altera DMA FIFO Memory for Altera SoCs.
454 config EDAC_ALTERA_USB
455 bool "Altera USB FIFO ECC"
456 depends on EDAC_ALTERA=y && USB_DWC2
458 Support for error detection and correction on the
459 Altera USB FIFO Memory for Altera SoCs.
461 config EDAC_ALTERA_QSPI
462 bool "Altera QSPI FIFO ECC"
463 depends on EDAC_ALTERA=y && SPI_CADENCE_QUADSPI
465 Support for error detection and correction on the
466 Altera QSPI FIFO Memory for Altera SoCs.
468 config EDAC_ALTERA_SDMMC
469 bool "Altera SDMMC FIFO ECC"
470 depends on EDAC_ALTERA=y && MMC_DW
472 Support for error detection and correction on the
473 Altera SDMMC FIFO Memory for Altera SoCs.
476 bool "Sifive platform EDAC driver"
477 depends on EDAC=y && SIFIVE_CCACHE
479 Support for error detection and correction on the SiFive SoCs.
481 config EDAC_ARMADA_XP
482 bool "Marvell Armada XP DDR and L2 Cache ECC"
483 depends on MACH_MVEBU_V7
485 Support for error correction and detection on the Marvell Aramada XP
486 DDR RAM and L2 cache controllers.
489 tristate "Synopsys DDR Memory Controller"
490 depends on ARCH_ZYNQ || ARCH_ZYNQMP || ARCH_INTEL_SOCFPGA || ARCH_MXC
492 Support for error detection and correction on the Synopsys DDR
496 tristate "APM X-Gene SoC"
497 depends on (ARM64 || COMPILE_TEST)
499 Support for error detection and correction on the
500 APM X-Gene family of SOCs.
503 tristate "Texas Instruments DDR3 ECC Controller"
504 depends on ARCH_KEYSTONE || SOC_DRA7XX
506 Support for error detection and correction on the TI SoCs.
509 tristate "QCOM EDAC Controller"
510 depends on ARCH_QCOM && QCOM_LLCC
512 Support for error detection and correction on the
513 Qualcomm Technologies, Inc. SoCs.
515 This driver reports Single Bit Errors (SBEs) and Double Bit Errors (DBEs).
516 As of now, it supports error reporting for Last Level Cache Controller (LLCC)
517 of Tag RAM and Data RAM.
519 For debugging issues having to do with stability and overall system
520 health, you should probably say 'Y' here.
523 tristate "Aspeed AST BMC SoC"
524 depends on ARCH_ASPEED
526 Support for error detection and correction on the Aspeed AST BMC SoC.
528 First, ECC must be configured in the bootloader. Then, this driver
529 will expose error counters via the EDAC kernel framework.
531 config EDAC_BLUEFIELD
532 tristate "Mellanox BlueField Memory ECC"
533 depends on ARM64 && ((MELLANOX_PLATFORM && ACPI) || COMPILE_TEST)
535 Support for error detection and correction on the
536 Mellanox BlueField SoCs.
539 tristate "ARM DMC-520 ECC"
542 Support for error detection and correction on the
543 SoCs with ARM DMC-520 DRAM controller.
546 tristate "Xilinx ZynqMP OCM Controller"
547 depends on ARCH_ZYNQMP || COMPILE_TEST
549 This driver supports error detection and correction for the
550 Xilinx ZynqMP OCM (On Chip Memory) controller. It can also be
551 built as a module. In that case it will be called zynqmp_edac.
554 tristate "Nuvoton NPCM DDR Memory Controller"
555 depends on (ARCH_NPCM || COMPILE_TEST)
557 Support for error detection and correction on the Nuvoton NPCM DDR
560 The memory controller supports single bit error correction, double bit
561 error detection (in-line ECC in which a section 1/8th of the memory
562 device used to store data is used for ECC storage).