3 # Copyright (c) 2008 Doug Thompson www.softwarebitmaker.com
4 # Licensed and distributed under the GPL
6 config EDAC_ATOMIC_SCRUB
13 tristate "EDAC (Error Detection And Correction) reporting"
14 depends on HAS_IOMEM && EDAC_SUPPORT && RAS
16 EDAC is a subsystem along with hardware-specific drivers designed to
17 report hardware errors. These are low-level errors that are reported
18 in the CPU or supporting chipset or other subsystems:
19 memory errors, cache errors, PCI errors, thermal throttling, etc..
20 If unsure, select 'Y'.
22 The mailing list for the EDAC project is linux-edac@vger.kernel.org.
26 config EDAC_LEGACY_SYSFS
27 bool "EDAC legacy sysfs"
30 Enable the compatibility sysfs nodes.
31 Use 'Y' if your edac utilities aren't ported to work with the newer
38 This turns on debugging information for the entire EDAC subsystem.
39 You do so by inserting edac_module with "edac_debug_level=x." Valid
40 levels are 0-4 (from low to high) and by default it is set to 2.
41 Usually you should select 'N' here.
43 config EDAC_DECODE_MCE
44 tristate "Decode MCEs in human-readable form (only on AMD for now)"
45 depends on CPU_SUP_AMD && X86_MCE_AMD
48 Enable this option if you want to decode Machine Check Exceptions
49 occurring on your machine in human-readable form.
51 You should definitely say Y here in case you want to decode MCEs
52 which occur really early upon boot, before the module infrastructure
56 tristate "Output ACPI APEI/GHES BIOS detected errors via EDAC"
57 depends on ACPI_APEI_GHES
60 Not all machines support hardware-driven error report. Some of those
61 provide a BIOS-driven error report mechanism via ACPI, using the
62 APEI/GHES driver. By enabling this option, the error reports provided
63 by GHES are sent to userspace via the EDAC API.
65 When this option is enabled, it will disable the hardware-driven
66 mechanisms, if a GHES BIOS is detected, entering into the
67 "Firmware First" mode.
69 It should be noticed that keeping both GHES and a hardware-driven
70 error mechanism won't work well, as BIOS will race with OS, while
71 reading the error registers. So, if you want to not use "Firmware
72 first" GHES error mechanism, you should disable GHES either at
73 compilation time or by passing "ghes.disable=1" Kernel parameter
79 tristate "AMD64 (Opteron, Athlon64)"
80 depends on AMD_NB && EDAC_DECODE_MCE
83 Support for error detection and correction of DRAM ECC errors on
84 the AMD64 families (>= K8) of memory controllers.
86 When EDAC_DEBUG is enabled, hardware error injection facilities
87 through sysfs are available:
89 AMD CPUs up to and excluding family 0x17 provide for Memory
90 Error Injection into the ECC detection circuits. The amd64_edac
91 module allows the operator/user to inject Uncorrectable and
92 Correctable errors into DRAM.
94 When enabled, in each of the respective memory controller directories
95 (/sys/devices/system/edac/mc/mcX), there are 3 input files:
97 - inject_section (0..3, 16-byte section of 64-byte cacheline),
98 - inject_word (0..8, 16-bit word of 16-byte section),
99 - inject_ecc_vector (hex ecc vector: select bits of inject word)
101 In addition, there are two control files, inject_read and inject_write,
102 which trigger the DRAM ECC Read and Write respectively.
105 tristate "Amazon's Annapurna Lab Memory Controller"
106 depends on (ARCH_ALPINE || COMPILE_TEST)
108 Support for error detection and correction for Amazon's Annapurna
109 Labs Alpine chips which allow 1 bit correction and 2 bits detection.
112 tristate "AMD 76x (760, 762, 768)"
113 depends on PCI && X86_32
115 Support for error detection and correction on the AMD 76x
116 series of chipsets used with the Athlon processor.
119 tristate "Intel e7xxx (e7205, e7500, e7501, e7505)"
120 depends on PCI && X86_32
122 Support for error detection and correction on the Intel
123 E7205, E7500, E7501 and E7505 server chipsets.
126 tristate "Intel e752x (e7520, e7525, e7320) and 3100"
127 depends on PCI && X86
129 Support for error detection and correction on the Intel
130 E7520, E7525, E7320 server chipsets.
132 config EDAC_I82443BXGX
133 tristate "Intel 82443BX/GX (440BX/GX)"
134 depends on PCI && X86_32
137 Support for error detection and correction on the Intel
138 82443BX/GX memory controllers (440BX/GX chipsets).
141 tristate "Intel 82875p (D82875P, E7210)"
142 depends on PCI && X86_32
144 Support for error detection and correction on the Intel
145 DP82785P and E7210 server chipsets.
148 tristate "Intel 82975x (D82975x)"
149 depends on PCI && X86
151 Support for error detection and correction on the Intel
152 DP82975x server chipsets.
155 tristate "Intel 3000/3010"
156 depends on PCI && X86
158 Support for error detection and correction on the Intel
159 3000 and 3010 server chipsets.
162 tristate "Intel 3200"
163 depends on PCI && X86
165 Support for error detection and correction on the Intel
166 3200 and 3210 server chipsets.
169 tristate "Intel e312xx"
170 depends on PCI && X86
172 Support for error detection and correction on the Intel
173 E3-1200 based DRAM controllers.
177 depends on PCI && X86
179 Support for error detection and correction on the Intel
183 tristate "Intel 5400 (Seaburg) chipsets"
184 depends on PCI && X86
186 Support for error detection and correction the Intel
187 i5400 MCH chipset (Seaburg).
190 tristate "Intel i7 Core (Nehalem) processors"
191 depends on PCI && X86 && X86_MCE_INTEL
193 Support for error detection and correction the Intel
194 i7 Core (Nehalem) Integrated Memory Controller that exists on
195 newer processors like i7 Core, i7 Core Extreme, Xeon 35xx
196 and Xeon 55xx processors.
199 tristate "Intel 82860"
200 depends on PCI && X86_32
202 Support for error detection and correction on the Intel
206 tristate "Radisys 82600 embedded chipset"
207 depends on PCI && X86_32
209 Support for error detection and correction on the Radisys
210 82600 embedded chipset.
213 tristate "Intel Greencreek/Blackford chipset"
214 depends on X86 && PCI
217 Support for error detection and correction the Intel
218 Greekcreek/Blackford chipsets.
221 tristate "Intel San Clemente MCH"
222 depends on X86 && PCI
224 Support for error detection and correction the Intel
228 tristate "Intel Clarksboro MCH"
229 depends on X86 && PCI
231 Support for error detection and correction the Intel
232 Clarksboro MCH (Intel 7300 chipset).
235 tristate "Intel Sandy-Bridge/Ivy-Bridge/Haswell Integrated MC"
236 depends on PCI && X86_64 && X86_MCE_INTEL && PCI_MMCONFIG
238 Support for error detection and correction the Intel
239 Sandy Bridge, Ivy Bridge and Haswell Integrated Memory Controllers.
242 tristate "Intel Skylake server Integrated MC"
243 depends on PCI && X86_64 && X86_MCE_INTEL && PCI_MMCONFIG && ACPI
244 depends on ACPI_NFIT || !ACPI_NFIT # if ACPI_NFIT=m, EDAC_SKX can't be y
248 Support for error detection and correction the Intel
249 Skylake server Integrated Memory Controllers. If your
250 system has non-volatile DIMMs you should also manually
251 select CONFIG_ACPI_NFIT.
254 tristate "Intel 10nm server Integrated MC"
255 depends on PCI && X86_64 && X86_MCE_INTEL && PCI_MMCONFIG && ACPI
256 depends on ACPI_NFIT || !ACPI_NFIT # if ACPI_NFIT=m, EDAC_I10NM can't be y
260 Support for error detection and correction the Intel
261 10nm server Integrated Memory Controllers. If your
262 system has non-volatile DIMMs you should also manually
263 select CONFIG_ACPI_NFIT.
266 tristate "Intel Pondicherry2"
267 depends on PCI && X86_64 && X86_MCE_INTEL
270 Support for error detection and correction on the Intel
271 Pondicherry2 Integrated Memory Controller. This SoC IP is
272 first used on the Apollo Lake platform and Denverton
273 micro-server but may appear on others in the future.
276 tristate "Intel client SoC Integrated MC"
277 depends on PCI && PCI_MMCONFIG && ARCH_HAVE_NMI_SAFE_CMPXCHG
278 depends on X86_64 && X86_MCE_INTEL
280 Support for error detection and correction on the Intel
281 client SoC Integrated Memory Controller using In-Band ECC IP.
282 This In-Band ECC is first used on the Elkhart Lake SoC but
283 may appear on others in the future.
286 bool "Freescale MPC83xx / MPC85xx"
287 depends on FSL_SOC && EDAC=y
289 Support for error detection and correction on the Freescale
290 MPC8349, MPC8560, MPC8540, MPC8548, T4240
292 config EDAC_LAYERSCAPE
293 tristate "Freescale Layerscape DDR"
294 depends on ARCH_LAYERSCAPE || SOC_LS1021A
296 Support for error detection and correction on Freescale memory
297 controllers on Layerscape SoCs.
300 tristate "PA Semi PWRficient"
301 depends on PPC_PASEMI && PCI
303 Support for error detection and correction on PA Semi
307 tristate "Cell Broadband Engine memory controller"
308 depends on PPC_CELL_COMMON
310 Support for error detection and correction on the
311 Cell Broadband Engine internal memory controller
312 on platform without a hypervisor
315 tristate "PPC4xx IBM DDR2 Memory Controller"
318 This enables support for EDAC on the ECC memory used
319 with the IBM DDR2 memory controller found in various
320 PowerPC 4xx embedded processors such as the 405EX[r],
321 440SP, 440SPe, 460EX, 460GT and 460SX.
324 tristate "AMD8131 HyperTransport PCI-X Tunnel"
325 depends on PCI && PPC_MAPLE
327 Support for error detection and correction on the
328 AMD8131 HyperTransport PCI-X Tunnel chip.
329 Note, add more Kconfig dependency if it's adopted
330 on some machine other than Maple.
333 tristate "AMD8111 HyperTransport I/O Hub"
334 depends on PCI && PPC_MAPLE
336 Support for error detection and correction on the
337 AMD8111 HyperTransport I/O Hub chip.
338 Note, add more Kconfig dependency if it's adopted
339 on some machine other than Maple.
342 tristate "IBM CPC925 Memory Controller (PPC970FX)"
345 Support for error detection and correction on the
346 IBM CPC925 Bridge and Memory Controller, which is
347 a companion chip to the PowerPC 970 family of
350 config EDAC_HIGHBANK_MC
351 tristate "Highbank Memory Controller"
352 depends on ARCH_HIGHBANK
354 Support for error detection and correction on the
355 Calxeda Highbank memory controller.
357 config EDAC_HIGHBANK_L2
358 tristate "Highbank L2 Cache"
359 depends on ARCH_HIGHBANK
361 Support for error detection and correction on the
362 Calxeda Highbank memory controller.
364 config EDAC_OCTEON_PC
365 tristate "Cavium Octeon Primary Caches"
366 depends on CPU_CAVIUM_OCTEON
368 Support for error detection and correction on the primary caches of
369 the cnMIPS cores of Cavium Octeon family SOCs.
371 config EDAC_OCTEON_L2C
372 tristate "Cavium Octeon Secondary Caches (L2C)"
373 depends on CAVIUM_OCTEON_SOC
375 Support for error detection and correction on the
376 Cavium Octeon family of SOCs.
378 config EDAC_OCTEON_LMC
379 tristate "Cavium Octeon DRAM Memory Controller (LMC)"
380 depends on CAVIUM_OCTEON_SOC
382 Support for error detection and correction on the
383 Cavium Octeon family of SOCs.
385 config EDAC_OCTEON_PCI
386 tristate "Cavium Octeon PCI Controller"
387 depends on PCI && CAVIUM_OCTEON_SOC
389 Support for error detection and correction on the
390 Cavium Octeon family of SOCs.
393 tristate "Cavium ThunderX EDAC"
397 Support for error detection and correction on the
398 Cavium ThunderX memory controllers (LMC), Cache
399 Coherent Processor Interconnect (CCPI) and L2 cache
400 blocks (TAD, CBC, MCI).
403 bool "Altera SOCFPGA ECC"
404 depends on EDAC=y && ARCH_INTEL_SOCFPGA
406 Support for error detection and correction on the
407 Altera SOCs. This is the global enable for the
408 various Altera peripherals.
410 config EDAC_ALTERA_SDRAM
411 bool "Altera SDRAM ECC"
412 depends on EDAC_ALTERA=y
414 Support for error detection and correction on the
415 Altera SDRAM Memory for Altera SoCs. Note that the
416 preloader must initialize the SDRAM before loading
419 config EDAC_ALTERA_L2C
420 bool "Altera L2 Cache ECC"
421 depends on EDAC_ALTERA=y && CACHE_L2X0
423 Support for error detection and correction on the
424 Altera L2 cache Memory for Altera SoCs. This option
427 config EDAC_ALTERA_OCRAM
428 bool "Altera On-Chip RAM ECC"
429 depends on EDAC_ALTERA=y && SRAM && GENERIC_ALLOCATOR
431 Support for error detection and correction on the
432 Altera On-Chip RAM Memory for Altera SoCs.
434 config EDAC_ALTERA_ETHERNET
435 bool "Altera Ethernet FIFO ECC"
436 depends on EDAC_ALTERA=y
438 Support for error detection and correction on the
439 Altera Ethernet FIFO Memory for Altera SoCs.
441 config EDAC_ALTERA_NAND
442 bool "Altera NAND FIFO ECC"
443 depends on EDAC_ALTERA=y && MTD_NAND_DENALI
445 Support for error detection and correction on the
446 Altera NAND FIFO Memory for Altera SoCs.
448 config EDAC_ALTERA_DMA
449 bool "Altera DMA FIFO ECC"
450 depends on EDAC_ALTERA=y && PL330_DMA=y
452 Support for error detection and correction on the
453 Altera DMA FIFO Memory for Altera SoCs.
455 config EDAC_ALTERA_USB
456 bool "Altera USB FIFO ECC"
457 depends on EDAC_ALTERA=y && USB_DWC2
459 Support for error detection and correction on the
460 Altera USB FIFO Memory for Altera SoCs.
462 config EDAC_ALTERA_QSPI
463 bool "Altera QSPI FIFO ECC"
464 depends on EDAC_ALTERA=y && SPI_CADENCE_QUADSPI
466 Support for error detection and correction on the
467 Altera QSPI FIFO Memory for Altera SoCs.
469 config EDAC_ALTERA_SDMMC
470 bool "Altera SDMMC FIFO ECC"
471 depends on EDAC_ALTERA=y && MMC_DW
473 Support for error detection and correction on the
474 Altera SDMMC FIFO Memory for Altera SoCs.
477 bool "Sifive platform EDAC driver"
478 depends on EDAC=y && SIFIVE_CCACHE
480 Support for error detection and correction on the SiFive SoCs.
482 config EDAC_ARMADA_XP
483 bool "Marvell Armada XP DDR and L2 Cache ECC"
484 depends on MACH_MVEBU_V7
486 Support for error correction and detection on the Marvell Aramada XP
487 DDR RAM and L2 cache controllers.
490 tristate "Synopsys DDR Memory Controller"
491 depends on ARCH_ZYNQ || ARCH_ZYNQMP || ARCH_INTEL_SOCFPGA || ARCH_MXC
493 Support for error detection and correction on the Synopsys DDR
497 tristate "APM X-Gene SoC"
498 depends on (ARM64 || COMPILE_TEST)
500 Support for error detection and correction on the
501 APM X-Gene family of SOCs.
504 tristate "Texas Instruments DDR3 ECC Controller"
505 depends on ARCH_KEYSTONE || SOC_DRA7XX
507 Support for error detection and correction on the TI SoCs.
510 tristate "QCOM EDAC Controller"
511 depends on ARCH_QCOM && QCOM_LLCC
513 Support for error detection and correction on the
514 Qualcomm Technologies, Inc. SoCs.
516 This driver reports Single Bit Errors (SBEs) and Double Bit Errors (DBEs).
517 As of now, it supports error reporting for Last Level Cache Controller (LLCC)
518 of Tag RAM and Data RAM.
520 For debugging issues having to do with stability and overall system
521 health, you should probably say 'Y' here.
524 tristate "Aspeed AST BMC SoC"
525 depends on ARCH_ASPEED
527 Support for error detection and correction on the Aspeed AST BMC SoC.
529 First, ECC must be configured in the bootloader. Then, this driver
530 will expose error counters via the EDAC kernel framework.
532 config EDAC_BLUEFIELD
533 tristate "Mellanox BlueField Memory ECC"
534 depends on ARM64 && ((MELLANOX_PLATFORM && ACPI) || COMPILE_TEST)
536 Support for error detection and correction on the
537 Mellanox BlueField SoCs.
540 tristate "ARM DMC-520 ECC"
543 Support for error detection and correction on the
544 SoCs with ARM DMC-520 DRAM controller.
547 tristate "Xilinx ZynqMP OCM Controller"
548 depends on ARCH_ZYNQMP || COMPILE_TEST
550 This driver supports error detection and correction for the
551 Xilinx ZynqMP OCM (On Chip Memory) controller. It can also be
552 built as a module. In that case it will be called zynqmp_edac.
555 tristate "Nuvoton NPCM DDR Memory Controller"
556 depends on (ARCH_NPCM || COMPILE_TEST)
558 Support for error detection and correction on the Nuvoton NPCM DDR
561 The memory controller supports single bit error correction, double bit
562 error detection (in-line ECC in which a section 1/8th of the memory
563 device used to store data is used for ECC storage).
566 tristate "Xilinx Versal DDR Memory Controller"
567 depends on ARCH_ZYNQMP || COMPILE_TEST
569 Support for error detection and correction on the Xilinx Versal DDR
572 Report both single bit errors (CE) and double bit errors (UE).
573 Support injecting both correctable and uncorrectable errors
574 for debugging purposes.