drivers/dma/stm32-dma.c

   1 /*
   2  * Driver for STM32 DMA controller
   3  *
   4  * Inspired by dma-jz4740.c and tegra20-apb-dma.c
   5  *
   6  * Copyright (C) M'boumba Cedric Madianga 2015
   7  * Author: M'boumba Cedric Madianga <cedric.madianga@gmail.com>
   8  *         Pierre-Yves Mordret <pierre-yves.mordret@st.com>
   9  *
  10  * License terms:  GNU General Public License (GPL), version 2
  11  */
  12
  13 #include <linux/clk.h>
  14 #include <linux/delay.h>
  15 #include <linux/dmaengine.h>
  16 #include <linux/dma-mapping.h>
  17 #include <linux/err.h>
  18 #include <linux/init.h>
  19 #include <linux/jiffies.h>
  20 #include <linux/list.h>
  21 #include <linux/module.h>
  22 #include <linux/of.h>
  23 #include <linux/of_device.h>
  24 #include <linux/of_dma.h>
  25 #include <linux/platform_device.h>
  26 #include <linux/reset.h>
  27 #include <linux/sched.h>
  28 #include <linux/slab.h>
  29
  30 #include "virt-dma.h"
  31
  32 #define STM32_DMA_LISR                  0x0000 /* DMA Low Int Status Reg */
  33 #define STM32_DMA_HISR                  0x0004 /* DMA High Int Status Reg */
  34 #define STM32_DMA_LIFCR                 0x0008 /* DMA Low Int Flag Clear Reg */
  35 #define STM32_DMA_HIFCR                 0x000c /* DMA High Int Flag Clear Reg */
  36 #define STM32_DMA_TCI                   BIT(5) /* Transfer Complete Interrupt */
  37 #define STM32_DMA_HTI                   BIT(4) /* Half Transfer Interrupt */
  38 #define STM32_DMA_TEI                   BIT(3) /* Transfer Error Interrupt */
  39 #define STM32_DMA_DMEI                  BIT(2) /* Direct Mode Error Interrupt */
  40 #define STM32_DMA_FEI                   BIT(0) /* FIFO Error Interrupt */
  41 #define STM32_DMA_MASKI                 (STM32_DMA_TCI \
  42                                          | STM32_DMA_TEI \
  43                                          | STM32_DMA_DMEI \
  44                                          | STM32_DMA_FEI)
  45
  46 /* DMA Stream x Configuration Register */
  47 #define STM32_DMA_SCR(x)                (0x0010 + 0x18 * (x)) /* x = 0..7 */
  48 #define STM32_DMA_SCR_REQ(n)            ((n & 0x7) << 25)
  49 #define STM32_DMA_SCR_MBURST_MASK       GENMASK(24, 23)
  50 #define STM32_DMA_SCR_MBURST(n)         ((n & 0x3) << 23)
  51 #define STM32_DMA_SCR_PBURST_MASK       GENMASK(22, 21)
  52 #define STM32_DMA_SCR_PBURST(n)         ((n & 0x3) << 21)
  53 #define STM32_DMA_SCR_PL_MASK           GENMASK(17, 16)
  54 #define STM32_DMA_SCR_PL(n)             ((n & 0x3) << 16)
  55 #define STM32_DMA_SCR_MSIZE_MASK        GENMASK(14, 13)
  56 #define STM32_DMA_SCR_MSIZE(n)          ((n & 0x3) << 13)
  57 #define STM32_DMA_SCR_PSIZE_MASK        GENMASK(12, 11)
  58 #define STM32_DMA_SCR_PSIZE(n)          ((n & 0x3) << 11)
  59 #define STM32_DMA_SCR_PSIZE_GET(n)      ((n & STM32_DMA_SCR_PSIZE_MASK) >> 11)
  60 #define STM32_DMA_SCR_DIR_MASK          GENMASK(7, 6)
  61 #define STM32_DMA_SCR_DIR(n)            ((n & 0x3) << 6)
  62 #define STM32_DMA_SCR_CT                BIT(19) /* Target in double buffer */
  63 #define STM32_DMA_SCR_DBM               BIT(18) /* Double Buffer Mode */
  64 #define STM32_DMA_SCR_PINCOS            BIT(15) /* Peripheral inc offset size */
  65 #define STM32_DMA_SCR_MINC              BIT(10) /* Memory increment mode */
  66 #define STM32_DMA_SCR_PINC              BIT(9) /* Peripheral increment mode */
  67 #define STM32_DMA_SCR_CIRC              BIT(8) /* Circular mode */
  68 #define STM32_DMA_SCR_PFCTRL            BIT(5) /* Peripheral Flow Controller */
  69 #define STM32_DMA_SCR_TCIE              BIT(4) /* Transfer Complete Int Enable
  70                                                 */
  71 #define STM32_DMA_SCR_TEIE              BIT(2) /* Transfer Error Int Enable */
  72 #define STM32_DMA_SCR_DMEIE             BIT(1) /* Direct Mode Err Int Enable */
  73 #define STM32_DMA_SCR_EN                BIT(0) /* Stream Enable */
  74 #define STM32_DMA_SCR_CFG_MASK          (STM32_DMA_SCR_PINC \
  75                                         | STM32_DMA_SCR_MINC \
  76                                         | STM32_DMA_SCR_PINCOS \
  77                                         | STM32_DMA_SCR_PL_MASK)
  78 #define STM32_DMA_SCR_IRQ_MASK          (STM32_DMA_SCR_TCIE \
  79                                         | STM32_DMA_SCR_TEIE \
  80                                         | STM32_DMA_SCR_DMEIE)
  81
  82 /* DMA Stream x number of data register */
  83 #define STM32_DMA_SNDTR(x)              (0x0014 + 0x18 * (x))
  84
  85 /* DMA stream peripheral address register */
  86 #define STM32_DMA_SPAR(x)               (0x0018 + 0x18 * (x))
  87
  88 /* DMA stream x memory 0 address register */
  89 #define STM32_DMA_SM0AR(x)              (0x001c + 0x18 * (x))
  90
  91 /* DMA stream x memory 1 address register */
  92 #define STM32_DMA_SM1AR(x)              (0x0020 + 0x18 * (x))
  93
  94 /* DMA stream x FIFO control register */
  95 #define STM32_DMA_SFCR(x)               (0x0024 + 0x18 * (x))
  96 #define STM32_DMA_SFCR_FTH_MASK         GENMASK(1, 0)
  97 #define STM32_DMA_SFCR_FTH(n)           (n & STM32_DMA_SFCR_FTH_MASK)
  98 #define STM32_DMA_SFCR_FEIE             BIT(7) /* FIFO error interrupt enable */
  99 #define STM32_DMA_SFCR_DMDIS            BIT(2) /* Direct mode disable */
 100 #define STM32_DMA_SFCR_MASK             (STM32_DMA_SFCR_FEIE \
 101                                         | STM32_DMA_SFCR_DMDIS)
 102
 103 /* DMA direction */
 104 #define STM32_DMA_DEV_TO_MEM            0x00
 105 #define STM32_DMA_MEM_TO_DEV            0x01
 106 #define STM32_DMA_MEM_TO_MEM            0x02
 107
 108 /* DMA priority level */
 109 #define STM32_DMA_PRIORITY_LOW          0x00
 110 #define STM32_DMA_PRIORITY_MEDIUM       0x01
 111 #define STM32_DMA_PRIORITY_HIGH         0x02
 112 #define STM32_DMA_PRIORITY_VERY_HIGH    0x03
 113
 114 /* DMA FIFO threshold selection */
 115 #define STM32_DMA_FIFO_THRESHOLD_1QUARTERFULL           0x00
 116 #define STM32_DMA_FIFO_THRESHOLD_HALFFULL               0x01
 117 #define STM32_DMA_FIFO_THRESHOLD_3QUARTERSFULL          0x02
 118 #define STM32_DMA_FIFO_THRESHOLD_FULL                   0x03
 119
 120 #define STM32_DMA_MAX_DATA_ITEMS        0xffff
 121 /*
 122  * Valid transfer starts from @0 to @0xFFFE leading to unaligned scatter
 123  * gather at boundary. Thus it's safer to round down this value on FIFO
 124  * size (16 Bytes)
 125  */
 126 #define STM32_DMA_ALIGNED_MAX_DATA_ITEMS        \
 127         ALIGN_DOWN(STM32_DMA_MAX_DATA_ITEMS, 16)
 128 #define STM32_DMA_MAX_CHANNELS          0x08
 129 #define STM32_DMA_MAX_REQUEST_ID        0x08
 130 #define STM32_DMA_MAX_DATA_PARAM        0x03
 131 #define STM32_DMA_FIFO_SIZE             16      /* FIFO is 16 bytes */
 132 #define STM32_DMA_MIN_BURST             4
 133 #define STM32_DMA_MAX_BURST             16
 134
 135 /* DMA Features */
 136 #define STM32_DMA_THRESHOLD_FTR_MASK    GENMASK(1, 0)
 137 #define STM32_DMA_THRESHOLD_FTR_GET(n)  ((n) & STM32_DMA_THRESHOLD_FTR_MASK)
 138
 139 enum stm32_dma_width {
 140         STM32_DMA_BYTE,
 141         STM32_DMA_HALF_WORD,
 142         STM32_DMA_WORD,
 143 };
 144
 145 enum stm32_dma_burst_size {
 146         STM32_DMA_BURST_SINGLE,
 147         STM32_DMA_BURST_INCR4,
 148         STM32_DMA_BURST_INCR8,
 149         STM32_DMA_BURST_INCR16,
 150 };
 151
 152 /**
 153  * struct stm32_dma_cfg - STM32 DMA custom configuration
 154  * @channel_id: channel ID
 155  * @request_line: DMA request
 156  * @stream_config: 32bit mask specifying the DMA channel configuration
 157  * @features: 32bit mask specifying the DMA Feature list
 158  */
 159 struct stm32_dma_cfg {
 160         u32 channel_id;
 161         u32 request_line;
 162         u32 stream_config;
 163         u32 features;
 164 };
 165
 166 struct stm32_dma_chan_reg {
 167         u32 dma_lisr;
 168         u32 dma_hisr;
 169         u32 dma_lifcr;
 170         u32 dma_hifcr;
 171         u32 dma_scr;
 172         u32 dma_sndtr;
 173         u32 dma_spar;
 174         u32 dma_sm0ar;
 175         u32 dma_sm1ar;
 176         u32 dma_sfcr;
 177 };
 178
 179 struct stm32_dma_sg_req {
 180         u32 len;
 181         struct stm32_dma_chan_reg chan_reg;
 182 };
 183
 184 struct stm32_dma_desc {
 185         struct virt_dma_desc vdesc;
 186         bool cyclic;
 187         u32 num_sgs;
 188         struct stm32_dma_sg_req sg_req[];
 189 };
 190
 191 struct stm32_dma_chan {
 192         struct virt_dma_chan vchan;
 193         bool config_init;
 194         bool busy;
 195         u32 id;
 196         u32 irq;
 197         struct stm32_dma_desc *desc;
 198         u32 next_sg;
 199         struct dma_slave_config dma_sconfig;
 200         struct stm32_dma_chan_reg chan_reg;
 201         u32 threshold;
 202         u32 mem_burst;
 203         u32 mem_width;
 204 };
 205
 206 struct stm32_dma_device {
 207         struct dma_device ddev;
 208         void __iomem *base;
 209         struct clk *clk;
 210         struct reset_control *rst;
 211         bool mem2mem;
 212         struct stm32_dma_chan chan[STM32_DMA_MAX_CHANNELS];
 213 };
 214
 215 static struct stm32_dma_device *stm32_dma_get_dev(struct stm32_dma_chan *chan)
 216 {
 217         return container_of(chan->vchan.chan.device, struct stm32_dma_device,
 218                             ddev);
 219 }
 220
 221 static struct stm32_dma_chan *to_stm32_dma_chan(struct dma_chan *c)
 222 {
 223         return container_of(c, struct stm32_dma_chan, vchan.chan);
 224 }
 225
 226 static struct stm32_dma_desc *to_stm32_dma_desc(struct virt_dma_desc *vdesc)
 227 {
 228         return container_of(vdesc, struct stm32_dma_desc, vdesc);
 229 }
 230
 231 static struct device *chan2dev(struct stm32_dma_chan *chan)
 232 {
 233         return &chan->vchan.chan.dev->device;
 234 }
 235
 236 static u32 stm32_dma_read(struct stm32_dma_device *dmadev, u32 reg)
 237 {
 238         return readl_relaxed(dmadev->base + reg);
 239 }
 240
 241 static void stm32_dma_write(struct stm32_dma_device *dmadev, u32 reg, u32 val)
 242 {
 243         writel_relaxed(val, dmadev->base + reg);
 244 }
 245
 246 static struct stm32_dma_desc *stm32_dma_alloc_desc(u32 num_sgs)
 247 {
 248         return kzalloc(sizeof(struct stm32_dma_desc) +
 249                        sizeof(struct stm32_dma_sg_req) * num_sgs, GFP_NOWAIT);
 250 }
 251
 252 static int stm32_dma_get_width(struct stm32_dma_chan *chan,
 253                                enum dma_slave_buswidth width)
 254 {
 255         switch (width) {
 256         case DMA_SLAVE_BUSWIDTH_1_BYTE:
 257                 return STM32_DMA_BYTE;
 258         case DMA_SLAVE_BUSWIDTH_2_BYTES:
 259                 return STM32_DMA_HALF_WORD;
 260         case DMA_SLAVE_BUSWIDTH_4_BYTES:
 261                 return STM32_DMA_WORD;
 262         default:
 263                 dev_err(chan2dev(chan), "Dma bus width not supported\n");
 264                 return -EINVAL;
 265         }
 266 }
 267
 268 static enum dma_slave_buswidth stm32_dma_get_max_width(u32 buf_len,
 269                                                        u32 threshold)
 270 {
 271         enum dma_slave_buswidth max_width;
 272
 273         if (threshold == STM32_DMA_FIFO_THRESHOLD_FULL)
 274                 max_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 275         else
 276                 max_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
 277
 278         while ((buf_len < max_width  || buf_len % max_width) &&
 279                max_width > DMA_SLAVE_BUSWIDTH_1_BYTE)
 280                 max_width = max_width >> 1;
 281
 282         return max_width;
 283 }
 284
 285 static bool stm32_dma_fifo_threshold_is_allowed(u32 burst, u32 threshold,
 286                                                 enum dma_slave_buswidth width)
 287 {
 288         u32 remaining;
 289
 290         if (width != DMA_SLAVE_BUSWIDTH_UNDEFINED) {
 291                 if (burst != 0) {
 292                         /*
 293                          * If number of beats fit in several whole bursts
 294                          * this configuration is allowed.
 295                          */
 296                         remaining = ((STM32_DMA_FIFO_SIZE / width) *
 297                                      (threshold + 1) / 4) % burst;
 298
 299                         if (remaining == 0)
 300                                 return true;
 301                 } else {
 302                         return true;
 303                 }
 304         }
 305
 306         return false;
 307 }
 308
 309 static bool stm32_dma_is_burst_possible(u32 buf_len, u32 threshold)
 310 {
 311         /*
 312          * Buffer or period length has to be aligned on FIFO depth.
 313          * Otherwise bytes may be stuck within FIFO at buffer or period
 314          * length.
 315          */
 316         return ((buf_len % ((threshold + 1) * 4)) == 0);
 317 }
 318
 319 static u32 stm32_dma_get_best_burst(u32 buf_len, u32 max_burst, u32 threshold,
 320                                     enum dma_slave_buswidth width)
 321 {
 322         u32 best_burst = max_burst;
 323
 324         if (best_burst == 1 || !stm32_dma_is_burst_possible(buf_len, threshold))
 325                 return 0;
 326
 327         while ((buf_len < best_burst * width && best_burst > 1) ||
 328                !stm32_dma_fifo_threshold_is_allowed(best_burst, threshold,
 329                                                     width)) {
 330                 if (best_burst > STM32_DMA_MIN_BURST)
 331                         best_burst = best_burst >> 1;
 332                 else
 333                         best_burst = 0;
 334         }
 335
 336         return best_burst;
 337 }
 338
 339 static int stm32_dma_get_burst(struct stm32_dma_chan *chan, u32 maxburst)
 340 {
 341         switch (maxburst) {
 342         case 0:
 343         case 1:
 344                 return STM32_DMA_BURST_SINGLE;
 345         case 4:
 346                 return STM32_DMA_BURST_INCR4;
 347         case 8:
 348                 return STM32_DMA_BURST_INCR8;
 349         case 16:
 350                 return STM32_DMA_BURST_INCR16;
 351         default:
 352                 dev_err(chan2dev(chan), "Dma burst size not supported\n");
 353                 return -EINVAL;
 354         }
 355 }
 356
 357 static void stm32_dma_set_fifo_config(struct stm32_dma_chan *chan,
 358                                       u32 src_burst, u32 dst_burst)
 359 {
 360         chan->chan_reg.dma_sfcr &= ~STM32_DMA_SFCR_MASK;
 361         chan->chan_reg.dma_scr &= ~STM32_DMA_SCR_DMEIE;
 362
 363         if (!src_burst && !dst_burst) {
 364                 /* Using direct mode */
 365                 chan->chan_reg.dma_scr |= STM32_DMA_SCR_DMEIE;
 366         } else {
 367                 /* Using FIFO mode */
 368                 chan->chan_reg.dma_sfcr |= STM32_DMA_SFCR_MASK;
 369         }
 370 }
 371
 372 static int stm32_dma_slave_config(struct dma_chan *c,
 373                                   struct dma_slave_config *config)
 374 {
 375         struct stm32_dma_chan *chan = to_stm32_dma_chan(c);
 376
 377         memcpy(&chan->dma_sconfig, config, sizeof(*config));
 378
 379         chan->config_init = true;
 380
 381         return 0;
 382 }
 383
 384 static u32 stm32_dma_irq_status(struct stm32_dma_chan *chan)
 385 {
 386         struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan);
 387         u32 flags, dma_isr;
 388
 389         /*
 390          * Read "flags" from DMA_xISR register corresponding to the selected
 391          * DMA channel at the correct bit offset inside that register.
 392          *
 393          * If (ch % 4) is 2 or 3, left shift the mask by 16 bits.
 394          * If (ch % 4) is 1 or 3, additionally left shift the mask by 6 bits.
 395          */
 396
 397         if (chan->id & 4)
 398                 dma_isr = stm32_dma_read(dmadev, STM32_DMA_HISR);
 399         else
 400                 dma_isr = stm32_dma_read(dmadev, STM32_DMA_LISR);
 401
 402         flags = dma_isr >> (((chan->id & 2) << 3) | ((chan->id & 1) * 6));
 403
 404         return flags & STM32_DMA_MASKI;
 405 }
 406
 407 static void stm32_dma_irq_clear(struct stm32_dma_chan *chan, u32 flags)
 408 {
 409         struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan);
 410         u32 dma_ifcr;
 411
 412         /*
 413          * Write "flags" to the DMA_xIFCR register corresponding to the selected
 414          * DMA channel at the correct bit offset inside that register.
 415          *
 416          * If (ch % 4) is 2 or 3, left shift the mask by 16 bits.
 417          * If (ch % 4) is 1 or 3, additionally left shift the mask by 6 bits.
 418          */
 419         flags &= STM32_DMA_MASKI;
 420         dma_ifcr = flags << (((chan->id & 2) << 3) | ((chan->id & 1) * 6));
 421
 422         if (chan->id & 4)
 423                 stm32_dma_write(dmadev, STM32_DMA_HIFCR, dma_ifcr);
 424         else
 425                 stm32_dma_write(dmadev, STM32_DMA_LIFCR, dma_ifcr);
 426 }
 427
 428 static int stm32_dma_disable_chan(struct stm32_dma_chan *chan)
 429 {
 430         struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan);
 431         unsigned long timeout = jiffies + msecs_to_jiffies(5000);
 432         u32 dma_scr, id;
 433
 434         id = chan->id;
 435         dma_scr = stm32_dma_read(dmadev, STM32_DMA_SCR(id));
 436
 437         if (dma_scr & STM32_DMA_SCR_EN) {
 438                 dma_scr &= ~STM32_DMA_SCR_EN;
 439                 stm32_dma_write(dmadev, STM32_DMA_SCR(id), dma_scr);
 440
 441                 do {
 442                         dma_scr = stm32_dma_read(dmadev, STM32_DMA_SCR(id));
 443                         dma_scr &= STM32_DMA_SCR_EN;
 444                         if (!dma_scr)
 445                                 break;
 446
 447                         if (time_after_eq(jiffies, timeout)) {
 448                                 dev_err(chan2dev(chan), "%s: timeout!\n",
 449                                         __func__);
 450                                 return -EBUSY;
 451                         }
 452                         cond_resched();
 453                 } while (1);
 454         }
 455
 456         return 0;
 457 }
 458
 459 static void stm32_dma_stop(struct stm32_dma_chan *chan)
 460 {
 461         struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan);
 462         u32 dma_scr, dma_sfcr, status;
 463         int ret;
 464
 465         /* Disable interrupts */
 466         dma_scr = stm32_dma_read(dmadev, STM32_DMA_SCR(chan->id));
 467         dma_scr &= ~STM32_DMA_SCR_IRQ_MASK;
 468         stm32_dma_write(dmadev, STM32_DMA_SCR(chan->id), dma_scr);
 469         dma_sfcr = stm32_dma_read(dmadev, STM32_DMA_SFCR(chan->id));
 470         dma_sfcr &= ~STM32_DMA_SFCR_FEIE;
 471         stm32_dma_write(dmadev, STM32_DMA_SFCR(chan->id), dma_sfcr);
 472
 473         /* Disable DMA */
 474         ret = stm32_dma_disable_chan(chan);
 475         if (ret < 0)
 476                 return;
 477
 478         /* Clear interrupt status if it is there */
 479         status = stm32_dma_irq_status(chan);
 480         if (status) {
 481                 dev_dbg(chan2dev(chan), "%s(): clearing interrupt: 0x%08x\n",
 482                         __func__, status);
 483                 stm32_dma_irq_clear(chan, status);
 484         }
 485
 486         chan->busy = false;
 487 }
 488
 489 static int stm32_dma_terminate_all(struct dma_chan *c)
 490 {
 491         struct stm32_dma_chan *chan = to_stm32_dma_chan(c);
 492         unsigned long flags;
 493         LIST_HEAD(head);
 494
 495         spin_lock_irqsave(&chan->vchan.lock, flags);
 496
 497         if (chan->busy) {
 498                 stm32_dma_stop(chan);
 499                 chan->desc = NULL;
 500         }
 501
 502         vchan_get_all_descriptors(&chan->vchan, &head);
 503         spin_unlock_irqrestore(&chan->vchan.lock, flags);
 504         vchan_dma_desc_free_list(&chan->vchan, &head);
 505
 506         return 0;
 507 }
 508
 509 static void stm32_dma_synchronize(struct dma_chan *c)
 510 {
 511         struct stm32_dma_chan *chan = to_stm32_dma_chan(c);
 512
 513         vchan_synchronize(&chan->vchan);
 514 }
 515
 516 static void stm32_dma_dump_reg(struct stm32_dma_chan *chan)
 517 {
 518         struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan);
 519         u32 scr = stm32_dma_read(dmadev, STM32_DMA_SCR(chan->id));
 520         u32 ndtr = stm32_dma_read(dmadev, STM32_DMA_SNDTR(chan->id));
 521         u32 spar = stm32_dma_read(dmadev, STM32_DMA_SPAR(chan->id));
 522         u32 sm0ar = stm32_dma_read(dmadev, STM32_DMA_SM0AR(chan->id));
 523         u32 sm1ar = stm32_dma_read(dmadev, STM32_DMA_SM1AR(chan->id));
 524         u32 sfcr = stm32_dma_read(dmadev, STM32_DMA_SFCR(chan->id));
 525
 526         dev_dbg(chan2dev(chan), "SCR:   0x%08x\n", scr);
 527         dev_dbg(chan2dev(chan), "NDTR:  0x%08x\n", ndtr);
 528         dev_dbg(chan2dev(chan), "SPAR:  0x%08x\n", spar);
 529         dev_dbg(chan2dev(chan), "SM0AR: 0x%08x\n", sm0ar);
 530         dev_dbg(chan2dev(chan), "SM1AR: 0x%08x\n", sm1ar);
 531         dev_dbg(chan2dev(chan), "SFCR:  0x%08x\n", sfcr);
 532 }
 533
 534 static void stm32_dma_configure_next_sg(struct stm32_dma_chan *chan);
 535
 536 static void stm32_dma_start_transfer(struct stm32_dma_chan *chan)
 537 {
 538         struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan);
 539         struct virt_dma_desc *vdesc;
 540         struct stm32_dma_sg_req *sg_req;
 541         struct stm32_dma_chan_reg *reg;
 542         u32 status;
 543         int ret;
 544
 545         ret = stm32_dma_disable_chan(chan);
 546         if (ret < 0)
 547                 return;
 548
 549         if (!chan->desc) {
 550                 vdesc = vchan_next_desc(&chan->vchan);
 551                 if (!vdesc)
 552                         return;
 553
 554                 chan->desc = to_stm32_dma_desc(vdesc);
 555                 chan->next_sg = 0;
 556         }
 557
 558         if (chan->next_sg == chan->desc->num_sgs)
 559                 chan->next_sg = 0;
 560
 561         sg_req = &chan->desc->sg_req[chan->next_sg];
 562         reg = &sg_req->chan_reg;
 563
 564         stm32_dma_write(dmadev, STM32_DMA_SCR(chan->id), reg->dma_scr);
 565         stm32_dma_write(dmadev, STM32_DMA_SPAR(chan->id), reg->dma_spar);
 566         stm32_dma_write(dmadev, STM32_DMA_SM0AR(chan->id), reg->dma_sm0ar);
 567         stm32_dma_write(dmadev, STM32_DMA_SFCR(chan->id), reg->dma_sfcr);
 568         stm32_dma_write(dmadev, STM32_DMA_SM1AR(chan->id), reg->dma_sm1ar);
 569         stm32_dma_write(dmadev, STM32_DMA_SNDTR(chan->id), reg->dma_sndtr);
 570
 571         chan->next_sg++;
 572
 573         /* Clear interrupt status if it is there */
 574         status = stm32_dma_irq_status(chan);
 575         if (status)
 576                 stm32_dma_irq_clear(chan, status);
 577
 578         if (chan->desc->cyclic)
 579                 stm32_dma_configure_next_sg(chan);
 580
 581         stm32_dma_dump_reg(chan);
 582
 583         /* Start DMA */
 584         reg->dma_scr |= STM32_DMA_SCR_EN;
 585         stm32_dma_write(dmadev, STM32_DMA_SCR(chan->id), reg->dma_scr);
 586
 587         chan->busy = true;
 588
 589         dev_dbg(chan2dev(chan), "vchan %pK: started\n", &chan->vchan);
 590 }
 591
 592 static void stm32_dma_configure_next_sg(struct stm32_dma_chan *chan)
 593 {
 594         struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan);
 595         struct stm32_dma_sg_req *sg_req;
 596         u32 dma_scr, dma_sm0ar, dma_sm1ar, id;
 597
 598         id = chan->id;
 599         dma_scr = stm32_dma_read(dmadev, STM32_DMA_SCR(id));
 600
 601         if (dma_scr & STM32_DMA_SCR_DBM) {
 602                 if (chan->next_sg == chan->desc->num_sgs)
 603                         chan->next_sg = 0;
 604
 605                 sg_req = &chan->desc->sg_req[chan->next_sg];
 606
 607                 if (dma_scr & STM32_DMA_SCR_CT) {
 608                         dma_sm0ar = sg_req->chan_reg.dma_sm0ar;
 609                         stm32_dma_write(dmadev, STM32_DMA_SM0AR(id), dma_sm0ar);
 610                         dev_dbg(chan2dev(chan), "CT=1 <=> SM0AR: 0x%08x\n",
 611                                 stm32_dma_read(dmadev, STM32_DMA_SM0AR(id)));
 612                 } else {
 613                         dma_sm1ar = sg_req->chan_reg.dma_sm1ar;
 614                         stm32_dma_write(dmadev, STM32_DMA_SM1AR(id), dma_sm1ar);
 615                         dev_dbg(chan2dev(chan), "CT=0 <=> SM1AR: 0x%08x\n",
 616                                 stm32_dma_read(dmadev, STM32_DMA_SM1AR(id)));
 617                 }
 618         }
 619 }
 620
 621 static void stm32_dma_handle_chan_done(struct stm32_dma_chan *chan)
 622 {
 623         if (chan->desc) {
 624                 if (chan->desc->cyclic) {
 625                         vchan_cyclic_callback(&chan->desc->vdesc);
 626                         chan->next_sg++;
 627                         stm32_dma_configure_next_sg(chan);
 628                 } else {
 629                         chan->busy = false;
 630                         if (chan->next_sg == chan->desc->num_sgs) {
 631                                 list_del(&chan->desc->vdesc.node);
 632                                 vchan_cookie_complete(&chan->desc->vdesc);
 633                                 chan->desc = NULL;
 634                         }
 635                         stm32_dma_start_transfer(chan);
 636                 }
 637         }
 638 }
 639
 640 static irqreturn_t stm32_dma_chan_irq(int irq, void *devid)
 641 {
 642         struct stm32_dma_chan *chan = devid;
 643         struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan);
 644         u32 status, scr;
 645
 646         spin_lock(&chan->vchan.lock);
 647
 648         status = stm32_dma_irq_status(chan);
 649         scr = stm32_dma_read(dmadev, STM32_DMA_SCR(chan->id));
 650
 651         if (status & STM32_DMA_TCI) {
 652                 stm32_dma_irq_clear(chan, STM32_DMA_TCI);
 653                 if (scr & STM32_DMA_SCR_TCIE)
 654                         stm32_dma_handle_chan_done(chan);
 655                 status &= ~STM32_DMA_TCI;
 656         }
 657         if (status & STM32_DMA_HTI) {
 658                 stm32_dma_irq_clear(chan, STM32_DMA_HTI);
 659                 status &= ~STM32_DMA_HTI;
 660         }
 661         if (status & STM32_DMA_FEI) {
 662                 stm32_dma_irq_clear(chan, STM32_DMA_FEI);
 663                 status &= ~STM32_DMA_FEI;
 664                 if (!(scr & STM32_DMA_SCR_EN))
 665                         dev_err(chan2dev(chan), "FIFO Error\n");
 666                 else
 667                         dev_dbg(chan2dev(chan), "FIFO over/underrun\n");
 668         }
 669         if (status) {
 670                 stm32_dma_irq_clear(chan, status);
 671                 dev_err(chan2dev(chan), "DMA error: status=0x%08x\n", status);
 672                 if (!(scr & STM32_DMA_SCR_EN))
 673                         dev_err(chan2dev(chan), "chan disabled by HW\n");
 674         }
 675
 676         spin_unlock(&chan->vchan.lock);
 677
 678         return IRQ_HANDLED;
 679 }
 680
 681 static void stm32_dma_issue_pending(struct dma_chan *c)
 682 {
 683         struct stm32_dma_chan *chan = to_stm32_dma_chan(c);
 684         unsigned long flags;
 685
 686         spin_lock_irqsave(&chan->vchan.lock, flags);
 687         if (vchan_issue_pending(&chan->vchan) && !chan->desc && !chan->busy) {
 688                 dev_dbg(chan2dev(chan), "vchan %pK: issued\n", &chan->vchan);
 689                 stm32_dma_start_transfer(chan);
 690
 691         }
 692         spin_unlock_irqrestore(&chan->vchan.lock, flags);
 693 }
 694
 695 static int stm32_dma_set_xfer_param(struct stm32_dma_chan *chan,
 696                                     enum dma_transfer_direction direction,
 697                                     enum dma_slave_buswidth *buswidth,
 698                                     u32 buf_len)
 699 {
 700         enum dma_slave_buswidth src_addr_width, dst_addr_width;
 701         int src_bus_width, dst_bus_width;
 702         int src_burst_size, dst_burst_size;
 703         u32 src_maxburst, dst_maxburst, src_best_burst, dst_best_burst;
 704         u32 dma_scr, threshold;
 705
 706         src_addr_width = chan->dma_sconfig.src_addr_width;
 707         dst_addr_width = chan->dma_sconfig.dst_addr_width;
 708         src_maxburst = chan->dma_sconfig.src_maxburst;
 709         dst_maxburst = chan->dma_sconfig.dst_maxburst;
 710         threshold = chan->threshold;
 711
 712         switch (direction) {
 713         case DMA_MEM_TO_DEV:
 714                 /* Set device data size */
 715                 dst_bus_width = stm32_dma_get_width(chan, dst_addr_width);
 716                 if (dst_bus_width < 0)
 717                         return dst_bus_width;
 718
 719                 /* Set device burst size */
 720                 dst_best_burst = stm32_dma_get_best_burst(buf_len,
 721                                                           dst_maxburst,
 722                                                           threshold,
 723                                                           dst_addr_width);
 724
 725                 dst_burst_size = stm32_dma_get_burst(chan, dst_best_burst);
 726                 if (dst_burst_size < 0)
 727                         return dst_burst_size;
 728
 729                 /* Set memory data size */
 730                 src_addr_width = stm32_dma_get_max_width(buf_len, threshold);
 731                 chan->mem_width = src_addr_width;
 732                 src_bus_width = stm32_dma_get_width(chan, src_addr_width);
 733                 if (src_bus_width < 0)
 734                         return src_bus_width;
 735
 736                 /* Set memory burst size */
 737                 src_maxburst = STM32_DMA_MAX_BURST;
 738                 src_best_burst = stm32_dma_get_best_burst(buf_len,
 739                                                           src_maxburst,
 740                                                           threshold,
 741                                                           src_addr_width);
 742                 src_burst_size = stm32_dma_get_burst(chan, src_best_burst);
 743                 if (src_burst_size < 0)
 744                         return src_burst_size;
 745
 746                 dma_scr = STM32_DMA_SCR_DIR(STM32_DMA_MEM_TO_DEV) |
 747                         STM32_DMA_SCR_PSIZE(dst_bus_width) |
 748                         STM32_DMA_SCR_MSIZE(src_bus_width) |
 749                         STM32_DMA_SCR_PBURST(dst_burst_size) |
 750                         STM32_DMA_SCR_MBURST(src_burst_size);
 751
 752                 /* Set FIFO threshold */
 753                 chan->chan_reg.dma_sfcr &= ~STM32_DMA_SFCR_FTH_MASK;
 754                 chan->chan_reg.dma_sfcr |= STM32_DMA_SFCR_FTH(threshold);
 755
 756                 /* Set peripheral address */
 757                 chan->chan_reg.dma_spar = chan->dma_sconfig.dst_addr;
 758                 *buswidth = dst_addr_width;
 759                 break;
 760
 761         case DMA_DEV_TO_MEM:
 762                 /* Set device data size */
 763                 src_bus_width = stm32_dma_get_width(chan, src_addr_width);
 764                 if (src_bus_width < 0)
 765                         return src_bus_width;
 766
 767                 /* Set device burst size */
 768                 src_best_burst = stm32_dma_get_best_burst(buf_len,
 769                                                           src_maxburst,
 770                                                           threshold,
 771                                                           src_addr_width);
 772                 chan->mem_burst = src_best_burst;
 773                 src_burst_size = stm32_dma_get_burst(chan, src_best_burst);
 774                 if (src_burst_size < 0)
 775                         return src_burst_size;
 776
 777                 /* Set memory data size */
 778                 dst_addr_width = stm32_dma_get_max_width(buf_len, threshold);
 779                 chan->mem_width = dst_addr_width;
 780                 dst_bus_width = stm32_dma_get_width(chan, dst_addr_width);
 781                 if (dst_bus_width < 0)
 782                         return dst_bus_width;
 783
 784                 /* Set memory burst size */
 785                 dst_maxburst = STM32_DMA_MAX_BURST;
 786                 dst_best_burst = stm32_dma_get_best_burst(buf_len,
 787                                                           dst_maxburst,
 788                                                           threshold,
 789                                                           dst_addr_width);
 790                 chan->mem_burst = dst_best_burst;
 791                 dst_burst_size = stm32_dma_get_burst(chan, dst_best_burst);
 792                 if (dst_burst_size < 0)
 793                         return dst_burst_size;
 794
 795                 dma_scr = STM32_DMA_SCR_DIR(STM32_DMA_DEV_TO_MEM) |
 796                         STM32_DMA_SCR_PSIZE(src_bus_width) |
 797                         STM32_DMA_SCR_MSIZE(dst_bus_width) |
 798                         STM32_DMA_SCR_PBURST(src_burst_size) |
 799                         STM32_DMA_SCR_MBURST(dst_burst_size);
 800
 801                 /* Set FIFO threshold */
 802                 chan->chan_reg.dma_sfcr &= ~STM32_DMA_SFCR_FTH_MASK;
 803                 chan->chan_reg.dma_sfcr |= STM32_DMA_SFCR_FTH(threshold);
 804
 805                 /* Set peripheral address */
 806                 chan->chan_reg.dma_spar = chan->dma_sconfig.src_addr;
 807                 *buswidth = chan->dma_sconfig.src_addr_width;
 808                 break;
 809
 810         default:
 811                 dev_err(chan2dev(chan), "Dma direction is not supported\n");
 812                 return -EINVAL;
 813         }
 814
 815         stm32_dma_set_fifo_config(chan, src_best_burst, dst_best_burst);
 816
 817         /* Set DMA control register */
 818         chan->chan_reg.dma_scr &= ~(STM32_DMA_SCR_DIR_MASK |
 819                         STM32_DMA_SCR_PSIZE_MASK | STM32_DMA_SCR_MSIZE_MASK |
 820                         STM32_DMA_SCR_PBURST_MASK | STM32_DMA_SCR_MBURST_MASK);
 821         chan->chan_reg.dma_scr |= dma_scr;
 822
 823         return 0;
 824 }
 825
 826 static void stm32_dma_clear_reg(struct stm32_dma_chan_reg *regs)
 827 {
 828         memset(regs, 0, sizeof(struct stm32_dma_chan_reg));
 829 }
 830
 831 static struct dma_async_tx_descriptor *stm32_dma_prep_slave_sg(
 832         struct dma_chan *c, struct scatterlist *sgl,
 833         u32 sg_len, enum dma_transfer_direction direction,
 834         unsigned long flags, void *context)
 835 {
 836         struct stm32_dma_chan *chan = to_stm32_dma_chan(c);
 837         struct stm32_dma_desc *desc;
 838         struct scatterlist *sg;
 839         enum dma_slave_buswidth buswidth;
 840         u32 nb_data_items;
 841         int i, ret;
 842
 843         if (!chan->config_init) {
 844                 dev_err(chan2dev(chan), "dma channel is not configured\n");
 845                 return NULL;
 846         }
 847
 848         if (sg_len < 1) {
 849                 dev_err(chan2dev(chan), "Invalid segment length %d\n", sg_len);
 850                 return NULL;
 851         }
 852
 853         desc = stm32_dma_alloc_desc(sg_len);
 854         if (!desc)
 855                 return NULL;
 856
 857         /* Set peripheral flow controller */
 858         if (chan->dma_sconfig.device_fc)
 859                 chan->chan_reg.dma_scr |= STM32_DMA_SCR_PFCTRL;
 860         else
 861                 chan->chan_reg.dma_scr &= ~STM32_DMA_SCR_PFCTRL;
 862
 863         for_each_sg(sgl, sg, sg_len, i) {
 864                 ret = stm32_dma_set_xfer_param(chan, direction, &buswidth,
 865                                                sg_dma_len(sg));
 866                 if (ret < 0)
 867                         goto err;
 868
 869                 desc->sg_req[i].len = sg_dma_len(sg);
 870
 871                 nb_data_items = desc->sg_req[i].len / buswidth;
 872                 if (nb_data_items > STM32_DMA_ALIGNED_MAX_DATA_ITEMS) {
 873                         dev_err(chan2dev(chan), "nb items not supported\n");
 874                         goto err;
 875                 }
 876
 877                 stm32_dma_clear_reg(&desc->sg_req[i].chan_reg);
 878                 desc->sg_req[i].chan_reg.dma_scr = chan->chan_reg.dma_scr;
 879                 desc->sg_req[i].chan_reg.dma_sfcr = chan->chan_reg.dma_sfcr;
 880                 desc->sg_req[i].chan_reg.dma_spar = chan->chan_reg.dma_spar;
 881                 desc->sg_req[i].chan_reg.dma_sm0ar = sg_dma_address(sg);
 882                 desc->sg_req[i].chan_reg.dma_sm1ar = sg_dma_address(sg);
 883                 desc->sg_req[i].chan_reg.dma_sndtr = nb_data_items;
 884         }
 885
 886         desc->num_sgs = sg_len;
 887         desc->cyclic = false;
 888
 889         return vchan_tx_prep(&chan->vchan, &desc->vdesc, flags);
 890
 891 err:
 892         kfree(desc);
 893         return NULL;
 894 }
 895
 896 static struct dma_async_tx_descriptor *stm32_dma_prep_dma_cyclic(
 897         struct dma_chan *c, dma_addr_t buf_addr, size_t buf_len,
 898         size_t period_len, enum dma_transfer_direction direction,
 899         unsigned long flags)
 900 {
 901         struct stm32_dma_chan *chan = to_stm32_dma_chan(c);
 902         struct stm32_dma_desc *desc;
 903         enum dma_slave_buswidth buswidth;
 904         u32 num_periods, nb_data_items;
 905         int i, ret;
 906
 907         if (!buf_len || !period_len) {
 908                 dev_err(chan2dev(chan), "Invalid buffer/period len\n");
 909                 return NULL;
 910         }
 911
 912         if (!chan->config_init) {
 913                 dev_err(chan2dev(chan), "dma channel is not configured\n");
 914                 return NULL;
 915         }
 916
 917         if (buf_len % period_len) {
 918                 dev_err(chan2dev(chan), "buf_len not multiple of period_len\n");
 919                 return NULL;
 920         }
 921
 922         /*
 923          * We allow to take more number of requests till DMA is
 924          * not started. The driver will loop over all requests.
 925          * Once DMA is started then new requests can be queued only after
 926          * terminating the DMA.
 927          */
 928         if (chan->busy) {
 929                 dev_err(chan2dev(chan), "Request not allowed when dma busy\n");
 930                 return NULL;
 931         }
 932
 933         ret = stm32_dma_set_xfer_param(chan, direction, &buswidth, period_len);
 934         if (ret < 0)
 935                 return NULL;
 936
 937         nb_data_items = period_len / buswidth;
 938         if (nb_data_items > STM32_DMA_ALIGNED_MAX_DATA_ITEMS) {
 939                 dev_err(chan2dev(chan), "number of items not supported\n");
 940                 return NULL;
 941         }
 942
 943         /*  Enable Circular mode or double buffer mode */
 944         if (buf_len == period_len)
 945                 chan->chan_reg.dma_scr |= STM32_DMA_SCR_CIRC;
 946         else
 947                 chan->chan_reg.dma_scr |= STM32_DMA_SCR_DBM;
 948
 949         /* Clear periph ctrl if client set it */
 950         chan->chan_reg.dma_scr &= ~STM32_DMA_SCR_PFCTRL;
 951
 952         num_periods = buf_len / period_len;
 953
 954         desc = stm32_dma_alloc_desc(num_periods);
 955         if (!desc)
 956                 return NULL;
 957
 958         for (i = 0; i < num_periods; i++) {
 959                 desc->sg_req[i].len = period_len;
 960
 961                 stm32_dma_clear_reg(&desc->sg_req[i].chan_reg);
 962                 desc->sg_req[i].chan_reg.dma_scr = chan->chan_reg.dma_scr;
 963                 desc->sg_req[i].chan_reg.dma_sfcr = chan->chan_reg.dma_sfcr;
 964                 desc->sg_req[i].chan_reg.dma_spar = chan->chan_reg.dma_spar;
 965                 desc->sg_req[i].chan_reg.dma_sm0ar = buf_addr;
 966                 desc->sg_req[i].chan_reg.dma_sm1ar = buf_addr;
 967                 desc->sg_req[i].chan_reg.dma_sndtr = nb_data_items;
 968                 buf_addr += period_len;
 969         }
 970
 971         desc->num_sgs = num_periods;
 972         desc->cyclic = true;
 973
 974         return vchan_tx_prep(&chan->vchan, &desc->vdesc, flags);
 975 }
 976
 977 static struct dma_async_tx_descriptor *stm32_dma_prep_dma_memcpy(
 978         struct dma_chan *c, dma_addr_t dest,
 979         dma_addr_t src, size_t len, unsigned long flags)
 980 {
 981         struct stm32_dma_chan *chan = to_stm32_dma_chan(c);
 982         enum dma_slave_buswidth max_width;
 983         struct stm32_dma_desc *desc;
 984         size_t xfer_count, offset;
 985         u32 num_sgs, best_burst, dma_burst, threshold;
 986         int i;
 987
 988         num_sgs = DIV_ROUND_UP(len, STM32_DMA_ALIGNED_MAX_DATA_ITEMS);
 989         desc = stm32_dma_alloc_desc(num_sgs);
 990         if (!desc)
 991                 return NULL;
 992
 993         threshold = chan->threshold;
 994
 995         for (offset = 0, i = 0; offset < len; offset += xfer_count, i++) {
 996                 xfer_count = min_t(size_t, len - offset,
 997                                    STM32_DMA_ALIGNED_MAX_DATA_ITEMS);
 998
 999                 /* Compute best burst size */
1000                 max_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1001                 best_burst = stm32_dma_get_best_burst(len, STM32_DMA_MAX_BURST,
1002                                                       threshold, max_width);
1003                 dma_burst = stm32_dma_get_burst(chan, best_burst);
1004
1005                 stm32_dma_clear_reg(&desc->sg_req[i].chan_reg);
1006                 desc->sg_req[i].chan_reg.dma_scr =
1007                         STM32_DMA_SCR_DIR(STM32_DMA_MEM_TO_MEM) |
1008                         STM32_DMA_SCR_PBURST(dma_burst) |
1009                         STM32_DMA_SCR_MBURST(dma_burst) |
1010                         STM32_DMA_SCR_MINC |
1011                         STM32_DMA_SCR_PINC |
1012                         STM32_DMA_SCR_TCIE |
1013                         STM32_DMA_SCR_TEIE;
1014                 desc->sg_req[i].chan_reg.dma_sfcr |= STM32_DMA_SFCR_MASK;
1015                 desc->sg_req[i].chan_reg.dma_sfcr |=
1016                         STM32_DMA_SFCR_FTH(threshold);
1017                 desc->sg_req[i].chan_reg.dma_spar = src + offset;
1018                 desc->sg_req[i].chan_reg.dma_sm0ar = dest + offset;
1019                 desc->sg_req[i].chan_reg.dma_sndtr = xfer_count;
1020                 desc->sg_req[i].len = xfer_count;
1021         }
1022
1023         desc->num_sgs = num_sgs;
1024         desc->cyclic = false;
1025
1026         return vchan_tx_prep(&chan->vchan, &desc->vdesc, flags);
1027 }
1028
1029 static u32 stm32_dma_get_remaining_bytes(struct stm32_dma_chan *chan)
1030 {
1031         u32 dma_scr, width, ndtr;
1032         struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan);
1033
1034         dma_scr = stm32_dma_read(dmadev, STM32_DMA_SCR(chan->id));
1035         width = STM32_DMA_SCR_PSIZE_GET(dma_scr);
1036         ndtr = stm32_dma_read(dmadev, STM32_DMA_SNDTR(chan->id));
1037
1038         return ndtr << width;
1039 }
1040
1041 static size_t stm32_dma_desc_residue(struct stm32_dma_chan *chan,
1042                                      struct stm32_dma_desc *desc,
1043                                      u32 next_sg)
1044 {
1045         u32 modulo, burst_size;
1046         u32 residue = 0;
1047         int i;
1048
1049         /*
1050          * In cyclic mode, for the last period, residue = remaining bytes from
1051          * NDTR
1052          */
1053         if (chan->desc->cyclic && next_sg == 0) {
1054                 residue = stm32_dma_get_remaining_bytes(chan);
1055                 goto end;
1056         }
1057
1058         /*
1059          * For all other periods in cyclic mode, and in sg mode,
1060          * residue = remaining bytes from NDTR + remaining periods/sg to be
1061          * transferred
1062          */
1063         for (i = next_sg; i < desc->num_sgs; i++)
1064                 residue += desc->sg_req[i].len;
1065         residue += stm32_dma_get_remaining_bytes(chan);
1066
1067 end:
1068         if (!chan->mem_burst)
1069                 return residue;
1070
1071         burst_size = chan->mem_burst * chan->mem_width;
1072         modulo = residue % burst_size;
1073         if (modulo)
1074                 residue = residue - modulo + burst_size;
1075
1076         return residue;
1077 }
1078
1079 static enum dma_status stm32_dma_tx_status(struct dma_chan *c,
1080                                            dma_cookie_t cookie,
1081                                            struct dma_tx_state *state)
1082 {
1083         struct stm32_dma_chan *chan = to_stm32_dma_chan(c);
1084         struct virt_dma_desc *vdesc;
1085         enum dma_status status;
1086         unsigned long flags;
1087         u32 residue = 0;
1088
1089         status = dma_cookie_status(c, cookie, state);
1090         if (status == DMA_COMPLETE || !state)
1091                 return status;
1092
1093         spin_lock_irqsave(&chan->vchan.lock, flags);
1094         vdesc = vchan_find_desc(&chan->vchan, cookie);
1095         if (chan->desc && cookie == chan->desc->vdesc.tx.cookie)
1096                 residue = stm32_dma_desc_residue(chan, chan->desc,
1097                                                  chan->next_sg);
1098         else if (vdesc)
1099                 residue = stm32_dma_desc_residue(chan,
1100                                                  to_stm32_dma_desc(vdesc), 0);
1101         dma_set_residue(state, residue);
1102
1103         spin_unlock_irqrestore(&chan->vchan.lock, flags);
1104
1105         return status;
1106 }
1107
1108 static int stm32_dma_alloc_chan_resources(struct dma_chan *c)
1109 {
1110         struct stm32_dma_chan *chan = to_stm32_dma_chan(c);
1111         struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan);
1112         int ret;
1113
1114         chan->config_init = false;
1115         ret = clk_prepare_enable(dmadev->clk);
1116         if (ret < 0) {
1117                 dev_err(chan2dev(chan), "clk_prepare_enable failed: %d\n", ret);
1118                 return ret;
1119         }
1120
1121         ret = stm32_dma_disable_chan(chan);
1122         if (ret < 0)
1123                 clk_disable_unprepare(dmadev->clk);
1124
1125         return ret;
1126 }
1127
1128 static void stm32_dma_free_chan_resources(struct dma_chan *c)
1129 {
1130         struct stm32_dma_chan *chan = to_stm32_dma_chan(c);
1131         struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan);
1132         unsigned long flags;
1133
1134         dev_dbg(chan2dev(chan), "Freeing channel %d\n", chan->id);
1135
1136         if (chan->busy) {
1137                 spin_lock_irqsave(&chan->vchan.lock, flags);
1138                 stm32_dma_stop(chan);
1139                 chan->desc = NULL;
1140                 spin_unlock_irqrestore(&chan->vchan.lock, flags);
1141         }
1142
1143         clk_disable_unprepare(dmadev->clk);
1144
1145         vchan_free_chan_resources(to_virt_chan(c));
1146 }
1147
1148 static void stm32_dma_desc_free(struct virt_dma_desc *vdesc)
1149 {
1150         kfree(container_of(vdesc, struct stm32_dma_desc, vdesc));
1151 }
1152
1153 static void stm32_dma_set_config(struct stm32_dma_chan *chan,
1154                                  struct stm32_dma_cfg *cfg)
1155 {
1156         stm32_dma_clear_reg(&chan->chan_reg);
1157
1158         chan->chan_reg.dma_scr = cfg->stream_config & STM32_DMA_SCR_CFG_MASK;
1159         chan->chan_reg.dma_scr |= STM32_DMA_SCR_REQ(cfg->request_line);
1160
1161         /* Enable Interrupts  */
1162         chan->chan_reg.dma_scr |= STM32_DMA_SCR_TEIE | STM32_DMA_SCR_TCIE;
1163
1164         chan->threshold = STM32_DMA_THRESHOLD_FTR_GET(cfg->features);
1165 }
1166
1167 static struct dma_chan *stm32_dma_of_xlate(struct of_phandle_args *dma_spec,
1168                                            struct of_dma *ofdma)
1169 {
1170         struct stm32_dma_device *dmadev = ofdma->of_dma_data;
1171         struct device *dev = dmadev->ddev.dev;
1172         struct stm32_dma_cfg cfg;
1173         struct stm32_dma_chan *chan;
1174         struct dma_chan *c;
1175
1176         if (dma_spec->args_count < 4) {
1177                 dev_err(dev, "Bad number of cells\n");
1178                 return NULL;
1179         }
1180
1181         cfg.channel_id = dma_spec->args[0];
1182         cfg.request_line = dma_spec->args[1];
1183         cfg.stream_config = dma_spec->args[2];
1184         cfg.features = dma_spec->args[3];
1185
1186         if (cfg.channel_id >= STM32_DMA_MAX_CHANNELS ||
1187             cfg.request_line >= STM32_DMA_MAX_REQUEST_ID) {
1188                 dev_err(dev, "Bad channel and/or request id\n");
1189                 return NULL;
1190         }
1191
1192         chan = &dmadev->chan[cfg.channel_id];
1193
1194         c = dma_get_slave_channel(&chan->vchan.chan);
1195         if (!c) {
1196                 dev_err(dev, "No more channels available\n");
1197                 return NULL;
1198         }
1199
1200         stm32_dma_set_config(chan, &cfg);
1201
1202         return c;
1203 }
1204
1205 static const struct of_device_id stm32_dma_of_match[] = {
1206         { .compatible = "st,stm32-dma", },
1207         { /* sentinel */ },
1208 };
1209 MODULE_DEVICE_TABLE(of, stm32_dma_of_match);
1210
1211 static int stm32_dma_probe(struct platform_device *pdev)
1212 {
1213         struct stm32_dma_chan *chan;
1214         struct stm32_dma_device *dmadev;
1215         struct dma_device *dd;
1216         const struct of_device_id *match;
1217         struct resource *res;
1218         int i, ret;
1219
1220         match = of_match_device(stm32_dma_of_match, &pdev->dev);
1221         if (!match) {
1222                 dev_err(&pdev->dev, "Error: No device match found\n");
1223                 return -ENODEV;
1224         }
1225
1226         dmadev = devm_kzalloc(&pdev->dev, sizeof(*dmadev), GFP_KERNEL);
1227         if (!dmadev)
1228                 return -ENOMEM;
1229
1230         dd = &dmadev->ddev;
1231
1232         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1233         dmadev->base = devm_ioremap_resource(&pdev->dev, res);
1234         if (IS_ERR(dmadev->base))
1235                 return PTR_ERR(dmadev->base);
1236
1237         dmadev->clk = devm_clk_get(&pdev->dev, NULL);
1238         if (IS_ERR(dmadev->clk)) {
1239                 dev_err(&pdev->dev, "Error: Missing controller clock\n");
1240                 return PTR_ERR(dmadev->clk);
1241         }
1242
1243         dmadev->mem2mem = of_property_read_bool(pdev->dev.of_node,
1244                                                 "st,mem2mem");
1245
1246         dmadev->rst = devm_reset_control_get(&pdev->dev, NULL);
1247         if (!IS_ERR(dmadev->rst)) {
1248                 reset_control_assert(dmadev->rst);
1249                 udelay(2);
1250                 reset_control_deassert(dmadev->rst);
1251         }
1252
1253         dma_cap_set(DMA_SLAVE, dd->cap_mask);
1254         dma_cap_set(DMA_PRIVATE, dd->cap_mask);
1255         dma_cap_set(DMA_CYCLIC, dd->cap_mask);
1256         dd->device_alloc_chan_resources = stm32_dma_alloc_chan_resources;
1257         dd->device_free_chan_resources = stm32_dma_free_chan_resources;
1258         dd->device_tx_status = stm32_dma_tx_status;
1259         dd->device_issue_pending = stm32_dma_issue_pending;
1260         dd->device_prep_slave_sg = stm32_dma_prep_slave_sg;
1261         dd->device_prep_dma_cyclic = stm32_dma_prep_dma_cyclic;
1262         dd->device_config = stm32_dma_slave_config;
1263         dd->device_terminate_all = stm32_dma_terminate_all;
1264         dd->device_synchronize = stm32_dma_synchronize;
1265         dd->src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) |
1266                 BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) |
1267                 BIT(DMA_SLAVE_BUSWIDTH_4_BYTES);
1268         dd->dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) |
1269                 BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) |
1270                 BIT(DMA_SLAVE_BUSWIDTH_4_BYTES);
1271         dd->directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
1272         dd->residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;
1273         dd->max_burst = STM32_DMA_MAX_BURST;
1274         dd->dev = &pdev->dev;
1275         INIT_LIST_HEAD(&dd->channels);
1276
1277         if (dmadev->mem2mem) {
1278                 dma_cap_set(DMA_MEMCPY, dd->cap_mask);
1279                 dd->device_prep_dma_memcpy = stm32_dma_prep_dma_memcpy;
1280                 dd->directions |= BIT(DMA_MEM_TO_MEM);
1281         }
1282
1283         for (i = 0; i < STM32_DMA_MAX_CHANNELS; i++) {
1284                 chan = &dmadev->chan[i];
1285                 chan->id = i;
1286                 chan->vchan.desc_free = stm32_dma_desc_free;
1287                 vchan_init(&chan->vchan, dd);
1288         }
1289
1290         ret = dma_async_device_register(dd);
1291         if (ret)
1292                 return ret;
1293
1294         for (i = 0; i < STM32_DMA_MAX_CHANNELS; i++) {
1295                 chan = &dmadev->chan[i];
1296                 res = platform_get_resource(pdev, IORESOURCE_IRQ, i);
1297                 if (!res) {
1298                         ret = -EINVAL;
1299                         dev_err(&pdev->dev, "No irq resource for chan %d\n", i);
1300                         goto err_unregister;
1301                 }
1302                 chan->irq = res->start;
1303                 ret = devm_request_irq(&pdev->dev, chan->irq,
1304                                        stm32_dma_chan_irq, 0,
1305                                        dev_name(chan2dev(chan)), chan);
1306                 if (ret) {
1307                         dev_err(&pdev->dev,
1308                                 "request_irq failed with err %d channel %d\n",
1309                                 ret, i);
1310                         goto err_unregister;
1311                 }
1312         }
1313
1314         ret = of_dma_controller_register(pdev->dev.of_node,
1315                                          stm32_dma_of_xlate, dmadev);
1316         if (ret < 0) {
1317                 dev_err(&pdev->dev,
1318                         "STM32 DMA DMA OF registration failed %d\n", ret);
1319                 goto err_unregister;
1320         }
1321
1322         platform_set_drvdata(pdev, dmadev);
1323
1324         dev_info(&pdev->dev, "STM32 DMA driver registered\n");
1325
1326         return 0;
1327
1328 err_unregister:
1329         dma_async_device_unregister(dd);
1330
1331         return ret;
1332 }
1333
1334 static struct platform_driver stm32_dma_driver = {
1335         .driver = {
1336                 .name = "stm32-dma",
1337                 .of_match_table = stm32_dma_of_match,
1338         },
1339 };
1340
1341 static int __init stm32_dma_init(void)
1342 {
1343         return platform_driver_probe(&stm32_dma_driver, stm32_dma_probe);
1344 }
1345 subsys_initcall(stm32_dma_init);