drivers/dma/sh/shdma.c

   1 /*
   2  * Renesas SuperH DMA Engine support
   3  *
   4  * base is drivers/dma/flsdma.c
   5  *
   6  * Copyright (C) 2011-2012 Guennadi Liakhovetski <g.liakhovetski@gmx.de>
   7  * Copyright (C) 2009 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
   8  * Copyright (C) 2009 Renesas Solutions, Inc. All rights reserved.
   9  * Copyright (C) 2007 Freescale Semiconductor, Inc. All rights reserved.
  10  *
  11  * This is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License as published by
  13  * the Free Software Foundation; either version 2 of the License, or
  14  * (at your option) any later version.
  15  *
  16  * - DMA of SuperH does not have Hardware DMA chain mode.
  17  * - MAX DMA size is 16MB.
  18  *
  19  */
  20
  21 #include <linux/init.h>
  22 #include <linux/module.h>
  23 #include <linux/slab.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/dmaengine.h>
  26 #include <linux/delay.h>
  27 #include <linux/platform_device.h>
  28 #include <linux/pm_runtime.h>
  29 #include <linux/sh_dma.h>
  30 #include <linux/notifier.h>
  31 #include <linux/kdebug.h>
  32 #include <linux/spinlock.h>
  33 #include <linux/rculist.h>
  34
  35 #include "../dmaengine.h"
  36 #include "shdma.h"
  37
  38 #define SH_DMAE_DRV_NAME "sh-dma-engine"
  39
  40 /* Default MEMCPY transfer size = 2^2 = 4 bytes */
  41 #define LOG2_DEFAULT_XFER_SIZE  2
  42 #define SH_DMA_SLAVE_NUMBER 256
  43 #define SH_DMA_TCR_MAX (16 * 1024 * 1024 - 1)
  44
  45 /*
  46  * Used for write-side mutual exclusion for the global device list,
  47  * read-side synchronization by way of RCU, and per-controller data.
  48  */
  49 static DEFINE_SPINLOCK(sh_dmae_lock);
  50 static LIST_HEAD(sh_dmae_devices);
  51
  52 static void chclr_write(struct sh_dmae_chan *sh_dc, u32 data)
  53 {
  54         struct sh_dmae_device *shdev = to_sh_dev(sh_dc);
  55
  56         __raw_writel(data, shdev->chan_reg +
  57                      shdev->pdata->channel[sh_dc->shdma_chan.id].chclr_offset);
  58 }
  59
  60 static void sh_dmae_writel(struct sh_dmae_chan *sh_dc, u32 data, u32 reg)
  61 {
  62         __raw_writel(data, sh_dc->base + reg / sizeof(u32));
  63 }
  64
  65 static u32 sh_dmae_readl(struct sh_dmae_chan *sh_dc, u32 reg)
  66 {
  67         return __raw_readl(sh_dc->base + reg / sizeof(u32));
  68 }
  69
  70 static u16 dmaor_read(struct sh_dmae_device *shdev)
  71 {
  72         u32 __iomem *addr = shdev->chan_reg + DMAOR / sizeof(u32);
  73
  74         if (shdev->pdata->dmaor_is_32bit)
  75                 return __raw_readl(addr);
  76         else
  77                 return __raw_readw(addr);
  78 }
  79
  80 static void dmaor_write(struct sh_dmae_device *shdev, u16 data)
  81 {
  82         u32 __iomem *addr = shdev->chan_reg + DMAOR / sizeof(u32);
  83
  84         if (shdev->pdata->dmaor_is_32bit)
  85                 __raw_writel(data, addr);
  86         else
  87                 __raw_writew(data, addr);
  88 }
  89
  90 static void chcr_write(struct sh_dmae_chan *sh_dc, u32 data)
  91 {
  92         struct sh_dmae_device *shdev = to_sh_dev(sh_dc);
  93
  94         __raw_writel(data, sh_dc->base + shdev->chcr_offset / sizeof(u32));
  95 }
  96
  97 static u32 chcr_read(struct sh_dmae_chan *sh_dc)
  98 {
  99         struct sh_dmae_device *shdev = to_sh_dev(sh_dc);
 100
 101         return __raw_readl(sh_dc->base + shdev->chcr_offset / sizeof(u32));
 102 }
 103
 104 /*
 105  * Reset DMA controller
 106  *
 107  * SH7780 has two DMAOR register
 108  */
 109 static void sh_dmae_ctl_stop(struct sh_dmae_device *shdev)
 110 {
 111         unsigned short dmaor;
 112         unsigned long flags;
 113
 114         spin_lock_irqsave(&sh_dmae_lock, flags);
 115
 116         dmaor = dmaor_read(shdev);
 117         dmaor_write(shdev, dmaor & ~(DMAOR_NMIF | DMAOR_AE | DMAOR_DME));
 118
 119         spin_unlock_irqrestore(&sh_dmae_lock, flags);
 120 }
 121
 122 static int sh_dmae_rst(struct sh_dmae_device *shdev)
 123 {
 124         unsigned short dmaor;
 125         unsigned long flags;
 126
 127         spin_lock_irqsave(&sh_dmae_lock, flags);
 128
 129         dmaor = dmaor_read(shdev) & ~(DMAOR_NMIF | DMAOR_AE | DMAOR_DME);
 130
 131         if (shdev->pdata->chclr_present) {
 132                 int i;
 133                 for (i = 0; i < shdev->pdata->channel_num; i++) {
 134                         struct sh_dmae_chan *sh_chan = shdev->chan[i];
 135                         if (sh_chan)
 136                                 chclr_write(sh_chan, 0);
 137                 }
 138         }
 139
 140         dmaor_write(shdev, dmaor | shdev->pdata->dmaor_init);
 141
 142         dmaor = dmaor_read(shdev);
 143
 144         spin_unlock_irqrestore(&sh_dmae_lock, flags);
 145
 146         if (dmaor & (DMAOR_AE | DMAOR_NMIF)) {
 147                 dev_warn(shdev->shdma_dev.dma_dev.dev, "Can't initialize DMAOR.\n");
 148                 return -EIO;
 149         }
 150         if (shdev->pdata->dmaor_init & ~dmaor)
 151                 dev_warn(shdev->shdma_dev.dma_dev.dev,
 152                          "DMAOR=0x%x hasn't latched the initial value 0x%x.\n",
 153                          dmaor, shdev->pdata->dmaor_init);
 154         return 0;
 155 }
 156
 157 static bool dmae_is_busy(struct sh_dmae_chan *sh_chan)
 158 {
 159         u32 chcr = chcr_read(sh_chan);
 160
 161         if ((chcr & (CHCR_DE | CHCR_TE)) == CHCR_DE)
 162                 return true; /* working */
 163
 164         return false; /* waiting */
 165 }
 166
 167 static unsigned int calc_xmit_shift(struct sh_dmae_chan *sh_chan, u32 chcr)
 168 {
 169         struct sh_dmae_device *shdev = to_sh_dev(sh_chan);
 170         struct sh_dmae_pdata *pdata = shdev->pdata;
 171         int cnt = ((chcr & pdata->ts_low_mask) >> pdata->ts_low_shift) |
 172                 ((chcr & pdata->ts_high_mask) >> pdata->ts_high_shift);
 173
 174         if (cnt >= pdata->ts_shift_num)
 175                 cnt = 0;
 176
 177         return pdata->ts_shift[cnt];
 178 }
 179
 180 static u32 log2size_to_chcr(struct sh_dmae_chan *sh_chan, int l2size)
 181 {
 182         struct sh_dmae_device *shdev = to_sh_dev(sh_chan);
 183         struct sh_dmae_pdata *pdata = shdev->pdata;
 184         int i;
 185
 186         for (i = 0; i < pdata->ts_shift_num; i++)
 187                 if (pdata->ts_shift[i] == l2size)
 188                         break;
 189
 190         if (i == pdata->ts_shift_num)
 191                 i = 0;
 192
 193         return ((i << pdata->ts_low_shift) & pdata->ts_low_mask) |
 194                 ((i << pdata->ts_high_shift) & pdata->ts_high_mask);
 195 }
 196
 197 static void dmae_set_reg(struct sh_dmae_chan *sh_chan, struct sh_dmae_regs *hw)
 198 {
 199         sh_dmae_writel(sh_chan, hw->sar, SAR);
 200         sh_dmae_writel(sh_chan, hw->dar, DAR);
 201         sh_dmae_writel(sh_chan, hw->tcr >> sh_chan->xmit_shift, TCR);
 202 }
 203
 204 static void dmae_start(struct sh_dmae_chan *sh_chan)
 205 {
 206         struct sh_dmae_device *shdev = to_sh_dev(sh_chan);
 207         u32 chcr = chcr_read(sh_chan);
 208
 209         if (shdev->pdata->needs_tend_set)
 210                 sh_dmae_writel(sh_chan, 0xFFFFFFFF, TEND);
 211
 212         chcr |= CHCR_DE | shdev->chcr_ie_bit;
 213         chcr_write(sh_chan, chcr & ~CHCR_TE);
 214 }
 215
 216 static void dmae_init(struct sh_dmae_chan *sh_chan)
 217 {
 218         /*
 219          * Default configuration for dual address memory-memory transfer.
 220          * 0x400 represents auto-request.
 221          */
 222         u32 chcr = DM_INC | SM_INC | 0x400 | log2size_to_chcr(sh_chan,
 223                                                    LOG2_DEFAULT_XFER_SIZE);
 224         sh_chan->xmit_shift = calc_xmit_shift(sh_chan, chcr);
 225         chcr_write(sh_chan, chcr);
 226 }
 227
 228 static int dmae_set_chcr(struct sh_dmae_chan *sh_chan, u32 val)
 229 {
 230         /* If DMA is active, cannot set CHCR. TODO: remove this superfluous check */
 231         if (dmae_is_busy(sh_chan))
 232                 return -EBUSY;
 233
 234         sh_chan->xmit_shift = calc_xmit_shift(sh_chan, val);
 235         chcr_write(sh_chan, val);
 236
 237         return 0;
 238 }
 239
 240 static int dmae_set_dmars(struct sh_dmae_chan *sh_chan, u16 val)
 241 {
 242         struct sh_dmae_device *shdev = to_sh_dev(sh_chan);
 243         struct sh_dmae_pdata *pdata = shdev->pdata;
 244         const struct sh_dmae_channel *chan_pdata = &pdata->channel[sh_chan->shdma_chan.id];
 245         u16 __iomem *addr = shdev->dmars;
 246         unsigned int shift = chan_pdata->dmars_bit;
 247
 248         if (dmae_is_busy(sh_chan))
 249                 return -EBUSY;
 250
 251         if (pdata->no_dmars)
 252                 return 0;
 253
 254         /* in the case of a missing DMARS resource use first memory window */
 255         if (!addr)
 256                 addr = (u16 __iomem *)shdev->chan_reg;
 257         addr += chan_pdata->dmars / sizeof(u16);
 258
 259         __raw_writew((__raw_readw(addr) & (0xff00 >> shift)) | (val << shift),
 260                      addr);
 261
 262         return 0;
 263 }
 264
 265 static void sh_dmae_start_xfer(struct shdma_chan *schan,
 266                                struct shdma_desc *sdesc)
 267 {
 268         struct sh_dmae_chan *sh_chan = container_of(schan, struct sh_dmae_chan,
 269                                                     shdma_chan);
 270         struct sh_dmae_desc *sh_desc = container_of(sdesc,
 271                                         struct sh_dmae_desc, shdma_desc);
 272         dev_dbg(sh_chan->shdma_chan.dev, "Queue #%d to %d: %u@%x -> %x\n",
 273                 sdesc->async_tx.cookie, sh_chan->shdma_chan.id,
 274                 sh_desc->hw.tcr, sh_desc->hw.sar, sh_desc->hw.dar);
 275         /* Get the ld start address from ld_queue */
 276         dmae_set_reg(sh_chan, &sh_desc->hw);
 277         dmae_start(sh_chan);
 278 }
 279
 280 static bool sh_dmae_channel_busy(struct shdma_chan *schan)
 281 {
 282         struct sh_dmae_chan *sh_chan = container_of(schan, struct sh_dmae_chan,
 283                                                     shdma_chan);
 284         return dmae_is_busy(sh_chan);
 285 }
 286
 287 static void sh_dmae_setup_xfer(struct shdma_chan *schan,
 288                                int slave_id)
 289 {
 290         struct sh_dmae_chan *sh_chan = container_of(schan, struct sh_dmae_chan,
 291                                                     shdma_chan);
 292
 293         if (slave_id >= 0) {
 294                 const struct sh_dmae_slave_config *cfg =
 295                         sh_chan->config;
 296
 297                 dmae_set_dmars(sh_chan, cfg->mid_rid);
 298                 dmae_set_chcr(sh_chan, cfg->chcr);
 299         } else {
 300                 dmae_init(sh_chan);
 301         }
 302 }
 303
 304 static const struct sh_dmae_slave_config *dmae_find_slave(
 305         struct sh_dmae_chan *sh_chan, int slave_id)
 306 {
 307         struct sh_dmae_device *shdev = to_sh_dev(sh_chan);
 308         struct sh_dmae_pdata *pdata = shdev->pdata;
 309         const struct sh_dmae_slave_config *cfg;
 310         int i;
 311
 312         if (slave_id >= SH_DMA_SLAVE_NUMBER)
 313                 return NULL;
 314
 315         for (i = 0, cfg = pdata->slave; i < pdata->slave_num; i++, cfg++)
 316                 if (cfg->slave_id == slave_id)
 317                         return cfg;
 318
 319         return NULL;
 320 }
 321
 322 static int sh_dmae_set_slave(struct shdma_chan *schan,
 323                              int slave_id)
 324 {
 325         struct sh_dmae_chan *sh_chan = container_of(schan, struct sh_dmae_chan,
 326                                                     shdma_chan);
 327         const struct sh_dmae_slave_config *cfg = dmae_find_slave(sh_chan, slave_id);
 328         if (!cfg)
 329                 return -ENODEV;
 330
 331         sh_chan->config = cfg;
 332
 333         return 0;
 334 }
 335
 336 static void dmae_halt(struct sh_dmae_chan *sh_chan)
 337 {
 338         struct sh_dmae_device *shdev = to_sh_dev(sh_chan);
 339         u32 chcr = chcr_read(sh_chan);
 340
 341         chcr &= ~(CHCR_DE | CHCR_TE | shdev->chcr_ie_bit);
 342         chcr_write(sh_chan, chcr);
 343 }
 344
 345 static int sh_dmae_desc_setup(struct shdma_chan *schan,
 346                               struct shdma_desc *sdesc,
 347                               dma_addr_t src, dma_addr_t dst, size_t *len)
 348 {
 349         struct sh_dmae_desc *sh_desc = container_of(sdesc,
 350                                         struct sh_dmae_desc, shdma_desc);
 351
 352         if (*len > schan->max_xfer_len)
 353                 *len = schan->max_xfer_len;
 354
 355         sh_desc->hw.sar = src;
 356         sh_desc->hw.dar = dst;
 357         sh_desc->hw.tcr = *len;
 358
 359         return 0;
 360 }
 361
 362 static void sh_dmae_halt(struct shdma_chan *schan)
 363 {
 364         struct sh_dmae_chan *sh_chan = container_of(schan, struct sh_dmae_chan,
 365                                                     shdma_chan);
 366         dmae_halt(sh_chan);
 367 }
 368
 369 static bool sh_dmae_chan_irq(struct shdma_chan *schan, int irq)
 370 {
 371         struct sh_dmae_chan *sh_chan = container_of(schan, struct sh_dmae_chan,
 372                                                     shdma_chan);
 373
 374         if (!(chcr_read(sh_chan) & CHCR_TE))
 375                 return false;
 376
 377         /* DMA stop */
 378         dmae_halt(sh_chan);
 379
 380         return true;
 381 }
 382
 383 /* Called from error IRQ or NMI */
 384 static bool sh_dmae_reset(struct sh_dmae_device *shdev)
 385 {
 386         bool ret;
 387
 388         /* halt the dma controller */
 389         sh_dmae_ctl_stop(shdev);
 390
 391         /* We cannot detect, which channel caused the error, have to reset all */
 392         ret = shdma_reset(&shdev->shdma_dev);
 393
 394         sh_dmae_rst(shdev);
 395
 396         return ret;
 397 }
 398
 399 static irqreturn_t sh_dmae_err(int irq, void *data)
 400 {
 401         struct sh_dmae_device *shdev = data;
 402
 403         if (!(dmaor_read(shdev) & DMAOR_AE))
 404                 return IRQ_NONE;
 405
 406         sh_dmae_reset(shdev);
 407         return IRQ_HANDLED;
 408 }
 409
 410 static bool sh_dmae_desc_completed(struct shdma_chan *schan,
 411                                    struct shdma_desc *sdesc)
 412 {
 413         struct sh_dmae_chan *sh_chan = container_of(schan,
 414                                         struct sh_dmae_chan, shdma_chan);
 415         struct sh_dmae_desc *sh_desc = container_of(sdesc,
 416                                         struct sh_dmae_desc, shdma_desc);
 417         u32 sar_buf = sh_dmae_readl(sh_chan, SAR);
 418         u32 dar_buf = sh_dmae_readl(sh_chan, DAR);
 419
 420         return  (sdesc->direction == DMA_DEV_TO_MEM &&
 421                  (sh_desc->hw.dar + sh_desc->hw.tcr) == dar_buf) ||
 422                 (sdesc->direction != DMA_DEV_TO_MEM &&
 423                  (sh_desc->hw.sar + sh_desc->hw.tcr) == sar_buf);
 424 }
 425
 426 static bool sh_dmae_nmi_notify(struct sh_dmae_device *shdev)
 427 {
 428         /* Fast path out if NMIF is not asserted for this controller */
 429         if ((dmaor_read(shdev) & DMAOR_NMIF) == 0)
 430                 return false;
 431
 432         return sh_dmae_reset(shdev);
 433 }
 434
 435 static int sh_dmae_nmi_handler(struct notifier_block *self,
 436                                unsigned long cmd, void *data)
 437 {
 438         struct sh_dmae_device *shdev;
 439         int ret = NOTIFY_DONE;
 440         bool triggered;
 441
 442         /*
 443          * Only concern ourselves with NMI events.
 444          *
 445          * Normally we would check the die chain value, but as this needs
 446          * to be architecture independent, check for NMI context instead.
 447          */
 448         if (!in_nmi())
 449                 return NOTIFY_DONE;
 450
 451         rcu_read_lock();
 452         list_for_each_entry_rcu(shdev, &sh_dmae_devices, node) {
 453                 /*
 454                  * Only stop if one of the controllers has NMIF asserted,
 455                  * we do not want to interfere with regular address error
 456                  * handling or NMI events that don't concern the DMACs.
 457                  */
 458                 triggered = sh_dmae_nmi_notify(shdev);
 459                 if (triggered == true)
 460                         ret = NOTIFY_OK;
 461         }
 462         rcu_read_unlock();
 463
 464         return ret;
 465 }
 466
 467 static struct notifier_block sh_dmae_nmi_notifier __read_mostly = {
 468         .notifier_call  = sh_dmae_nmi_handler,
 469
 470         /* Run before NMI debug handler and KGDB */
 471         .priority       = 1,
 472 };
 473
 474 static int __devinit sh_dmae_chan_probe(struct sh_dmae_device *shdev, int id,
 475                                         int irq, unsigned long flags)
 476 {
 477         const struct sh_dmae_channel *chan_pdata = &shdev->pdata->channel[id];
 478         struct shdma_dev *sdev = &shdev->shdma_dev;
 479         struct platform_device *pdev = to_platform_device(sdev->dma_dev.dev);
 480         struct sh_dmae_chan *sh_chan;
 481         struct shdma_chan *schan;
 482         int err;
 483
 484         sh_chan = kzalloc(sizeof(struct sh_dmae_chan), GFP_KERNEL);
 485         if (!sh_chan) {
 486                 dev_err(sdev->dma_dev.dev,
 487                         "No free memory for allocating dma channels!\n");
 488                 return -ENOMEM;
 489         }
 490
 491         schan = &sh_chan->shdma_chan;
 492         schan->max_xfer_len = SH_DMA_TCR_MAX + 1;
 493
 494         shdma_chan_probe(sdev, schan, id);
 495
 496         sh_chan->base = shdev->chan_reg + chan_pdata->offset / sizeof(u32);
 497
 498         /* set up channel irq */
 499         if (pdev->id >= 0)
 500                 snprintf(sh_chan->dev_id, sizeof(sh_chan->dev_id),
 501                          "sh-dmae%d.%d", pdev->id, id);
 502         else
 503                 snprintf(sh_chan->dev_id, sizeof(sh_chan->dev_id),
 504                          "sh-dma%d", id);
 505
 506         err = shdma_request_irq(schan, irq, flags, sh_chan->dev_id);
 507         if (err) {
 508                 dev_err(sdev->dma_dev.dev,
 509                         "DMA channel %d request_irq error %d\n",
 510                         id, err);
 511                 goto err_no_irq;
 512         }
 513
 514         shdev->chan[id] = sh_chan;
 515         return 0;
 516
 517 err_no_irq:
 518         /* remove from dmaengine device node */
 519         shdma_chan_remove(schan);
 520         kfree(sh_chan);
 521         return err;
 522 }
 523
 524 static void sh_dmae_chan_remove(struct sh_dmae_device *shdev)
 525 {
 526         struct dma_device *dma_dev = &shdev->shdma_dev.dma_dev;
 527         struct shdma_chan *schan;
 528         int i;
 529
 530         shdma_for_each_chan(schan, &shdev->shdma_dev, i) {
 531                 struct sh_dmae_chan *sh_chan = container_of(schan,
 532                                         struct sh_dmae_chan, shdma_chan);
 533                 BUG_ON(!schan);
 534
 535                 shdma_free_irq(&sh_chan->shdma_chan);
 536
 537                 shdma_chan_remove(schan);
 538                 kfree(sh_chan);
 539         }
 540         dma_dev->chancnt = 0;
 541 }
 542
 543 static void sh_dmae_shutdown(struct platform_device *pdev)
 544 {
 545         struct sh_dmae_device *shdev = platform_get_drvdata(pdev);
 546         sh_dmae_ctl_stop(shdev);
 547 }
 548
 549 static int sh_dmae_runtime_suspend(struct device *dev)
 550 {
 551         return 0;
 552 }
 553
 554 static int sh_dmae_runtime_resume(struct device *dev)
 555 {
 556         struct sh_dmae_device *shdev = dev_get_drvdata(dev);
 557
 558         return sh_dmae_rst(shdev);
 559 }
 560
 561 #ifdef CONFIG_PM
 562 static int sh_dmae_suspend(struct device *dev)
 563 {
 564         return 0;
 565 }
 566
 567 static int sh_dmae_resume(struct device *dev)
 568 {
 569         struct sh_dmae_device *shdev = dev_get_drvdata(dev);
 570         int i, ret;
 571
 572         ret = sh_dmae_rst(shdev);
 573         if (ret < 0)
 574                 dev_err(dev, "Failed to reset!\n");
 575
 576         for (i = 0; i < shdev->pdata->channel_num; i++) {
 577                 struct sh_dmae_chan *sh_chan = shdev->chan[i];
 578
 579                 if (!sh_chan->shdma_chan.desc_num)
 580                         continue;
 581
 582                 if (sh_chan->shdma_chan.slave_id >= 0) {
 583                         const struct sh_dmae_slave_config *cfg = sh_chan->config;
 584                         dmae_set_dmars(sh_chan, cfg->mid_rid);
 585                         dmae_set_chcr(sh_chan, cfg->chcr);
 586                 } else {
 587                         dmae_init(sh_chan);
 588                 }
 589         }
 590
 591         return 0;
 592 }
 593 #else
 594 #define sh_dmae_suspend NULL
 595 #define sh_dmae_resume NULL
 596 #endif
 597
 598 const struct dev_pm_ops sh_dmae_pm = {
 599         .suspend                = sh_dmae_suspend,
 600         .resume                 = sh_dmae_resume,
 601         .runtime_suspend        = sh_dmae_runtime_suspend,
 602         .runtime_resume         = sh_dmae_runtime_resume,
 603 };
 604
 605 static dma_addr_t sh_dmae_slave_addr(struct shdma_chan *schan)
 606 {
 607         struct sh_dmae_chan *sh_chan = container_of(schan,
 608                                         struct sh_dmae_chan, shdma_chan);
 609
 610         /*
 611          * Implicit BUG_ON(!sh_chan->config)
 612          * This is an exclusive slave DMA operation, may only be called after a
 613          * successful slave configuration.
 614          */
 615         return sh_chan->config->addr;
 616 }
 617
 618 static struct shdma_desc *sh_dmae_embedded_desc(void *buf, int i)
 619 {
 620         return &((struct sh_dmae_desc *)buf)[i].shdma_desc;
 621 }
 622
 623 static const struct shdma_ops sh_dmae_shdma_ops = {
 624         .desc_completed = sh_dmae_desc_completed,
 625         .halt_channel = sh_dmae_halt,
 626         .channel_busy = sh_dmae_channel_busy,
 627         .slave_addr = sh_dmae_slave_addr,
 628         .desc_setup = sh_dmae_desc_setup,
 629         .set_slave = sh_dmae_set_slave,
 630         .setup_xfer = sh_dmae_setup_xfer,
 631         .start_xfer = sh_dmae_start_xfer,
 632         .embedded_desc = sh_dmae_embedded_desc,
 633         .chan_irq = sh_dmae_chan_irq,
 634 };
 635
 636 static int __devinit sh_dmae_probe(struct platform_device *pdev)
 637 {
 638         struct sh_dmae_pdata *pdata = pdev->dev.platform_data;
 639         unsigned long irqflags = IRQF_DISABLED,
 640                 chan_flag[SH_DMAE_MAX_CHANNELS] = {};
 641         int errirq, chan_irq[SH_DMAE_MAX_CHANNELS];
 642         int err, i, irq_cnt = 0, irqres = 0, irq_cap = 0;
 643         struct sh_dmae_device *shdev;
 644         struct dma_device *dma_dev;
 645         struct resource *chan, *dmars, *errirq_res, *chanirq_res;
 646
 647         /* get platform data */
 648         if (!pdata || !pdata->channel_num)
 649                 return -ENODEV;
 650
 651         chan = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 652         /* DMARS area is optional */
 653         dmars = platform_get_resource(pdev, IORESOURCE_MEM, 1);
 654         /*
 655          * IRQ resources:
 656          * 1. there always must be at least one IRQ IO-resource. On SH4 it is
 657          *    the error IRQ, in which case it is the only IRQ in this resource:
 658          *    start == end. If it is the only IRQ resource, all channels also
 659          *    use the same IRQ.
 660          * 2. DMA channel IRQ resources can be specified one per resource or in
 661          *    ranges (start != end)
 662          * 3. iff all events (channels and, optionally, error) on this
 663          *    controller use the same IRQ, only one IRQ resource can be
 664          *    specified, otherwise there must be one IRQ per channel, even if
 665          *    some of them are equal
 666          * 4. if all IRQs on this controller are equal or if some specific IRQs
 667          *    specify IORESOURCE_IRQ_SHAREABLE in their resources, they will be
 668          *    requested with the IRQF_SHARED flag
 669          */
 670         errirq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
 671         if (!chan || !errirq_res)
 672                 return -ENODEV;
 673
 674         if (!request_mem_region(chan->start, resource_size(chan), pdev->name)) {
 675                 dev_err(&pdev->dev, "DMAC register region already claimed\n");
 676                 return -EBUSY;
 677         }
 678
 679         if (dmars && !request_mem_region(dmars->start, resource_size(dmars), pdev->name)) {
 680                 dev_err(&pdev->dev, "DMAC DMARS region already claimed\n");
 681                 err = -EBUSY;
 682                 goto ermrdmars;
 683         }
 684
 685         err = -ENOMEM;
 686         shdev = kzalloc(sizeof(struct sh_dmae_device), GFP_KERNEL);
 687         if (!shdev) {
 688                 dev_err(&pdev->dev, "Not enough memory\n");
 689                 goto ealloc;
 690         }
 691
 692         dma_dev = &shdev->shdma_dev.dma_dev;
 693
 694         shdev->chan_reg = ioremap(chan->start, resource_size(chan));
 695         if (!shdev->chan_reg)
 696                 goto emapchan;
 697         if (dmars) {
 698                 shdev->dmars = ioremap(dmars->start, resource_size(dmars));
 699                 if (!shdev->dmars)
 700                         goto emapdmars;
 701         }
 702
 703         if (!pdata->slave_only)
 704                 dma_cap_set(DMA_MEMCPY, dma_dev->cap_mask);
 705         if (pdata->slave && pdata->slave_num)
 706                 dma_cap_set(DMA_SLAVE, dma_dev->cap_mask);
 707
 708         /* Default transfer size of 32 bytes requires 32-byte alignment */
 709         dma_dev->copy_align = LOG2_DEFAULT_XFER_SIZE;
 710
 711         shdev->shdma_dev.ops = &sh_dmae_shdma_ops;
 712         shdev->shdma_dev.desc_size = sizeof(struct sh_dmae_desc);
 713         err = shdma_init(&pdev->dev, &shdev->shdma_dev,
 714                               pdata->channel_num);
 715         if (err < 0)
 716                 goto eshdma;
 717
 718         /* platform data */
 719         shdev->pdata = pdev->dev.platform_data;
 720
 721         if (pdata->chcr_offset)
 722                 shdev->chcr_offset = pdata->chcr_offset;
 723         else
 724                 shdev->chcr_offset = CHCR;
 725
 726         if (pdata->chcr_ie_bit)
 727                 shdev->chcr_ie_bit = pdata->chcr_ie_bit;
 728         else
 729                 shdev->chcr_ie_bit = CHCR_IE;
 730
 731         platform_set_drvdata(pdev, shdev);
 732
 733         pm_runtime_enable(&pdev->dev);
 734         err = pm_runtime_get_sync(&pdev->dev);
 735         if (err < 0)
 736                 dev_err(&pdev->dev, "%s(): GET = %d\n", __func__, err);
 737
 738         spin_lock_irq(&sh_dmae_lock);
 739         list_add_tail_rcu(&shdev->node, &sh_dmae_devices);
 740         spin_unlock_irq(&sh_dmae_lock);
 741
 742         /* reset dma controller - only needed as a test */
 743         err = sh_dmae_rst(shdev);
 744         if (err)
 745                 goto rst_err;
 746
 747 #if defined(CONFIG_CPU_SH4) || defined(CONFIG_ARCH_SHMOBILE)
 748         chanirq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 1);
 749
 750         if (!chanirq_res)
 751                 chanirq_res = errirq_res;
 752         else
 753                 irqres++;
 754
 755         if (chanirq_res == errirq_res ||
 756             (errirq_res->flags & IORESOURCE_BITS) == IORESOURCE_IRQ_SHAREABLE)
 757                 irqflags = IRQF_SHARED;
 758
 759         errirq = errirq_res->start;
 760
 761         err = request_irq(errirq, sh_dmae_err, irqflags,
 762                           "DMAC Address Error", shdev);
 763         if (err) {
 764                 dev_err(&pdev->dev,
 765                         "DMA failed requesting irq #%d, error %d\n",
 766                         errirq, err);
 767                 goto eirq_err;
 768         }
 769
 770 #else
 771         chanirq_res = errirq_res;
 772 #endif /* CONFIG_CPU_SH4 || CONFIG_ARCH_SHMOBILE */
 773
 774         if (chanirq_res->start == chanirq_res->end &&
 775             !platform_get_resource(pdev, IORESOURCE_IRQ, 1)) {
 776                 /* Special case - all multiplexed */
 777                 for (; irq_cnt < pdata->channel_num; irq_cnt++) {
 778                         if (irq_cnt < SH_DMAE_MAX_CHANNELS) {
 779                                 chan_irq[irq_cnt] = chanirq_res->start;
 780                                 chan_flag[irq_cnt] = IRQF_SHARED;
 781                         } else {
 782                                 irq_cap = 1;
 783                                 break;
 784                         }
 785                 }
 786         } else {
 787                 do {
 788                         for (i = chanirq_res->start; i <= chanirq_res->end; i++) {
 789                                 if (irq_cnt >= SH_DMAE_MAX_CHANNELS) {
 790                                         irq_cap = 1;
 791                                         break;
 792                                 }
 793
 794                                 if ((errirq_res->flags & IORESOURCE_BITS) ==
 795                                     IORESOURCE_IRQ_SHAREABLE)
 796                                         chan_flag[irq_cnt] = IRQF_SHARED;
 797                                 else
 798                                         chan_flag[irq_cnt] = IRQF_DISABLED;
 799                                 dev_dbg(&pdev->dev,
 800                                         "Found IRQ %d for channel %d\n",
 801                                         i, irq_cnt);
 802                                 chan_irq[irq_cnt++] = i;
 803                         }
 804
 805                         if (irq_cnt >= SH_DMAE_MAX_CHANNELS)
 806                                 break;
 807
 808                         chanirq_res = platform_get_resource(pdev,
 809                                                 IORESOURCE_IRQ, ++irqres);
 810                 } while (irq_cnt < pdata->channel_num && chanirq_res);
 811         }
 812
 813         /* Create DMA Channel */
 814         for (i = 0; i < irq_cnt; i++) {
 815                 err = sh_dmae_chan_probe(shdev, i, chan_irq[i], chan_flag[i]);
 816                 if (err)
 817                         goto chan_probe_err;
 818         }
 819
 820         if (irq_cap)
 821                 dev_notice(&pdev->dev, "Attempting to register %d DMA "
 822                            "channels when a maximum of %d are supported.\n",
 823                            pdata->channel_num, SH_DMAE_MAX_CHANNELS);
 824
 825         pm_runtime_put(&pdev->dev);
 826
 827         err = dma_async_device_register(&shdev->shdma_dev.dma_dev);
 828         if (err < 0)
 829                 goto edmadevreg;
 830
 831         return err;
 832
 833 edmadevreg:
 834         pm_runtime_get(&pdev->dev);
 835
 836 chan_probe_err:
 837         sh_dmae_chan_remove(shdev);
 838
 839 #if defined(CONFIG_CPU_SH4) || defined(CONFIG_ARCH_SHMOBILE)
 840         free_irq(errirq, shdev);
 841 eirq_err:
 842 #endif
 843 rst_err:
 844         spin_lock_irq(&sh_dmae_lock);
 845         list_del_rcu(&shdev->node);
 846         spin_unlock_irq(&sh_dmae_lock);
 847
 848         pm_runtime_put(&pdev->dev);
 849         pm_runtime_disable(&pdev->dev);
 850
 851         platform_set_drvdata(pdev, NULL);
 852         shdma_cleanup(&shdev->shdma_dev);
 853 eshdma:
 854         if (dmars)
 855                 iounmap(shdev->dmars);
 856 emapdmars:
 857         iounmap(shdev->chan_reg);
 858         synchronize_rcu();
 859 emapchan:
 860         kfree(shdev);
 861 ealloc:
 862         if (dmars)
 863                 release_mem_region(dmars->start, resource_size(dmars));
 864 ermrdmars:
 865         release_mem_region(chan->start, resource_size(chan));
 866
 867         return err;
 868 }
 869
 870 static int __devexit sh_dmae_remove(struct platform_device *pdev)
 871 {
 872         struct sh_dmae_device *shdev = platform_get_drvdata(pdev);
 873         struct dma_device *dma_dev = &shdev->shdma_dev.dma_dev;
 874         struct resource *res;
 875         int errirq = platform_get_irq(pdev, 0);
 876
 877         dma_async_device_unregister(dma_dev);
 878
 879         if (errirq > 0)
 880                 free_irq(errirq, shdev);
 881
 882         spin_lock_irq(&sh_dmae_lock);
 883         list_del_rcu(&shdev->node);
 884         spin_unlock_irq(&sh_dmae_lock);
 885
 886         pm_runtime_disable(&pdev->dev);
 887
 888         sh_dmae_chan_remove(shdev);
 889         shdma_cleanup(&shdev->shdma_dev);
 890
 891         if (shdev->dmars)
 892                 iounmap(shdev->dmars);
 893         iounmap(shdev->chan_reg);
 894
 895         platform_set_drvdata(pdev, NULL);
 896
 897         synchronize_rcu();
 898         kfree(shdev);
 899
 900         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 901         if (res)
 902                 release_mem_region(res->start, resource_size(res));
 903         res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
 904         if (res)
 905                 release_mem_region(res->start, resource_size(res));
 906
 907         return 0;
 908 }
 909
 910 static struct platform_driver sh_dmae_driver = {
 911         .driver         = {
 912                 .owner  = THIS_MODULE,
 913                 .pm     = &sh_dmae_pm,
 914                 .name   = SH_DMAE_DRV_NAME,
 915         },
 916         .remove         = __devexit_p(sh_dmae_remove),
 917         .shutdown       = sh_dmae_shutdown,
 918 };
 919
 920 static int __init sh_dmae_init(void)
 921 {
 922         /* Wire up NMI handling */
 923         int err = register_die_notifier(&sh_dmae_nmi_notifier);
 924         if (err)
 925                 return err;
 926
 927         return platform_driver_probe(&sh_dmae_driver, sh_dmae_probe);
 928 }
 929 module_init(sh_dmae_init);
 930
 931 static void __exit sh_dmae_exit(void)
 932 {
 933         platform_driver_unregister(&sh_dmae_driver);
 934
 935         unregister_die_notifier(&sh_dmae_nmi_notifier);
 936 }
 937 module_exit(sh_dmae_exit);
 938
 939 MODULE_AUTHOR("Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>");
 940 MODULE_DESCRIPTION("Renesas SH DMA Engine driver");
 941 MODULE_LICENSE("GPL");
 942 MODULE_ALIAS("platform:" SH_DMAE_DRV_NAME);