drivers/dma/qcom/hidma.c

   1 /*
   2  * Qualcomm Technologies HIDMA DMA engine interface
   3  *
   4  * Copyright (c) 2015-2017, The Linux Foundation. All rights reserved.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 and
   8  * only version 2 as published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 /*
  17  * Copyright (C) Freescale Semicondutor, Inc. 2007, 2008.
  18  * Copyright (C) Semihalf 2009
  19  * Copyright (C) Ilya Yanok, Emcraft Systems 2010
  20  * Copyright (C) Alexander Popov, Promcontroller 2014
  21  *
  22  * Written by Piotr Ziecik <kosmo@semihalf.com>. Hardware description
  23  * (defines, structures and comments) was taken from MPC5121 DMA driver
  24  * written by Hongjun Chen <hong-jun.chen@freescale.com>.
  25  *
  26  * Approved as OSADL project by a majority of OSADL members and funded
  27  * by OSADL membership fees in 2009;  for details see www.osadl.org.
  28  *
  29  * This program is free software; you can redistribute it and/or modify it
  30  * under the terms of the GNU General Public License as published by the Free
  31  * Software Foundation; either version 2 of the License, or (at your option)
  32  * any later version.
  33  *
  34  * This program is distributed in the hope that it will be useful, but WITHOUT
  35  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  36  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  37  * more details.
  38  *
  39  * The full GNU General Public License is included in this distribution in the
  40  * file called COPYING.
  41  */
  42
  43 /* Linux Foundation elects GPLv2 license only. */
  44
  45 #include <linux/dmaengine.h>
  46 #include <linux/dma-mapping.h>
  47 #include <linux/list.h>
  48 #include <linux/module.h>
  49 #include <linux/platform_device.h>
  50 #include <linux/slab.h>
  51 #include <linux/spinlock.h>
  52 #include <linux/of_dma.h>
  53 #include <linux/of_device.h>
  54 #include <linux/property.h>
  55 #include <linux/delay.h>
  56 #include <linux/acpi.h>
  57 #include <linux/irq.h>
  58 #include <linux/atomic.h>
  59 #include <linux/pm_runtime.h>
  60 #include <linux/msi.h>
  61
  62 #include "../dmaengine.h"
  63 #include "hidma.h"
  64
  65 /*
  66  * Default idle time is 2 seconds. This parameter can
  67  * be overridden by changing the following
  68  * /sys/bus/platform/devices/QCOM8061:<xy>/power/autosuspend_delay_ms
  69  * during kernel boot.
  70  */
  71 #define HIDMA_AUTOSUSPEND_TIMEOUT               2000
  72 #define HIDMA_ERR_INFO_SW                       0xFF
  73 #define HIDMA_ERR_CODE_UNEXPECTED_TERMINATE     0x0
  74 #define HIDMA_NR_DEFAULT_DESC                   10
  75 #define HIDMA_MSI_INTS                          11
  76
  77 static inline struct hidma_dev *to_hidma_dev(struct dma_device *dmadev)
  78 {
  79         return container_of(dmadev, struct hidma_dev, ddev);
  80 }
  81
  82 static inline
  83 struct hidma_dev *to_hidma_dev_from_lldev(struct hidma_lldev **_lldevp)
  84 {
  85         return container_of(_lldevp, struct hidma_dev, lldev);
  86 }
  87
  88 static inline struct hidma_chan *to_hidma_chan(struct dma_chan *dmach)
  89 {
  90         return container_of(dmach, struct hidma_chan, chan);
  91 }
  92
  93 static inline
  94 struct hidma_desc *to_hidma_desc(struct dma_async_tx_descriptor *t)
  95 {
  96         return container_of(t, struct hidma_desc, desc);
  97 }
  98
  99 static void hidma_free(struct hidma_dev *dmadev)
 100 {
 101         INIT_LIST_HEAD(&dmadev->ddev.channels);
 102 }
 103
 104 static unsigned int nr_desc_prm;
 105 module_param(nr_desc_prm, uint, 0644);
 106 MODULE_PARM_DESC(nr_desc_prm, "number of descriptors (default: 0)");
 107
 108 enum hidma_cap {
 109         HIDMA_MSI_CAP = 1,
 110         HIDMA_IDENTITY_CAP,
 111 };
 112
 113 /* process completed descriptors */
 114 static void hidma_process_completed(struct hidma_chan *mchan)
 115 {
 116         struct dma_device *ddev = mchan->chan.device;
 117         struct hidma_dev *mdma = to_hidma_dev(ddev);
 118         struct dma_async_tx_descriptor *desc;
 119         dma_cookie_t last_cookie;
 120         struct hidma_desc *mdesc;
 121         struct hidma_desc *next;
 122         unsigned long irqflags;
 123         struct list_head list;
 124
 125         INIT_LIST_HEAD(&list);
 126
 127         /* Get all completed descriptors */
 128         spin_lock_irqsave(&mchan->lock, irqflags);
 129         list_splice_tail_init(&mchan->completed, &list);
 130         spin_unlock_irqrestore(&mchan->lock, irqflags);
 131
 132         /* Execute callbacks and run dependencies */
 133         list_for_each_entry_safe(mdesc, next, &list, node) {
 134                 enum dma_status llstat;
 135                 struct dmaengine_desc_callback cb;
 136                 struct dmaengine_result result;
 137
 138                 desc = &mdesc->desc;
 139                 last_cookie = desc->cookie;
 140
 141                 spin_lock_irqsave(&mchan->lock, irqflags);
 142                 dma_cookie_complete(desc);
 143                 spin_unlock_irqrestore(&mchan->lock, irqflags);
 144
 145                 llstat = hidma_ll_status(mdma->lldev, mdesc->tre_ch);
 146                 dmaengine_desc_get_callback(desc, &cb);
 147
 148                 dma_run_dependencies(desc);
 149
 150                 spin_lock_irqsave(&mchan->lock, irqflags);
 151                 list_move(&mdesc->node, &mchan->free);
 152
 153                 if (llstat == DMA_COMPLETE) {
 154                         mchan->last_success = last_cookie;
 155                         result.result = DMA_TRANS_NOERROR;
 156                 } else
 157                         result.result = DMA_TRANS_ABORTED;
 158
 159                 spin_unlock_irqrestore(&mchan->lock, irqflags);
 160
 161                 dmaengine_desc_callback_invoke(&cb, &result);
 162         }
 163 }
 164
 165 /*
 166  * Called once for each submitted descriptor.
 167  * PM is locked once for each descriptor that is currently
 168  * in execution.
 169  */
 170 static void hidma_callback(void *data)
 171 {
 172         struct hidma_desc *mdesc = data;
 173         struct hidma_chan *mchan = to_hidma_chan(mdesc->desc.chan);
 174         struct dma_device *ddev = mchan->chan.device;
 175         struct hidma_dev *dmadev = to_hidma_dev(ddev);
 176         unsigned long irqflags;
 177         bool queued = false;
 178
 179         spin_lock_irqsave(&mchan->lock, irqflags);
 180         if (mdesc->node.next) {
 181                 /* Delete from the active list, add to completed list */
 182                 list_move_tail(&mdesc->node, &mchan->completed);
 183                 queued = true;
 184
 185                 /* calculate the next running descriptor */
 186                 mchan->running = list_first_entry(&mchan->active,
 187                                                   struct hidma_desc, node);
 188         }
 189         spin_unlock_irqrestore(&mchan->lock, irqflags);
 190
 191         hidma_process_completed(mchan);
 192
 193         if (queued) {
 194                 pm_runtime_mark_last_busy(dmadev->ddev.dev);
 195                 pm_runtime_put_autosuspend(dmadev->ddev.dev);
 196         }
 197 }
 198
 199 static int hidma_chan_init(struct hidma_dev *dmadev, u32 dma_sig)
 200 {
 201         struct hidma_chan *mchan;
 202         struct dma_device *ddev;
 203
 204         mchan = devm_kzalloc(dmadev->ddev.dev, sizeof(*mchan), GFP_KERNEL);
 205         if (!mchan)
 206                 return -ENOMEM;
 207
 208         ddev = &dmadev->ddev;
 209         mchan->dma_sig = dma_sig;
 210         mchan->dmadev = dmadev;
 211         mchan->chan.device = ddev;
 212         dma_cookie_init(&mchan->chan);
 213
 214         INIT_LIST_HEAD(&mchan->free);
 215         INIT_LIST_HEAD(&mchan->prepared);
 216         INIT_LIST_HEAD(&mchan->active);
 217         INIT_LIST_HEAD(&mchan->completed);
 218         INIT_LIST_HEAD(&mchan->queued);
 219
 220         spin_lock_init(&mchan->lock);
 221         list_add_tail(&mchan->chan.device_node, &ddev->channels);
 222         dmadev->ddev.chancnt++;
 223         return 0;
 224 }
 225
 226 static void hidma_issue_task(unsigned long arg)
 227 {
 228         struct hidma_dev *dmadev = (struct hidma_dev *)arg;
 229
 230         pm_runtime_get_sync(dmadev->ddev.dev);
 231         hidma_ll_start(dmadev->lldev);
 232 }
 233
 234 static void hidma_issue_pending(struct dma_chan *dmach)
 235 {
 236         struct hidma_chan *mchan = to_hidma_chan(dmach);
 237         struct hidma_dev *dmadev = mchan->dmadev;
 238         unsigned long flags;
 239         struct hidma_desc *qdesc, *next;
 240         int status;
 241
 242         spin_lock_irqsave(&mchan->lock, flags);
 243         list_for_each_entry_safe(qdesc, next, &mchan->queued, node) {
 244                 hidma_ll_queue_request(dmadev->lldev, qdesc->tre_ch);
 245                 list_move_tail(&qdesc->node, &mchan->active);
 246         }
 247
 248         if (!mchan->running) {
 249                 struct hidma_desc *desc = list_first_entry(&mchan->active,
 250                                                            struct hidma_desc,
 251                                                            node);
 252                 mchan->running = desc;
 253         }
 254         spin_unlock_irqrestore(&mchan->lock, flags);
 255
 256         /* PM will be released in hidma_callback function. */
 257         status = pm_runtime_get(dmadev->ddev.dev);
 258         if (status < 0)
 259                 tasklet_schedule(&dmadev->task);
 260         else
 261                 hidma_ll_start(dmadev->lldev);
 262 }
 263
 264 static inline bool hidma_txn_is_success(dma_cookie_t cookie,
 265                 dma_cookie_t last_success, dma_cookie_t last_used)
 266 {
 267         if (last_success <= last_used) {
 268                 if ((cookie <= last_success) || (cookie > last_used))
 269                         return true;
 270         } else {
 271                 if ((cookie <= last_success) && (cookie > last_used))
 272                         return true;
 273         }
 274         return false;
 275 }
 276
 277 static enum dma_status hidma_tx_status(struct dma_chan *dmach,
 278                                        dma_cookie_t cookie,
 279                                        struct dma_tx_state *txstate)
 280 {
 281         struct hidma_chan *mchan = to_hidma_chan(dmach);
 282         enum dma_status ret;
 283
 284         ret = dma_cookie_status(dmach, cookie, txstate);
 285         if (ret == DMA_COMPLETE) {
 286                 bool is_success;
 287
 288                 is_success = hidma_txn_is_success(cookie, mchan->last_success,
 289                                                   dmach->cookie);
 290                 return is_success ? ret : DMA_ERROR;
 291         }
 292
 293         if (mchan->paused && (ret == DMA_IN_PROGRESS)) {
 294                 unsigned long flags;
 295                 dma_cookie_t runcookie;
 296
 297                 spin_lock_irqsave(&mchan->lock, flags);
 298                 if (mchan->running)
 299                         runcookie = mchan->running->desc.cookie;
 300                 else
 301                         runcookie = -EINVAL;
 302
 303                 if (runcookie == cookie)
 304                         ret = DMA_PAUSED;
 305
 306                 spin_unlock_irqrestore(&mchan->lock, flags);
 307         }
 308
 309         return ret;
 310 }
 311
 312 /*
 313  * Submit descriptor to hardware.
 314  * Lock the PM for each descriptor we are sending.
 315  */
 316 static dma_cookie_t hidma_tx_submit(struct dma_async_tx_descriptor *txd)
 317 {
 318         struct hidma_chan *mchan = to_hidma_chan(txd->chan);
 319         struct hidma_dev *dmadev = mchan->dmadev;
 320         struct hidma_desc *mdesc;
 321         unsigned long irqflags;
 322         dma_cookie_t cookie;
 323
 324         pm_runtime_get_sync(dmadev->ddev.dev);
 325         if (!hidma_ll_isenabled(dmadev->lldev)) {
 326                 pm_runtime_mark_last_busy(dmadev->ddev.dev);
 327                 pm_runtime_put_autosuspend(dmadev->ddev.dev);
 328                 return -ENODEV;
 329         }
 330         pm_runtime_mark_last_busy(dmadev->ddev.dev);
 331         pm_runtime_put_autosuspend(dmadev->ddev.dev);
 332
 333         mdesc = container_of(txd, struct hidma_desc, desc);
 334         spin_lock_irqsave(&mchan->lock, irqflags);
 335
 336         /* Move descriptor to queued */
 337         list_move_tail(&mdesc->node, &mchan->queued);
 338
 339         /* Update cookie */
 340         cookie = dma_cookie_assign(txd);
 341
 342         spin_unlock_irqrestore(&mchan->lock, irqflags);
 343
 344         return cookie;
 345 }
 346
 347 static int hidma_alloc_chan_resources(struct dma_chan *dmach)
 348 {
 349         struct hidma_chan *mchan = to_hidma_chan(dmach);
 350         struct hidma_dev *dmadev = mchan->dmadev;
 351         struct hidma_desc *mdesc, *tmp;
 352         unsigned long irqflags;
 353         LIST_HEAD(descs);
 354         unsigned int i;
 355         int rc = 0;
 356
 357         if (mchan->allocated)
 358                 return 0;
 359
 360         /* Alloc descriptors for this channel */
 361         for (i = 0; i < dmadev->nr_descriptors; i++) {
 362                 mdesc = kzalloc(sizeof(struct hidma_desc), GFP_NOWAIT);
 363                 if (!mdesc) {
 364                         rc = -ENOMEM;
 365                         break;
 366                 }
 367                 dma_async_tx_descriptor_init(&mdesc->desc, dmach);
 368                 mdesc->desc.tx_submit = hidma_tx_submit;
 369
 370                 rc = hidma_ll_request(dmadev->lldev, mchan->dma_sig,
 371                                       "DMA engine", hidma_callback, mdesc,
 372                                       &mdesc->tre_ch);
 373                 if (rc) {
 374                         dev_err(dmach->device->dev,
 375                                 "channel alloc failed at %u\n", i);
 376                         kfree(mdesc);
 377                         break;
 378                 }
 379                 list_add_tail(&mdesc->node, &descs);
 380         }
 381
 382         if (rc) {
 383                 /* return the allocated descriptors */
 384                 list_for_each_entry_safe(mdesc, tmp, &descs, node) {
 385                         hidma_ll_free(dmadev->lldev, mdesc->tre_ch);
 386                         kfree(mdesc);
 387                 }
 388                 return rc;
 389         }
 390
 391         spin_lock_irqsave(&mchan->lock, irqflags);
 392         list_splice_tail_init(&descs, &mchan->free);
 393         mchan->allocated = true;
 394         spin_unlock_irqrestore(&mchan->lock, irqflags);
 395         return 1;
 396 }
 397
 398 static struct dma_async_tx_descriptor *
 399 hidma_prep_dma_memcpy(struct dma_chan *dmach, dma_addr_t dest, dma_addr_t src,
 400                 size_t len, unsigned long flags)
 401 {
 402         struct hidma_chan *mchan = to_hidma_chan(dmach);
 403         struct hidma_desc *mdesc = NULL;
 404         struct hidma_dev *mdma = mchan->dmadev;
 405         unsigned long irqflags;
 406
 407         /* Get free descriptor */
 408         spin_lock_irqsave(&mchan->lock, irqflags);
 409         if (!list_empty(&mchan->free)) {
 410                 mdesc = list_first_entry(&mchan->free, struct hidma_desc, node);
 411                 list_del(&mdesc->node);
 412         }
 413         spin_unlock_irqrestore(&mchan->lock, irqflags);
 414
 415         if (!mdesc)
 416                 return NULL;
 417
 418         hidma_ll_set_transfer_params(mdma->lldev, mdesc->tre_ch,
 419                                      src, dest, len, flags,
 420                                      HIDMA_TRE_MEMCPY);
 421
 422         /* Place descriptor in prepared list */
 423         spin_lock_irqsave(&mchan->lock, irqflags);
 424         list_add_tail(&mdesc->node, &mchan->prepared);
 425         spin_unlock_irqrestore(&mchan->lock, irqflags);
 426
 427         return &mdesc->desc;
 428 }
 429
 430 static struct dma_async_tx_descriptor *
 431 hidma_prep_dma_memset(struct dma_chan *dmach, dma_addr_t dest, int value,
 432                 size_t len, unsigned long flags)
 433 {
 434         struct hidma_chan *mchan = to_hidma_chan(dmach);
 435         struct hidma_desc *mdesc = NULL;
 436         struct hidma_dev *mdma = mchan->dmadev;
 437         unsigned long irqflags;
 438
 439         /* Get free descriptor */
 440         spin_lock_irqsave(&mchan->lock, irqflags);
 441         if (!list_empty(&mchan->free)) {
 442                 mdesc = list_first_entry(&mchan->free, struct hidma_desc, node);
 443                 list_del(&mdesc->node);
 444         }
 445         spin_unlock_irqrestore(&mchan->lock, irqflags);
 446
 447         if (!mdesc)
 448                 return NULL;
 449
 450         hidma_ll_set_transfer_params(mdma->lldev, mdesc->tre_ch,
 451                                      value, dest, len, flags,
 452                                      HIDMA_TRE_MEMSET);
 453
 454         /* Place descriptor in prepared list */
 455         spin_lock_irqsave(&mchan->lock, irqflags);
 456         list_add_tail(&mdesc->node, &mchan->prepared);
 457         spin_unlock_irqrestore(&mchan->lock, irqflags);
 458
 459         return &mdesc->desc;
 460 }
 461
 462 static int hidma_terminate_channel(struct dma_chan *chan)
 463 {
 464         struct hidma_chan *mchan = to_hidma_chan(chan);
 465         struct hidma_dev *dmadev = to_hidma_dev(mchan->chan.device);
 466         struct hidma_desc *tmp, *mdesc;
 467         unsigned long irqflags;
 468         LIST_HEAD(list);
 469         int rc;
 470
 471         pm_runtime_get_sync(dmadev->ddev.dev);
 472         /* give completed requests a chance to finish */
 473         hidma_process_completed(mchan);
 474
 475         spin_lock_irqsave(&mchan->lock, irqflags);
 476         mchan->last_success = 0;
 477         list_splice_init(&mchan->active, &list);
 478         list_splice_init(&mchan->prepared, &list);
 479         list_splice_init(&mchan->completed, &list);
 480         list_splice_init(&mchan->queued, &list);
 481         spin_unlock_irqrestore(&mchan->lock, irqflags);
 482
 483         /* this suspends the existing transfer */
 484         rc = hidma_ll_disable(dmadev->lldev);
 485         if (rc) {
 486                 dev_err(dmadev->ddev.dev, "channel did not pause\n");
 487                 goto out;
 488         }
 489
 490         /* return all user requests */
 491         list_for_each_entry_safe(mdesc, tmp, &list, node) {
 492                 struct dma_async_tx_descriptor *txd = &mdesc->desc;
 493
 494                 dma_descriptor_unmap(txd);
 495                 dmaengine_desc_get_callback_invoke(txd, NULL);
 496                 dma_run_dependencies(txd);
 497
 498                 /* move myself to free_list */
 499                 list_move(&mdesc->node, &mchan->free);
 500         }
 501
 502         rc = hidma_ll_enable(dmadev->lldev);
 503 out:
 504         pm_runtime_mark_last_busy(dmadev->ddev.dev);
 505         pm_runtime_put_autosuspend(dmadev->ddev.dev);
 506         return rc;
 507 }
 508
 509 static int hidma_terminate_all(struct dma_chan *chan)
 510 {
 511         struct hidma_chan *mchan = to_hidma_chan(chan);
 512         struct hidma_dev *dmadev = to_hidma_dev(mchan->chan.device);
 513         int rc;
 514
 515         rc = hidma_terminate_channel(chan);
 516         if (rc)
 517                 return rc;
 518
 519         /* reinitialize the hardware */
 520         pm_runtime_get_sync(dmadev->ddev.dev);
 521         rc = hidma_ll_setup(dmadev->lldev);
 522         pm_runtime_mark_last_busy(dmadev->ddev.dev);
 523         pm_runtime_put_autosuspend(dmadev->ddev.dev);
 524         return rc;
 525 }
 526
 527 static void hidma_free_chan_resources(struct dma_chan *dmach)
 528 {
 529         struct hidma_chan *mchan = to_hidma_chan(dmach);
 530         struct hidma_dev *mdma = mchan->dmadev;
 531         struct hidma_desc *mdesc, *tmp;
 532         unsigned long irqflags;
 533         LIST_HEAD(descs);
 534
 535         /* terminate running transactions and free descriptors */
 536         hidma_terminate_channel(dmach);
 537
 538         spin_lock_irqsave(&mchan->lock, irqflags);
 539
 540         /* Move data */
 541         list_splice_tail_init(&mchan->free, &descs);
 542
 543         /* Free descriptors */
 544         list_for_each_entry_safe(mdesc, tmp, &descs, node) {
 545                 hidma_ll_free(mdma->lldev, mdesc->tre_ch);
 546                 list_del(&mdesc->node);
 547                 kfree(mdesc);
 548         }
 549
 550         mchan->allocated = 0;
 551         spin_unlock_irqrestore(&mchan->lock, irqflags);
 552 }
 553
 554 static int hidma_pause(struct dma_chan *chan)
 555 {
 556         struct hidma_chan *mchan;
 557         struct hidma_dev *dmadev;
 558
 559         mchan = to_hidma_chan(chan);
 560         dmadev = to_hidma_dev(mchan->chan.device);
 561         if (!mchan->paused) {
 562                 pm_runtime_get_sync(dmadev->ddev.dev);
 563                 if (hidma_ll_disable(dmadev->lldev))
 564                         dev_warn(dmadev->ddev.dev, "channel did not stop\n");
 565                 mchan->paused = true;
 566                 pm_runtime_mark_last_busy(dmadev->ddev.dev);
 567                 pm_runtime_put_autosuspend(dmadev->ddev.dev);
 568         }
 569         return 0;
 570 }
 571
 572 static int hidma_resume(struct dma_chan *chan)
 573 {
 574         struct hidma_chan *mchan;
 575         struct hidma_dev *dmadev;
 576         int rc = 0;
 577
 578         mchan = to_hidma_chan(chan);
 579         dmadev = to_hidma_dev(mchan->chan.device);
 580         if (mchan->paused) {
 581                 pm_runtime_get_sync(dmadev->ddev.dev);
 582                 rc = hidma_ll_enable(dmadev->lldev);
 583                 if (!rc)
 584                         mchan->paused = false;
 585                 else
 586                         dev_err(dmadev->ddev.dev,
 587                                 "failed to resume the channel");
 588                 pm_runtime_mark_last_busy(dmadev->ddev.dev);
 589                 pm_runtime_put_autosuspend(dmadev->ddev.dev);
 590         }
 591         return rc;
 592 }
 593
 594 static irqreturn_t hidma_chirq_handler(int chirq, void *arg)
 595 {
 596         struct hidma_lldev *lldev = arg;
 597
 598         /*
 599          * All interrupts are request driven.
 600          * HW doesn't send an interrupt by itself.
 601          */
 602         return hidma_ll_inthandler(chirq, lldev);
 603 }
 604
 605 #ifdef CONFIG_GENERIC_MSI_IRQ_DOMAIN
 606 static irqreturn_t hidma_chirq_handler_msi(int chirq, void *arg)
 607 {
 608         struct hidma_lldev **lldevp = arg;
 609         struct hidma_dev *dmadev = to_hidma_dev_from_lldev(lldevp);
 610
 611         return hidma_ll_inthandler_msi(chirq, *lldevp,
 612                                        1 << (chirq - dmadev->msi_virqbase));
 613 }
 614 #endif
 615
 616 static ssize_t hidma_show_values(struct device *dev,
 617                                  struct device_attribute *attr, char *buf)
 618 {
 619         struct hidma_dev *mdev = dev_get_drvdata(dev);
 620
 621         buf[0] = 0;
 622
 623         if (strcmp(attr->attr.name, "chid") == 0)
 624                 sprintf(buf, "%d\n", mdev->chidx);
 625
 626         return strlen(buf);
 627 }
 628
 629 static inline void  hidma_sysfs_uninit(struct hidma_dev *dev)
 630 {
 631         device_remove_file(dev->ddev.dev, dev->chid_attrs);
 632 }
 633
 634 static struct device_attribute*
 635 hidma_create_sysfs_entry(struct hidma_dev *dev, char *name, int mode)
 636 {
 637         struct device_attribute *attrs;
 638         char *name_copy;
 639
 640         attrs = devm_kmalloc(dev->ddev.dev, sizeof(struct device_attribute),
 641                              GFP_KERNEL);
 642         if (!attrs)
 643                 return NULL;
 644
 645         name_copy = devm_kstrdup(dev->ddev.dev, name, GFP_KERNEL);
 646         if (!name_copy)
 647                 return NULL;
 648
 649         attrs->attr.name = name_copy;
 650         attrs->attr.mode = mode;
 651         attrs->show = hidma_show_values;
 652         sysfs_attr_init(&attrs->attr);
 653
 654         return attrs;
 655 }
 656
 657 static int hidma_sysfs_init(struct hidma_dev *dev)
 658 {
 659         dev->chid_attrs = hidma_create_sysfs_entry(dev, "chid", S_IRUGO);
 660         if (!dev->chid_attrs)
 661                 return -ENOMEM;
 662
 663         return device_create_file(dev->ddev.dev, dev->chid_attrs);
 664 }
 665
 666 #ifdef CONFIG_GENERIC_MSI_IRQ_DOMAIN
 667 static void hidma_write_msi_msg(struct msi_desc *desc, struct msi_msg *msg)
 668 {
 669         struct device *dev = msi_desc_to_dev(desc);
 670         struct hidma_dev *dmadev = dev_get_drvdata(dev);
 671
 672         if (!desc->platform.msi_index) {
 673                 writel(msg->address_lo, dmadev->dev_evca + 0x118);
 674                 writel(msg->address_hi, dmadev->dev_evca + 0x11C);
 675                 writel(msg->data, dmadev->dev_evca + 0x120);
 676         }
 677 }
 678 #endif
 679
 680 static void hidma_free_msis(struct hidma_dev *dmadev)
 681 {
 682 #ifdef CONFIG_GENERIC_MSI_IRQ_DOMAIN
 683         struct device *dev = dmadev->ddev.dev;
 684         struct msi_desc *desc;
 685
 686         /* free allocated MSI interrupts above */
 687         for_each_msi_entry(desc, dev)
 688                 devm_free_irq(dev, desc->irq, &dmadev->lldev);
 689
 690         platform_msi_domain_free_irqs(dev);
 691 #endif
 692 }
 693
 694 static int hidma_request_msi(struct hidma_dev *dmadev,
 695                              struct platform_device *pdev)
 696 {
 697 #ifdef CONFIG_GENERIC_MSI_IRQ_DOMAIN
 698         int rc;
 699         struct msi_desc *desc;
 700         struct msi_desc *failed_desc = NULL;
 701
 702         rc = platform_msi_domain_alloc_irqs(&pdev->dev, HIDMA_MSI_INTS,
 703                                             hidma_write_msi_msg);
 704         if (rc)
 705                 return rc;
 706
 707         for_each_msi_entry(desc, &pdev->dev) {
 708                 if (!desc->platform.msi_index)
 709                         dmadev->msi_virqbase = desc->irq;
 710
 711                 rc = devm_request_irq(&pdev->dev, desc->irq,
 712                                        hidma_chirq_handler_msi,
 713                                        0, "qcom-hidma-msi",
 714                                        &dmadev->lldev);
 715                 if (rc) {
 716                         failed_desc = desc;
 717                         break;
 718                 }
 719         }
 720
 721         if (rc) {
 722                 /* free allocated MSI interrupts above */
 723                 for_each_msi_entry(desc, &pdev->dev) {
 724                         if (desc == failed_desc)
 725                                 break;
 726                         devm_free_irq(&pdev->dev, desc->irq,
 727                                       &dmadev->lldev);
 728                 }
 729         } else {
 730                 /* Add callback to free MSIs on teardown */
 731                 hidma_ll_setup_irq(dmadev->lldev, true);
 732
 733         }
 734         if (rc)
 735                 dev_warn(&pdev->dev,
 736                          "failed to request MSI irq, falling back to wired IRQ\n");
 737         return rc;
 738 #else
 739         return -EINVAL;
 740 #endif
 741 }
 742
 743 static bool hidma_test_capability(struct device *dev, enum hidma_cap test_cap)
 744 {
 745         enum hidma_cap cap;
 746
 747         cap = (enum hidma_cap) device_get_match_data(dev);
 748         return cap ? ((cap & test_cap) > 0) : 0;
 749 }
 750
 751 static int hidma_probe(struct platform_device *pdev)
 752 {
 753         struct hidma_dev *dmadev;
 754         struct resource *trca_resource;
 755         struct resource *evca_resource;
 756         int chirq;
 757         void __iomem *evca;
 758         void __iomem *trca;
 759         int rc;
 760         bool msi;
 761
 762         pm_runtime_set_autosuspend_delay(&pdev->dev, HIDMA_AUTOSUSPEND_TIMEOUT);
 763         pm_runtime_use_autosuspend(&pdev->dev);
 764         pm_runtime_set_active(&pdev->dev);
 765         pm_runtime_enable(&pdev->dev);
 766
 767         trca_resource = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 768         trca = devm_ioremap_resource(&pdev->dev, trca_resource);
 769         if (IS_ERR(trca)) {
 770                 rc = -ENOMEM;
 771                 goto bailout;
 772         }
 773
 774         evca_resource = platform_get_resource(pdev, IORESOURCE_MEM, 1);
 775         evca = devm_ioremap_resource(&pdev->dev, evca_resource);
 776         if (IS_ERR(evca)) {
 777                 rc = -ENOMEM;
 778                 goto bailout;
 779         }
 780
 781         /*
 782          * This driver only handles the channel IRQs.
 783          * Common IRQ is handled by the management driver.
 784          */
 785         chirq = platform_get_irq(pdev, 0);
 786         if (chirq < 0) {
 787                 rc = -ENODEV;
 788                 goto bailout;
 789         }
 790
 791         dmadev = devm_kzalloc(&pdev->dev, sizeof(*dmadev), GFP_KERNEL);
 792         if (!dmadev) {
 793                 rc = -ENOMEM;
 794                 goto bailout;
 795         }
 796
 797         INIT_LIST_HEAD(&dmadev->ddev.channels);
 798         spin_lock_init(&dmadev->lock);
 799         dmadev->ddev.dev = &pdev->dev;
 800         pm_runtime_get_sync(dmadev->ddev.dev);
 801
 802         dma_cap_set(DMA_MEMCPY, dmadev->ddev.cap_mask);
 803         dma_cap_set(DMA_MEMSET, dmadev->ddev.cap_mask);
 804         if (WARN_ON(!pdev->dev.dma_mask)) {
 805                 rc = -ENXIO;
 806                 goto dmafree;
 807         }
 808
 809         dmadev->dev_evca = evca;
 810         dmadev->evca_resource = evca_resource;
 811         dmadev->dev_trca = trca;
 812         dmadev->trca_resource = trca_resource;
 813         dmadev->ddev.device_prep_dma_memcpy = hidma_prep_dma_memcpy;
 814         dmadev->ddev.device_prep_dma_memset = hidma_prep_dma_memset;
 815         dmadev->ddev.device_alloc_chan_resources = hidma_alloc_chan_resources;
 816         dmadev->ddev.device_free_chan_resources = hidma_free_chan_resources;
 817         dmadev->ddev.device_tx_status = hidma_tx_status;
 818         dmadev->ddev.device_issue_pending = hidma_issue_pending;
 819         dmadev->ddev.device_pause = hidma_pause;
 820         dmadev->ddev.device_resume = hidma_resume;
 821         dmadev->ddev.device_terminate_all = hidma_terminate_all;
 822         dmadev->ddev.copy_align = 8;
 823
 824         /*
 825          * Determine the MSI capability of the platform. Old HW doesn't
 826          * support MSI.
 827          */
 828         msi = hidma_test_capability(&pdev->dev, HIDMA_MSI_CAP);
 829         device_property_read_u32(&pdev->dev, "desc-count",
 830                                  &dmadev->nr_descriptors);
 831
 832         if (nr_desc_prm) {
 833                 dev_info(&pdev->dev, "overriding number of descriptors as %d\n",
 834                          nr_desc_prm);
 835                 dmadev->nr_descriptors = nr_desc_prm;
 836         }
 837
 838         if (!dmadev->nr_descriptors)
 839                 dmadev->nr_descriptors = HIDMA_NR_DEFAULT_DESC;
 840
 841         if (hidma_test_capability(&pdev->dev, HIDMA_IDENTITY_CAP))
 842                 dmadev->chidx = readl(dmadev->dev_trca + 0x40);
 843         else
 844                 dmadev->chidx = readl(dmadev->dev_trca + 0x28);
 845
 846         /* Set DMA mask to 64 bits. */
 847         rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
 848         if (rc) {
 849                 dev_warn(&pdev->dev, "unable to set coherent mask to 64");
 850                 rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
 851                 if (rc)
 852                         goto dmafree;
 853         }
 854
 855         dmadev->lldev = hidma_ll_init(dmadev->ddev.dev,
 856                                       dmadev->nr_descriptors, dmadev->dev_trca,
 857                                       dmadev->dev_evca, dmadev->chidx);
 858         if (!dmadev->lldev) {
 859                 rc = -EPROBE_DEFER;
 860                 goto dmafree;
 861         }
 862
 863         platform_set_drvdata(pdev, dmadev);
 864         if (msi)
 865                 rc = hidma_request_msi(dmadev, pdev);
 866
 867         if (!msi || rc) {
 868                 hidma_ll_setup_irq(dmadev->lldev, false);
 869                 rc = devm_request_irq(&pdev->dev, chirq, hidma_chirq_handler,
 870                                       0, "qcom-hidma", dmadev->lldev);
 871                 if (rc)
 872                         goto uninit;
 873         }
 874
 875         INIT_LIST_HEAD(&dmadev->ddev.channels);
 876         rc = hidma_chan_init(dmadev, 0);
 877         if (rc)
 878                 goto uninit;
 879
 880         rc = dma_async_device_register(&dmadev->ddev);
 881         if (rc)
 882                 goto uninit;
 883
 884         dmadev->irq = chirq;
 885         tasklet_init(&dmadev->task, hidma_issue_task, (unsigned long)dmadev);
 886         hidma_debug_init(dmadev);
 887         hidma_sysfs_init(dmadev);
 888         dev_info(&pdev->dev, "HI-DMA engine driver registration complete\n");
 889         pm_runtime_mark_last_busy(dmadev->ddev.dev);
 890         pm_runtime_put_autosuspend(dmadev->ddev.dev);
 891         return 0;
 892
 893 uninit:
 894         if (msi)
 895                 hidma_free_msis(dmadev);
 896
 897         hidma_debug_uninit(dmadev);
 898         hidma_ll_uninit(dmadev->lldev);
 899 dmafree:
 900         if (dmadev)
 901                 hidma_free(dmadev);
 902 bailout:
 903         pm_runtime_put_sync(&pdev->dev);
 904         pm_runtime_disable(&pdev->dev);
 905         return rc;
 906 }
 907
 908 static void hidma_shutdown(struct platform_device *pdev)
 909 {
 910         struct hidma_dev *dmadev = platform_get_drvdata(pdev);
 911
 912         dev_info(dmadev->ddev.dev, "HI-DMA engine shutdown\n");
 913
 914         pm_runtime_get_sync(dmadev->ddev.dev);
 915         if (hidma_ll_disable(dmadev->lldev))
 916                 dev_warn(dmadev->ddev.dev, "channel did not stop\n");
 917         pm_runtime_mark_last_busy(dmadev->ddev.dev);
 918         pm_runtime_put_autosuspend(dmadev->ddev.dev);
 919
 920 }
 921
 922 static int hidma_remove(struct platform_device *pdev)
 923 {
 924         struct hidma_dev *dmadev = platform_get_drvdata(pdev);
 925
 926         pm_runtime_get_sync(dmadev->ddev.dev);
 927         dma_async_device_unregister(&dmadev->ddev);
 928         if (!dmadev->lldev->msi_support)
 929                 devm_free_irq(dmadev->ddev.dev, dmadev->irq, dmadev->lldev);
 930         else
 931                 hidma_free_msis(dmadev);
 932
 933         tasklet_kill(&dmadev->task);
 934         hidma_sysfs_uninit(dmadev);
 935         hidma_debug_uninit(dmadev);
 936         hidma_ll_uninit(dmadev->lldev);
 937         hidma_free(dmadev);
 938
 939         dev_info(&pdev->dev, "HI-DMA engine removed\n");
 940         pm_runtime_put_sync_suspend(&pdev->dev);
 941         pm_runtime_disable(&pdev->dev);
 942
 943         return 0;
 944 }
 945
 946 #if IS_ENABLED(CONFIG_ACPI)
 947 static const struct acpi_device_id hidma_acpi_ids[] = {
 948         {"QCOM8061"},
 949         {"QCOM8062", HIDMA_MSI_CAP},
 950         {"QCOM8063", (HIDMA_MSI_CAP | HIDMA_IDENTITY_CAP)},
 951         {},
 952 };
 953 MODULE_DEVICE_TABLE(acpi, hidma_acpi_ids);
 954 #endif
 955
 956 static const struct of_device_id hidma_match[] = {
 957         {.compatible = "qcom,hidma-1.0",},
 958         {.compatible = "qcom,hidma-1.1", .data = (void *)(HIDMA_MSI_CAP),},
 959         {.compatible = "qcom,hidma-1.2",
 960          .data = (void *)(HIDMA_MSI_CAP | HIDMA_IDENTITY_CAP),},
 961         {},
 962 };
 963 MODULE_DEVICE_TABLE(of, hidma_match);
 964
 965 static struct platform_driver hidma_driver = {
 966         .probe = hidma_probe,
 967         .remove = hidma_remove,
 968         .shutdown = hidma_shutdown,
 969         .driver = {
 970                    .name = "hidma",
 971                    .of_match_table = hidma_match,
 972                    .acpi_match_table = ACPI_PTR(hidma_acpi_ids),
 973         },
 974 };
 975
 976 module_platform_driver(hidma_driver);
 977 MODULE_LICENSE("GPL v2");