1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
6 * Copyright (C) 2010 Samsung Electronics Co. Ltd.
7 * Jaswinder Singh <jassi.brar@samsung.com>
10 #include <linux/debugfs.h>
11 #include <linux/kernel.h>
13 #include <linux/init.h>
14 #include <linux/slab.h>
15 #include <linux/module.h>
16 #include <linux/string.h>
17 #include <linux/delay.h>
18 #include <linux/interrupt.h>
19 #include <linux/dma-mapping.h>
20 #include <linux/dmaengine.h>
21 #include <linux/amba/bus.h>
22 #include <linux/scatterlist.h>
24 #include <linux/of_dma.h>
25 #include <linux/err.h>
26 #include <linux/pm_runtime.h>
27 #include <linux/bug.h>
29 #include "dmaengine.h"
30 #define PL330_MAX_CHAN 8
31 #define PL330_MAX_IRQS 32
32 #define PL330_MAX_PERI 32
33 #define PL330_MAX_BURST 16
35 #define PL330_QUIRK_BROKEN_NO_FLUSHP BIT(0)
37 enum pl330_cachectrl {
38 CCTRL0, /* Noncacheable and nonbufferable */
39 CCTRL1, /* Bufferable only */
40 CCTRL2, /* Cacheable, but do not allocate */
41 CCTRL3, /* Cacheable and bufferable, but do not allocate */
42 INVALID1, /* AWCACHE = 0x1000 */
44 CCTRL6, /* Cacheable write-through, allocate on writes only */
45 CCTRL7, /* Cacheable write-back, allocate on writes only */
56 /* Register and Bit field Definitions */
58 #define DS_ST_STOP 0x0
59 #define DS_ST_EXEC 0x1
60 #define DS_ST_CMISS 0x2
61 #define DS_ST_UPDTPC 0x3
63 #define DS_ST_ATBRR 0x5
64 #define DS_ST_QBUSY 0x6
66 #define DS_ST_KILL 0x8
67 #define DS_ST_CMPLT 0x9
68 #define DS_ST_FLTCMP 0xe
69 #define DS_ST_FAULT 0xf
74 #define INTSTATUS 0x28
81 #define FTC(n) (_FTC + (n)*0x4)
84 #define CS(n) (_CS + (n)*0x8)
85 #define CS_CNS (1 << 21)
88 #define CPC(n) (_CPC + (n)*0x8)
91 #define SA(n) (_SA + (n)*0x20)
94 #define DA(n) (_DA + (n)*0x20)
97 #define CC(n) (_CC + (n)*0x20)
99 #define CC_SRCINC (1 << 0)
100 #define CC_DSTINC (1 << 14)
101 #define CC_SRCPRI (1 << 8)
102 #define CC_DSTPRI (1 << 22)
103 #define CC_SRCNS (1 << 9)
104 #define CC_DSTNS (1 << 23)
105 #define CC_SRCIA (1 << 10)
106 #define CC_DSTIA (1 << 24)
107 #define CC_SRCBRSTLEN_SHFT 4
108 #define CC_DSTBRSTLEN_SHFT 18
109 #define CC_SRCBRSTSIZE_SHFT 1
110 #define CC_DSTBRSTSIZE_SHFT 15
111 #define CC_SRCCCTRL_SHFT 11
112 #define CC_SRCCCTRL_MASK 0x7
113 #define CC_DSTCCTRL_SHFT 25
114 #define CC_DRCCCTRL_MASK 0x7
115 #define CC_SWAP_SHFT 28
118 #define LC0(n) (_LC0 + (n)*0x20)
121 #define LC1(n) (_LC1 + (n)*0x20)
123 #define DBGSTATUS 0xd00
124 #define DBG_BUSY (1 << 0)
127 #define DBGINST0 0xd08
128 #define DBGINST1 0xd0c
137 #define PERIPH_ID 0xfe0
138 #define PERIPH_REV_SHIFT 20
139 #define PERIPH_REV_MASK 0xf
140 #define PERIPH_REV_R0P0 0
141 #define PERIPH_REV_R1P0 1
142 #define PERIPH_REV_R1P1 2
144 #define CR0_PERIPH_REQ_SET (1 << 0)
145 #define CR0_BOOT_EN_SET (1 << 1)
146 #define CR0_BOOT_MAN_NS (1 << 2)
147 #define CR0_NUM_CHANS_SHIFT 4
148 #define CR0_NUM_CHANS_MASK 0x7
149 #define CR0_NUM_PERIPH_SHIFT 12
150 #define CR0_NUM_PERIPH_MASK 0x1f
151 #define CR0_NUM_EVENTS_SHIFT 17
152 #define CR0_NUM_EVENTS_MASK 0x1f
154 #define CR1_ICACHE_LEN_SHIFT 0
155 #define CR1_ICACHE_LEN_MASK 0x7
156 #define CR1_NUM_ICACHELINES_SHIFT 4
157 #define CR1_NUM_ICACHELINES_MASK 0xf
159 #define CRD_DATA_WIDTH_SHIFT 0
160 #define CRD_DATA_WIDTH_MASK 0x7
161 #define CRD_WR_CAP_SHIFT 4
162 #define CRD_WR_CAP_MASK 0x7
163 #define CRD_WR_Q_DEP_SHIFT 8
164 #define CRD_WR_Q_DEP_MASK 0xf
165 #define CRD_RD_CAP_SHIFT 12
166 #define CRD_RD_CAP_MASK 0x7
167 #define CRD_RD_Q_DEP_SHIFT 16
168 #define CRD_RD_Q_DEP_MASK 0xf
169 #define CRD_DATA_BUFF_SHIFT 20
170 #define CRD_DATA_BUFF_MASK 0x3ff
173 #define DESIGNER 0x41
175 #define INTEG_CFG 0x0
176 #define PERIPH_ID_VAL ((PART << 0) | (DESIGNER << 12))
178 #define PL330_STATE_STOPPED (1 << 0)
179 #define PL330_STATE_EXECUTING (1 << 1)
180 #define PL330_STATE_WFE (1 << 2)
181 #define PL330_STATE_FAULTING (1 << 3)
182 #define PL330_STATE_COMPLETING (1 << 4)
183 #define PL330_STATE_WFP (1 << 5)
184 #define PL330_STATE_KILLING (1 << 6)
185 #define PL330_STATE_FAULT_COMPLETING (1 << 7)
186 #define PL330_STATE_CACHEMISS (1 << 8)
187 #define PL330_STATE_UPDTPC (1 << 9)
188 #define PL330_STATE_ATBARRIER (1 << 10)
189 #define PL330_STATE_QUEUEBUSY (1 << 11)
190 #define PL330_STATE_INVALID (1 << 15)
192 #define PL330_STABLE_STATES (PL330_STATE_STOPPED | PL330_STATE_EXECUTING \
193 | PL330_STATE_WFE | PL330_STATE_FAULTING)
195 #define CMD_DMAADDH 0x54
196 #define CMD_DMAEND 0x00
197 #define CMD_DMAFLUSHP 0x35
198 #define CMD_DMAGO 0xa0
199 #define CMD_DMALD 0x04
200 #define CMD_DMALDP 0x25
201 #define CMD_DMALP 0x20
202 #define CMD_DMALPEND 0x28
203 #define CMD_DMAKILL 0x01
204 #define CMD_DMAMOV 0xbc
205 #define CMD_DMANOP 0x18
206 #define CMD_DMARMB 0x12
207 #define CMD_DMASEV 0x34
208 #define CMD_DMAST 0x08
209 #define CMD_DMASTP 0x29
210 #define CMD_DMASTZ 0x0c
211 #define CMD_DMAWFE 0x36
212 #define CMD_DMAWFP 0x30
213 #define CMD_DMAWMB 0x13
217 #define SZ_DMAFLUSHP 2
221 #define SZ_DMALPEND 2
235 #define BRST_LEN(ccr) ((((ccr) >> CC_SRCBRSTLEN_SHFT) & 0xf) + 1)
236 #define BRST_SIZE(ccr) (1 << (((ccr) >> CC_SRCBRSTSIZE_SHFT) & 0x7))
238 #define BYTE_TO_BURST(b, ccr) ((b) / BRST_SIZE(ccr) / BRST_LEN(ccr))
239 #define BURST_TO_BYTE(c, ccr) ((c) * BRST_SIZE(ccr) * BRST_LEN(ccr))
242 * With 256 bytes, we can do more than 2.5MB and 5MB xfers per req
243 * at 1byte/burst for P<->M and M<->M respectively.
244 * For typical scenario, at 1word/burst, 10MB and 20MB xfers per req
245 * should be enough for P<->M and M<->M respectively.
247 #define MCODE_BUFF_PER_REQ 256
249 /* Use this _only_ to wait on transient states */
250 #define UNTIL(t, s) while (!(_state(t) & (s))) cpu_relax();
252 #ifdef PL330_DEBUG_MCGEN
253 static unsigned cmd_line;
254 #define PL330_DBGCMD_DUMP(off, x...) do { \
255 printk("%x:", cmd_line); \
259 #define PL330_DBGMC_START(addr) (cmd_line = addr)
261 #define PL330_DBGCMD_DUMP(off, x...) do {} while (0)
262 #define PL330_DBGMC_START(addr) do {} while (0)
265 /* The number of default descriptors */
267 #define NR_DEFAULT_DESC 16
269 /* Delay for runtime PM autosuspend, ms */
270 #define PL330_AUTOSUSPEND_DELAY 20
272 /* Populated by the PL330 core driver for DMA API driver's info */
273 struct pl330_config {
275 #define DMAC_MODE_NS (1 << 0)
277 unsigned int data_bus_width:10; /* In number of bits */
278 unsigned int data_buf_dep:11;
279 unsigned int num_chan:4;
280 unsigned int num_peri:6;
282 unsigned int num_events:6;
287 * Request Configuration.
288 * The PL330 core does not modify this and uses the last
289 * working configuration if the request doesn't provide any.
291 * The Client may want to provide this info only for the
292 * first request and a request with new settings.
294 struct pl330_reqcfg {
295 /* Address Incrementing */
300 * For now, the SRC & DST protection levels
301 * and burst size/length are assumed same.
307 unsigned brst_size:3; /* in power of 2 */
309 enum pl330_cachectrl dcctl;
310 enum pl330_cachectrl scctl;
311 enum pl330_byteswap swap;
312 struct pl330_config *pcfg;
316 * One cycle of DMAC operation.
317 * There may be more than one xfer in a request.
326 /* The xfer callbacks are made with one of these arguments. */
328 /* The all xfers in the request were success. */
330 /* If req aborted due to global error. */
332 /* If req failed due to problem with Channel. */
353 struct dma_pl330_desc;
358 struct dma_pl330_desc *desc;
361 /* ToBeDone for tasklet */
369 struct pl330_thread {
372 /* If the channel is not yet acquired by any client */
375 struct pl330_dmac *dmac;
376 /* Only two at a time */
377 struct _pl330_req req[2];
378 /* Index of the last enqueued request */
380 /* Index of the last submitted request or -1 if the DMA is stopped */
384 enum pl330_dmac_state {
391 /* In the DMAC pool */
394 * Allocated to some channel during prep_xxx
395 * Also may be sitting on the work_list.
399 * Sitting on the work_list and already submitted
400 * to the PL330 core. Not more than two descriptors
401 * of a channel can be BUSY at any time.
405 * Sitting on the channel work_list but xfer done
411 struct dma_pl330_chan {
412 /* Schedule desc completion */
413 struct tasklet_struct task;
415 /* DMA-Engine Channel */
416 struct dma_chan chan;
418 /* List of submitted descriptors */
419 struct list_head submitted_list;
420 /* List of issued descriptors */
421 struct list_head work_list;
422 /* List of completed descriptors */
423 struct list_head completed_list;
425 /* Pointer to the DMAC that manages this channel,
426 * NULL if the channel is available to be acquired.
427 * As the parent, this DMAC also provides descriptors
430 struct pl330_dmac *dmac;
432 /* To protect channel manipulation */
436 * Hardware channel thread of PL330 DMAC. NULL if the channel is
439 struct pl330_thread *thread;
441 /* For D-to-M and M-to-D channels */
442 int burst_sz; /* the peripheral fifo width */
443 int burst_len; /* the number of burst */
444 phys_addr_t fifo_addr;
445 /* DMA-mapped view of the FIFO; may differ if an IOMMU is present */
447 enum dma_data_direction dir;
448 struct dma_slave_config slave_config;
450 /* for cyclic capability */
453 /* for runtime pm tracking */
458 /* DMA-Engine Device */
459 struct dma_device ddma;
461 /* Holds info about sg limitations */
462 struct device_dma_parameters dma_parms;
464 /* Pool of descriptors available for the DMAC's channels */
465 struct list_head desc_pool;
466 /* To protect desc_pool manipulation */
467 spinlock_t pool_lock;
469 /* Size of MicroCode buffers for each channel. */
471 /* ioremap'ed address of PL330 registers. */
473 /* Populated by the PL330 core driver during pl330_add */
474 struct pl330_config pcfg;
477 /* Maximum possible events/irqs */
479 /* BUS address of MicroCode buffer */
480 dma_addr_t mcode_bus;
481 /* CPU address of MicroCode buffer */
483 /* List of all Channel threads */
484 struct pl330_thread *channels;
485 /* Pointer to the MANAGER thread */
486 struct pl330_thread *manager;
487 /* To handle bad news in interrupt */
488 struct tasklet_struct tasks;
489 struct _pl330_tbd dmac_tbd;
490 /* State of DMAC operation */
491 enum pl330_dmac_state state;
492 /* Holds list of reqs with due callbacks */
493 struct list_head req_done;
495 /* Peripheral channels connected to this DMAC */
496 unsigned int num_peripherals;
497 struct dma_pl330_chan *peripherals; /* keep at end */
501 static struct pl330_of_quirks {
506 .quirk = "arm,pl330-broken-no-flushp",
507 .id = PL330_QUIRK_BROKEN_NO_FLUSHP,
511 struct dma_pl330_desc {
512 /* To attach to a queue as child */
513 struct list_head node;
515 /* Descriptor for the DMA Engine API */
516 struct dma_async_tx_descriptor txd;
518 /* Xfer for PL330 core */
519 struct pl330_xfer px;
521 struct pl330_reqcfg rqcfg;
523 enum desc_status status;
528 /* The channel which currently holds this desc */
529 struct dma_pl330_chan *pchan;
531 enum dma_transfer_direction rqtype;
532 /* Index of peripheral for the xfer. */
534 /* Hook to attach to DMAC's list of reqs with due callback */
535 struct list_head rqd;
540 struct dma_pl330_desc *desc;
543 static int pl330_config_write(struct dma_chan *chan,
544 struct dma_slave_config *slave_config,
545 enum dma_transfer_direction direction);
547 static inline bool _queue_full(struct pl330_thread *thrd)
549 return thrd->req[0].desc != NULL && thrd->req[1].desc != NULL;
552 static inline bool is_manager(struct pl330_thread *thrd)
554 return thrd->dmac->manager == thrd;
557 /* If manager of the thread is in Non-Secure mode */
558 static inline bool _manager_ns(struct pl330_thread *thrd)
560 return (thrd->dmac->pcfg.mode & DMAC_MODE_NS) ? true : false;
563 static inline u32 get_revision(u32 periph_id)
565 return (periph_id >> PERIPH_REV_SHIFT) & PERIPH_REV_MASK;
568 static inline u32 _emit_END(unsigned dry_run, u8 buf[])
575 PL330_DBGCMD_DUMP(SZ_DMAEND, "\tDMAEND\n");
580 static inline u32 _emit_FLUSHP(unsigned dry_run, u8 buf[], u8 peri)
585 buf[0] = CMD_DMAFLUSHP;
591 PL330_DBGCMD_DUMP(SZ_DMAFLUSHP, "\tDMAFLUSHP %u\n", peri >> 3);
596 static inline u32 _emit_LD(unsigned dry_run, u8 buf[], enum pl330_cond cond)
604 buf[0] |= (0 << 1) | (1 << 0);
605 else if (cond == BURST)
606 buf[0] |= (1 << 1) | (1 << 0);
608 PL330_DBGCMD_DUMP(SZ_DMALD, "\tDMALD%c\n",
609 cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'A'));
614 static inline u32 _emit_LDP(unsigned dry_run, u8 buf[],
615 enum pl330_cond cond, u8 peri)
629 PL330_DBGCMD_DUMP(SZ_DMALDP, "\tDMALDP%c %u\n",
630 cond == SINGLE ? 'S' : 'B', peri >> 3);
635 static inline u32 _emit_LP(unsigned dry_run, u8 buf[],
636 unsigned loop, u8 cnt)
646 cnt--; /* DMAC increments by 1 internally */
649 PL330_DBGCMD_DUMP(SZ_DMALP, "\tDMALP_%c %u\n", loop ? '1' : '0', cnt);
655 enum pl330_cond cond;
661 static inline u32 _emit_LPEND(unsigned dry_run, u8 buf[],
662 const struct _arg_LPEND *arg)
664 enum pl330_cond cond = arg->cond;
665 bool forever = arg->forever;
666 unsigned loop = arg->loop;
667 u8 bjump = arg->bjump;
672 buf[0] = CMD_DMALPEND;
681 buf[0] |= (0 << 1) | (1 << 0);
682 else if (cond == BURST)
683 buf[0] |= (1 << 1) | (1 << 0);
687 PL330_DBGCMD_DUMP(SZ_DMALPEND, "\tDMALP%s%c_%c bjmpto_%x\n",
688 forever ? "FE" : "END",
689 cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'A'),
696 static inline u32 _emit_KILL(unsigned dry_run, u8 buf[])
701 buf[0] = CMD_DMAKILL;
706 static inline u32 _emit_MOV(unsigned dry_run, u8 buf[],
707 enum dmamov_dst dst, u32 val)
719 PL330_DBGCMD_DUMP(SZ_DMAMOV, "\tDMAMOV %s 0x%x\n",
720 dst == SAR ? "SAR" : (dst == DAR ? "DAR" : "CCR"), val);
725 static inline u32 _emit_RMB(unsigned dry_run, u8 buf[])
732 PL330_DBGCMD_DUMP(SZ_DMARMB, "\tDMARMB\n");
737 static inline u32 _emit_SEV(unsigned dry_run, u8 buf[], u8 ev)
748 PL330_DBGCMD_DUMP(SZ_DMASEV, "\tDMASEV %u\n", ev >> 3);
753 static inline u32 _emit_ST(unsigned dry_run, u8 buf[], enum pl330_cond cond)
761 buf[0] |= (0 << 1) | (1 << 0);
762 else if (cond == BURST)
763 buf[0] |= (1 << 1) | (1 << 0);
765 PL330_DBGCMD_DUMP(SZ_DMAST, "\tDMAST%c\n",
766 cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'A'));
771 static inline u32 _emit_STP(unsigned dry_run, u8 buf[],
772 enum pl330_cond cond, u8 peri)
786 PL330_DBGCMD_DUMP(SZ_DMASTP, "\tDMASTP%c %u\n",
787 cond == SINGLE ? 'S' : 'B', peri >> 3);
792 static inline u32 _emit_WFP(unsigned dry_run, u8 buf[],
793 enum pl330_cond cond, u8 peri)
801 buf[0] |= (0 << 1) | (0 << 0);
802 else if (cond == BURST)
803 buf[0] |= (1 << 1) | (0 << 0);
805 buf[0] |= (0 << 1) | (1 << 0);
811 PL330_DBGCMD_DUMP(SZ_DMAWFP, "\tDMAWFP%c %u\n",
812 cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'P'), peri >> 3);
817 static inline u32 _emit_WMB(unsigned dry_run, u8 buf[])
824 PL330_DBGCMD_DUMP(SZ_DMAWMB, "\tDMAWMB\n");
835 static inline u32 _emit_GO(unsigned dry_run, u8 buf[],
836 const struct _arg_GO *arg)
839 u32 addr = arg->addr;
840 unsigned ns = arg->ns;
856 #define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t)
858 /* Returns Time-Out */
859 static bool _until_dmac_idle(struct pl330_thread *thrd)
861 void __iomem *regs = thrd->dmac->base;
862 unsigned long loops = msecs_to_loops(5);
865 /* Until Manager is Idle */
866 if (!(readl(regs + DBGSTATUS) & DBG_BUSY))
878 static inline void _execute_DBGINSN(struct pl330_thread *thrd,
879 u8 insn[], bool as_manager)
881 void __iomem *regs = thrd->dmac->base;
884 val = (insn[0] << 16) | (insn[1] << 24);
887 val |= (thrd->id << 8); /* Channel Number */
889 writel(val, regs + DBGINST0);
891 val = le32_to_cpu(*((__le32 *)&insn[2]));
892 writel(val, regs + DBGINST1);
894 /* If timed out due to halted state-machine */
895 if (_until_dmac_idle(thrd)) {
896 dev_err(thrd->dmac->ddma.dev, "DMAC halted!\n");
901 writel(0, regs + DBGCMD);
904 static inline u32 _state(struct pl330_thread *thrd)
906 void __iomem *regs = thrd->dmac->base;
909 if (is_manager(thrd))
910 val = readl(regs + DS) & 0xf;
912 val = readl(regs + CS(thrd->id)) & 0xf;
916 return PL330_STATE_STOPPED;
918 return PL330_STATE_EXECUTING;
920 return PL330_STATE_CACHEMISS;
922 return PL330_STATE_UPDTPC;
924 return PL330_STATE_WFE;
926 return PL330_STATE_FAULTING;
928 if (is_manager(thrd))
929 return PL330_STATE_INVALID;
931 return PL330_STATE_ATBARRIER;
933 if (is_manager(thrd))
934 return PL330_STATE_INVALID;
936 return PL330_STATE_QUEUEBUSY;
938 if (is_manager(thrd))
939 return PL330_STATE_INVALID;
941 return PL330_STATE_WFP;
943 if (is_manager(thrd))
944 return PL330_STATE_INVALID;
946 return PL330_STATE_KILLING;
948 if (is_manager(thrd))
949 return PL330_STATE_INVALID;
951 return PL330_STATE_COMPLETING;
953 if (is_manager(thrd))
954 return PL330_STATE_INVALID;
956 return PL330_STATE_FAULT_COMPLETING;
958 return PL330_STATE_INVALID;
962 static void _stop(struct pl330_thread *thrd)
964 void __iomem *regs = thrd->dmac->base;
965 u8 insn[6] = {0, 0, 0, 0, 0, 0};
966 u32 inten = readl(regs + INTEN);
968 if (_state(thrd) == PL330_STATE_FAULT_COMPLETING)
969 UNTIL(thrd, PL330_STATE_FAULTING | PL330_STATE_KILLING);
971 /* Return if nothing needs to be done */
972 if (_state(thrd) == PL330_STATE_COMPLETING
973 || _state(thrd) == PL330_STATE_KILLING
974 || _state(thrd) == PL330_STATE_STOPPED)
979 _execute_DBGINSN(thrd, insn, is_manager(thrd));
981 /* clear the event */
982 if (inten & (1 << thrd->ev))
983 writel(1 << thrd->ev, regs + INTCLR);
984 /* Stop generating interrupts for SEV */
985 writel(inten & ~(1 << thrd->ev), regs + INTEN);
988 /* Start doing req 'idx' of thread 'thrd' */
989 static bool _trigger(struct pl330_thread *thrd)
991 void __iomem *regs = thrd->dmac->base;
992 struct _pl330_req *req;
993 struct dma_pl330_desc *desc;
996 u8 insn[6] = {0, 0, 0, 0, 0, 0};
999 /* Return if already ACTIVE */
1000 if (_state(thrd) != PL330_STATE_STOPPED)
1003 idx = 1 - thrd->lstenq;
1004 if (thrd->req[idx].desc != NULL) {
1005 req = &thrd->req[idx];
1008 if (thrd->req[idx].desc != NULL)
1009 req = &thrd->req[idx];
1014 /* Return if no request */
1018 /* Return if req is running */
1019 if (idx == thrd->req_running)
1024 ns = desc->rqcfg.nonsecure ? 1 : 0;
1026 /* See 'Abort Sources' point-4 at Page 2-25 */
1027 if (_manager_ns(thrd) && !ns)
1028 dev_info(thrd->dmac->ddma.dev, "%s:%d Recipe for ABORT!\n",
1029 __func__, __LINE__);
1032 go.addr = req->mc_bus;
1034 _emit_GO(0, insn, &go);
1036 /* Set to generate interrupts for SEV */
1037 writel(readl(regs + INTEN) | (1 << thrd->ev), regs + INTEN);
1039 /* Only manager can execute GO */
1040 _execute_DBGINSN(thrd, insn, true);
1042 thrd->req_running = idx;
1047 static bool _start(struct pl330_thread *thrd)
1049 switch (_state(thrd)) {
1050 case PL330_STATE_FAULT_COMPLETING:
1051 UNTIL(thrd, PL330_STATE_FAULTING | PL330_STATE_KILLING);
1053 if (_state(thrd) == PL330_STATE_KILLING)
1054 UNTIL(thrd, PL330_STATE_STOPPED)
1057 case PL330_STATE_FAULTING:
1061 case PL330_STATE_KILLING:
1062 case PL330_STATE_COMPLETING:
1063 UNTIL(thrd, PL330_STATE_STOPPED)
1066 case PL330_STATE_STOPPED:
1067 return _trigger(thrd);
1069 case PL330_STATE_WFP:
1070 case PL330_STATE_QUEUEBUSY:
1071 case PL330_STATE_ATBARRIER:
1072 case PL330_STATE_UPDTPC:
1073 case PL330_STATE_CACHEMISS:
1074 case PL330_STATE_EXECUTING:
1077 case PL330_STATE_WFE: /* For RESUME, nothing yet */
1083 static inline int _ldst_memtomem(unsigned dry_run, u8 buf[],
1084 const struct _xfer_spec *pxs, int cyc)
1087 struct pl330_config *pcfg = pxs->desc->rqcfg.pcfg;
1089 /* check lock-up free version */
1090 if (get_revision(pcfg->periph_id) >= PERIPH_REV_R1P0) {
1092 off += _emit_LD(dry_run, &buf[off], ALWAYS);
1093 off += _emit_ST(dry_run, &buf[off], ALWAYS);
1097 off += _emit_LD(dry_run, &buf[off], ALWAYS);
1098 off += _emit_RMB(dry_run, &buf[off]);
1099 off += _emit_ST(dry_run, &buf[off], ALWAYS);
1100 off += _emit_WMB(dry_run, &buf[off]);
1107 static u32 _emit_load(unsigned int dry_run, u8 buf[],
1108 enum pl330_cond cond, enum dma_transfer_direction direction,
1113 switch (direction) {
1114 case DMA_MEM_TO_MEM:
1116 case DMA_MEM_TO_DEV:
1117 off += _emit_LD(dry_run, &buf[off], cond);
1120 case DMA_DEV_TO_MEM:
1121 if (cond == ALWAYS) {
1122 off += _emit_LDP(dry_run, &buf[off], SINGLE,
1124 off += _emit_LDP(dry_run, &buf[off], BURST,
1127 off += _emit_LDP(dry_run, &buf[off], cond,
1133 /* this code should be unreachable */
1141 static inline u32 _emit_store(unsigned int dry_run, u8 buf[],
1142 enum pl330_cond cond, enum dma_transfer_direction direction,
1147 switch (direction) {
1148 case DMA_MEM_TO_MEM:
1150 case DMA_DEV_TO_MEM:
1151 off += _emit_ST(dry_run, &buf[off], cond);
1154 case DMA_MEM_TO_DEV:
1155 if (cond == ALWAYS) {
1156 off += _emit_STP(dry_run, &buf[off], SINGLE,
1158 off += _emit_STP(dry_run, &buf[off], BURST,
1161 off += _emit_STP(dry_run, &buf[off], cond,
1167 /* this code should be unreachable */
1175 static inline int _ldst_peripheral(struct pl330_dmac *pl330,
1176 unsigned dry_run, u8 buf[],
1177 const struct _xfer_spec *pxs, int cyc,
1178 enum pl330_cond cond)
1182 if (pl330->quirks & PL330_QUIRK_BROKEN_NO_FLUSHP)
1186 * do FLUSHP at beginning to clear any stale dma requests before the
1189 if (!(pl330->quirks & PL330_QUIRK_BROKEN_NO_FLUSHP))
1190 off += _emit_FLUSHP(dry_run, &buf[off], pxs->desc->peri);
1192 off += _emit_WFP(dry_run, &buf[off], cond, pxs->desc->peri);
1193 off += _emit_load(dry_run, &buf[off], cond, pxs->desc->rqtype,
1195 off += _emit_store(dry_run, &buf[off], cond, pxs->desc->rqtype,
1202 static int _bursts(struct pl330_dmac *pl330, unsigned dry_run, u8 buf[],
1203 const struct _xfer_spec *pxs, int cyc)
1206 enum pl330_cond cond = BRST_LEN(pxs->ccr) > 1 ? BURST : SINGLE;
1208 switch (pxs->desc->rqtype) {
1209 case DMA_MEM_TO_DEV:
1211 case DMA_DEV_TO_MEM:
1212 off += _ldst_peripheral(pl330, dry_run, &buf[off], pxs, cyc,
1216 case DMA_MEM_TO_MEM:
1217 off += _ldst_memtomem(dry_run, &buf[off], pxs, cyc);
1221 /* this code should be unreachable */
1230 * transfer dregs with single transfers to peripheral, or a reduced size burst
1233 static int _dregs(struct pl330_dmac *pl330, unsigned int dry_run, u8 buf[],
1234 const struct _xfer_spec *pxs, int transfer_length)
1239 if (transfer_length == 0)
1242 switch (pxs->desc->rqtype) {
1243 case DMA_MEM_TO_DEV:
1245 case DMA_DEV_TO_MEM:
1246 off += _ldst_peripheral(pl330, dry_run, &buf[off], pxs,
1247 transfer_length, SINGLE);
1250 case DMA_MEM_TO_MEM:
1251 dregs_ccr = pxs->ccr;
1252 dregs_ccr &= ~((0xf << CC_SRCBRSTLEN_SHFT) |
1253 (0xf << CC_DSTBRSTLEN_SHFT));
1254 dregs_ccr |= (((transfer_length - 1) & 0xf) <<
1255 CC_SRCBRSTLEN_SHFT);
1256 dregs_ccr |= (((transfer_length - 1) & 0xf) <<
1257 CC_DSTBRSTLEN_SHFT);
1258 off += _emit_MOV(dry_run, &buf[off], CCR, dregs_ccr);
1259 off += _ldst_memtomem(dry_run, &buf[off], pxs, 1);
1263 /* this code should be unreachable */
1271 /* Returns bytes consumed and updates bursts */
1272 static inline int _loop(struct pl330_dmac *pl330, unsigned dry_run, u8 buf[],
1273 unsigned long *bursts, const struct _xfer_spec *pxs)
1275 int cyc, cycmax, szlp, szlpend, szbrst, off;
1276 unsigned lcnt0, lcnt1, ljmp0, ljmp1;
1277 struct _arg_LPEND lpend;
1280 return _bursts(pl330, dry_run, buf, pxs, 1);
1282 /* Max iterations possible in DMALP is 256 */
1283 if (*bursts >= 256*256) {
1286 cyc = *bursts / lcnt1 / lcnt0;
1287 } else if (*bursts > 256) {
1289 lcnt0 = *bursts / lcnt1;
1297 szlp = _emit_LP(1, buf, 0, 0);
1298 szbrst = _bursts(pl330, 1, buf, pxs, 1);
1300 lpend.cond = ALWAYS;
1301 lpend.forever = false;
1304 szlpend = _emit_LPEND(1, buf, &lpend);
1312 * Max bursts that we can unroll due to limit on the
1313 * size of backward jump that can be encoded in DMALPEND
1314 * which is 8-bits and hence 255
1316 cycmax = (255 - (szlp + szlpend)) / szbrst;
1318 cyc = (cycmax < cyc) ? cycmax : cyc;
1323 off += _emit_LP(dry_run, &buf[off], 0, lcnt0);
1327 off += _emit_LP(dry_run, &buf[off], 1, lcnt1);
1330 off += _bursts(pl330, dry_run, &buf[off], pxs, cyc);
1332 lpend.cond = ALWAYS;
1333 lpend.forever = false;
1335 lpend.bjump = off - ljmp1;
1336 off += _emit_LPEND(dry_run, &buf[off], &lpend);
1339 lpend.cond = ALWAYS;
1340 lpend.forever = false;
1342 lpend.bjump = off - ljmp0;
1343 off += _emit_LPEND(dry_run, &buf[off], &lpend);
1346 *bursts = lcnt1 * cyc;
1353 static inline int _setup_loops(struct pl330_dmac *pl330,
1354 unsigned dry_run, u8 buf[],
1355 const struct _xfer_spec *pxs)
1357 struct pl330_xfer *x = &pxs->desc->px;
1359 unsigned long c, bursts = BYTE_TO_BURST(x->bytes, ccr);
1360 int num_dregs = (x->bytes - BURST_TO_BYTE(bursts, ccr)) /
1366 off += _loop(pl330, dry_run, &buf[off], &c, pxs);
1369 off += _dregs(pl330, dry_run, &buf[off], pxs, num_dregs);
1374 static inline int _setup_xfer(struct pl330_dmac *pl330,
1375 unsigned dry_run, u8 buf[],
1376 const struct _xfer_spec *pxs)
1378 struct pl330_xfer *x = &pxs->desc->px;
1381 /* DMAMOV SAR, x->src_addr */
1382 off += _emit_MOV(dry_run, &buf[off], SAR, x->src_addr);
1383 /* DMAMOV DAR, x->dst_addr */
1384 off += _emit_MOV(dry_run, &buf[off], DAR, x->dst_addr);
1387 off += _setup_loops(pl330, dry_run, &buf[off], pxs);
1393 * A req is a sequence of one or more xfer units.
1394 * Returns the number of bytes taken to setup the MC for the req.
1396 static int _setup_req(struct pl330_dmac *pl330, unsigned dry_run,
1397 struct pl330_thread *thrd, unsigned index,
1398 struct _xfer_spec *pxs)
1400 struct _pl330_req *req = &thrd->req[index];
1401 u8 *buf = req->mc_cpu;
1404 PL330_DBGMC_START(req->mc_bus);
1406 /* DMAMOV CCR, ccr */
1407 off += _emit_MOV(dry_run, &buf[off], CCR, pxs->ccr);
1409 off += _setup_xfer(pl330, dry_run, &buf[off], pxs);
1411 /* DMASEV peripheral/event */
1412 off += _emit_SEV(dry_run, &buf[off], thrd->ev);
1414 off += _emit_END(dry_run, &buf[off]);
1419 static inline u32 _prepare_ccr(const struct pl330_reqcfg *rqc)
1429 /* We set same protection levels for Src and DST for now */
1430 if (rqc->privileged)
1431 ccr |= CC_SRCPRI | CC_DSTPRI;
1433 ccr |= CC_SRCNS | CC_DSTNS;
1434 if (rqc->insnaccess)
1435 ccr |= CC_SRCIA | CC_DSTIA;
1437 ccr |= (((rqc->brst_len - 1) & 0xf) << CC_SRCBRSTLEN_SHFT);
1438 ccr |= (((rqc->brst_len - 1) & 0xf) << CC_DSTBRSTLEN_SHFT);
1440 ccr |= (rqc->brst_size << CC_SRCBRSTSIZE_SHFT);
1441 ccr |= (rqc->brst_size << CC_DSTBRSTSIZE_SHFT);
1443 ccr |= (rqc->scctl << CC_SRCCCTRL_SHFT);
1444 ccr |= (rqc->dcctl << CC_DSTCCTRL_SHFT);
1446 ccr |= (rqc->swap << CC_SWAP_SHFT);
1452 * Submit a list of xfers after which the client wants notification.
1453 * Client is not notified after each xfer unit, just once after all
1454 * xfer units are done or some error occurs.
1456 static int pl330_submit_req(struct pl330_thread *thrd,
1457 struct dma_pl330_desc *desc)
1459 struct pl330_dmac *pl330 = thrd->dmac;
1460 struct _xfer_spec xs;
1461 unsigned long flags;
1466 switch (desc->rqtype) {
1467 case DMA_MEM_TO_DEV:
1470 case DMA_DEV_TO_MEM:
1473 case DMA_MEM_TO_MEM:
1480 if (pl330->state == DYING
1481 || pl330->dmac_tbd.reset_chan & (1 << thrd->id)) {
1482 dev_info(thrd->dmac->ddma.dev, "%s:%d\n",
1483 __func__, __LINE__);
1487 /* If request for non-existing peripheral */
1488 if (desc->rqtype != DMA_MEM_TO_MEM &&
1489 desc->peri >= pl330->pcfg.num_peri) {
1490 dev_info(thrd->dmac->ddma.dev,
1491 "%s:%d Invalid peripheral(%u)!\n",
1492 __func__, __LINE__, desc->peri);
1496 spin_lock_irqsave(&pl330->lock, flags);
1498 if (_queue_full(thrd)) {
1503 /* Prefer Secure Channel */
1504 if (!_manager_ns(thrd))
1505 desc->rqcfg.nonsecure = 0;
1507 desc->rqcfg.nonsecure = 1;
1509 ccr = _prepare_ccr(&desc->rqcfg);
1511 idx = thrd->req[0].desc == NULL ? 0 : 1;
1516 /* First dry run to check if req is acceptable */
1517 ret = _setup_req(pl330, 1, thrd, idx, &xs);
1521 if (ret > pl330->mcbufsz / 2) {
1522 dev_info(pl330->ddma.dev, "%s:%d Try increasing mcbufsz (%i/%i)\n",
1523 __func__, __LINE__, ret, pl330->mcbufsz / 2);
1528 /* Hook the request */
1530 thrd->req[idx].desc = desc;
1531 _setup_req(pl330, 0, thrd, idx, &xs);
1536 spin_unlock_irqrestore(&pl330->lock, flags);
1541 static void dma_pl330_rqcb(struct dma_pl330_desc *desc, enum pl330_op_err err)
1543 struct dma_pl330_chan *pch;
1544 unsigned long flags;
1551 /* If desc aborted */
1555 spin_lock_irqsave(&pch->lock, flags);
1557 desc->status = DONE;
1559 spin_unlock_irqrestore(&pch->lock, flags);
1561 tasklet_schedule(&pch->task);
1564 static void pl330_dotask(unsigned long data)
1566 struct pl330_dmac *pl330 = (struct pl330_dmac *) data;
1567 unsigned long flags;
1570 spin_lock_irqsave(&pl330->lock, flags);
1572 /* The DMAC itself gone nuts */
1573 if (pl330->dmac_tbd.reset_dmac) {
1574 pl330->state = DYING;
1575 /* Reset the manager too */
1576 pl330->dmac_tbd.reset_mngr = true;
1577 /* Clear the reset flag */
1578 pl330->dmac_tbd.reset_dmac = false;
1581 if (pl330->dmac_tbd.reset_mngr) {
1582 _stop(pl330->manager);
1583 /* Reset all channels */
1584 pl330->dmac_tbd.reset_chan = (1 << pl330->pcfg.num_chan) - 1;
1585 /* Clear the reset flag */
1586 pl330->dmac_tbd.reset_mngr = false;
1589 for (i = 0; i < pl330->pcfg.num_chan; i++) {
1591 if (pl330->dmac_tbd.reset_chan & (1 << i)) {
1592 struct pl330_thread *thrd = &pl330->channels[i];
1593 void __iomem *regs = pl330->base;
1594 enum pl330_op_err err;
1598 if (readl(regs + FSC) & (1 << thrd->id))
1599 err = PL330_ERR_FAIL;
1601 err = PL330_ERR_ABORT;
1603 spin_unlock_irqrestore(&pl330->lock, flags);
1604 dma_pl330_rqcb(thrd->req[1 - thrd->lstenq].desc, err);
1605 dma_pl330_rqcb(thrd->req[thrd->lstenq].desc, err);
1606 spin_lock_irqsave(&pl330->lock, flags);
1608 thrd->req[0].desc = NULL;
1609 thrd->req[1].desc = NULL;
1610 thrd->req_running = -1;
1612 /* Clear the reset flag */
1613 pl330->dmac_tbd.reset_chan &= ~(1 << i);
1617 spin_unlock_irqrestore(&pl330->lock, flags);
1622 /* Returns 1 if state was updated, 0 otherwise */
1623 static int pl330_update(struct pl330_dmac *pl330)
1625 struct dma_pl330_desc *descdone;
1626 unsigned long flags;
1629 int id, ev, ret = 0;
1633 spin_lock_irqsave(&pl330->lock, flags);
1635 val = readl(regs + FSM) & 0x1;
1637 pl330->dmac_tbd.reset_mngr = true;
1639 pl330->dmac_tbd.reset_mngr = false;
1641 val = readl(regs + FSC) & ((1 << pl330->pcfg.num_chan) - 1);
1642 pl330->dmac_tbd.reset_chan |= val;
1645 while (i < pl330->pcfg.num_chan) {
1646 if (val & (1 << i)) {
1647 dev_info(pl330->ddma.dev,
1648 "Reset Channel-%d\t CS-%x FTC-%x\n",
1649 i, readl(regs + CS(i)),
1650 readl(regs + FTC(i)));
1651 _stop(&pl330->channels[i]);
1657 /* Check which event happened i.e, thread notified */
1658 val = readl(regs + ES);
1659 if (pl330->pcfg.num_events < 32
1660 && val & ~((1 << pl330->pcfg.num_events) - 1)) {
1661 pl330->dmac_tbd.reset_dmac = true;
1662 dev_err(pl330->ddma.dev, "%s:%d Unexpected!\n", __func__,
1668 for (ev = 0; ev < pl330->pcfg.num_events; ev++) {
1669 if (val & (1 << ev)) { /* Event occurred */
1670 struct pl330_thread *thrd;
1671 u32 inten = readl(regs + INTEN);
1674 /* Clear the event */
1675 if (inten & (1 << ev))
1676 writel(1 << ev, regs + INTCLR);
1680 id = pl330->events[ev];
1682 thrd = &pl330->channels[id];
1684 active = thrd->req_running;
1685 if (active == -1) /* Aborted */
1688 /* Detach the req */
1689 descdone = thrd->req[active].desc;
1690 thrd->req[active].desc = NULL;
1692 thrd->req_running = -1;
1694 /* Get going again ASAP */
1697 /* For now, just make a list of callbacks to be done */
1698 list_add_tail(&descdone->rqd, &pl330->req_done);
1702 /* Now that we are in no hurry, do the callbacks */
1703 while (!list_empty(&pl330->req_done)) {
1704 descdone = list_first_entry(&pl330->req_done,
1705 struct dma_pl330_desc, rqd);
1706 list_del(&descdone->rqd);
1707 spin_unlock_irqrestore(&pl330->lock, flags);
1708 dma_pl330_rqcb(descdone, PL330_ERR_NONE);
1709 spin_lock_irqsave(&pl330->lock, flags);
1713 spin_unlock_irqrestore(&pl330->lock, flags);
1715 if (pl330->dmac_tbd.reset_dmac
1716 || pl330->dmac_tbd.reset_mngr
1717 || pl330->dmac_tbd.reset_chan) {
1719 tasklet_schedule(&pl330->tasks);
1725 /* Reserve an event */
1726 static inline int _alloc_event(struct pl330_thread *thrd)
1728 struct pl330_dmac *pl330 = thrd->dmac;
1731 for (ev = 0; ev < pl330->pcfg.num_events; ev++)
1732 if (pl330->events[ev] == -1) {
1733 pl330->events[ev] = thrd->id;
1740 static bool _chan_ns(const struct pl330_dmac *pl330, int i)
1742 return pl330->pcfg.irq_ns & (1 << i);
1745 /* Upon success, returns IdentityToken for the
1746 * allocated channel, NULL otherwise.
1748 static struct pl330_thread *pl330_request_channel(struct pl330_dmac *pl330)
1750 struct pl330_thread *thrd = NULL;
1753 if (pl330->state == DYING)
1756 chans = pl330->pcfg.num_chan;
1758 for (i = 0; i < chans; i++) {
1759 thrd = &pl330->channels[i];
1760 if ((thrd->free) && (!_manager_ns(thrd) ||
1761 _chan_ns(pl330, i))) {
1762 thrd->ev = _alloc_event(thrd);
1763 if (thrd->ev >= 0) {
1766 thrd->req[0].desc = NULL;
1767 thrd->req[1].desc = NULL;
1768 thrd->req_running = -1;
1778 /* Release an event */
1779 static inline void _free_event(struct pl330_thread *thrd, int ev)
1781 struct pl330_dmac *pl330 = thrd->dmac;
1783 /* If the event is valid and was held by the thread */
1784 if (ev >= 0 && ev < pl330->pcfg.num_events
1785 && pl330->events[ev] == thrd->id)
1786 pl330->events[ev] = -1;
1789 static void pl330_release_channel(struct pl330_thread *thrd)
1791 if (!thrd || thrd->free)
1796 dma_pl330_rqcb(thrd->req[1 - thrd->lstenq].desc, PL330_ERR_ABORT);
1797 dma_pl330_rqcb(thrd->req[thrd->lstenq].desc, PL330_ERR_ABORT);
1799 _free_event(thrd, thrd->ev);
1803 /* Initialize the structure for PL330 configuration, that can be used
1804 * by the client driver the make best use of the DMAC
1806 static void read_dmac_config(struct pl330_dmac *pl330)
1808 void __iomem *regs = pl330->base;
1811 val = readl(regs + CRD) >> CRD_DATA_WIDTH_SHIFT;
1812 val &= CRD_DATA_WIDTH_MASK;
1813 pl330->pcfg.data_bus_width = 8 * (1 << val);
1815 val = readl(regs + CRD) >> CRD_DATA_BUFF_SHIFT;
1816 val &= CRD_DATA_BUFF_MASK;
1817 pl330->pcfg.data_buf_dep = val + 1;
1819 val = readl(regs + CR0) >> CR0_NUM_CHANS_SHIFT;
1820 val &= CR0_NUM_CHANS_MASK;
1822 pl330->pcfg.num_chan = val;
1824 val = readl(regs + CR0);
1825 if (val & CR0_PERIPH_REQ_SET) {
1826 val = (val >> CR0_NUM_PERIPH_SHIFT) & CR0_NUM_PERIPH_MASK;
1828 pl330->pcfg.num_peri = val;
1829 pl330->pcfg.peri_ns = readl(regs + CR4);
1831 pl330->pcfg.num_peri = 0;
1834 val = readl(regs + CR0);
1835 if (val & CR0_BOOT_MAN_NS)
1836 pl330->pcfg.mode |= DMAC_MODE_NS;
1838 pl330->pcfg.mode &= ~DMAC_MODE_NS;
1840 val = readl(regs + CR0) >> CR0_NUM_EVENTS_SHIFT;
1841 val &= CR0_NUM_EVENTS_MASK;
1843 pl330->pcfg.num_events = val;
1845 pl330->pcfg.irq_ns = readl(regs + CR3);
1848 static inline void _reset_thread(struct pl330_thread *thrd)
1850 struct pl330_dmac *pl330 = thrd->dmac;
1852 thrd->req[0].mc_cpu = pl330->mcode_cpu
1853 + (thrd->id * pl330->mcbufsz);
1854 thrd->req[0].mc_bus = pl330->mcode_bus
1855 + (thrd->id * pl330->mcbufsz);
1856 thrd->req[0].desc = NULL;
1858 thrd->req[1].mc_cpu = thrd->req[0].mc_cpu
1859 + pl330->mcbufsz / 2;
1860 thrd->req[1].mc_bus = thrd->req[0].mc_bus
1861 + pl330->mcbufsz / 2;
1862 thrd->req[1].desc = NULL;
1864 thrd->req_running = -1;
1867 static int dmac_alloc_threads(struct pl330_dmac *pl330)
1869 int chans = pl330->pcfg.num_chan;
1870 struct pl330_thread *thrd;
1873 /* Allocate 1 Manager and 'chans' Channel threads */
1874 pl330->channels = kcalloc(1 + chans, sizeof(*thrd),
1876 if (!pl330->channels)
1879 /* Init Channel threads */
1880 for (i = 0; i < chans; i++) {
1881 thrd = &pl330->channels[i];
1884 _reset_thread(thrd);
1888 /* MANAGER is indexed at the end */
1889 thrd = &pl330->channels[chans];
1893 pl330->manager = thrd;
1898 static int dmac_alloc_resources(struct pl330_dmac *pl330)
1900 int chans = pl330->pcfg.num_chan;
1904 * Alloc MicroCode buffer for 'chans' Channel threads.
1905 * A channel's buffer offset is (Channel_Id * MCODE_BUFF_PERCHAN)
1907 pl330->mcode_cpu = dma_alloc_attrs(pl330->ddma.dev,
1908 chans * pl330->mcbufsz,
1909 &pl330->mcode_bus, GFP_KERNEL,
1910 DMA_ATTR_PRIVILEGED);
1911 if (!pl330->mcode_cpu) {
1912 dev_err(pl330->ddma.dev, "%s:%d Can't allocate memory!\n",
1913 __func__, __LINE__);
1917 ret = dmac_alloc_threads(pl330);
1919 dev_err(pl330->ddma.dev, "%s:%d Can't to create channels for DMAC!\n",
1920 __func__, __LINE__);
1921 dma_free_coherent(pl330->ddma.dev,
1922 chans * pl330->mcbufsz,
1923 pl330->mcode_cpu, pl330->mcode_bus);
1930 static int pl330_add(struct pl330_dmac *pl330)
1934 /* Check if we can handle this DMAC */
1935 if ((pl330->pcfg.periph_id & 0xfffff) != PERIPH_ID_VAL) {
1936 dev_err(pl330->ddma.dev, "PERIPH_ID 0x%x !\n",
1937 pl330->pcfg.periph_id);
1941 /* Read the configuration of the DMAC */
1942 read_dmac_config(pl330);
1944 if (pl330->pcfg.num_events == 0) {
1945 dev_err(pl330->ddma.dev, "%s:%d Can't work without events!\n",
1946 __func__, __LINE__);
1950 spin_lock_init(&pl330->lock);
1952 INIT_LIST_HEAD(&pl330->req_done);
1954 /* Use default MC buffer size if not provided */
1955 if (!pl330->mcbufsz)
1956 pl330->mcbufsz = MCODE_BUFF_PER_REQ * 2;
1958 /* Mark all events as free */
1959 for (i = 0; i < pl330->pcfg.num_events; i++)
1960 pl330->events[i] = -1;
1962 /* Allocate resources needed by the DMAC */
1963 ret = dmac_alloc_resources(pl330);
1965 dev_err(pl330->ddma.dev, "Unable to create channels for DMAC\n");
1969 tasklet_init(&pl330->tasks, pl330_dotask, (unsigned long) pl330);
1971 pl330->state = INIT;
1976 static int dmac_free_threads(struct pl330_dmac *pl330)
1978 struct pl330_thread *thrd;
1981 /* Release Channel threads */
1982 for (i = 0; i < pl330->pcfg.num_chan; i++) {
1983 thrd = &pl330->channels[i];
1984 pl330_release_channel(thrd);
1988 kfree(pl330->channels);
1993 static void pl330_del(struct pl330_dmac *pl330)
1995 pl330->state = UNINIT;
1997 tasklet_kill(&pl330->tasks);
1999 /* Free DMAC resources */
2000 dmac_free_threads(pl330);
2002 dma_free_coherent(pl330->ddma.dev,
2003 pl330->pcfg.num_chan * pl330->mcbufsz, pl330->mcode_cpu,
2007 /* forward declaration */
2008 static struct amba_driver pl330_driver;
2010 static inline struct dma_pl330_chan *
2011 to_pchan(struct dma_chan *ch)
2016 return container_of(ch, struct dma_pl330_chan, chan);
2019 static inline struct dma_pl330_desc *
2020 to_desc(struct dma_async_tx_descriptor *tx)
2022 return container_of(tx, struct dma_pl330_desc, txd);
2025 static inline void fill_queue(struct dma_pl330_chan *pch)
2027 struct dma_pl330_desc *desc;
2030 list_for_each_entry(desc, &pch->work_list, node) {
2032 /* If already submitted */
2033 if (desc->status == BUSY)
2036 ret = pl330_submit_req(pch->thread, desc);
2038 desc->status = BUSY;
2039 } else if (ret == -EAGAIN) {
2040 /* QFull or DMAC Dying */
2043 /* Unacceptable request */
2044 desc->status = DONE;
2045 dev_err(pch->dmac->ddma.dev, "%s:%d Bad Desc(%d)\n",
2046 __func__, __LINE__, desc->txd.cookie);
2047 tasklet_schedule(&pch->task);
2052 static void pl330_tasklet(unsigned long data)
2054 struct dma_pl330_chan *pch = (struct dma_pl330_chan *)data;
2055 struct dma_pl330_desc *desc, *_dt;
2056 unsigned long flags;
2057 bool power_down = false;
2059 spin_lock_irqsave(&pch->lock, flags);
2061 /* Pick up ripe tomatoes */
2062 list_for_each_entry_safe(desc, _dt, &pch->work_list, node)
2063 if (desc->status == DONE) {
2065 dma_cookie_complete(&desc->txd);
2066 list_move_tail(&desc->node, &pch->completed_list);
2069 /* Try to submit a req imm. next to the last completed cookie */
2072 if (list_empty(&pch->work_list)) {
2073 spin_lock(&pch->thread->dmac->lock);
2075 spin_unlock(&pch->thread->dmac->lock);
2077 pch->active = false;
2079 /* Make sure the PL330 Channel thread is active */
2080 spin_lock(&pch->thread->dmac->lock);
2081 _start(pch->thread);
2082 spin_unlock(&pch->thread->dmac->lock);
2085 while (!list_empty(&pch->completed_list)) {
2086 struct dmaengine_desc_callback cb;
2088 desc = list_first_entry(&pch->completed_list,
2089 struct dma_pl330_desc, node);
2091 dmaengine_desc_get_callback(&desc->txd, &cb);
2094 desc->status = PREP;
2095 list_move_tail(&desc->node, &pch->work_list);
2098 spin_lock(&pch->thread->dmac->lock);
2099 _start(pch->thread);
2100 spin_unlock(&pch->thread->dmac->lock);
2104 desc->status = FREE;
2105 list_move_tail(&desc->node, &pch->dmac->desc_pool);
2108 dma_descriptor_unmap(&desc->txd);
2110 if (dmaengine_desc_callback_valid(&cb)) {
2111 spin_unlock_irqrestore(&pch->lock, flags);
2112 dmaengine_desc_callback_invoke(&cb, NULL);
2113 spin_lock_irqsave(&pch->lock, flags);
2116 spin_unlock_irqrestore(&pch->lock, flags);
2118 /* If work list empty, power down */
2120 pm_runtime_mark_last_busy(pch->dmac->ddma.dev);
2121 pm_runtime_put_autosuspend(pch->dmac->ddma.dev);
2125 static struct dma_chan *of_dma_pl330_xlate(struct of_phandle_args *dma_spec,
2126 struct of_dma *ofdma)
2128 int count = dma_spec->args_count;
2129 struct pl330_dmac *pl330 = ofdma->of_dma_data;
2130 unsigned int chan_id;
2138 chan_id = dma_spec->args[0];
2139 if (chan_id >= pl330->num_peripherals)
2142 return dma_get_slave_channel(&pl330->peripherals[chan_id].chan);
2145 static int pl330_alloc_chan_resources(struct dma_chan *chan)
2147 struct dma_pl330_chan *pch = to_pchan(chan);
2148 struct pl330_dmac *pl330 = pch->dmac;
2149 unsigned long flags;
2151 spin_lock_irqsave(&pl330->lock, flags);
2153 dma_cookie_init(chan);
2154 pch->cyclic = false;
2156 pch->thread = pl330_request_channel(pl330);
2158 spin_unlock_irqrestore(&pl330->lock, flags);
2162 tasklet_init(&pch->task, pl330_tasklet, (unsigned long) pch);
2164 spin_unlock_irqrestore(&pl330->lock, flags);
2170 * We need the data direction between the DMAC (the dma-mapping "device") and
2171 * the FIFO (the dmaengine "dev"), from the FIFO's point of view. Confusing!
2173 static enum dma_data_direction
2174 pl330_dma_slave_map_dir(enum dma_transfer_direction dir)
2177 case DMA_MEM_TO_DEV:
2178 return DMA_FROM_DEVICE;
2179 case DMA_DEV_TO_MEM:
2180 return DMA_TO_DEVICE;
2181 case DMA_DEV_TO_DEV:
2182 return DMA_BIDIRECTIONAL;
2188 static void pl330_unprep_slave_fifo(struct dma_pl330_chan *pch)
2190 if (pch->dir != DMA_NONE)
2191 dma_unmap_resource(pch->chan.device->dev, pch->fifo_dma,
2192 1 << pch->burst_sz, pch->dir, 0);
2193 pch->dir = DMA_NONE;
2197 static bool pl330_prep_slave_fifo(struct dma_pl330_chan *pch,
2198 enum dma_transfer_direction dir)
2200 struct device *dev = pch->chan.device->dev;
2201 enum dma_data_direction dma_dir = pl330_dma_slave_map_dir(dir);
2203 /* Already mapped for this config? */
2204 if (pch->dir == dma_dir)
2207 pl330_unprep_slave_fifo(pch);
2208 pch->fifo_dma = dma_map_resource(dev, pch->fifo_addr,
2209 1 << pch->burst_sz, dma_dir, 0);
2210 if (dma_mapping_error(dev, pch->fifo_dma))
2217 static int fixup_burst_len(int max_burst_len, int quirks)
2219 if (quirks & PL330_QUIRK_BROKEN_NO_FLUSHP)
2221 else if (max_burst_len > PL330_MAX_BURST)
2222 return PL330_MAX_BURST;
2223 else if (max_burst_len < 1)
2226 return max_burst_len;
2229 static int pl330_config_write(struct dma_chan *chan,
2230 struct dma_slave_config *slave_config,
2231 enum dma_transfer_direction direction)
2233 struct dma_pl330_chan *pch = to_pchan(chan);
2235 pl330_unprep_slave_fifo(pch);
2236 if (direction == DMA_MEM_TO_DEV) {
2237 if (slave_config->dst_addr)
2238 pch->fifo_addr = slave_config->dst_addr;
2239 if (slave_config->dst_addr_width)
2240 pch->burst_sz = __ffs(slave_config->dst_addr_width);
2241 pch->burst_len = fixup_burst_len(slave_config->dst_maxburst,
2243 } else if (direction == DMA_DEV_TO_MEM) {
2244 if (slave_config->src_addr)
2245 pch->fifo_addr = slave_config->src_addr;
2246 if (slave_config->src_addr_width)
2247 pch->burst_sz = __ffs(slave_config->src_addr_width);
2248 pch->burst_len = fixup_burst_len(slave_config->src_maxburst,
2255 static int pl330_config(struct dma_chan *chan,
2256 struct dma_slave_config *slave_config)
2258 struct dma_pl330_chan *pch = to_pchan(chan);
2260 memcpy(&pch->slave_config, slave_config, sizeof(*slave_config));
2265 static int pl330_terminate_all(struct dma_chan *chan)
2267 struct dma_pl330_chan *pch = to_pchan(chan);
2268 struct dma_pl330_desc *desc;
2269 unsigned long flags;
2270 struct pl330_dmac *pl330 = pch->dmac;
2271 bool power_down = false;
2273 pm_runtime_get_sync(pl330->ddma.dev);
2274 spin_lock_irqsave(&pch->lock, flags);
2276 spin_lock(&pl330->lock);
2278 pch->thread->req[0].desc = NULL;
2279 pch->thread->req[1].desc = NULL;
2280 pch->thread->req_running = -1;
2281 spin_unlock(&pl330->lock);
2283 power_down = pch->active;
2284 pch->active = false;
2286 /* Mark all desc done */
2287 list_for_each_entry(desc, &pch->submitted_list, node) {
2288 desc->status = FREE;
2289 dma_cookie_complete(&desc->txd);
2292 list_for_each_entry(desc, &pch->work_list , node) {
2293 desc->status = FREE;
2294 dma_cookie_complete(&desc->txd);
2297 list_splice_tail_init(&pch->submitted_list, &pl330->desc_pool);
2298 list_splice_tail_init(&pch->work_list, &pl330->desc_pool);
2299 list_splice_tail_init(&pch->completed_list, &pl330->desc_pool);
2300 spin_unlock_irqrestore(&pch->lock, flags);
2301 pm_runtime_mark_last_busy(pl330->ddma.dev);
2303 pm_runtime_put_autosuspend(pl330->ddma.dev);
2304 pm_runtime_put_autosuspend(pl330->ddma.dev);
2310 * We don't support DMA_RESUME command because of hardware
2311 * limitations, so after pausing the channel we cannot restore
2312 * it to active state. We have to terminate channel and setup
2313 * DMA transfer again. This pause feature was implemented to
2314 * allow safely read residue before channel termination.
2316 static int pl330_pause(struct dma_chan *chan)
2318 struct dma_pl330_chan *pch = to_pchan(chan);
2319 struct pl330_dmac *pl330 = pch->dmac;
2320 unsigned long flags;
2322 pm_runtime_get_sync(pl330->ddma.dev);
2323 spin_lock_irqsave(&pch->lock, flags);
2325 spin_lock(&pl330->lock);
2327 spin_unlock(&pl330->lock);
2329 spin_unlock_irqrestore(&pch->lock, flags);
2330 pm_runtime_mark_last_busy(pl330->ddma.dev);
2331 pm_runtime_put_autosuspend(pl330->ddma.dev);
2336 static void pl330_free_chan_resources(struct dma_chan *chan)
2338 struct dma_pl330_chan *pch = to_pchan(chan);
2339 struct pl330_dmac *pl330 = pch->dmac;
2340 unsigned long flags;
2342 tasklet_kill(&pch->task);
2344 pm_runtime_get_sync(pch->dmac->ddma.dev);
2345 spin_lock_irqsave(&pl330->lock, flags);
2347 pl330_release_channel(pch->thread);
2351 list_splice_tail_init(&pch->work_list, &pch->dmac->desc_pool);
2353 spin_unlock_irqrestore(&pl330->lock, flags);
2354 pm_runtime_mark_last_busy(pch->dmac->ddma.dev);
2355 pm_runtime_put_autosuspend(pch->dmac->ddma.dev);
2356 pl330_unprep_slave_fifo(pch);
2359 static int pl330_get_current_xferred_count(struct dma_pl330_chan *pch,
2360 struct dma_pl330_desc *desc)
2362 struct pl330_thread *thrd = pch->thread;
2363 struct pl330_dmac *pl330 = pch->dmac;
2364 void __iomem *regs = thrd->dmac->base;
2367 pm_runtime_get_sync(pl330->ddma.dev);
2369 if (desc->rqcfg.src_inc) {
2370 val = readl(regs + SA(thrd->id));
2371 addr = desc->px.src_addr;
2373 val = readl(regs + DA(thrd->id));
2374 addr = desc->px.dst_addr;
2376 pm_runtime_mark_last_busy(pch->dmac->ddma.dev);
2377 pm_runtime_put_autosuspend(pl330->ddma.dev);
2379 /* If DMAMOV hasn't finished yet, SAR/DAR can be zero */
2386 static enum dma_status
2387 pl330_tx_status(struct dma_chan *chan, dma_cookie_t cookie,
2388 struct dma_tx_state *txstate)
2390 enum dma_status ret;
2391 unsigned long flags;
2392 struct dma_pl330_desc *desc, *running = NULL, *last_enq = NULL;
2393 struct dma_pl330_chan *pch = to_pchan(chan);
2394 unsigned int transferred, residual = 0;
2396 ret = dma_cookie_status(chan, cookie, txstate);
2401 if (ret == DMA_COMPLETE)
2404 spin_lock_irqsave(&pch->lock, flags);
2405 spin_lock(&pch->thread->dmac->lock);
2407 if (pch->thread->req_running != -1)
2408 running = pch->thread->req[pch->thread->req_running].desc;
2410 last_enq = pch->thread->req[pch->thread->lstenq].desc;
2412 /* Check in pending list */
2413 list_for_each_entry(desc, &pch->work_list, node) {
2414 if (desc->status == DONE)
2415 transferred = desc->bytes_requested;
2416 else if (running && desc == running)
2418 pl330_get_current_xferred_count(pch, desc);
2419 else if (desc->status == BUSY)
2421 * Busy but not running means either just enqueued,
2422 * or finished and not yet marked done
2424 if (desc == last_enq)
2427 transferred = desc->bytes_requested;
2430 residual += desc->bytes_requested - transferred;
2431 if (desc->txd.cookie == cookie) {
2432 switch (desc->status) {
2438 ret = DMA_IN_PROGRESS;
2448 spin_unlock(&pch->thread->dmac->lock);
2449 spin_unlock_irqrestore(&pch->lock, flags);
2452 dma_set_residue(txstate, residual);
2457 static void pl330_issue_pending(struct dma_chan *chan)
2459 struct dma_pl330_chan *pch = to_pchan(chan);
2460 unsigned long flags;
2462 spin_lock_irqsave(&pch->lock, flags);
2463 if (list_empty(&pch->work_list)) {
2465 * Warn on nothing pending. Empty submitted_list may
2466 * break our pm_runtime usage counter as it is
2467 * updated on work_list emptiness status.
2469 WARN_ON(list_empty(&pch->submitted_list));
2471 pm_runtime_get_sync(pch->dmac->ddma.dev);
2473 list_splice_tail_init(&pch->submitted_list, &pch->work_list);
2474 spin_unlock_irqrestore(&pch->lock, flags);
2476 pl330_tasklet((unsigned long)pch);
2480 * We returned the last one of the circular list of descriptor(s)
2481 * from prep_xxx, so the argument to submit corresponds to the last
2482 * descriptor of the list.
2484 static dma_cookie_t pl330_tx_submit(struct dma_async_tx_descriptor *tx)
2486 struct dma_pl330_desc *desc, *last = to_desc(tx);
2487 struct dma_pl330_chan *pch = to_pchan(tx->chan);
2488 dma_cookie_t cookie;
2489 unsigned long flags;
2491 spin_lock_irqsave(&pch->lock, flags);
2493 /* Assign cookies to all nodes */
2494 while (!list_empty(&last->node)) {
2495 desc = list_entry(last->node.next, struct dma_pl330_desc, node);
2497 desc->txd.callback = last->txd.callback;
2498 desc->txd.callback_param = last->txd.callback_param;
2502 dma_cookie_assign(&desc->txd);
2504 list_move_tail(&desc->node, &pch->submitted_list);
2508 cookie = dma_cookie_assign(&last->txd);
2509 list_add_tail(&last->node, &pch->submitted_list);
2510 spin_unlock_irqrestore(&pch->lock, flags);
2515 static inline void _init_desc(struct dma_pl330_desc *desc)
2517 desc->rqcfg.swap = SWAP_NO;
2518 desc->rqcfg.scctl = CCTRL0;
2519 desc->rqcfg.dcctl = CCTRL0;
2520 desc->txd.tx_submit = pl330_tx_submit;
2522 INIT_LIST_HEAD(&desc->node);
2525 /* Returns the number of descriptors added to the DMAC pool */
2526 static int add_desc(struct list_head *pool, spinlock_t *lock,
2527 gfp_t flg, int count)
2529 struct dma_pl330_desc *desc;
2530 unsigned long flags;
2533 desc = kcalloc(count, sizeof(*desc), flg);
2537 spin_lock_irqsave(lock, flags);
2539 for (i = 0; i < count; i++) {
2540 _init_desc(&desc[i]);
2541 list_add_tail(&desc[i].node, pool);
2544 spin_unlock_irqrestore(lock, flags);
2549 static struct dma_pl330_desc *pluck_desc(struct list_head *pool,
2552 struct dma_pl330_desc *desc = NULL;
2553 unsigned long flags;
2555 spin_lock_irqsave(lock, flags);
2557 if (!list_empty(pool)) {
2558 desc = list_entry(pool->next,
2559 struct dma_pl330_desc, node);
2561 list_del_init(&desc->node);
2563 desc->status = PREP;
2564 desc->txd.callback = NULL;
2567 spin_unlock_irqrestore(lock, flags);
2572 static struct dma_pl330_desc *pl330_get_desc(struct dma_pl330_chan *pch)
2574 struct pl330_dmac *pl330 = pch->dmac;
2575 u8 *peri_id = pch->chan.private;
2576 struct dma_pl330_desc *desc;
2578 /* Pluck one desc from the pool of DMAC */
2579 desc = pluck_desc(&pl330->desc_pool, &pl330->pool_lock);
2581 /* If the DMAC pool is empty, alloc new */
2583 DEFINE_SPINLOCK(lock);
2586 if (!add_desc(&pool, &lock, GFP_ATOMIC, 1))
2589 desc = pluck_desc(&pool, &lock);
2590 WARN_ON(!desc || !list_empty(&pool));
2593 /* Initialize the descriptor */
2595 desc->txd.cookie = 0;
2596 async_tx_ack(&desc->txd);
2598 desc->peri = peri_id ? pch->chan.chan_id : 0;
2599 desc->rqcfg.pcfg = &pch->dmac->pcfg;
2601 dma_async_tx_descriptor_init(&desc->txd, &pch->chan);
2606 static inline void fill_px(struct pl330_xfer *px,
2607 dma_addr_t dst, dma_addr_t src, size_t len)
2614 static struct dma_pl330_desc *
2615 __pl330_prep_dma_memcpy(struct dma_pl330_chan *pch, dma_addr_t dst,
2616 dma_addr_t src, size_t len)
2618 struct dma_pl330_desc *desc = pl330_get_desc(pch);
2621 dev_err(pch->dmac->ddma.dev, "%s:%d Unable to fetch desc\n",
2622 __func__, __LINE__);
2627 * Ideally we should lookout for reqs bigger than
2628 * those that can be programmed with 256 bytes of
2629 * MC buffer, but considering a req size is seldom
2630 * going to be word-unaligned and more than 200MB,
2632 * Also, should the limit is reached we'd rather
2633 * have the platform increase MC buffer size than
2634 * complicating this API driver.
2636 fill_px(&desc->px, dst, src, len);
2641 /* Call after fixing burst size */
2642 static inline int get_burst_len(struct dma_pl330_desc *desc, size_t len)
2644 struct dma_pl330_chan *pch = desc->pchan;
2645 struct pl330_dmac *pl330 = pch->dmac;
2648 burst_len = pl330->pcfg.data_bus_width / 8;
2649 burst_len *= pl330->pcfg.data_buf_dep / pl330->pcfg.num_chan;
2650 burst_len >>= desc->rqcfg.brst_size;
2652 /* src/dst_burst_len can't be more than 16 */
2653 if (burst_len > PL330_MAX_BURST)
2654 burst_len = PL330_MAX_BURST;
2659 static struct dma_async_tx_descriptor *pl330_prep_dma_cyclic(
2660 struct dma_chan *chan, dma_addr_t dma_addr, size_t len,
2661 size_t period_len, enum dma_transfer_direction direction,
2662 unsigned long flags)
2664 struct dma_pl330_desc *desc = NULL, *first = NULL;
2665 struct dma_pl330_chan *pch = to_pchan(chan);
2666 struct pl330_dmac *pl330 = pch->dmac;
2671 if (len % period_len != 0)
2674 if (!is_slave_direction(direction)) {
2675 dev_err(pch->dmac->ddma.dev, "%s:%d Invalid dma direction\n",
2676 __func__, __LINE__);
2680 pl330_config_write(chan, &pch->slave_config, direction);
2682 if (!pl330_prep_slave_fifo(pch, direction))
2685 for (i = 0; i < len / period_len; i++) {
2686 desc = pl330_get_desc(pch);
2688 dev_err(pch->dmac->ddma.dev, "%s:%d Unable to fetch desc\n",
2689 __func__, __LINE__);
2694 spin_lock_irqsave(&pl330->pool_lock, flags);
2696 while (!list_empty(&first->node)) {
2697 desc = list_entry(first->node.next,
2698 struct dma_pl330_desc, node);
2699 list_move_tail(&desc->node, &pl330->desc_pool);
2702 list_move_tail(&first->node, &pl330->desc_pool);
2704 spin_unlock_irqrestore(&pl330->pool_lock, flags);
2709 switch (direction) {
2710 case DMA_MEM_TO_DEV:
2711 desc->rqcfg.src_inc = 1;
2712 desc->rqcfg.dst_inc = 0;
2714 dst = pch->fifo_dma;
2716 case DMA_DEV_TO_MEM:
2717 desc->rqcfg.src_inc = 0;
2718 desc->rqcfg.dst_inc = 1;
2719 src = pch->fifo_dma;
2726 desc->rqtype = direction;
2727 desc->rqcfg.brst_size = pch->burst_sz;
2728 desc->rqcfg.brst_len = pch->burst_len;
2729 desc->bytes_requested = period_len;
2730 fill_px(&desc->px, dst, src, period_len);
2735 list_add_tail(&desc->node, &first->node);
2737 dma_addr += period_len;
2744 desc->txd.flags = flags;
2749 static struct dma_async_tx_descriptor *
2750 pl330_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dst,
2751 dma_addr_t src, size_t len, unsigned long flags)
2753 struct dma_pl330_desc *desc;
2754 struct dma_pl330_chan *pch = to_pchan(chan);
2755 struct pl330_dmac *pl330;
2758 if (unlikely(!pch || !len))
2763 desc = __pl330_prep_dma_memcpy(pch, dst, src, len);
2767 desc->rqcfg.src_inc = 1;
2768 desc->rqcfg.dst_inc = 1;
2769 desc->rqtype = DMA_MEM_TO_MEM;
2771 /* Select max possible burst size */
2772 burst = pl330->pcfg.data_bus_width / 8;
2775 * Make sure we use a burst size that aligns with all the memcpy
2776 * parameters because our DMA programming algorithm doesn't cope with
2777 * transfers which straddle an entry in the DMA device's MFIFO.
2779 while ((src | dst | len) & (burst - 1))
2782 desc->rqcfg.brst_size = 0;
2783 while (burst != (1 << desc->rqcfg.brst_size))
2784 desc->rqcfg.brst_size++;
2787 * If burst size is smaller than bus width then make sure we only
2788 * transfer one at a time to avoid a burst stradling an MFIFO entry.
2790 if (desc->rqcfg.brst_size * 8 < pl330->pcfg.data_bus_width)
2791 desc->rqcfg.brst_len = 1;
2793 desc->rqcfg.brst_len = get_burst_len(desc, len);
2794 desc->bytes_requested = len;
2796 desc->txd.flags = flags;
2801 static void __pl330_giveback_desc(struct pl330_dmac *pl330,
2802 struct dma_pl330_desc *first)
2804 unsigned long flags;
2805 struct dma_pl330_desc *desc;
2810 spin_lock_irqsave(&pl330->pool_lock, flags);
2812 while (!list_empty(&first->node)) {
2813 desc = list_entry(first->node.next,
2814 struct dma_pl330_desc, node);
2815 list_move_tail(&desc->node, &pl330->desc_pool);
2818 list_move_tail(&first->node, &pl330->desc_pool);
2820 spin_unlock_irqrestore(&pl330->pool_lock, flags);
2823 static struct dma_async_tx_descriptor *
2824 pl330_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
2825 unsigned int sg_len, enum dma_transfer_direction direction,
2826 unsigned long flg, void *context)
2828 struct dma_pl330_desc *first, *desc = NULL;
2829 struct dma_pl330_chan *pch = to_pchan(chan);
2830 struct scatterlist *sg;
2833 if (unlikely(!pch || !sgl || !sg_len))
2836 pl330_config_write(chan, &pch->slave_config, direction);
2838 if (!pl330_prep_slave_fifo(pch, direction))
2843 for_each_sg(sgl, sg, sg_len, i) {
2845 desc = pl330_get_desc(pch);
2847 struct pl330_dmac *pl330 = pch->dmac;
2849 dev_err(pch->dmac->ddma.dev,
2850 "%s:%d Unable to fetch desc\n",
2851 __func__, __LINE__);
2852 __pl330_giveback_desc(pl330, first);
2860 list_add_tail(&desc->node, &first->node);
2862 if (direction == DMA_MEM_TO_DEV) {
2863 desc->rqcfg.src_inc = 1;
2864 desc->rqcfg.dst_inc = 0;
2865 fill_px(&desc->px, pch->fifo_dma, sg_dma_address(sg),
2868 desc->rqcfg.src_inc = 0;
2869 desc->rqcfg.dst_inc = 1;
2870 fill_px(&desc->px, sg_dma_address(sg), pch->fifo_dma,
2874 desc->rqcfg.brst_size = pch->burst_sz;
2875 desc->rqcfg.brst_len = pch->burst_len;
2876 desc->rqtype = direction;
2877 desc->bytes_requested = sg_dma_len(sg);
2880 /* Return the last desc in the chain */
2881 desc->txd.flags = flg;
2885 static irqreturn_t pl330_irq_handler(int irq, void *data)
2887 if (pl330_update(data))
2893 #define PL330_DMA_BUSWIDTHS \
2894 BIT(DMA_SLAVE_BUSWIDTH_UNDEFINED) | \
2895 BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \
2896 BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \
2897 BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) | \
2898 BIT(DMA_SLAVE_BUSWIDTH_8_BYTES)
2900 #ifdef CONFIG_DEBUG_FS
2901 static int pl330_debugfs_show(struct seq_file *s, void *data)
2903 struct pl330_dmac *pl330 = s->private;
2904 int chans, pchs, ch, pr;
2906 chans = pl330->pcfg.num_chan;
2907 pchs = pl330->num_peripherals;
2909 seq_puts(s, "PL330 physical channels:\n");
2910 seq_puts(s, "THREAD:\t\tCHANNEL:\n");
2911 seq_puts(s, "--------\t-----\n");
2912 for (ch = 0; ch < chans; ch++) {
2913 struct pl330_thread *thrd = &pl330->channels[ch];
2916 for (pr = 0; pr < pchs; pr++) {
2917 struct dma_pl330_chan *pch = &pl330->peripherals[pr];
2919 if (!pch->thread || thrd->id != pch->thread->id)
2925 seq_printf(s, "%d\t\t", thrd->id);
2927 seq_puts(s, "--\n");
2929 seq_printf(s, "%d\n", found);
2935 DEFINE_SHOW_ATTRIBUTE(pl330_debugfs);
2937 static inline void init_pl330_debugfs(struct pl330_dmac *pl330)
2939 debugfs_create_file(dev_name(pl330->ddma.dev),
2940 S_IFREG | 0444, NULL, pl330,
2941 &pl330_debugfs_fops);
2944 static inline void init_pl330_debugfs(struct pl330_dmac *pl330)
2950 * Runtime PM callbacks are provided by amba/bus.c driver.
2952 * It is assumed here that IRQ safe runtime PM is chosen in probe and amba
2953 * bus driver will only disable/enable the clock in runtime PM callbacks.
2955 static int __maybe_unused pl330_suspend(struct device *dev)
2957 struct amba_device *pcdev = to_amba_device(dev);
2959 pm_runtime_disable(dev);
2961 if (!pm_runtime_status_suspended(dev)) {
2962 /* amba did not disable the clock */
2963 amba_pclk_disable(pcdev);
2965 amba_pclk_unprepare(pcdev);
2970 static int __maybe_unused pl330_resume(struct device *dev)
2972 struct amba_device *pcdev = to_amba_device(dev);
2975 ret = amba_pclk_prepare(pcdev);
2979 if (!pm_runtime_status_suspended(dev))
2980 ret = amba_pclk_enable(pcdev);
2982 pm_runtime_enable(dev);
2987 static SIMPLE_DEV_PM_OPS(pl330_pm, pl330_suspend, pl330_resume);
2990 pl330_probe(struct amba_device *adev, const struct amba_id *id)
2992 struct pl330_config *pcfg;
2993 struct pl330_dmac *pl330;
2994 struct dma_pl330_chan *pch, *_p;
2995 struct dma_device *pd;
2996 struct resource *res;
2999 struct device_node *np = adev->dev.of_node;
3001 ret = dma_set_mask_and_coherent(&adev->dev, DMA_BIT_MASK(32));
3005 /* Allocate a new DMAC and its Channels */
3006 pl330 = devm_kzalloc(&adev->dev, sizeof(*pl330), GFP_KERNEL);
3011 pd->dev = &adev->dev;
3016 for (i = 0; i < ARRAY_SIZE(of_quirks); i++)
3017 if (of_property_read_bool(np, of_quirks[i].quirk))
3018 pl330->quirks |= of_quirks[i].id;
3021 pl330->base = devm_ioremap_resource(&adev->dev, res);
3022 if (IS_ERR(pl330->base))
3023 return PTR_ERR(pl330->base);
3025 amba_set_drvdata(adev, pl330);
3027 for (i = 0; i < AMBA_NR_IRQS; i++) {
3030 ret = devm_request_irq(&adev->dev, irq,
3031 pl330_irq_handler, 0,
3032 dev_name(&adev->dev), pl330);
3040 pcfg = &pl330->pcfg;
3042 pcfg->periph_id = adev->periphid;
3043 ret = pl330_add(pl330);
3047 INIT_LIST_HEAD(&pl330->desc_pool);
3048 spin_lock_init(&pl330->pool_lock);
3050 /* Create a descriptor pool of default size */
3051 if (!add_desc(&pl330->desc_pool, &pl330->pool_lock,
3052 GFP_KERNEL, NR_DEFAULT_DESC))
3053 dev_warn(&adev->dev, "unable to allocate desc\n");
3055 INIT_LIST_HEAD(&pd->channels);
3057 /* Initialize channel parameters */
3058 num_chan = max_t(int, pcfg->num_peri, pcfg->num_chan);
3060 pl330->num_peripherals = num_chan;
3062 pl330->peripherals = kcalloc(num_chan, sizeof(*pch), GFP_KERNEL);
3063 if (!pl330->peripherals) {
3068 for (i = 0; i < num_chan; i++) {
3069 pch = &pl330->peripherals[i];
3071 pch->chan.private = adev->dev.of_node;
3072 INIT_LIST_HEAD(&pch->submitted_list);
3073 INIT_LIST_HEAD(&pch->work_list);
3074 INIT_LIST_HEAD(&pch->completed_list);
3075 spin_lock_init(&pch->lock);
3077 pch->chan.device = pd;
3079 pch->dir = DMA_NONE;
3081 /* Add the channel to the DMAC list */
3082 list_add_tail(&pch->chan.device_node, &pd->channels);
3085 dma_cap_set(DMA_MEMCPY, pd->cap_mask);
3086 if (pcfg->num_peri) {
3087 dma_cap_set(DMA_SLAVE, pd->cap_mask);
3088 dma_cap_set(DMA_CYCLIC, pd->cap_mask);
3089 dma_cap_set(DMA_PRIVATE, pd->cap_mask);
3092 pd->device_alloc_chan_resources = pl330_alloc_chan_resources;
3093 pd->device_free_chan_resources = pl330_free_chan_resources;
3094 pd->device_prep_dma_memcpy = pl330_prep_dma_memcpy;
3095 pd->device_prep_dma_cyclic = pl330_prep_dma_cyclic;
3096 pd->device_tx_status = pl330_tx_status;
3097 pd->device_prep_slave_sg = pl330_prep_slave_sg;
3098 pd->device_config = pl330_config;
3099 pd->device_pause = pl330_pause;
3100 pd->device_terminate_all = pl330_terminate_all;
3101 pd->device_issue_pending = pl330_issue_pending;
3102 pd->src_addr_widths = PL330_DMA_BUSWIDTHS;
3103 pd->dst_addr_widths = PL330_DMA_BUSWIDTHS;
3104 pd->directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
3105 pd->residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;
3106 pd->max_burst = ((pl330->quirks & PL330_QUIRK_BROKEN_NO_FLUSHP) ?
3107 1 : PL330_MAX_BURST);
3109 ret = dma_async_device_register(pd);
3111 dev_err(&adev->dev, "unable to register DMAC\n");
3115 if (adev->dev.of_node) {
3116 ret = of_dma_controller_register(adev->dev.of_node,
3117 of_dma_pl330_xlate, pl330);
3120 "unable to register DMA to the generic DT DMA helpers\n");
3124 adev->dev.dma_parms = &pl330->dma_parms;
3127 * This is the limit for transfers with a buswidth of 1, larger
3128 * buswidths will have larger limits.
3130 ret = dma_set_max_seg_size(&adev->dev, 1900800);
3132 dev_err(&adev->dev, "unable to set the seg size\n");
3135 init_pl330_debugfs(pl330);
3136 dev_info(&adev->dev,
3137 "Loaded driver for PL330 DMAC-%x\n", adev->periphid);
3138 dev_info(&adev->dev,
3139 "\tDBUFF-%ux%ubytes Num_Chans-%u Num_Peri-%u Num_Events-%u\n",
3140 pcfg->data_buf_dep, pcfg->data_bus_width / 8, pcfg->num_chan,
3141 pcfg->num_peri, pcfg->num_events);
3143 pm_runtime_irq_safe(&adev->dev);
3144 pm_runtime_use_autosuspend(&adev->dev);
3145 pm_runtime_set_autosuspend_delay(&adev->dev, PL330_AUTOSUSPEND_DELAY);
3146 pm_runtime_mark_last_busy(&adev->dev);
3147 pm_runtime_put_autosuspend(&adev->dev);
3152 list_for_each_entry_safe(pch, _p, &pl330->ddma.channels,
3155 /* Remove the channel */
3156 list_del(&pch->chan.device_node);
3158 /* Flush the channel */
3160 pl330_terminate_all(&pch->chan);
3161 pl330_free_chan_resources(&pch->chan);
3170 static int pl330_remove(struct amba_device *adev)
3172 struct pl330_dmac *pl330 = amba_get_drvdata(adev);
3173 struct dma_pl330_chan *pch, *_p;
3176 pm_runtime_get_noresume(pl330->ddma.dev);
3178 if (adev->dev.of_node)
3179 of_dma_controller_free(adev->dev.of_node);
3181 for (i = 0; i < AMBA_NR_IRQS; i++) {
3184 devm_free_irq(&adev->dev, irq, pl330);
3187 dma_async_device_unregister(&pl330->ddma);
3190 list_for_each_entry_safe(pch, _p, &pl330->ddma.channels,
3193 /* Remove the channel */
3194 list_del(&pch->chan.device_node);
3196 /* Flush the channel */
3198 pl330_terminate_all(&pch->chan);
3199 pl330_free_chan_resources(&pch->chan);
3208 static const struct amba_id pl330_ids[] = {
3216 MODULE_DEVICE_TABLE(amba, pl330_ids);
3218 static struct amba_driver pl330_driver = {
3220 .owner = THIS_MODULE,
3221 .name = "dma-pl330",
3224 .id_table = pl330_ids,
3225 .probe = pl330_probe,
3226 .remove = pl330_remove,
3229 module_amba_driver(pl330_driver);
3231 MODULE_AUTHOR("Jaswinder Singh <jassisinghbrar@gmail.com>");
3232 MODULE_DESCRIPTION("API Driver for PL330 DMAC");
3233 MODULE_LICENSE("GPL");