1 // SPDX-License-Identifier: GPL-2.0-only
3 * MOXA ART SoCs DMA Engine support.
5 * Copyright (C) 2013 Jonas Jensen
7 * Jonas Jensen <jonas.jensen@gmail.com>
10 #include <linux/dmaengine.h>
11 #include <linux/dma-mapping.h>
12 #include <linux/err.h>
13 #include <linux/init.h>
14 #include <linux/interrupt.h>
15 #include <linux/list.h>
16 #include <linux/module.h>
17 #include <linux/platform_device.h>
18 #include <linux/slab.h>
19 #include <linux/spinlock.h>
20 #include <linux/of_address.h>
21 #include <linux/of_irq.h>
22 #include <linux/of_dma.h>
23 #include <linux/bitops.h>
25 #include <asm/cacheflush.h>
27 #include "dmaengine.h"
30 #define APB_DMA_MAX_CHANNEL 4
32 #define REG_OFF_ADDRESS_SOURCE 0
33 #define REG_OFF_ADDRESS_DEST 4
34 #define REG_OFF_CYCLES 8
35 #define REG_OFF_CTRL 12
36 #define REG_OFF_CHAN_SIZE 16
38 #define APB_DMA_ENABLE BIT(0)
39 #define APB_DMA_FIN_INT_STS BIT(1)
40 #define APB_DMA_FIN_INT_EN BIT(2)
41 #define APB_DMA_BURST_MODE BIT(3)
42 #define APB_DMA_ERR_INT_STS BIT(4)
43 #define APB_DMA_ERR_INT_EN BIT(5)
49 #define APB_DMA_SOURCE_SELECT 0x40
50 #define APB_DMA_DEST_SELECT 0x80
52 #define APB_DMA_SOURCE 0x100
53 #define APB_DMA_DEST 0x1000
55 #define APB_DMA_SOURCE_MASK 0x700
56 #define APB_DMA_DEST_MASK 0x7000
60 * 001: +1 (Burst=0), +4 (Burst=1)
61 * 010: +2 (Burst=0), +8 (Burst=1)
62 * 011: +4 (Burst=0), +16 (Burst=1)
63 * 101: -1 (Burst=0), -4 (Burst=1)
64 * 110: -2 (Burst=0), -8 (Burst=1)
65 * 111: -4 (Burst=0), -16 (Burst=1)
67 #define APB_DMA_SOURCE_INC_0 0
68 #define APB_DMA_SOURCE_INC_1_4 0x100
69 #define APB_DMA_SOURCE_INC_2_8 0x200
70 #define APB_DMA_SOURCE_INC_4_16 0x300
71 #define APB_DMA_SOURCE_DEC_1_4 0x500
72 #define APB_DMA_SOURCE_DEC_2_8 0x600
73 #define APB_DMA_SOURCE_DEC_4_16 0x700
74 #define APB_DMA_DEST_INC_0 0
75 #define APB_DMA_DEST_INC_1_4 0x1000
76 #define APB_DMA_DEST_INC_2_8 0x2000
77 #define APB_DMA_DEST_INC_4_16 0x3000
78 #define APB_DMA_DEST_DEC_1_4 0x5000
79 #define APB_DMA_DEST_DEC_2_8 0x6000
80 #define APB_DMA_DEST_DEC_4_16 0x7000
83 * Request signal select source/destination address for DMA hardware handshake.
85 * The request line number is a property of the DMA controller itself,
86 * e.g. MMC must always request channels where dma_slave_config->slave_id is 5.
88 * 0: No request / Grant signal
89 * 1-15: Request / Grant signal
91 #define APB_DMA_SOURCE_REQ_NO 0x1000000
92 #define APB_DMA_SOURCE_REQ_NO_MASK 0xf000000
93 #define APB_DMA_DEST_REQ_NO 0x10000
94 #define APB_DMA_DEST_REQ_NO_MASK 0xf0000
96 #define APB_DMA_DATA_WIDTH 0x100000
97 #define APB_DMA_DATA_WIDTH_MASK 0x300000
99 * Data width of transfer:
105 #define APB_DMA_DATA_WIDTH_4 0
106 #define APB_DMA_DATA_WIDTH_2 0x100000
107 #define APB_DMA_DATA_WIDTH_1 0x200000
109 #define APB_DMA_CYCLES_MASK 0x00ffffff
111 #define MOXART_DMA_DATA_TYPE_S8 0x00
112 #define MOXART_DMA_DATA_TYPE_S16 0x01
113 #define MOXART_DMA_DATA_TYPE_S32 0x02
121 enum dma_transfer_direction dma_dir;
124 unsigned int dma_cycles;
125 struct virt_dma_desc vd;
127 struct moxart_sg sg[] __counted_by(sglen);
131 struct virt_dma_chan vc;
134 struct moxart_desc *desc;
136 struct dma_slave_config cfg;
141 unsigned int line_reqno;
145 struct moxart_dmadev {
146 struct dma_device dma_slave;
147 struct moxart_chan slave_chans[APB_DMA_MAX_CHANNEL];
151 struct moxart_filter_data {
152 struct moxart_dmadev *mdc;
153 struct of_phandle_args *dma_spec;
156 static const unsigned int es_bytes[] = {
157 [MOXART_DMA_DATA_TYPE_S8] = 1,
158 [MOXART_DMA_DATA_TYPE_S16] = 2,
159 [MOXART_DMA_DATA_TYPE_S32] = 4,
162 static struct device *chan2dev(struct dma_chan *chan)
164 return &chan->dev->device;
167 static inline struct moxart_chan *to_moxart_dma_chan(struct dma_chan *c)
169 return container_of(c, struct moxart_chan, vc.chan);
172 static inline struct moxart_desc *to_moxart_dma_desc(
173 struct dma_async_tx_descriptor *t)
175 return container_of(t, struct moxart_desc, vd.tx);
178 static void moxart_dma_desc_free(struct virt_dma_desc *vd)
180 kfree(container_of(vd, struct moxart_desc, vd));
183 static int moxart_terminate_all(struct dma_chan *chan)
185 struct moxart_chan *ch = to_moxart_dma_chan(chan);
190 dev_dbg(chan2dev(chan), "%s: ch=%p\n", __func__, ch);
192 spin_lock_irqsave(&ch->vc.lock, flags);
195 moxart_dma_desc_free(&ch->desc->vd);
199 ctrl = readl(ch->base + REG_OFF_CTRL);
200 ctrl &= ~(APB_DMA_ENABLE | APB_DMA_FIN_INT_EN | APB_DMA_ERR_INT_EN);
201 writel(ctrl, ch->base + REG_OFF_CTRL);
203 vchan_get_all_descriptors(&ch->vc, &head);
204 spin_unlock_irqrestore(&ch->vc.lock, flags);
205 vchan_dma_desc_free_list(&ch->vc, &head);
210 static int moxart_slave_config(struct dma_chan *chan,
211 struct dma_slave_config *cfg)
213 struct moxart_chan *ch = to_moxart_dma_chan(chan);
218 ctrl = readl(ch->base + REG_OFF_CTRL);
219 ctrl |= APB_DMA_BURST_MODE;
220 ctrl &= ~(APB_DMA_DEST_MASK | APB_DMA_SOURCE_MASK);
221 ctrl &= ~(APB_DMA_DEST_REQ_NO_MASK | APB_DMA_SOURCE_REQ_NO_MASK);
223 switch (ch->cfg.src_addr_width) {
224 case DMA_SLAVE_BUSWIDTH_1_BYTE:
225 ctrl |= APB_DMA_DATA_WIDTH_1;
226 if (ch->cfg.direction != DMA_MEM_TO_DEV)
227 ctrl |= APB_DMA_DEST_INC_1_4;
229 ctrl |= APB_DMA_SOURCE_INC_1_4;
231 case DMA_SLAVE_BUSWIDTH_2_BYTES:
232 ctrl |= APB_DMA_DATA_WIDTH_2;
233 if (ch->cfg.direction != DMA_MEM_TO_DEV)
234 ctrl |= APB_DMA_DEST_INC_2_8;
236 ctrl |= APB_DMA_SOURCE_INC_2_8;
238 case DMA_SLAVE_BUSWIDTH_4_BYTES:
239 ctrl &= ~APB_DMA_DATA_WIDTH;
240 if (ch->cfg.direction != DMA_MEM_TO_DEV)
241 ctrl |= APB_DMA_DEST_INC_4_16;
243 ctrl |= APB_DMA_SOURCE_INC_4_16;
249 if (ch->cfg.direction == DMA_MEM_TO_DEV) {
250 ctrl &= ~APB_DMA_DEST_SELECT;
251 ctrl |= APB_DMA_SOURCE_SELECT;
252 ctrl |= (ch->line_reqno << 16 &
253 APB_DMA_DEST_REQ_NO_MASK);
255 ctrl |= APB_DMA_DEST_SELECT;
256 ctrl &= ~APB_DMA_SOURCE_SELECT;
257 ctrl |= (ch->line_reqno << 24 &
258 APB_DMA_SOURCE_REQ_NO_MASK);
261 writel(ctrl, ch->base + REG_OFF_CTRL);
266 static struct dma_async_tx_descriptor *moxart_prep_slave_sg(
267 struct dma_chan *chan, struct scatterlist *sgl,
268 unsigned int sg_len, enum dma_transfer_direction dir,
269 unsigned long tx_flags, void *context)
271 struct moxart_chan *ch = to_moxart_dma_chan(chan);
272 struct moxart_desc *d;
273 enum dma_slave_buswidth dev_width;
275 struct scatterlist *sgent;
279 if (!is_slave_direction(dir)) {
280 dev_err(chan2dev(chan), "%s: invalid DMA direction\n",
285 if (dir == DMA_DEV_TO_MEM) {
286 dev_addr = ch->cfg.src_addr;
287 dev_width = ch->cfg.src_addr_width;
289 dev_addr = ch->cfg.dst_addr;
290 dev_width = ch->cfg.dst_addr_width;
294 case DMA_SLAVE_BUSWIDTH_1_BYTE:
295 es = MOXART_DMA_DATA_TYPE_S8;
297 case DMA_SLAVE_BUSWIDTH_2_BYTES:
298 es = MOXART_DMA_DATA_TYPE_S16;
300 case DMA_SLAVE_BUSWIDTH_4_BYTES:
301 es = MOXART_DMA_DATA_TYPE_S32;
304 dev_err(chan2dev(chan), "%s: unsupported data width (%u)\n",
305 __func__, dev_width);
309 d = kzalloc(struct_size(d, sg, sg_len), GFP_ATOMIC);
315 d->dev_addr = dev_addr;
318 for_each_sg(sgl, sgent, sg_len, i) {
319 d->sg[i].addr = sg_dma_address(sgent);
320 d->sg[i].len = sg_dma_len(sgent);
325 return vchan_tx_prep(&ch->vc, &d->vd, tx_flags);
328 static struct dma_chan *moxart_of_xlate(struct of_phandle_args *dma_spec,
329 struct of_dma *ofdma)
331 struct moxart_dmadev *mdc = ofdma->of_dma_data;
332 struct dma_chan *chan;
333 struct moxart_chan *ch;
335 chan = dma_get_any_slave_channel(&mdc->dma_slave);
339 ch = to_moxart_dma_chan(chan);
340 ch->line_reqno = dma_spec->args[0];
345 static int moxart_alloc_chan_resources(struct dma_chan *chan)
347 struct moxart_chan *ch = to_moxart_dma_chan(chan);
349 dev_dbg(chan2dev(chan), "%s: allocating channel #%u\n",
350 __func__, ch->ch_num);
356 static void moxart_free_chan_resources(struct dma_chan *chan)
358 struct moxart_chan *ch = to_moxart_dma_chan(chan);
360 vchan_free_chan_resources(&ch->vc);
362 dev_dbg(chan2dev(chan), "%s: freeing channel #%u\n",
363 __func__, ch->ch_num);
367 static void moxart_dma_set_params(struct moxart_chan *ch, dma_addr_t src_addr,
370 writel(src_addr, ch->base + REG_OFF_ADDRESS_SOURCE);
371 writel(dst_addr, ch->base + REG_OFF_ADDRESS_DEST);
374 static void moxart_set_transfer_params(struct moxart_chan *ch, unsigned int len)
376 struct moxart_desc *d = ch->desc;
377 unsigned int sglen_div = es_bytes[d->es];
379 d->dma_cycles = len >> sglen_div;
382 * There are 4 cycles on 64 bytes copied, i.e. one cycle copies 16
383 * bytes ( when width is APB_DMAB_DATA_WIDTH_4 ).
385 writel(d->dma_cycles, ch->base + REG_OFF_CYCLES);
387 dev_dbg(chan2dev(&ch->vc.chan), "%s: set %u DMA cycles (len=%u)\n",
388 __func__, d->dma_cycles, len);
391 static void moxart_start_dma(struct moxart_chan *ch)
395 ctrl = readl(ch->base + REG_OFF_CTRL);
396 ctrl |= (APB_DMA_ENABLE | APB_DMA_FIN_INT_EN | APB_DMA_ERR_INT_EN);
397 writel(ctrl, ch->base + REG_OFF_CTRL);
400 static void moxart_dma_start_sg(struct moxart_chan *ch, unsigned int idx)
402 struct moxart_desc *d = ch->desc;
403 struct moxart_sg *sg = ch->desc->sg + idx;
405 if (ch->desc->dma_dir == DMA_MEM_TO_DEV)
406 moxart_dma_set_params(ch, sg->addr, d->dev_addr);
407 else if (ch->desc->dma_dir == DMA_DEV_TO_MEM)
408 moxart_dma_set_params(ch, d->dev_addr, sg->addr);
410 moxart_set_transfer_params(ch, sg->len);
412 moxart_start_dma(ch);
415 static void moxart_dma_start_desc(struct dma_chan *chan)
417 struct moxart_chan *ch = to_moxart_dma_chan(chan);
418 struct virt_dma_desc *vd;
420 vd = vchan_next_desc(&ch->vc);
429 ch->desc = to_moxart_dma_desc(&vd->tx);
432 moxart_dma_start_sg(ch, 0);
435 static void moxart_issue_pending(struct dma_chan *chan)
437 struct moxart_chan *ch = to_moxart_dma_chan(chan);
440 spin_lock_irqsave(&ch->vc.lock, flags);
441 if (vchan_issue_pending(&ch->vc) && !ch->desc)
442 moxart_dma_start_desc(chan);
443 spin_unlock_irqrestore(&ch->vc.lock, flags);
446 static size_t moxart_dma_desc_size(struct moxart_desc *d,
447 unsigned int completed_sgs)
452 for (size = i = completed_sgs; i < d->sglen; i++)
453 size += d->sg[i].len;
458 static size_t moxart_dma_desc_size_in_flight(struct moxart_chan *ch)
461 unsigned int completed_cycles, cycles;
463 size = moxart_dma_desc_size(ch->desc, ch->sgidx);
464 cycles = readl(ch->base + REG_OFF_CYCLES);
465 completed_cycles = (ch->desc->dma_cycles - cycles);
466 size -= completed_cycles << es_bytes[ch->desc->es];
468 dev_dbg(chan2dev(&ch->vc.chan), "%s: size=%zu\n", __func__, size);
473 static enum dma_status moxart_tx_status(struct dma_chan *chan,
475 struct dma_tx_state *txstate)
477 struct moxart_chan *ch = to_moxart_dma_chan(chan);
478 struct virt_dma_desc *vd;
479 struct moxart_desc *d;
484 * dma_cookie_status() assigns initial residue value.
486 ret = dma_cookie_status(chan, cookie, txstate);
488 spin_lock_irqsave(&ch->vc.lock, flags);
489 vd = vchan_find_desc(&ch->vc, cookie);
491 d = to_moxart_dma_desc(&vd->tx);
492 txstate->residue = moxart_dma_desc_size(d, 0);
493 } else if (ch->desc && ch->desc->vd.tx.cookie == cookie) {
494 txstate->residue = moxart_dma_desc_size_in_flight(ch);
496 spin_unlock_irqrestore(&ch->vc.lock, flags);
504 static void moxart_dma_init(struct dma_device *dma, struct device *dev)
506 dma->device_prep_slave_sg = moxart_prep_slave_sg;
507 dma->device_alloc_chan_resources = moxart_alloc_chan_resources;
508 dma->device_free_chan_resources = moxart_free_chan_resources;
509 dma->device_issue_pending = moxart_issue_pending;
510 dma->device_tx_status = moxart_tx_status;
511 dma->device_config = moxart_slave_config;
512 dma->device_terminate_all = moxart_terminate_all;
515 INIT_LIST_HEAD(&dma->channels);
518 static irqreturn_t moxart_dma_interrupt(int irq, void *devid)
520 struct moxart_dmadev *mc = devid;
521 struct moxart_chan *ch = &mc->slave_chans[0];
525 dev_dbg(chan2dev(&ch->vc.chan), "%s\n", __func__);
527 for (i = 0; i < APB_DMA_MAX_CHANNEL; i++, ch++) {
531 ctrl = readl(ch->base + REG_OFF_CTRL);
533 dev_dbg(chan2dev(&ch->vc.chan), "%s: ch=%p ch->base=%p ctrl=%x\n",
534 __func__, ch, ch->base, ctrl);
536 if (ctrl & APB_DMA_FIN_INT_STS) {
537 ctrl &= ~APB_DMA_FIN_INT_STS;
539 spin_lock(&ch->vc.lock);
540 if (++ch->sgidx < ch->desc->sglen) {
541 moxart_dma_start_sg(ch, ch->sgidx);
543 vchan_cookie_complete(&ch->desc->vd);
544 moxart_dma_start_desc(&ch->vc.chan);
546 spin_unlock(&ch->vc.lock);
550 if (ctrl & APB_DMA_ERR_INT_STS) {
551 ctrl &= ~APB_DMA_ERR_INT_STS;
555 writel(ctrl, ch->base + REG_OFF_CTRL);
561 static int moxart_probe(struct platform_device *pdev)
563 struct device *dev = &pdev->dev;
564 struct device_node *node = dev->of_node;
565 void __iomem *dma_base_addr;
568 struct moxart_chan *ch;
569 struct moxart_dmadev *mdc;
571 mdc = devm_kzalloc(dev, sizeof(*mdc), GFP_KERNEL);
575 irq = irq_of_parse_and_map(node, 0);
577 dev_err(dev, "no IRQ resource\n");
581 dma_base_addr = devm_platform_ioremap_resource(pdev, 0);
582 if (IS_ERR(dma_base_addr))
583 return PTR_ERR(dma_base_addr);
585 dma_cap_zero(mdc->dma_slave.cap_mask);
586 dma_cap_set(DMA_SLAVE, mdc->dma_slave.cap_mask);
587 dma_cap_set(DMA_PRIVATE, mdc->dma_slave.cap_mask);
589 moxart_dma_init(&mdc->dma_slave, dev);
591 ch = &mdc->slave_chans[0];
592 for (i = 0; i < APB_DMA_MAX_CHANNEL; i++, ch++) {
594 ch->base = dma_base_addr + i * REG_OFF_CHAN_SIZE;
597 ch->vc.desc_free = moxart_dma_desc_free;
598 vchan_init(&ch->vc, &mdc->dma_slave);
600 dev_dbg(dev, "%s: chs[%d]: ch->ch_num=%u ch->base=%p\n",
601 __func__, i, ch->ch_num, ch->base);
604 platform_set_drvdata(pdev, mdc);
606 ret = devm_request_irq(dev, irq, moxart_dma_interrupt, 0,
607 "moxart-dma-engine", mdc);
609 dev_err(dev, "devm_request_irq failed\n");
614 ret = dma_async_device_register(&mdc->dma_slave);
616 dev_err(dev, "dma_async_device_register failed\n");
620 ret = of_dma_controller_register(node, moxart_of_xlate, mdc);
622 dev_err(dev, "of_dma_controller_register failed\n");
623 dma_async_device_unregister(&mdc->dma_slave);
627 dev_dbg(dev, "%s: IRQ=%u\n", __func__, irq);
632 static void moxart_remove(struct platform_device *pdev)
634 struct moxart_dmadev *m = platform_get_drvdata(pdev);
636 devm_free_irq(&pdev->dev, m->irq, m);
638 dma_async_device_unregister(&m->dma_slave);
640 if (pdev->dev.of_node)
641 of_dma_controller_free(pdev->dev.of_node);
644 static const struct of_device_id moxart_dma_match[] = {
645 { .compatible = "moxa,moxart-dma" },
648 MODULE_DEVICE_TABLE(of, moxart_dma_match);
650 static struct platform_driver moxart_driver = {
651 .probe = moxart_probe,
652 .remove_new = moxart_remove,
654 .name = "moxart-dma-engine",
655 .of_match_table = moxart_dma_match,
659 static int moxart_init(void)
661 return platform_driver_register(&moxart_driver);
663 subsys_initcall(moxart_init);
665 static void __exit moxart_exit(void)
667 platform_driver_unregister(&moxart_driver);
669 module_exit(moxart_exit);
671 MODULE_AUTHOR("Jonas Jensen <jonas.jensen@gmail.com>");
672 MODULE_DESCRIPTION("MOXART DMA engine driver");
673 MODULE_LICENSE("GPL v2");