1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2013 - 2015 Linaro Ltd.
4 * Copyright (c) 2013 Hisilicon Limited.
6 #include <linux/sched.h>
7 #include <linux/device.h>
8 #include <linux/dma-mapping.h>
9 #include <linux/dmapool.h>
10 #include <linux/dmaengine.h>
11 #include <linux/init.h>
12 #include <linux/interrupt.h>
13 #include <linux/kernel.h>
14 #include <linux/module.h>
15 #include <linux/platform_device.h>
16 #include <linux/slab.h>
17 #include <linux/spinlock.h>
18 #include <linux/of_device.h>
20 #include <linux/clk.h>
21 #include <linux/of_dma.h>
25 #define DRIVER_NAME "k3-dma"
26 #define DMA_MAX_SIZE 0x1ffc
27 #define DMA_CYCLIC_MAX_PERIOD 0x1000
28 #define LLI_BLOCK_SIZE (4 * PAGE_SIZE)
35 #define INT_TC1_MASK 0x18
36 #define INT_TC2_MASK 0x1c
37 #define INT_ERR1_MASK 0x20
38 #define INT_ERR2_MASK 0x24
39 #define INT_TC1_RAW 0x600
40 #define INT_TC2_RAW 0x608
41 #define INT_ERR1_RAW 0x610
42 #define INT_ERR2_RAW 0x618
45 #define CX_CUR_CNT 0x704
53 #define CX_LLI_CHAIN_EN 0x2
55 #define CX_CFG_NODEIRQ BIT(1)
56 #define CX_CFG_MEM2PER (0x1 << 2)
57 #define CX_CFG_PER2MEM (0x2 << 2)
58 #define CX_CFG_SRCINCR (0x1 << 31)
59 #define CX_CFG_DSTINCR (0x1 << 30)
70 struct k3_dma_desc_sw {
71 struct virt_dma_desc vd;
72 dma_addr_t desc_hw_lli;
75 struct k3_desc_hw *desc_hw;
82 struct virt_dma_chan vc;
83 struct k3_dma_phy *phy;
84 struct list_head node;
86 enum dma_status status;
88 struct dma_slave_config slave_config;
94 struct k3_dma_chan *vchan;
95 struct k3_dma_desc_sw *ds_run;
96 struct k3_dma_desc_sw *ds_done;
100 struct dma_device slave;
102 struct tasklet_struct task;
104 struct list_head chan_pending;
105 struct k3_dma_phy *phy;
106 struct k3_dma_chan *chans;
108 struct dma_pool *pool;
111 u32 dma_channel_mask;
116 #define K3_FLAG_NOCLK BIT(1)
118 struct k3dma_soc_data {
123 #define to_k3_dma(dmadev) container_of(dmadev, struct k3_dma_dev, slave)
125 static int k3_dma_config_write(struct dma_chan *chan,
126 enum dma_transfer_direction dir,
127 struct dma_slave_config *cfg);
129 static struct k3_dma_chan *to_k3_chan(struct dma_chan *chan)
131 return container_of(chan, struct k3_dma_chan, vc.chan);
134 static void k3_dma_pause_dma(struct k3_dma_phy *phy, bool on)
139 val = readl_relaxed(phy->base + CX_CFG);
141 writel_relaxed(val, phy->base + CX_CFG);
143 val = readl_relaxed(phy->base + CX_CFG);
145 writel_relaxed(val, phy->base + CX_CFG);
149 static void k3_dma_terminate_chan(struct k3_dma_phy *phy, struct k3_dma_dev *d)
153 k3_dma_pause_dma(phy, false);
155 val = 0x1 << phy->idx;
156 writel_relaxed(val, d->base + INT_TC1_RAW);
157 writel_relaxed(val, d->base + INT_TC2_RAW);
158 writel_relaxed(val, d->base + INT_ERR1_RAW);
159 writel_relaxed(val, d->base + INT_ERR2_RAW);
162 static void k3_dma_set_desc(struct k3_dma_phy *phy, struct k3_desc_hw *hw)
164 writel_relaxed(hw->lli, phy->base + CX_LLI);
165 writel_relaxed(hw->count, phy->base + CX_CNT0);
166 writel_relaxed(hw->saddr, phy->base + CX_SRC);
167 writel_relaxed(hw->daddr, phy->base + CX_DST);
168 writel_relaxed(hw->config, phy->base + CX_CFG);
171 static u32 k3_dma_get_curr_cnt(struct k3_dma_dev *d, struct k3_dma_phy *phy)
175 cnt = readl_relaxed(d->base + CX_CUR_CNT + phy->idx * 0x10);
180 static u32 k3_dma_get_curr_lli(struct k3_dma_phy *phy)
182 return readl_relaxed(phy->base + CX_LLI);
185 static u32 k3_dma_get_chan_stat(struct k3_dma_dev *d)
187 return readl_relaxed(d->base + CH_STAT);
190 static void k3_dma_enable_dma(struct k3_dma_dev *d, bool on)
193 /* set same priority */
194 writel_relaxed(0x0, d->base + CH_PRI);
197 writel_relaxed(0xffff, d->base + INT_TC1_MASK);
198 writel_relaxed(0xffff, d->base + INT_TC2_MASK);
199 writel_relaxed(0xffff, d->base + INT_ERR1_MASK);
200 writel_relaxed(0xffff, d->base + INT_ERR2_MASK);
203 writel_relaxed(0x0, d->base + INT_TC1_MASK);
204 writel_relaxed(0x0, d->base + INT_TC2_MASK);
205 writel_relaxed(0x0, d->base + INT_ERR1_MASK);
206 writel_relaxed(0x0, d->base + INT_ERR2_MASK);
210 static irqreturn_t k3_dma_int_handler(int irq, void *dev_id)
212 struct k3_dma_dev *d = (struct k3_dma_dev *)dev_id;
213 struct k3_dma_phy *p;
214 struct k3_dma_chan *c;
215 u32 stat = readl_relaxed(d->base + INT_STAT);
216 u32 tc1 = readl_relaxed(d->base + INT_TC1);
217 u32 tc2 = readl_relaxed(d->base + INT_TC2);
218 u32 err1 = readl_relaxed(d->base + INT_ERR1);
219 u32 err2 = readl_relaxed(d->base + INT_ERR2);
225 if (likely(tc1 & BIT(i)) || (tc2 & BIT(i))) {
230 if (c && (tc1 & BIT(i))) {
231 spin_lock_irqsave(&c->vc.lock, flags);
232 if (p->ds_run != NULL) {
233 vchan_cookie_complete(&p->ds_run->vd);
234 p->ds_done = p->ds_run;
237 spin_unlock_irqrestore(&c->vc.lock, flags);
239 if (c && (tc2 & BIT(i))) {
240 spin_lock_irqsave(&c->vc.lock, flags);
241 if (p->ds_run != NULL)
242 vchan_cyclic_callback(&p->ds_run->vd);
243 spin_unlock_irqrestore(&c->vc.lock, flags);
247 if (unlikely((err1 & BIT(i)) || (err2 & BIT(i))))
248 dev_warn(d->slave.dev, "DMA ERR\n");
251 writel_relaxed(irq_chan, d->base + INT_TC1_RAW);
252 writel_relaxed(irq_chan, d->base + INT_TC2_RAW);
253 writel_relaxed(err1, d->base + INT_ERR1_RAW);
254 writel_relaxed(err2, d->base + INT_ERR2_RAW);
257 tasklet_schedule(&d->task);
259 if (irq_chan || err1 || err2)
265 static int k3_dma_start_txd(struct k3_dma_chan *c)
267 struct k3_dma_dev *d = to_k3_dma(c->vc.chan.device);
268 struct virt_dma_desc *vd = vchan_next_desc(&c->vc);
273 if (BIT(c->phy->idx) & k3_dma_get_chan_stat(d))
276 /* Avoid losing track of ds_run if a transaction is in flight */
281 struct k3_dma_desc_sw *ds =
282 container_of(vd, struct k3_dma_desc_sw, vd);
284 * fetch and remove request from vc->desc_issued
285 * so vc->desc_issued only contains desc pending
287 list_del(&ds->vd.node);
290 c->phy->ds_done = NULL;
292 k3_dma_set_desc(c->phy, &ds->desc_hw[0]);
295 c->phy->ds_run = NULL;
296 c->phy->ds_done = NULL;
300 static void k3_dma_tasklet(struct tasklet_struct *t)
302 struct k3_dma_dev *d = from_tasklet(d, t, task);
303 struct k3_dma_phy *p;
304 struct k3_dma_chan *c, *cn;
305 unsigned pch, pch_alloc = 0;
307 /* check new dma request of running channel in vc->desc_issued */
308 list_for_each_entry_safe(c, cn, &d->slave.channels, vc.chan.device_node) {
309 spin_lock_irq(&c->vc.lock);
311 if (p && p->ds_done) {
312 if (k3_dma_start_txd(c)) {
313 /* No current txd associated with this channel */
314 dev_dbg(d->slave.dev, "pchan %u: free\n", p->idx);
315 /* Mark this channel free */
320 spin_unlock_irq(&c->vc.lock);
323 /* check new channel request in d->chan_pending */
324 spin_lock_irq(&d->lock);
325 for (pch = 0; pch < d->dma_channels; pch++) {
326 if (!(d->dma_channel_mask & (1 << pch)))
331 if (p->vchan == NULL && !list_empty(&d->chan_pending)) {
332 c = list_first_entry(&d->chan_pending,
333 struct k3_dma_chan, node);
334 /* remove from d->chan_pending */
335 list_del_init(&c->node);
336 pch_alloc |= 1 << pch;
337 /* Mark this channel allocated */
340 dev_dbg(d->slave.dev, "pchan %u: alloc vchan %p\n", pch, &c->vc);
343 spin_unlock_irq(&d->lock);
345 for (pch = 0; pch < d->dma_channels; pch++) {
346 if (!(d->dma_channel_mask & (1 << pch)))
349 if (pch_alloc & (1 << pch)) {
353 spin_lock_irq(&c->vc.lock);
355 spin_unlock_irq(&c->vc.lock);
361 static void k3_dma_free_chan_resources(struct dma_chan *chan)
363 struct k3_dma_chan *c = to_k3_chan(chan);
364 struct k3_dma_dev *d = to_k3_dma(chan->device);
367 spin_lock_irqsave(&d->lock, flags);
368 list_del_init(&c->node);
369 spin_unlock_irqrestore(&d->lock, flags);
371 vchan_free_chan_resources(&c->vc);
375 static enum dma_status k3_dma_tx_status(struct dma_chan *chan,
376 dma_cookie_t cookie, struct dma_tx_state *state)
378 struct k3_dma_chan *c = to_k3_chan(chan);
379 struct k3_dma_dev *d = to_k3_dma(chan->device);
380 struct k3_dma_phy *p;
381 struct virt_dma_desc *vd;
386 ret = dma_cookie_status(&c->vc.chan, cookie, state);
387 if (ret == DMA_COMPLETE)
390 spin_lock_irqsave(&c->vc.lock, flags);
395 * If the cookie is on our issue queue, then the residue is
398 vd = vchan_find_desc(&c->vc, cookie);
399 if (vd && !c->cyclic) {
400 bytes = container_of(vd, struct k3_dma_desc_sw, vd)->size;
401 } else if ((!p) || (!p->ds_run)) {
404 struct k3_dma_desc_sw *ds = p->ds_run;
405 u32 clli = 0, index = 0;
407 bytes = k3_dma_get_curr_cnt(d, p);
408 clli = k3_dma_get_curr_lli(p);
409 index = ((clli - ds->desc_hw_lli) /
410 sizeof(struct k3_desc_hw)) + 1;
411 for (; index < ds->desc_num; index++) {
412 bytes += ds->desc_hw[index].count;
414 if (!ds->desc_hw[index].lli)
418 spin_unlock_irqrestore(&c->vc.lock, flags);
419 dma_set_residue(state, bytes);
423 static void k3_dma_issue_pending(struct dma_chan *chan)
425 struct k3_dma_chan *c = to_k3_chan(chan);
426 struct k3_dma_dev *d = to_k3_dma(chan->device);
429 spin_lock_irqsave(&c->vc.lock, flags);
430 /* add request to vc->desc_issued */
431 if (vchan_issue_pending(&c->vc)) {
434 if (list_empty(&c->node)) {
435 /* if new channel, add chan_pending */
436 list_add_tail(&c->node, &d->chan_pending);
437 /* check in tasklet */
438 tasklet_schedule(&d->task);
439 dev_dbg(d->slave.dev, "vchan %p: issued\n", &c->vc);
442 spin_unlock(&d->lock);
444 dev_dbg(d->slave.dev, "vchan %p: nothing to issue\n", &c->vc);
445 spin_unlock_irqrestore(&c->vc.lock, flags);
448 static void k3_dma_fill_desc(struct k3_dma_desc_sw *ds, dma_addr_t dst,
449 dma_addr_t src, size_t len, u32 num, u32 ccfg)
451 if (num != ds->desc_num - 1)
452 ds->desc_hw[num].lli = ds->desc_hw_lli + (num + 1) *
453 sizeof(struct k3_desc_hw);
455 ds->desc_hw[num].lli |= CX_LLI_CHAIN_EN;
456 ds->desc_hw[num].count = len;
457 ds->desc_hw[num].saddr = src;
458 ds->desc_hw[num].daddr = dst;
459 ds->desc_hw[num].config = ccfg;
462 static struct k3_dma_desc_sw *k3_dma_alloc_desc_resource(int num,
463 struct dma_chan *chan)
465 struct k3_dma_chan *c = to_k3_chan(chan);
466 struct k3_dma_desc_sw *ds;
467 struct k3_dma_dev *d = to_k3_dma(chan->device);
468 int lli_limit = LLI_BLOCK_SIZE / sizeof(struct k3_desc_hw);
470 if (num > lli_limit) {
471 dev_dbg(chan->device->dev, "vch %p: sg num %d exceed max %d\n",
472 &c->vc, num, lli_limit);
476 ds = kzalloc(sizeof(*ds), GFP_NOWAIT);
480 ds->desc_hw = dma_pool_zalloc(d->pool, GFP_NOWAIT, &ds->desc_hw_lli);
482 dev_dbg(chan->device->dev, "vch %p: dma alloc fail\n", &c->vc);
490 static struct dma_async_tx_descriptor *k3_dma_prep_memcpy(
491 struct dma_chan *chan, dma_addr_t dst, dma_addr_t src,
492 size_t len, unsigned long flags)
494 struct k3_dma_chan *c = to_k3_chan(chan);
495 struct k3_dma_desc_sw *ds;
502 num = DIV_ROUND_UP(len, DMA_MAX_SIZE);
504 ds = k3_dma_alloc_desc_resource(num, chan);
513 /* default is memtomem, without calling device_config */
514 c->ccfg = CX_CFG_SRCINCR | CX_CFG_DSTINCR | CX_CFG_EN;
515 c->ccfg |= (0xf << 20) | (0xf << 24); /* burst = 16 */
516 c->ccfg |= (0x3 << 12) | (0x3 << 16); /* width = 64 bit */
520 copy = min_t(size_t, len, DMA_MAX_SIZE);
521 k3_dma_fill_desc(ds, dst, src, copy, num++, c->ccfg);
528 ds->desc_hw[num-1].lli = 0; /* end of link */
529 return vchan_tx_prep(&c->vc, &ds->vd, flags);
532 static struct dma_async_tx_descriptor *k3_dma_prep_slave_sg(
533 struct dma_chan *chan, struct scatterlist *sgl, unsigned int sglen,
534 enum dma_transfer_direction dir, unsigned long flags, void *context)
536 struct k3_dma_chan *c = to_k3_chan(chan);
537 struct k3_dma_desc_sw *ds;
538 size_t len, avail, total = 0;
539 struct scatterlist *sg;
540 dma_addr_t addr, src = 0, dst = 0;
548 for_each_sg(sgl, sg, sglen, i) {
549 avail = sg_dma_len(sg);
550 if (avail > DMA_MAX_SIZE)
551 num += DIV_ROUND_UP(avail, DMA_MAX_SIZE) - 1;
554 ds = k3_dma_alloc_desc_resource(num, chan);
558 k3_dma_config_write(chan, dir, &c->slave_config);
560 for_each_sg(sgl, sg, sglen, i) {
561 addr = sg_dma_address(sg);
562 avail = sg_dma_len(sg);
566 len = min_t(size_t, avail, DMA_MAX_SIZE);
568 if (dir == DMA_MEM_TO_DEV) {
571 } else if (dir == DMA_DEV_TO_MEM) {
576 k3_dma_fill_desc(ds, dst, src, len, num++, c->ccfg);
583 ds->desc_hw[num-1].lli = 0; /* end of link */
585 return vchan_tx_prep(&c->vc, &ds->vd, flags);
588 static struct dma_async_tx_descriptor *
589 k3_dma_prep_dma_cyclic(struct dma_chan *chan, dma_addr_t buf_addr,
590 size_t buf_len, size_t period_len,
591 enum dma_transfer_direction dir,
594 struct k3_dma_chan *c = to_k3_chan(chan);
595 struct k3_dma_desc_sw *ds;
596 size_t len, avail, total = 0;
597 dma_addr_t addr, src = 0, dst = 0;
598 int num = 1, since = 0;
599 size_t modulo = DMA_CYCLIC_MAX_PERIOD;
602 dev_dbg(chan->device->dev, "%s: buf %pad, dst %pad, buf len %zu, period_len = %zu, dir %d\n",
603 __func__, &buf_addr, &to_k3_chan(chan)->dev_addr,
604 buf_len, period_len, (int)dir);
608 num += DIV_ROUND_UP(avail, modulo) - 1;
610 ds = k3_dma_alloc_desc_resource(num, chan);
619 k3_dma_config_write(chan, dir, &c->slave_config);
621 if (period_len < modulo)
625 len = min_t(size_t, avail, modulo);
627 if (dir == DMA_MEM_TO_DEV) {
630 } else if (dir == DMA_DEV_TO_MEM) {
635 if (since >= period_len) {
636 /* descriptor asks for TC2 interrupt on completion */
637 en_tc2 = CX_CFG_NODEIRQ;
642 k3_dma_fill_desc(ds, dst, src, len, num++, c->ccfg | en_tc2);
648 /* "Cyclic" == end of link points back to start of link */
649 ds->desc_hw[num - 1].lli |= ds->desc_hw_lli;
653 return vchan_tx_prep(&c->vc, &ds->vd, flags);
656 static int k3_dma_config(struct dma_chan *chan,
657 struct dma_slave_config *cfg)
659 struct k3_dma_chan *c = to_k3_chan(chan);
661 memcpy(&c->slave_config, cfg, sizeof(*cfg));
666 static int k3_dma_config_write(struct dma_chan *chan,
667 enum dma_transfer_direction dir,
668 struct dma_slave_config *cfg)
670 struct k3_dma_chan *c = to_k3_chan(chan);
671 u32 maxburst = 0, val = 0;
672 enum dma_slave_buswidth width = DMA_SLAVE_BUSWIDTH_UNDEFINED;
674 if (dir == DMA_DEV_TO_MEM) {
675 c->ccfg = CX_CFG_DSTINCR;
676 c->dev_addr = cfg->src_addr;
677 maxburst = cfg->src_maxburst;
678 width = cfg->src_addr_width;
679 } else if (dir == DMA_MEM_TO_DEV) {
680 c->ccfg = CX_CFG_SRCINCR;
681 c->dev_addr = cfg->dst_addr;
682 maxburst = cfg->dst_maxburst;
683 width = cfg->dst_addr_width;
686 case DMA_SLAVE_BUSWIDTH_1_BYTE:
687 case DMA_SLAVE_BUSWIDTH_2_BYTES:
688 case DMA_SLAVE_BUSWIDTH_4_BYTES:
689 case DMA_SLAVE_BUSWIDTH_8_BYTES:
696 c->ccfg |= (val << 12) | (val << 16);
698 if ((maxburst == 0) || (maxburst > 16))
702 c->ccfg |= (val << 20) | (val << 24);
703 c->ccfg |= CX_CFG_MEM2PER | CX_CFG_EN;
705 /* specific request line */
706 c->ccfg |= c->vc.chan.chan_id << 4;
711 static void k3_dma_free_desc(struct virt_dma_desc *vd)
713 struct k3_dma_desc_sw *ds =
714 container_of(vd, struct k3_dma_desc_sw, vd);
715 struct k3_dma_dev *d = to_k3_dma(vd->tx.chan->device);
717 dma_pool_free(d->pool, ds->desc_hw, ds->desc_hw_lli);
721 static int k3_dma_terminate_all(struct dma_chan *chan)
723 struct k3_dma_chan *c = to_k3_chan(chan);
724 struct k3_dma_dev *d = to_k3_dma(chan->device);
725 struct k3_dma_phy *p = c->phy;
729 dev_dbg(d->slave.dev, "vchan %p: terminate all\n", &c->vc);
731 /* Prevent this channel being scheduled */
733 list_del_init(&c->node);
734 spin_unlock(&d->lock);
736 /* Clear the tx descriptor lists */
737 spin_lock_irqsave(&c->vc.lock, flags);
738 vchan_get_all_descriptors(&c->vc, &head);
740 /* vchan is assigned to a pchan - stop the channel */
741 k3_dma_terminate_chan(p, d);
745 vchan_terminate_vdesc(&p->ds_run->vd);
750 spin_unlock_irqrestore(&c->vc.lock, flags);
751 vchan_dma_desc_free_list(&c->vc, &head);
756 static void k3_dma_synchronize(struct dma_chan *chan)
758 struct k3_dma_chan *c = to_k3_chan(chan);
760 vchan_synchronize(&c->vc);
763 static int k3_dma_transfer_pause(struct dma_chan *chan)
765 struct k3_dma_chan *c = to_k3_chan(chan);
766 struct k3_dma_dev *d = to_k3_dma(chan->device);
767 struct k3_dma_phy *p = c->phy;
769 dev_dbg(d->slave.dev, "vchan %p: pause\n", &c->vc);
770 if (c->status == DMA_IN_PROGRESS) {
771 c->status = DMA_PAUSED;
773 k3_dma_pause_dma(p, false);
776 list_del_init(&c->node);
777 spin_unlock(&d->lock);
784 static int k3_dma_transfer_resume(struct dma_chan *chan)
786 struct k3_dma_chan *c = to_k3_chan(chan);
787 struct k3_dma_dev *d = to_k3_dma(chan->device);
788 struct k3_dma_phy *p = c->phy;
791 dev_dbg(d->slave.dev, "vchan %p: resume\n", &c->vc);
792 spin_lock_irqsave(&c->vc.lock, flags);
793 if (c->status == DMA_PAUSED) {
794 c->status = DMA_IN_PROGRESS;
796 k3_dma_pause_dma(p, true);
797 } else if (!list_empty(&c->vc.desc_issued)) {
799 list_add_tail(&c->node, &d->chan_pending);
800 spin_unlock(&d->lock);
803 spin_unlock_irqrestore(&c->vc.lock, flags);
808 static const struct k3dma_soc_data k3_v1_dma_data = {
812 static const struct k3dma_soc_data asp_v1_dma_data = {
813 .flags = K3_FLAG_NOCLK,
816 static const struct of_device_id k3_pdma_dt_ids[] = {
817 { .compatible = "hisilicon,k3-dma-1.0",
818 .data = &k3_v1_dma_data
820 { .compatible = "hisilicon,hisi-pcm-asp-dma-1.0",
821 .data = &asp_v1_dma_data
825 MODULE_DEVICE_TABLE(of, k3_pdma_dt_ids);
827 static struct dma_chan *k3_of_dma_simple_xlate(struct of_phandle_args *dma_spec,
828 struct of_dma *ofdma)
830 struct k3_dma_dev *d = ofdma->of_dma_data;
831 unsigned int request = dma_spec->args[0];
833 if (request >= d->dma_requests)
836 return dma_get_slave_channel(&(d->chans[request].vc.chan));
839 static int k3_dma_probe(struct platform_device *op)
841 const struct k3dma_soc_data *soc_data;
842 struct k3_dma_dev *d;
843 const struct of_device_id *of_id;
846 d = devm_kzalloc(&op->dev, sizeof(*d), GFP_KERNEL);
850 soc_data = device_get_match_data(&op->dev);
854 d->base = devm_platform_ioremap_resource(op, 0);
856 return PTR_ERR(d->base);
858 of_id = of_match_device(k3_pdma_dt_ids, &op->dev);
860 of_property_read_u32((&op->dev)->of_node,
861 "dma-channels", &d->dma_channels);
862 of_property_read_u32((&op->dev)->of_node,
863 "dma-requests", &d->dma_requests);
864 ret = of_property_read_u32((&op->dev)->of_node,
865 "dma-channel-mask", &d->dma_channel_mask);
868 "dma-channel-mask doesn't exist, considering all as available.\n");
869 d->dma_channel_mask = (u32)~0UL;
873 if (!(soc_data->flags & K3_FLAG_NOCLK)) {
874 d->clk = devm_clk_get(&op->dev, NULL);
875 if (IS_ERR(d->clk)) {
876 dev_err(&op->dev, "no dma clk\n");
877 return PTR_ERR(d->clk);
881 irq = platform_get_irq(op, 0);
882 ret = devm_request_irq(&op->dev, irq,
883 k3_dma_int_handler, 0, DRIVER_NAME, d);
889 /* A DMA memory pool for LLIs, align on 32-byte boundary */
890 d->pool = dmam_pool_create(DRIVER_NAME, &op->dev,
891 LLI_BLOCK_SIZE, 32, 0);
895 /* init phy channel */
896 d->phy = devm_kcalloc(&op->dev,
897 d->dma_channels, sizeof(struct k3_dma_phy), GFP_KERNEL);
901 for (i = 0; i < d->dma_channels; i++) {
902 struct k3_dma_phy *p;
904 if (!(d->dma_channel_mask & BIT(i)))
909 p->base = d->base + i * 0x40;
912 INIT_LIST_HEAD(&d->slave.channels);
913 dma_cap_set(DMA_SLAVE, d->slave.cap_mask);
914 dma_cap_set(DMA_MEMCPY, d->slave.cap_mask);
915 dma_cap_set(DMA_CYCLIC, d->slave.cap_mask);
916 d->slave.dev = &op->dev;
917 d->slave.device_free_chan_resources = k3_dma_free_chan_resources;
918 d->slave.device_tx_status = k3_dma_tx_status;
919 d->slave.device_prep_dma_memcpy = k3_dma_prep_memcpy;
920 d->slave.device_prep_slave_sg = k3_dma_prep_slave_sg;
921 d->slave.device_prep_dma_cyclic = k3_dma_prep_dma_cyclic;
922 d->slave.device_issue_pending = k3_dma_issue_pending;
923 d->slave.device_config = k3_dma_config;
924 d->slave.device_pause = k3_dma_transfer_pause;
925 d->slave.device_resume = k3_dma_transfer_resume;
926 d->slave.device_terminate_all = k3_dma_terminate_all;
927 d->slave.device_synchronize = k3_dma_synchronize;
928 d->slave.copy_align = DMAENGINE_ALIGN_8_BYTES;
930 /* init virtual channel */
931 d->chans = devm_kcalloc(&op->dev,
932 d->dma_requests, sizeof(struct k3_dma_chan), GFP_KERNEL);
933 if (d->chans == NULL)
936 for (i = 0; i < d->dma_requests; i++) {
937 struct k3_dma_chan *c = &d->chans[i];
939 c->status = DMA_IN_PROGRESS;
940 INIT_LIST_HEAD(&c->node);
941 c->vc.desc_free = k3_dma_free_desc;
942 vchan_init(&c->vc, &d->slave);
945 /* Enable clock before accessing registers */
946 ret = clk_prepare_enable(d->clk);
948 dev_err(&op->dev, "clk_prepare_enable failed: %d\n", ret);
952 k3_dma_enable_dma(d, true);
954 ret = dma_async_device_register(&d->slave);
956 goto dma_async_register_fail;
958 ret = of_dma_controller_register((&op->dev)->of_node,
959 k3_of_dma_simple_xlate, d);
961 goto of_dma_register_fail;
963 spin_lock_init(&d->lock);
964 INIT_LIST_HEAD(&d->chan_pending);
965 tasklet_setup(&d->task, k3_dma_tasklet);
966 platform_set_drvdata(op, d);
967 dev_info(&op->dev, "initialized\n");
971 of_dma_register_fail:
972 dma_async_device_unregister(&d->slave);
973 dma_async_register_fail:
974 clk_disable_unprepare(d->clk);
978 static int k3_dma_remove(struct platform_device *op)
980 struct k3_dma_chan *c, *cn;
981 struct k3_dma_dev *d = platform_get_drvdata(op);
983 dma_async_device_unregister(&d->slave);
984 of_dma_controller_free((&op->dev)->of_node);
986 devm_free_irq(&op->dev, d->irq, d);
988 list_for_each_entry_safe(c, cn, &d->slave.channels, vc.chan.device_node) {
989 list_del(&c->vc.chan.device_node);
990 tasklet_kill(&c->vc.task);
992 tasklet_kill(&d->task);
993 clk_disable_unprepare(d->clk);
997 #ifdef CONFIG_PM_SLEEP
998 static int k3_dma_suspend_dev(struct device *dev)
1000 struct k3_dma_dev *d = dev_get_drvdata(dev);
1003 stat = k3_dma_get_chan_stat(d);
1005 dev_warn(d->slave.dev,
1006 "chan %d is running fail to suspend\n", stat);
1009 k3_dma_enable_dma(d, false);
1010 clk_disable_unprepare(d->clk);
1014 static int k3_dma_resume_dev(struct device *dev)
1016 struct k3_dma_dev *d = dev_get_drvdata(dev);
1019 ret = clk_prepare_enable(d->clk);
1021 dev_err(d->slave.dev, "clk_prepare_enable failed: %d\n", ret);
1024 k3_dma_enable_dma(d, true);
1029 static SIMPLE_DEV_PM_OPS(k3_dma_pmops, k3_dma_suspend_dev, k3_dma_resume_dev);
1031 static struct platform_driver k3_pdma_driver = {
1033 .name = DRIVER_NAME,
1034 .pm = &k3_dma_pmops,
1035 .of_match_table = k3_pdma_dt_ids,
1037 .probe = k3_dma_probe,
1038 .remove = k3_dma_remove,
1041 module_platform_driver(k3_pdma_driver);
1043 MODULE_DESCRIPTION("Hisilicon k3 DMA Driver");
1044 MODULE_ALIAS("platform:k3dma");
1045 MODULE_LICENSE("GPL v2");