2 * This file is provided under a dual BSD/GPLv2 license. When using or
3 * redistributing this file, you may do so under either license.
7 * Copyright(c) 2004 - 2009 Intel Corporation. All rights reserved.
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms and conditions of the GNU General Public License,
11 * version 2, as published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
18 * You should have received a copy of the GNU General Public License along with
19 * this program; if not, write to the Free Software Foundation, Inc.,
20 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
22 * The full GNU General Public License is included in this distribution in
23 * the file called "COPYING".
27 * Copyright(c) 2004-2009 Intel Corporation. All rights reserved.
29 * Redistribution and use in source and binary forms, with or without
30 * modification, are permitted provided that the following conditions are met:
32 * * Redistributions of source code must retain the above copyright
33 * notice, this list of conditions and the following disclaimer.
34 * * Redistributions in binary form must reproduce the above copyright
35 * notice, this list of conditions and the following disclaimer in
36 * the documentation and/or other materials provided with the
38 * * Neither the name of Intel Corporation nor the names of its
39 * contributors may be used to endorse or promote products derived
40 * from this software without specific prior written permission.
42 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
43 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
44 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
45 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
46 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
47 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
48 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
49 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
50 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
51 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
52 * POSSIBILITY OF SUCH DAMAGE.
56 * Support routines for v3+ hardware
59 #include <linux/pci.h>
60 #include <linux/gfp.h>
61 #include <linux/dmaengine.h>
62 #include <linux/dma-mapping.h>
63 #include <linux/prefetch.h>
64 #include "registers.h"
69 /* ioat hardware assumes at least two sources for raid operations */
70 #define src_cnt_to_sw(x) ((x) + 2)
71 #define src_cnt_to_hw(x) ((x) - 2)
73 /* provide a lookup table for setting the source address in the base or
74 * extended descriptor of an xor or pq descriptor
76 static const u8 xor_idx_to_desc = 0xe0;
77 static const u8 xor_idx_to_field[] = { 1, 4, 5, 6, 7, 0, 1, 2 };
78 static const u8 pq_idx_to_desc = 0xf8;
79 static const u8 pq_idx_to_field[] = { 1, 4, 5, 0, 1, 2, 4, 5 };
81 static dma_addr_t xor_get_src(struct ioat_raw_descriptor *descs[2], int idx)
83 struct ioat_raw_descriptor *raw = descs[xor_idx_to_desc >> idx & 1];
85 return raw->field[xor_idx_to_field[idx]];
88 static void xor_set_src(struct ioat_raw_descriptor *descs[2],
89 dma_addr_t addr, u32 offset, int idx)
91 struct ioat_raw_descriptor *raw = descs[xor_idx_to_desc >> idx & 1];
93 raw->field[xor_idx_to_field[idx]] = addr + offset;
96 static dma_addr_t pq_get_src(struct ioat_raw_descriptor *descs[2], int idx)
98 struct ioat_raw_descriptor *raw = descs[pq_idx_to_desc >> idx & 1];
100 return raw->field[pq_idx_to_field[idx]];
103 static void pq_set_src(struct ioat_raw_descriptor *descs[2],
104 dma_addr_t addr, u32 offset, u8 coef, int idx)
106 struct ioat_pq_descriptor *pq = (struct ioat_pq_descriptor *) descs[0];
107 struct ioat_raw_descriptor *raw = descs[pq_idx_to_desc >> idx & 1];
109 raw->field[pq_idx_to_field[idx]] = addr + offset;
110 pq->coef[idx] = coef;
113 static void ioat3_dma_unmap(struct ioat2_dma_chan *ioat,
114 struct ioat_ring_ent *desc, int idx)
116 struct ioat_chan_common *chan = &ioat->base;
117 struct pci_dev *pdev = chan->device->pdev;
118 size_t len = desc->len;
119 size_t offset = len - desc->hw->size;
120 struct dma_async_tx_descriptor *tx = &desc->txd;
121 enum dma_ctrl_flags flags = tx->flags;
123 switch (desc->hw->ctl_f.op) {
125 if (!desc->hw->ctl_f.null) /* skip 'interrupt' ops */
126 ioat_dma_unmap(chan, flags, len, desc->hw);
129 struct ioat_fill_descriptor *hw = desc->fill;
131 if (!(flags & DMA_COMPL_SKIP_DEST_UNMAP))
132 ioat_unmap(pdev, hw->dst_addr - offset, len,
133 PCI_DMA_FROMDEVICE, flags, 1);
136 case IOAT_OP_XOR_VAL:
138 struct ioat_xor_descriptor *xor = desc->xor;
139 struct ioat_ring_ent *ext;
140 struct ioat_xor_ext_descriptor *xor_ex = NULL;
141 int src_cnt = src_cnt_to_sw(xor->ctl_f.src_cnt);
142 struct ioat_raw_descriptor *descs[2];
146 ext = ioat2_get_ring_ent(ioat, idx + 1);
147 xor_ex = ext->xor_ex;
150 if (!(flags & DMA_COMPL_SKIP_SRC_UNMAP)) {
151 descs[0] = (struct ioat_raw_descriptor *) xor;
152 descs[1] = (struct ioat_raw_descriptor *) xor_ex;
153 for (i = 0; i < src_cnt; i++) {
154 dma_addr_t src = xor_get_src(descs, i);
156 ioat_unmap(pdev, src - offset, len,
157 PCI_DMA_TODEVICE, flags, 0);
160 /* dest is a source in xor validate operations */
161 if (xor->ctl_f.op == IOAT_OP_XOR_VAL) {
162 ioat_unmap(pdev, xor->dst_addr - offset, len,
163 PCI_DMA_TODEVICE, flags, 1);
168 if (!(flags & DMA_COMPL_SKIP_DEST_UNMAP))
169 ioat_unmap(pdev, xor->dst_addr - offset, len,
170 PCI_DMA_FROMDEVICE, flags, 1);
175 struct ioat_pq_descriptor *pq = desc->pq;
176 struct ioat_ring_ent *ext;
177 struct ioat_pq_ext_descriptor *pq_ex = NULL;
178 int src_cnt = src_cnt_to_sw(pq->ctl_f.src_cnt);
179 struct ioat_raw_descriptor *descs[2];
183 ext = ioat2_get_ring_ent(ioat, idx + 1);
187 /* in the 'continue' case don't unmap the dests as sources */
188 if (dmaf_p_disabled_continue(flags))
190 else if (dmaf_continue(flags))
193 if (!(flags & DMA_COMPL_SKIP_SRC_UNMAP)) {
194 descs[0] = (struct ioat_raw_descriptor *) pq;
195 descs[1] = (struct ioat_raw_descriptor *) pq_ex;
196 for (i = 0; i < src_cnt; i++) {
197 dma_addr_t src = pq_get_src(descs, i);
199 ioat_unmap(pdev, src - offset, len,
200 PCI_DMA_TODEVICE, flags, 0);
203 /* the dests are sources in pq validate operations */
204 if (pq->ctl_f.op == IOAT_OP_XOR_VAL) {
205 if (!(flags & DMA_PREP_PQ_DISABLE_P))
206 ioat_unmap(pdev, pq->p_addr - offset,
207 len, PCI_DMA_TODEVICE, flags, 0);
208 if (!(flags & DMA_PREP_PQ_DISABLE_Q))
209 ioat_unmap(pdev, pq->q_addr - offset,
210 len, PCI_DMA_TODEVICE, flags, 0);
215 if (!(flags & DMA_COMPL_SKIP_DEST_UNMAP)) {
216 if (!(flags & DMA_PREP_PQ_DISABLE_P))
217 ioat_unmap(pdev, pq->p_addr - offset, len,
218 PCI_DMA_BIDIRECTIONAL, flags, 1);
219 if (!(flags & DMA_PREP_PQ_DISABLE_Q))
220 ioat_unmap(pdev, pq->q_addr - offset, len,
221 PCI_DMA_BIDIRECTIONAL, flags, 1);
226 dev_err(&pdev->dev, "%s: unknown op type: %#x\n",
227 __func__, desc->hw->ctl_f.op);
231 static bool desc_has_ext(struct ioat_ring_ent *desc)
233 struct ioat_dma_descriptor *hw = desc->hw;
235 if (hw->ctl_f.op == IOAT_OP_XOR ||
236 hw->ctl_f.op == IOAT_OP_XOR_VAL) {
237 struct ioat_xor_descriptor *xor = desc->xor;
239 if (src_cnt_to_sw(xor->ctl_f.src_cnt) > 5)
241 } else if (hw->ctl_f.op == IOAT_OP_PQ ||
242 hw->ctl_f.op == IOAT_OP_PQ_VAL) {
243 struct ioat_pq_descriptor *pq = desc->pq;
245 if (src_cnt_to_sw(pq->ctl_f.src_cnt) > 3)
253 * __cleanup - reclaim used descriptors
254 * @ioat: channel (ring) to clean
256 * The difference from the dma_v2.c __cleanup() is that this routine
257 * handles extended descriptors and dma-unmapping raid operations.
259 static void __cleanup(struct ioat2_dma_chan *ioat, unsigned long phys_complete)
261 struct ioat_chan_common *chan = &ioat->base;
262 struct ioat_ring_ent *desc;
263 bool seen_current = false;
264 int idx = ioat->tail, i;
267 dev_dbg(to_dev(chan), "%s: head: %#x tail: %#x issued: %#x\n",
268 __func__, ioat->head, ioat->tail, ioat->issued);
270 active = ioat2_ring_active(ioat);
271 for (i = 0; i < active && !seen_current; i++) {
272 struct dma_async_tx_descriptor *tx;
274 smp_read_barrier_depends();
275 prefetch(ioat2_get_ring_ent(ioat, idx + i + 1));
276 desc = ioat2_get_ring_ent(ioat, idx + i);
277 dump_desc_dbg(ioat, desc);
280 dma_cookie_complete(tx);
281 ioat3_dma_unmap(ioat, desc, idx + i);
283 tx->callback(tx->callback_param);
288 if (tx->phys == phys_complete)
291 /* skip extended descriptors */
292 if (desc_has_ext(desc)) {
293 BUG_ON(i + 1 >= active);
297 smp_mb(); /* finish all descriptor reads before incrementing tail */
298 ioat->tail = idx + i;
299 BUG_ON(active && !seen_current); /* no active descs have written a completion? */
300 chan->last_completion = phys_complete;
302 if (active - i == 0) {
303 dev_dbg(to_dev(chan), "%s: cancel completion timeout\n",
305 clear_bit(IOAT_COMPLETION_PENDING, &chan->state);
306 mod_timer(&chan->timer, jiffies + IDLE_TIMEOUT);
308 /* 5 microsecond delay per pending descriptor */
309 writew(min((5 * (active - i)), IOAT_INTRDELAY_MASK),
310 chan->device->reg_base + IOAT_INTRDELAY_OFFSET);
313 static void ioat3_cleanup(struct ioat2_dma_chan *ioat)
315 struct ioat_chan_common *chan = &ioat->base;
316 unsigned long phys_complete;
318 spin_lock_bh(&chan->cleanup_lock);
319 if (ioat_cleanup_preamble(chan, &phys_complete))
320 __cleanup(ioat, phys_complete);
321 spin_unlock_bh(&chan->cleanup_lock);
324 static void ioat3_cleanup_event(unsigned long data)
326 struct ioat2_dma_chan *ioat = to_ioat2_chan((void *) data);
329 writew(IOAT_CHANCTRL_RUN, ioat->base.reg_base + IOAT_CHANCTRL_OFFSET);
332 static void ioat3_restart_channel(struct ioat2_dma_chan *ioat)
334 struct ioat_chan_common *chan = &ioat->base;
335 unsigned long phys_complete;
337 ioat2_quiesce(chan, 0);
338 if (ioat_cleanup_preamble(chan, &phys_complete))
339 __cleanup(ioat, phys_complete);
341 __ioat2_restart_chan(ioat);
344 static void ioat3_timer_event(unsigned long data)
346 struct ioat2_dma_chan *ioat = to_ioat2_chan((void *) data);
347 struct ioat_chan_common *chan = &ioat->base;
349 if (test_bit(IOAT_COMPLETION_PENDING, &chan->state)) {
350 unsigned long phys_complete;
353 status = ioat_chansts(chan);
355 /* when halted due to errors check for channel
356 * programming errors before advancing the completion state
358 if (is_ioat_halted(status)) {
361 chanerr = readl(chan->reg_base + IOAT_CHANERR_OFFSET);
362 dev_err(to_dev(chan), "%s: Channel halted (%x)\n",
364 if (test_bit(IOAT_RUN, &chan->state))
365 BUG_ON(is_ioat_bug(chanerr));
366 else /* we never got off the ground */
370 /* if we haven't made progress and we have already
371 * acknowledged a pending completion once, then be more
372 * forceful with a restart
374 spin_lock_bh(&chan->cleanup_lock);
375 if (ioat_cleanup_preamble(chan, &phys_complete))
376 __cleanup(ioat, phys_complete);
377 else if (test_bit(IOAT_COMPLETION_ACK, &chan->state)) {
378 spin_lock_bh(&ioat->prep_lock);
379 ioat3_restart_channel(ioat);
380 spin_unlock_bh(&ioat->prep_lock);
382 set_bit(IOAT_COMPLETION_ACK, &chan->state);
383 mod_timer(&chan->timer, jiffies + COMPLETION_TIMEOUT);
385 spin_unlock_bh(&chan->cleanup_lock);
389 /* if the ring is idle, empty, and oversized try to step
392 spin_lock_bh(&chan->cleanup_lock);
393 spin_lock_bh(&ioat->prep_lock);
394 active = ioat2_ring_active(ioat);
395 if (active == 0 && ioat->alloc_order > ioat_get_alloc_order())
396 reshape_ring(ioat, ioat->alloc_order-1);
397 spin_unlock_bh(&ioat->prep_lock);
398 spin_unlock_bh(&chan->cleanup_lock);
400 /* keep shrinking until we get back to our minimum
403 if (ioat->alloc_order > ioat_get_alloc_order())
404 mod_timer(&chan->timer, jiffies + IDLE_TIMEOUT);
408 static enum dma_status
409 ioat3_tx_status(struct dma_chan *c, dma_cookie_t cookie,
410 struct dma_tx_state *txstate)
412 struct ioat2_dma_chan *ioat = to_ioat2_chan(c);
414 if (ioat_tx_status(c, cookie, txstate) == DMA_SUCCESS)
419 return ioat_tx_status(c, cookie, txstate);
422 static struct dma_async_tx_descriptor *
423 ioat3_prep_memset_lock(struct dma_chan *c, dma_addr_t dest, int value,
424 size_t len, unsigned long flags)
426 struct ioat2_dma_chan *ioat = to_ioat2_chan(c);
427 struct ioat_ring_ent *desc;
428 size_t total_len = len;
429 struct ioat_fill_descriptor *fill;
430 u64 src_data = (0x0101010101010101ULL) * (value & 0xff);
431 int num_descs, idx, i;
433 num_descs = ioat2_xferlen_to_descs(ioat, len);
434 if (likely(num_descs) && ioat2_check_space_lock(ioat, num_descs) == 0)
440 size_t xfer_size = min_t(size_t, len, 1 << ioat->xfercap_log);
442 desc = ioat2_get_ring_ent(ioat, idx + i);
445 fill->size = xfer_size;
446 fill->src_data = src_data;
447 fill->dst_addr = dest;
449 fill->ctl_f.op = IOAT_OP_FILL;
453 dump_desc_dbg(ioat, desc);
454 } while (++i < num_descs);
456 desc->txd.flags = flags;
457 desc->len = total_len;
458 fill->ctl_f.int_en = !!(flags & DMA_PREP_INTERRUPT);
459 fill->ctl_f.fence = !!(flags & DMA_PREP_FENCE);
460 fill->ctl_f.compl_write = 1;
461 dump_desc_dbg(ioat, desc);
463 /* we leave the channel locked to ensure in order submission */
467 static struct dma_async_tx_descriptor *
468 __ioat3_prep_xor_lock(struct dma_chan *c, enum sum_check_flags *result,
469 dma_addr_t dest, dma_addr_t *src, unsigned int src_cnt,
470 size_t len, unsigned long flags)
472 struct ioat2_dma_chan *ioat = to_ioat2_chan(c);
473 struct ioat_ring_ent *compl_desc;
474 struct ioat_ring_ent *desc;
475 struct ioat_ring_ent *ext;
476 size_t total_len = len;
477 struct ioat_xor_descriptor *xor;
478 struct ioat_xor_ext_descriptor *xor_ex = NULL;
479 struct ioat_dma_descriptor *hw;
480 int num_descs, with_ext, idx, i;
482 u8 op = result ? IOAT_OP_XOR_VAL : IOAT_OP_XOR;
486 num_descs = ioat2_xferlen_to_descs(ioat, len);
487 /* we need 2x the number of descriptors to cover greater than 5
496 /* completion writes from the raid engine may pass completion
497 * writes from the legacy engine, so we need one extra null
498 * (legacy) descriptor to ensure all completion writes arrive in
501 if (likely(num_descs) && ioat2_check_space_lock(ioat, num_descs+1) == 0)
507 struct ioat_raw_descriptor *descs[2];
508 size_t xfer_size = min_t(size_t, len, 1 << ioat->xfercap_log);
511 desc = ioat2_get_ring_ent(ioat, idx + i);
514 /* save a branch by unconditionally retrieving the
515 * extended descriptor xor_set_src() knows to not write
516 * to it in the single descriptor case
518 ext = ioat2_get_ring_ent(ioat, idx + i + 1);
519 xor_ex = ext->xor_ex;
521 descs[0] = (struct ioat_raw_descriptor *) xor;
522 descs[1] = (struct ioat_raw_descriptor *) xor_ex;
523 for (s = 0; s < src_cnt; s++)
524 xor_set_src(descs, src[s], offset, s);
525 xor->size = xfer_size;
526 xor->dst_addr = dest + offset;
529 xor->ctl_f.src_cnt = src_cnt_to_hw(src_cnt);
533 dump_desc_dbg(ioat, desc);
534 } while ((i += 1 + with_ext) < num_descs);
536 /* last xor descriptor carries the unmap parameters and fence bit */
537 desc->txd.flags = flags;
538 desc->len = total_len;
540 desc->result = result;
541 xor->ctl_f.fence = !!(flags & DMA_PREP_FENCE);
543 /* completion descriptor carries interrupt bit */
544 compl_desc = ioat2_get_ring_ent(ioat, idx + i);
545 compl_desc->txd.flags = flags & DMA_PREP_INTERRUPT;
549 hw->ctl_f.int_en = !!(flags & DMA_PREP_INTERRUPT);
550 hw->ctl_f.compl_write = 1;
551 hw->size = NULL_DESC_BUFFER_SIZE;
552 dump_desc_dbg(ioat, compl_desc);
554 /* we leave the channel locked to ensure in order submission */
555 return &compl_desc->txd;
558 static struct dma_async_tx_descriptor *
559 ioat3_prep_xor(struct dma_chan *chan, dma_addr_t dest, dma_addr_t *src,
560 unsigned int src_cnt, size_t len, unsigned long flags)
562 return __ioat3_prep_xor_lock(chan, NULL, dest, src, src_cnt, len, flags);
565 struct dma_async_tx_descriptor *
566 ioat3_prep_xor_val(struct dma_chan *chan, dma_addr_t *src,
567 unsigned int src_cnt, size_t len,
568 enum sum_check_flags *result, unsigned long flags)
570 /* the cleanup routine only sets bits on validate failure, it
571 * does not clear bits on validate success... so clear it here
575 return __ioat3_prep_xor_lock(chan, result, src[0], &src[1],
576 src_cnt - 1, len, flags);
580 dump_pq_desc_dbg(struct ioat2_dma_chan *ioat, struct ioat_ring_ent *desc, struct ioat_ring_ent *ext)
582 struct device *dev = to_dev(&ioat->base);
583 struct ioat_pq_descriptor *pq = desc->pq;
584 struct ioat_pq_ext_descriptor *pq_ex = ext ? ext->pq_ex : NULL;
585 struct ioat_raw_descriptor *descs[] = { (void *) pq, (void *) pq_ex };
586 int src_cnt = src_cnt_to_sw(pq->ctl_f.src_cnt);
589 dev_dbg(dev, "desc[%d]: (%#llx->%#llx) flags: %#x"
590 " sz: %#x ctl: %#x (op: %d int: %d compl: %d pq: '%s%s' src_cnt: %d)\n",
591 desc_id(desc), (unsigned long long) desc->txd.phys,
592 (unsigned long long) (pq_ex ? pq_ex->next : pq->next),
593 desc->txd.flags, pq->size, pq->ctl, pq->ctl_f.op, pq->ctl_f.int_en,
594 pq->ctl_f.compl_write,
595 pq->ctl_f.p_disable ? "" : "p", pq->ctl_f.q_disable ? "" : "q",
597 for (i = 0; i < src_cnt; i++)
598 dev_dbg(dev, "\tsrc[%d]: %#llx coef: %#x\n", i,
599 (unsigned long long) pq_get_src(descs, i), pq->coef[i]);
600 dev_dbg(dev, "\tP: %#llx\n", pq->p_addr);
601 dev_dbg(dev, "\tQ: %#llx\n", pq->q_addr);
604 static struct dma_async_tx_descriptor *
605 __ioat3_prep_pq_lock(struct dma_chan *c, enum sum_check_flags *result,
606 const dma_addr_t *dst, const dma_addr_t *src,
607 unsigned int src_cnt, const unsigned char *scf,
608 size_t len, unsigned long flags)
610 struct ioat2_dma_chan *ioat = to_ioat2_chan(c);
611 struct ioat_chan_common *chan = &ioat->base;
612 struct ioat_ring_ent *compl_desc;
613 struct ioat_ring_ent *desc;
614 struct ioat_ring_ent *ext;
615 size_t total_len = len;
616 struct ioat_pq_descriptor *pq;
617 struct ioat_pq_ext_descriptor *pq_ex = NULL;
618 struct ioat_dma_descriptor *hw;
620 u8 op = result ? IOAT_OP_PQ_VAL : IOAT_OP_PQ;
621 int i, s, idx, with_ext, num_descs;
623 dev_dbg(to_dev(chan), "%s\n", __func__);
624 /* the engine requires at least two sources (we provide
625 * at least 1 implied source in the DMA_PREP_CONTINUE case)
627 BUG_ON(src_cnt + dmaf_continue(flags) < 2);
629 num_descs = ioat2_xferlen_to_descs(ioat, len);
630 /* we need 2x the number of descriptors to cover greater than 3
631 * sources (we need 1 extra source in the q-only continuation
632 * case and 3 extra sources in the p+q continuation case.
634 if (src_cnt + dmaf_p_disabled_continue(flags) > 3 ||
635 (dmaf_continue(flags) && !dmaf_p_disabled_continue(flags))) {
641 /* completion writes from the raid engine may pass completion
642 * writes from the legacy engine, so we need one extra null
643 * (legacy) descriptor to ensure all completion writes arrive in
646 if (likely(num_descs) &&
647 ioat2_check_space_lock(ioat, num_descs+1) == 0)
653 struct ioat_raw_descriptor *descs[2];
654 size_t xfer_size = min_t(size_t, len, 1 << ioat->xfercap_log);
656 desc = ioat2_get_ring_ent(ioat, idx + i);
659 /* save a branch by unconditionally retrieving the
660 * extended descriptor pq_set_src() knows to not write
661 * to it in the single descriptor case
663 ext = ioat2_get_ring_ent(ioat, idx + i + with_ext);
666 descs[0] = (struct ioat_raw_descriptor *) pq;
667 descs[1] = (struct ioat_raw_descriptor *) pq_ex;
669 for (s = 0; s < src_cnt; s++)
670 pq_set_src(descs, src[s], offset, scf[s], s);
672 /* see the comment for dma_maxpq in include/linux/dmaengine.h */
673 if (dmaf_p_disabled_continue(flags))
674 pq_set_src(descs, dst[1], offset, 1, s++);
675 else if (dmaf_continue(flags)) {
676 pq_set_src(descs, dst[0], offset, 0, s++);
677 pq_set_src(descs, dst[1], offset, 1, s++);
678 pq_set_src(descs, dst[1], offset, 0, s++);
680 pq->size = xfer_size;
681 pq->p_addr = dst[0] + offset;
682 pq->q_addr = dst[1] + offset;
685 pq->ctl_f.src_cnt = src_cnt_to_hw(s);
686 pq->ctl_f.p_disable = !!(flags & DMA_PREP_PQ_DISABLE_P);
687 pq->ctl_f.q_disable = !!(flags & DMA_PREP_PQ_DISABLE_Q);
691 } while ((i += 1 + with_ext) < num_descs);
693 /* last pq descriptor carries the unmap parameters and fence bit */
694 desc->txd.flags = flags;
695 desc->len = total_len;
697 desc->result = result;
698 pq->ctl_f.fence = !!(flags & DMA_PREP_FENCE);
699 dump_pq_desc_dbg(ioat, desc, ext);
701 /* completion descriptor carries interrupt bit */
702 compl_desc = ioat2_get_ring_ent(ioat, idx + i);
703 compl_desc->txd.flags = flags & DMA_PREP_INTERRUPT;
707 hw->ctl_f.int_en = !!(flags & DMA_PREP_INTERRUPT);
708 hw->ctl_f.compl_write = 1;
709 hw->size = NULL_DESC_BUFFER_SIZE;
710 dump_desc_dbg(ioat, compl_desc);
712 /* we leave the channel locked to ensure in order submission */
713 return &compl_desc->txd;
716 static struct dma_async_tx_descriptor *
717 ioat3_prep_pq(struct dma_chan *chan, dma_addr_t *dst, dma_addr_t *src,
718 unsigned int src_cnt, const unsigned char *scf, size_t len,
721 /* specify valid address for disabled result */
722 if (flags & DMA_PREP_PQ_DISABLE_P)
724 if (flags & DMA_PREP_PQ_DISABLE_Q)
727 /* handle the single source multiply case from the raid6
730 if ((flags & DMA_PREP_PQ_DISABLE_P) && src_cnt == 1) {
731 dma_addr_t single_source[2];
732 unsigned char single_source_coef[2];
734 BUG_ON(flags & DMA_PREP_PQ_DISABLE_Q);
735 single_source[0] = src[0];
736 single_source[1] = src[0];
737 single_source_coef[0] = scf[0];
738 single_source_coef[1] = 0;
740 return __ioat3_prep_pq_lock(chan, NULL, dst, single_source, 2,
741 single_source_coef, len, flags);
743 return __ioat3_prep_pq_lock(chan, NULL, dst, src, src_cnt, scf,
747 struct dma_async_tx_descriptor *
748 ioat3_prep_pq_val(struct dma_chan *chan, dma_addr_t *pq, dma_addr_t *src,
749 unsigned int src_cnt, const unsigned char *scf, size_t len,
750 enum sum_check_flags *pqres, unsigned long flags)
752 /* specify valid address for disabled result */
753 if (flags & DMA_PREP_PQ_DISABLE_P)
755 if (flags & DMA_PREP_PQ_DISABLE_Q)
758 /* the cleanup routine only sets bits on validate failure, it
759 * does not clear bits on validate success... so clear it here
763 return __ioat3_prep_pq_lock(chan, pqres, pq, src, src_cnt, scf, len,
767 static struct dma_async_tx_descriptor *
768 ioat3_prep_pqxor(struct dma_chan *chan, dma_addr_t dst, dma_addr_t *src,
769 unsigned int src_cnt, size_t len, unsigned long flags)
771 unsigned char scf[src_cnt];
774 memset(scf, 0, src_cnt);
776 flags |= DMA_PREP_PQ_DISABLE_Q;
777 pq[1] = dst; /* specify valid address for disabled result */
779 return __ioat3_prep_pq_lock(chan, NULL, pq, src, src_cnt, scf, len,
783 struct dma_async_tx_descriptor *
784 ioat3_prep_pqxor_val(struct dma_chan *chan, dma_addr_t *src,
785 unsigned int src_cnt, size_t len,
786 enum sum_check_flags *result, unsigned long flags)
788 unsigned char scf[src_cnt];
791 /* the cleanup routine only sets bits on validate failure, it
792 * does not clear bits on validate success... so clear it here
796 memset(scf, 0, src_cnt);
798 flags |= DMA_PREP_PQ_DISABLE_Q;
799 pq[1] = pq[0]; /* specify valid address for disabled result */
801 return __ioat3_prep_pq_lock(chan, result, pq, &src[1], src_cnt - 1, scf,
805 static struct dma_async_tx_descriptor *
806 ioat3_prep_interrupt_lock(struct dma_chan *c, unsigned long flags)
808 struct ioat2_dma_chan *ioat = to_ioat2_chan(c);
809 struct ioat_ring_ent *desc;
810 struct ioat_dma_descriptor *hw;
812 if (ioat2_check_space_lock(ioat, 1) == 0)
813 desc = ioat2_get_ring_ent(ioat, ioat->head);
820 hw->ctl_f.int_en = 1;
821 hw->ctl_f.fence = !!(flags & DMA_PREP_FENCE);
822 hw->ctl_f.compl_write = 1;
823 hw->size = NULL_DESC_BUFFER_SIZE;
827 desc->txd.flags = flags;
830 dump_desc_dbg(ioat, desc);
832 /* we leave the channel locked to ensure in order submission */
836 static void __devinit ioat3_dma_test_callback(void *dma_async_param)
838 struct completion *cmp = dma_async_param;
843 #define IOAT_NUM_SRC_TEST 6 /* must be <= 8 */
844 static int __devinit ioat_xor_val_self_test(struct ioatdma_device *device)
848 struct page *xor_srcs[IOAT_NUM_SRC_TEST];
849 struct page *xor_val_srcs[IOAT_NUM_SRC_TEST + 1];
850 dma_addr_t dma_srcs[IOAT_NUM_SRC_TEST + 1];
851 dma_addr_t dma_addr, dest_dma;
852 struct dma_async_tx_descriptor *tx;
853 struct dma_chan *dma_chan;
859 struct completion cmp;
861 struct device *dev = &device->pdev->dev;
862 struct dma_device *dma = &device->common;
864 dev_dbg(dev, "%s\n", __func__);
866 if (!dma_has_cap(DMA_XOR, dma->cap_mask))
869 for (src_idx = 0; src_idx < IOAT_NUM_SRC_TEST; src_idx++) {
870 xor_srcs[src_idx] = alloc_page(GFP_KERNEL);
871 if (!xor_srcs[src_idx]) {
873 __free_page(xor_srcs[src_idx]);
878 dest = alloc_page(GFP_KERNEL);
881 __free_page(xor_srcs[src_idx]);
885 /* Fill in src buffers */
886 for (src_idx = 0; src_idx < IOAT_NUM_SRC_TEST; src_idx++) {
887 u8 *ptr = page_address(xor_srcs[src_idx]);
888 for (i = 0; i < PAGE_SIZE; i++)
889 ptr[i] = (1 << src_idx);
892 for (src_idx = 0; src_idx < IOAT_NUM_SRC_TEST; src_idx++)
893 cmp_byte ^= (u8) (1 << src_idx);
895 cmp_word = (cmp_byte << 24) | (cmp_byte << 16) |
896 (cmp_byte << 8) | cmp_byte;
898 memset(page_address(dest), 0, PAGE_SIZE);
900 dma_chan = container_of(dma->channels.next, struct dma_chan,
902 if (dma->device_alloc_chan_resources(dma_chan) < 1) {
908 dest_dma = dma_map_page(dev, dest, 0, PAGE_SIZE, DMA_FROM_DEVICE);
909 for (i = 0; i < IOAT_NUM_SRC_TEST; i++)
910 dma_srcs[i] = dma_map_page(dev, xor_srcs[i], 0, PAGE_SIZE,
912 tx = dma->device_prep_dma_xor(dma_chan, dest_dma, dma_srcs,
913 IOAT_NUM_SRC_TEST, PAGE_SIZE,
917 dev_err(dev, "Self-test xor prep failed\n");
923 init_completion(&cmp);
924 tx->callback = ioat3_dma_test_callback;
925 tx->callback_param = &cmp;
926 cookie = tx->tx_submit(tx);
928 dev_err(dev, "Self-test xor setup failed\n");
932 dma->device_issue_pending(dma_chan);
934 tmo = wait_for_completion_timeout(&cmp, msecs_to_jiffies(3000));
936 if (dma->device_tx_status(dma_chan, cookie, NULL) != DMA_SUCCESS) {
937 dev_err(dev, "Self-test xor timed out\n");
942 dma_sync_single_for_cpu(dev, dest_dma, PAGE_SIZE, DMA_FROM_DEVICE);
943 for (i = 0; i < (PAGE_SIZE / sizeof(u32)); i++) {
944 u32 *ptr = page_address(dest);
945 if (ptr[i] != cmp_word) {
946 dev_err(dev, "Self-test xor failed compare\n");
951 dma_sync_single_for_device(dev, dest_dma, PAGE_SIZE, DMA_TO_DEVICE);
953 /* skip validate if the capability is not present */
954 if (!dma_has_cap(DMA_XOR_VAL, dma_chan->device->cap_mask))
957 /* validate the sources with the destintation page */
958 for (i = 0; i < IOAT_NUM_SRC_TEST; i++)
959 xor_val_srcs[i] = xor_srcs[i];
960 xor_val_srcs[i] = dest;
964 for (i = 0; i < IOAT_NUM_SRC_TEST + 1; i++)
965 dma_srcs[i] = dma_map_page(dev, xor_val_srcs[i], 0, PAGE_SIZE,
967 tx = dma->device_prep_dma_xor_val(dma_chan, dma_srcs,
968 IOAT_NUM_SRC_TEST + 1, PAGE_SIZE,
969 &xor_val_result, DMA_PREP_INTERRUPT);
971 dev_err(dev, "Self-test zero prep failed\n");
977 init_completion(&cmp);
978 tx->callback = ioat3_dma_test_callback;
979 tx->callback_param = &cmp;
980 cookie = tx->tx_submit(tx);
982 dev_err(dev, "Self-test zero setup failed\n");
986 dma->device_issue_pending(dma_chan);
988 tmo = wait_for_completion_timeout(&cmp, msecs_to_jiffies(3000));
990 if (dma->device_tx_status(dma_chan, cookie, NULL) != DMA_SUCCESS) {
991 dev_err(dev, "Self-test validate timed out\n");
996 if (xor_val_result != 0) {
997 dev_err(dev, "Self-test validate failed compare\n");
1002 /* skip memset if the capability is not present */
1003 if (!dma_has_cap(DMA_MEMSET, dma_chan->device->cap_mask))
1004 goto free_resources;
1007 dma_addr = dma_map_page(dev, dest, 0,
1008 PAGE_SIZE, DMA_FROM_DEVICE);
1009 tx = dma->device_prep_dma_memset(dma_chan, dma_addr, 0, PAGE_SIZE,
1010 DMA_PREP_INTERRUPT);
1012 dev_err(dev, "Self-test memset prep failed\n");
1014 goto free_resources;
1018 init_completion(&cmp);
1019 tx->callback = ioat3_dma_test_callback;
1020 tx->callback_param = &cmp;
1021 cookie = tx->tx_submit(tx);
1023 dev_err(dev, "Self-test memset setup failed\n");
1025 goto free_resources;
1027 dma->device_issue_pending(dma_chan);
1029 tmo = wait_for_completion_timeout(&cmp, msecs_to_jiffies(3000));
1031 if (dma->device_tx_status(dma_chan, cookie, NULL) != DMA_SUCCESS) {
1032 dev_err(dev, "Self-test memset timed out\n");
1034 goto free_resources;
1037 for (i = 0; i < PAGE_SIZE/sizeof(u32); i++) {
1038 u32 *ptr = page_address(dest);
1040 dev_err(dev, "Self-test memset failed compare\n");
1042 goto free_resources;
1046 /* test for non-zero parity sum */
1048 for (i = 0; i < IOAT_NUM_SRC_TEST + 1; i++)
1049 dma_srcs[i] = dma_map_page(dev, xor_val_srcs[i], 0, PAGE_SIZE,
1051 tx = dma->device_prep_dma_xor_val(dma_chan, dma_srcs,
1052 IOAT_NUM_SRC_TEST + 1, PAGE_SIZE,
1053 &xor_val_result, DMA_PREP_INTERRUPT);
1055 dev_err(dev, "Self-test 2nd zero prep failed\n");
1057 goto free_resources;
1061 init_completion(&cmp);
1062 tx->callback = ioat3_dma_test_callback;
1063 tx->callback_param = &cmp;
1064 cookie = tx->tx_submit(tx);
1066 dev_err(dev, "Self-test 2nd zero setup failed\n");
1068 goto free_resources;
1070 dma->device_issue_pending(dma_chan);
1072 tmo = wait_for_completion_timeout(&cmp, msecs_to_jiffies(3000));
1074 if (dma->device_tx_status(dma_chan, cookie, NULL) != DMA_SUCCESS) {
1075 dev_err(dev, "Self-test 2nd validate timed out\n");
1077 goto free_resources;
1080 if (xor_val_result != SUM_CHECK_P_RESULT) {
1081 dev_err(dev, "Self-test validate failed compare\n");
1083 goto free_resources;
1087 dma->device_free_chan_resources(dma_chan);
1089 src_idx = IOAT_NUM_SRC_TEST;
1091 __free_page(xor_srcs[src_idx]);
1096 static int __devinit ioat3_dma_self_test(struct ioatdma_device *device)
1098 int rc = ioat_dma_self_test(device);
1103 rc = ioat_xor_val_self_test(device);
1110 static int ioat3_reset_hw(struct ioat_chan_common *chan)
1112 /* throw away whatever the channel was doing and get it
1113 * initialized, with ioat3 specific workarounds
1115 struct ioatdma_device *device = chan->device;
1116 struct pci_dev *pdev = device->pdev;
1121 ioat2_quiesce(chan, msecs_to_jiffies(100));
1123 chanerr = readl(chan->reg_base + IOAT_CHANERR_OFFSET);
1124 writel(chanerr, chan->reg_base + IOAT_CHANERR_OFFSET);
1126 /* -= IOAT ver.3 workarounds =- */
1127 /* Write CHANERRMSK_INT with 3E07h to mask out the errors
1128 * that can cause stability issues for IOAT ver.3, and clear any
1131 pci_write_config_dword(pdev, IOAT_PCI_CHANERRMASK_INT_OFFSET, 0x3e07);
1132 err = pci_read_config_dword(pdev, IOAT_PCI_CHANERR_INT_OFFSET, &chanerr);
1134 dev_err(&pdev->dev, "channel error register unreachable\n");
1137 pci_write_config_dword(pdev, IOAT_PCI_CHANERR_INT_OFFSET, chanerr);
1139 /* Clear DMAUNCERRSTS Cfg-Reg Parity Error status bit
1140 * (workaround for spurious config parity error after restart)
1142 pci_read_config_word(pdev, IOAT_PCI_DEVICE_ID_OFFSET, &dev_id);
1143 if (dev_id == PCI_DEVICE_ID_INTEL_IOAT_TBG0)
1144 pci_write_config_dword(pdev, IOAT_PCI_DMAUNCERRSTS_OFFSET, 0x10);
1146 return ioat2_reset_sync(chan, msecs_to_jiffies(200));
1149 int __devinit ioat3_dma_probe(struct ioatdma_device *device, int dca)
1151 struct pci_dev *pdev = device->pdev;
1152 int dca_en = system_has_dca_enabled(pdev);
1153 struct dma_device *dma;
1155 struct ioat_chan_common *chan;
1156 bool is_raid_device = false;
1160 device->enumerate_channels = ioat2_enumerate_channels;
1161 device->reset_hw = ioat3_reset_hw;
1162 device->self_test = ioat3_dma_self_test;
1163 dma = &device->common;
1164 dma->device_prep_dma_memcpy = ioat2_dma_prep_memcpy_lock;
1165 dma->device_issue_pending = ioat2_issue_pending;
1166 dma->device_alloc_chan_resources = ioat2_alloc_chan_resources;
1167 dma->device_free_chan_resources = ioat2_free_chan_resources;
1169 dma_cap_set(DMA_INTERRUPT, dma->cap_mask);
1170 dma->device_prep_dma_interrupt = ioat3_prep_interrupt_lock;
1172 cap = readl(device->reg_base + IOAT_DMA_CAP_OFFSET);
1174 /* dca is incompatible with raid operations */
1175 if (dca_en && (cap & (IOAT_CAP_XOR|IOAT_CAP_PQ)))
1176 cap &= ~(IOAT_CAP_XOR|IOAT_CAP_PQ);
1178 if (cap & IOAT_CAP_XOR) {
1179 is_raid_device = true;
1183 dma_cap_set(DMA_XOR, dma->cap_mask);
1184 dma->device_prep_dma_xor = ioat3_prep_xor;
1186 dma_cap_set(DMA_XOR_VAL, dma->cap_mask);
1187 dma->device_prep_dma_xor_val = ioat3_prep_xor_val;
1189 if (cap & IOAT_CAP_PQ) {
1190 is_raid_device = true;
1191 dma_set_maxpq(dma, 8, 0);
1194 dma_cap_set(DMA_PQ, dma->cap_mask);
1195 dma->device_prep_dma_pq = ioat3_prep_pq;
1197 dma_cap_set(DMA_PQ_VAL, dma->cap_mask);
1198 dma->device_prep_dma_pq_val = ioat3_prep_pq_val;
1200 if (!(cap & IOAT_CAP_XOR)) {
1204 dma_cap_set(DMA_XOR, dma->cap_mask);
1205 dma->device_prep_dma_xor = ioat3_prep_pqxor;
1207 dma_cap_set(DMA_XOR_VAL, dma->cap_mask);
1208 dma->device_prep_dma_xor_val = ioat3_prep_pqxor_val;
1211 if (is_raid_device && (cap & IOAT_CAP_FILL_BLOCK)) {
1212 dma_cap_set(DMA_MEMSET, dma->cap_mask);
1213 dma->device_prep_dma_memset = ioat3_prep_memset_lock;
1217 if (is_raid_device) {
1218 dma->device_tx_status = ioat3_tx_status;
1219 device->cleanup_fn = ioat3_cleanup_event;
1220 device->timer_fn = ioat3_timer_event;
1222 dma->device_tx_status = ioat_dma_tx_status;
1223 device->cleanup_fn = ioat2_cleanup_event;
1224 device->timer_fn = ioat2_timer_event;
1227 #ifdef CONFIG_ASYNC_TX_DISABLE_PQ_VAL_DMA
1228 dma_cap_clear(DMA_PQ_VAL, dma->cap_mask);
1229 dma->device_prep_dma_pq_val = NULL;
1232 #ifdef CONFIG_ASYNC_TX_DISABLE_XOR_VAL_DMA
1233 dma_cap_clear(DMA_XOR_VAL, dma->cap_mask);
1234 dma->device_prep_dma_xor_val = NULL;
1237 err = ioat_probe(device);
1240 ioat_set_tcp_copy_break(262144);
1242 list_for_each_entry(c, &dma->channels, device_node) {
1243 chan = to_chan_common(c);
1244 writel(IOAT_DMA_DCA_ANY_CPU,
1245 chan->reg_base + IOAT_DCACTRL_OFFSET);
1248 err = ioat_register(device);
1252 ioat_kobject_add(device, &ioat2_ktype);
1255 device->dca = ioat3_dca_init(pdev, device->reg_base);