2 * Intel I/OAT DMA Linux driver
3 * Copyright(c) 2004 - 2009 Intel Corporation.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
24 * This driver supports an Intel I/OAT DMA engine, which does asynchronous
28 #include <linux/init.h>
29 #include <linux/module.h>
30 #include <linux/slab.h>
31 #include <linux/pci.h>
32 #include <linux/interrupt.h>
33 #include <linux/dmaengine.h>
34 #include <linux/delay.h>
35 #include <linux/dma-mapping.h>
36 #include <linux/workqueue.h>
37 #include <linux/prefetch.h>
38 #include <linux/i7300_idle.h>
40 #include "registers.h"
43 #include "../dmaengine.h"
45 int ioat_pending_level = 4;
46 module_param(ioat_pending_level, int, 0644);
47 MODULE_PARM_DESC(ioat_pending_level,
48 "high-water mark for pushing ioat descriptors (default: 4)");
50 /* internal functions */
51 static void ioat1_cleanup(struct ioat_dma_chan *ioat);
52 static void ioat1_dma_start_null_desc(struct ioat_dma_chan *ioat);
55 * ioat_dma_do_interrupt - handler used for single vector interrupt mode
57 * @data: interrupt data
59 static irqreturn_t ioat_dma_do_interrupt(int irq, void *data)
61 struct ioatdma_device *instance = data;
62 struct ioat_chan_common *chan;
63 unsigned long attnstatus;
67 intrctrl = readb(instance->reg_base + IOAT_INTRCTRL_OFFSET);
69 if (!(intrctrl & IOAT_INTRCTRL_MASTER_INT_EN))
72 if (!(intrctrl & IOAT_INTRCTRL_INT_STATUS)) {
73 writeb(intrctrl, instance->reg_base + IOAT_INTRCTRL_OFFSET);
77 attnstatus = readl(instance->reg_base + IOAT_ATTNSTATUS_OFFSET);
78 for_each_set_bit(bit, &attnstatus, BITS_PER_LONG) {
79 chan = ioat_chan_by_index(instance, bit);
80 tasklet_schedule(&chan->cleanup_task);
83 writeb(intrctrl, instance->reg_base + IOAT_INTRCTRL_OFFSET);
88 * ioat_dma_do_interrupt_msix - handler used for vector-per-channel interrupt mode
90 * @data: interrupt data
92 static irqreturn_t ioat_dma_do_interrupt_msix(int irq, void *data)
94 struct ioat_chan_common *chan = data;
96 tasklet_schedule(&chan->cleanup_task);
101 /* common channel initialization */
102 void ioat_init_channel(struct ioatdma_device *device, struct ioat_chan_common *chan, int idx)
104 struct dma_device *dma = &device->common;
105 struct dma_chan *c = &chan->common;
106 unsigned long data = (unsigned long) c;
108 chan->device = device;
109 chan->reg_base = device->reg_base + (0x80 * (idx + 1));
110 spin_lock_init(&chan->cleanup_lock);
111 chan->common.device = dma;
112 list_add_tail(&chan->common.device_node, &dma->channels);
113 device->idx[idx] = chan;
114 init_timer(&chan->timer);
115 chan->timer.function = device->timer_fn;
116 chan->timer.data = data;
117 tasklet_init(&chan->cleanup_task, device->cleanup_fn, data);
118 tasklet_disable(&chan->cleanup_task);
122 * ioat1_dma_enumerate_channels - find and initialize the device's channels
123 * @device: the device to be enumerated
125 static int ioat1_enumerate_channels(struct ioatdma_device *device)
130 struct ioat_dma_chan *ioat;
131 struct device *dev = &device->pdev->dev;
132 struct dma_device *dma = &device->common;
134 INIT_LIST_HEAD(&dma->channels);
135 dma->chancnt = readb(device->reg_base + IOAT_CHANCNT_OFFSET);
136 dma->chancnt &= 0x1f; /* bits [4:0] valid */
137 if (dma->chancnt > ARRAY_SIZE(device->idx)) {
138 dev_warn(dev, "(%d) exceeds max supported channels (%zu)\n",
139 dma->chancnt, ARRAY_SIZE(device->idx));
140 dma->chancnt = ARRAY_SIZE(device->idx);
142 xfercap_scale = readb(device->reg_base + IOAT_XFERCAP_OFFSET);
143 xfercap_scale &= 0x1f; /* bits [4:0] valid */
144 xfercap = (xfercap_scale == 0 ? -1 : (1UL << xfercap_scale));
145 dev_dbg(dev, "%s: xfercap = %d\n", __func__, xfercap);
147 #ifdef CONFIG_I7300_IDLE_IOAT_CHANNEL
148 if (i7300_idle_platform_probe(NULL, NULL, 1) == 0)
151 for (i = 0; i < dma->chancnt; i++) {
152 ioat = devm_kzalloc(dev, sizeof(*ioat), GFP_KERNEL);
156 ioat_init_channel(device, &ioat->base, i);
157 ioat->xfercap = xfercap;
158 spin_lock_init(&ioat->desc_lock);
159 INIT_LIST_HEAD(&ioat->free_desc);
160 INIT_LIST_HEAD(&ioat->used_desc);
167 * ioat_dma_memcpy_issue_pending - push potentially unrecognized appended
169 * @chan: DMA channel handle
172 __ioat1_dma_memcpy_issue_pending(struct ioat_dma_chan *ioat)
174 void __iomem *reg_base = ioat->base.reg_base;
176 dev_dbg(to_dev(&ioat->base), "%s: pending: %d\n",
177 __func__, ioat->pending);
179 writeb(IOAT_CHANCMD_APPEND, reg_base + IOAT1_CHANCMD_OFFSET);
182 static void ioat1_dma_memcpy_issue_pending(struct dma_chan *chan)
184 struct ioat_dma_chan *ioat = to_ioat_chan(chan);
186 if (ioat->pending > 0) {
187 spin_lock_bh(&ioat->desc_lock);
188 __ioat1_dma_memcpy_issue_pending(ioat);
189 spin_unlock_bh(&ioat->desc_lock);
194 * ioat1_reset_channel - restart a channel
195 * @ioat: IOAT DMA channel handle
197 static void ioat1_reset_channel(struct ioat_dma_chan *ioat)
199 struct ioat_chan_common *chan = &ioat->base;
200 void __iomem *reg_base = chan->reg_base;
201 u32 chansts, chanerr;
203 dev_warn(to_dev(chan), "reset\n");
204 chanerr = readl(reg_base + IOAT_CHANERR_OFFSET);
205 chansts = *chan->completion & IOAT_CHANSTS_STATUS;
207 dev_err(to_dev(chan),
208 "chan%d, CHANSTS = 0x%08x CHANERR = 0x%04x, clearing\n",
209 chan_num(chan), chansts, chanerr);
210 writel(chanerr, reg_base + IOAT_CHANERR_OFFSET);
214 * whack it upside the head with a reset
215 * and wait for things to settle out.
216 * force the pending count to a really big negative
217 * to make sure no one forces an issue_pending
218 * while we're waiting.
221 ioat->pending = INT_MIN;
222 writeb(IOAT_CHANCMD_RESET,
223 reg_base + IOAT_CHANCMD_OFFSET(chan->device->version));
224 set_bit(IOAT_RESET_PENDING, &chan->state);
225 mod_timer(&chan->timer, jiffies + RESET_DELAY);
228 static dma_cookie_t ioat1_tx_submit(struct dma_async_tx_descriptor *tx)
230 struct dma_chan *c = tx->chan;
231 struct ioat_dma_chan *ioat = to_ioat_chan(c);
232 struct ioat_desc_sw *desc = tx_to_ioat_desc(tx);
233 struct ioat_chan_common *chan = &ioat->base;
234 struct ioat_desc_sw *first;
235 struct ioat_desc_sw *chain_tail;
238 spin_lock_bh(&ioat->desc_lock);
239 /* cookie incr and addition to used_list must be atomic */
240 cookie = dma_cookie_assign(tx);
241 dev_dbg(to_dev(&ioat->base), "%s: cookie: %d\n", __func__, cookie);
243 /* write address into NextDescriptor field of last desc in chain */
244 first = to_ioat_desc(desc->tx_list.next);
245 chain_tail = to_ioat_desc(ioat->used_desc.prev);
246 /* make descriptor updates globally visible before chaining */
248 chain_tail->hw->next = first->txd.phys;
249 list_splice_tail_init(&desc->tx_list, &ioat->used_desc);
250 dump_desc_dbg(ioat, chain_tail);
251 dump_desc_dbg(ioat, first);
253 if (!test_and_set_bit(IOAT_COMPLETION_PENDING, &chan->state))
254 mod_timer(&chan->timer, jiffies + COMPLETION_TIMEOUT);
256 ioat->active += desc->hw->tx_cnt;
257 ioat->pending += desc->hw->tx_cnt;
258 if (ioat->pending >= ioat_pending_level)
259 __ioat1_dma_memcpy_issue_pending(ioat);
260 spin_unlock_bh(&ioat->desc_lock);
266 * ioat_dma_alloc_descriptor - allocate and return a sw and hw descriptor pair
267 * @ioat: the channel supplying the memory pool for the descriptors
268 * @flags: allocation flags
270 static struct ioat_desc_sw *
271 ioat_dma_alloc_descriptor(struct ioat_dma_chan *ioat, gfp_t flags)
273 struct ioat_dma_descriptor *desc;
274 struct ioat_desc_sw *desc_sw;
275 struct ioatdma_device *ioatdma_device;
278 ioatdma_device = ioat->base.device;
279 desc = pci_pool_alloc(ioatdma_device->dma_pool, flags, &phys);
283 desc_sw = kzalloc(sizeof(*desc_sw), flags);
284 if (unlikely(!desc_sw)) {
285 pci_pool_free(ioatdma_device->dma_pool, desc, phys);
289 memset(desc, 0, sizeof(*desc));
291 INIT_LIST_HEAD(&desc_sw->tx_list);
292 dma_async_tx_descriptor_init(&desc_sw->txd, &ioat->base.common);
293 desc_sw->txd.tx_submit = ioat1_tx_submit;
295 desc_sw->txd.phys = phys;
296 set_desc_id(desc_sw, -1);
301 static int ioat_initial_desc_count = 256;
302 module_param(ioat_initial_desc_count, int, 0644);
303 MODULE_PARM_DESC(ioat_initial_desc_count,
304 "ioat1: initial descriptors per channel (default: 256)");
306 * ioat1_dma_alloc_chan_resources - returns the number of allocated descriptors
307 * @chan: the channel to be filled out
309 static int ioat1_dma_alloc_chan_resources(struct dma_chan *c)
311 struct ioat_dma_chan *ioat = to_ioat_chan(c);
312 struct ioat_chan_common *chan = &ioat->base;
313 struct ioat_desc_sw *desc;
318 /* have we already been set up? */
319 if (!list_empty(&ioat->free_desc))
320 return ioat->desccount;
322 /* Setup register to interrupt and write completion status on error */
323 writew(IOAT_CHANCTRL_RUN, chan->reg_base + IOAT_CHANCTRL_OFFSET);
325 chanerr = readl(chan->reg_base + IOAT_CHANERR_OFFSET);
327 dev_err(to_dev(chan), "CHANERR = %x, clearing\n", chanerr);
328 writel(chanerr, chan->reg_base + IOAT_CHANERR_OFFSET);
331 /* Allocate descriptors */
332 for (i = 0; i < ioat_initial_desc_count; i++) {
333 desc = ioat_dma_alloc_descriptor(ioat, GFP_KERNEL);
335 dev_err(to_dev(chan), "Only %d initial descriptors\n", i);
338 set_desc_id(desc, i);
339 list_add_tail(&desc->node, &tmp_list);
341 spin_lock_bh(&ioat->desc_lock);
343 list_splice(&tmp_list, &ioat->free_desc);
344 spin_unlock_bh(&ioat->desc_lock);
346 /* allocate a completion writeback area */
347 /* doing 2 32bit writes to mmio since 1 64b write doesn't work */
348 chan->completion = pci_pool_alloc(chan->device->completion_pool,
349 GFP_KERNEL, &chan->completion_dma);
350 memset(chan->completion, 0, sizeof(*chan->completion));
351 writel(((u64) chan->completion_dma) & 0x00000000FFFFFFFF,
352 chan->reg_base + IOAT_CHANCMP_OFFSET_LOW);
353 writel(((u64) chan->completion_dma) >> 32,
354 chan->reg_base + IOAT_CHANCMP_OFFSET_HIGH);
356 tasklet_enable(&chan->cleanup_task);
357 ioat1_dma_start_null_desc(ioat); /* give chain to dma device */
358 dev_dbg(to_dev(chan), "%s: allocated %d descriptors\n",
359 __func__, ioat->desccount);
360 return ioat->desccount;
364 * ioat1_dma_free_chan_resources - release all the descriptors
365 * @chan: the channel to be cleaned
367 static void ioat1_dma_free_chan_resources(struct dma_chan *c)
369 struct ioat_dma_chan *ioat = to_ioat_chan(c);
370 struct ioat_chan_common *chan = &ioat->base;
371 struct ioatdma_device *ioatdma_device = chan->device;
372 struct ioat_desc_sw *desc, *_desc;
373 int in_use_descs = 0;
375 /* Before freeing channel resources first check
376 * if they have been previously allocated for this channel.
378 if (ioat->desccount == 0)
381 tasklet_disable(&chan->cleanup_task);
382 del_timer_sync(&chan->timer);
385 /* Delay 100ms after reset to allow internal DMA logic to quiesce
386 * before removing DMA descriptor resources.
388 writeb(IOAT_CHANCMD_RESET,
389 chan->reg_base + IOAT_CHANCMD_OFFSET(chan->device->version));
392 spin_lock_bh(&ioat->desc_lock);
393 list_for_each_entry_safe(desc, _desc, &ioat->used_desc, node) {
394 dev_dbg(to_dev(chan), "%s: freeing %d from used list\n",
395 __func__, desc_id(desc));
396 dump_desc_dbg(ioat, desc);
398 list_del(&desc->node);
399 pci_pool_free(ioatdma_device->dma_pool, desc->hw,
403 list_for_each_entry_safe(desc, _desc,
404 &ioat->free_desc, node) {
405 list_del(&desc->node);
406 pci_pool_free(ioatdma_device->dma_pool, desc->hw,
410 spin_unlock_bh(&ioat->desc_lock);
412 pci_pool_free(ioatdma_device->completion_pool,
414 chan->completion_dma);
416 /* one is ok since we left it on there on purpose */
417 if (in_use_descs > 1)
418 dev_err(to_dev(chan), "Freeing %d in use descriptors!\n",
421 chan->last_completion = 0;
422 chan->completion_dma = 0;
428 * ioat1_dma_get_next_descriptor - return the next available descriptor
429 * @ioat: IOAT DMA channel handle
431 * Gets the next descriptor from the chain, and must be called with the
432 * channel's desc_lock held. Allocates more descriptors if the channel
435 static struct ioat_desc_sw *
436 ioat1_dma_get_next_descriptor(struct ioat_dma_chan *ioat)
438 struct ioat_desc_sw *new;
440 if (!list_empty(&ioat->free_desc)) {
441 new = to_ioat_desc(ioat->free_desc.next);
442 list_del(&new->node);
444 /* try to get another desc */
445 new = ioat_dma_alloc_descriptor(ioat, GFP_ATOMIC);
447 dev_err(to_dev(&ioat->base), "alloc failed\n");
451 dev_dbg(to_dev(&ioat->base), "%s: allocated: %d\n",
452 __func__, desc_id(new));
457 static struct dma_async_tx_descriptor *
458 ioat1_dma_prep_memcpy(struct dma_chan *c, dma_addr_t dma_dest,
459 dma_addr_t dma_src, size_t len, unsigned long flags)
461 struct ioat_dma_chan *ioat = to_ioat_chan(c);
462 struct ioat_desc_sw *desc;
465 dma_addr_t src = dma_src;
466 dma_addr_t dest = dma_dest;
467 size_t total_len = len;
468 struct ioat_dma_descriptor *hw = NULL;
471 spin_lock_bh(&ioat->desc_lock);
472 desc = ioat1_dma_get_next_descriptor(ioat);
478 copy = min_t(size_t, len, ioat->xfercap);
486 list_add_tail(&desc->node, &chain);
492 struct ioat_desc_sw *next;
494 async_tx_ack(&desc->txd);
495 next = ioat1_dma_get_next_descriptor(ioat);
496 hw->next = next ? next->txd.phys : 0;
497 dump_desc_dbg(ioat, desc);
504 struct ioat_chan_common *chan = &ioat->base;
506 dev_err(to_dev(chan),
507 "chan%d - get_next_desc failed\n", chan_num(chan));
508 list_splice(&chain, &ioat->free_desc);
509 spin_unlock_bh(&ioat->desc_lock);
512 spin_unlock_bh(&ioat->desc_lock);
514 desc->txd.flags = flags;
515 desc->len = total_len;
516 list_splice(&chain, &desc->tx_list);
517 hw->ctl_f.int_en = !!(flags & DMA_PREP_INTERRUPT);
518 hw->ctl_f.compl_write = 1;
520 dump_desc_dbg(ioat, desc);
525 static void ioat1_cleanup_event(unsigned long data)
527 struct ioat_dma_chan *ioat = to_ioat_chan((void *) data);
530 writew(IOAT_CHANCTRL_RUN, ioat->base.reg_base + IOAT_CHANCTRL_OFFSET);
533 void ioat_dma_unmap(struct ioat_chan_common *chan, enum dma_ctrl_flags flags,
534 size_t len, struct ioat_dma_descriptor *hw)
536 struct pci_dev *pdev = chan->device->pdev;
537 size_t offset = len - hw->size;
539 if (!(flags & DMA_COMPL_SKIP_DEST_UNMAP))
540 ioat_unmap(pdev, hw->dst_addr - offset, len,
541 PCI_DMA_FROMDEVICE, flags, 1);
543 if (!(flags & DMA_COMPL_SKIP_SRC_UNMAP))
544 ioat_unmap(pdev, hw->src_addr - offset, len,
545 PCI_DMA_TODEVICE, flags, 0);
548 unsigned long ioat_get_current_completion(struct ioat_chan_common *chan)
550 unsigned long phys_complete;
553 completion = *chan->completion;
554 phys_complete = ioat_chansts_to_addr(completion);
556 dev_dbg(to_dev(chan), "%s: phys_complete: %#llx\n", __func__,
557 (unsigned long long) phys_complete);
559 if (is_ioat_halted(completion)) {
560 u32 chanerr = readl(chan->reg_base + IOAT_CHANERR_OFFSET);
561 dev_err(to_dev(chan), "Channel halted, chanerr = %x\n",
564 /* TODO do something to salvage the situation */
567 return phys_complete;
570 bool ioat_cleanup_preamble(struct ioat_chan_common *chan,
571 unsigned long *phys_complete)
573 *phys_complete = ioat_get_current_completion(chan);
574 if (*phys_complete == chan->last_completion)
576 clear_bit(IOAT_COMPLETION_ACK, &chan->state);
577 mod_timer(&chan->timer, jiffies + COMPLETION_TIMEOUT);
582 static void __cleanup(struct ioat_dma_chan *ioat, unsigned long phys_complete)
584 struct ioat_chan_common *chan = &ioat->base;
585 struct list_head *_desc, *n;
586 struct dma_async_tx_descriptor *tx;
588 dev_dbg(to_dev(chan), "%s: phys_complete: %lx\n",
589 __func__, phys_complete);
590 list_for_each_safe(_desc, n, &ioat->used_desc) {
591 struct ioat_desc_sw *desc;
594 desc = list_entry(_desc, typeof(*desc), node);
597 * Incoming DMA requests may use multiple descriptors,
598 * due to exceeding xfercap, perhaps. If so, only the
599 * last one will have a cookie, and require unmapping.
601 dump_desc_dbg(ioat, desc);
603 chan->common.completed_cookie = tx->cookie;
605 ioat_dma_unmap(chan, tx->flags, desc->len, desc->hw);
606 ioat->active -= desc->hw->tx_cnt;
608 tx->callback(tx->callback_param);
613 if (tx->phys != phys_complete) {
615 * a completed entry, but not the last, so clean
616 * up if the client is done with the descriptor
618 if (async_tx_test_ack(tx))
619 list_move_tail(&desc->node, &ioat->free_desc);
622 * last used desc. Do not remove, so we can
626 /* if nothing else is pending, cancel the
629 if (n == &ioat->used_desc) {
630 dev_dbg(to_dev(chan),
631 "%s cancel completion timeout\n",
633 clear_bit(IOAT_COMPLETION_PENDING, &chan->state);
636 /* TODO check status bits? */
641 chan->last_completion = phys_complete;
645 * ioat1_cleanup - cleanup up finished descriptors
646 * @chan: ioat channel to be cleaned up
648 * To prevent lock contention we defer cleanup when the locks are
649 * contended with a terminal timeout that forces cleanup and catches
650 * completion notification errors.
652 static void ioat1_cleanup(struct ioat_dma_chan *ioat)
654 struct ioat_chan_common *chan = &ioat->base;
655 unsigned long phys_complete;
657 prefetch(chan->completion);
659 if (!spin_trylock_bh(&chan->cleanup_lock))
662 if (!ioat_cleanup_preamble(chan, &phys_complete)) {
663 spin_unlock_bh(&chan->cleanup_lock);
667 if (!spin_trylock_bh(&ioat->desc_lock)) {
668 spin_unlock_bh(&chan->cleanup_lock);
672 __cleanup(ioat, phys_complete);
674 spin_unlock_bh(&ioat->desc_lock);
675 spin_unlock_bh(&chan->cleanup_lock);
678 static void ioat1_timer_event(unsigned long data)
680 struct ioat_dma_chan *ioat = to_ioat_chan((void *) data);
681 struct ioat_chan_common *chan = &ioat->base;
683 dev_dbg(to_dev(chan), "%s: state: %lx\n", __func__, chan->state);
685 spin_lock_bh(&chan->cleanup_lock);
686 if (test_and_clear_bit(IOAT_RESET_PENDING, &chan->state)) {
687 struct ioat_desc_sw *desc;
689 spin_lock_bh(&ioat->desc_lock);
691 /* restart active descriptors */
692 desc = to_ioat_desc(ioat->used_desc.prev);
693 ioat_set_chainaddr(ioat, desc->txd.phys);
697 set_bit(IOAT_COMPLETION_PENDING, &chan->state);
698 mod_timer(&chan->timer, jiffies + COMPLETION_TIMEOUT);
699 spin_unlock_bh(&ioat->desc_lock);
700 } else if (test_bit(IOAT_COMPLETION_PENDING, &chan->state)) {
701 unsigned long phys_complete;
703 spin_lock_bh(&ioat->desc_lock);
704 /* if we haven't made progress and we have already
705 * acknowledged a pending completion once, then be more
706 * forceful with a restart
708 if (ioat_cleanup_preamble(chan, &phys_complete))
709 __cleanup(ioat, phys_complete);
710 else if (test_bit(IOAT_COMPLETION_ACK, &chan->state))
711 ioat1_reset_channel(ioat);
713 u64 status = ioat_chansts(chan);
715 /* manually update the last completion address */
716 if (ioat_chansts_to_addr(status) != 0)
717 *chan->completion = status;
719 set_bit(IOAT_COMPLETION_ACK, &chan->state);
720 mod_timer(&chan->timer, jiffies + COMPLETION_TIMEOUT);
722 spin_unlock_bh(&ioat->desc_lock);
724 spin_unlock_bh(&chan->cleanup_lock);
728 ioat_dma_tx_status(struct dma_chan *c, dma_cookie_t cookie,
729 struct dma_tx_state *txstate)
731 struct ioat_chan_common *chan = to_chan_common(c);
732 struct ioatdma_device *device = chan->device;
734 if (ioat_tx_status(c, cookie, txstate) == DMA_SUCCESS)
737 device->cleanup_fn((unsigned long) c);
739 return ioat_tx_status(c, cookie, txstate);
742 static void ioat1_dma_start_null_desc(struct ioat_dma_chan *ioat)
744 struct ioat_chan_common *chan = &ioat->base;
745 struct ioat_desc_sw *desc;
746 struct ioat_dma_descriptor *hw;
748 spin_lock_bh(&ioat->desc_lock);
750 desc = ioat1_dma_get_next_descriptor(ioat);
753 dev_err(to_dev(chan),
754 "Unable to start null desc - get next desc failed\n");
755 spin_unlock_bh(&ioat->desc_lock);
762 hw->ctl_f.int_en = 1;
763 hw->ctl_f.compl_write = 1;
764 /* set size to non-zero value (channel returns error when size is 0) */
765 hw->size = NULL_DESC_BUFFER_SIZE;
768 async_tx_ack(&desc->txd);
770 list_add_tail(&desc->node, &ioat->used_desc);
771 dump_desc_dbg(ioat, desc);
773 ioat_set_chainaddr(ioat, desc->txd.phys);
775 spin_unlock_bh(&ioat->desc_lock);
779 * Perform a IOAT transaction to verify the HW works.
781 #define IOAT_TEST_SIZE 2000
783 static void __devinit ioat_dma_test_callback(void *dma_async_param)
785 struct completion *cmp = dma_async_param;
791 * ioat_dma_self_test - Perform a IOAT transaction to verify the HW works.
792 * @device: device to be tested
794 int __devinit ioat_dma_self_test(struct ioatdma_device *device)
799 struct dma_device *dma = &device->common;
800 struct device *dev = &device->pdev->dev;
801 struct dma_chan *dma_chan;
802 struct dma_async_tx_descriptor *tx;
803 dma_addr_t dma_dest, dma_src;
806 struct completion cmp;
810 src = kzalloc(sizeof(u8) * IOAT_TEST_SIZE, GFP_KERNEL);
813 dest = kzalloc(sizeof(u8) * IOAT_TEST_SIZE, GFP_KERNEL);
819 /* Fill in src buffer */
820 for (i = 0; i < IOAT_TEST_SIZE; i++)
823 /* Start copy, using first DMA channel */
824 dma_chan = container_of(dma->channels.next, struct dma_chan,
826 if (dma->device_alloc_chan_resources(dma_chan) < 1) {
827 dev_err(dev, "selftest cannot allocate chan resource\n");
832 dma_src = dma_map_single(dev, src, IOAT_TEST_SIZE, DMA_TO_DEVICE);
833 dma_dest = dma_map_single(dev, dest, IOAT_TEST_SIZE, DMA_FROM_DEVICE);
834 flags = DMA_COMPL_SRC_UNMAP_SINGLE | DMA_COMPL_DEST_UNMAP_SINGLE |
836 tx = device->common.device_prep_dma_memcpy(dma_chan, dma_dest, dma_src,
837 IOAT_TEST_SIZE, flags);
839 dev_err(dev, "Self-test prep failed, disabling\n");
845 init_completion(&cmp);
846 tx->callback = ioat_dma_test_callback;
847 tx->callback_param = &cmp;
848 cookie = tx->tx_submit(tx);
850 dev_err(dev, "Self-test setup failed, disabling\n");
854 dma->device_issue_pending(dma_chan);
856 tmo = wait_for_completion_timeout(&cmp, msecs_to_jiffies(3000));
859 dma->device_tx_status(dma_chan, cookie, NULL)
861 dev_err(dev, "Self-test copy timed out, disabling\n");
865 if (memcmp(src, dest, IOAT_TEST_SIZE)) {
866 dev_err(dev, "Self-test copy failed compare, disabling\n");
872 dma->device_free_chan_resources(dma_chan);
879 static char ioat_interrupt_style[32] = "msix";
880 module_param_string(ioat_interrupt_style, ioat_interrupt_style,
881 sizeof(ioat_interrupt_style), 0644);
882 MODULE_PARM_DESC(ioat_interrupt_style,
883 "set ioat interrupt style: msix (default), "
884 "msix-single-vector, msi, intx)");
887 * ioat_dma_setup_interrupts - setup interrupt handler
888 * @device: ioat device
890 static int ioat_dma_setup_interrupts(struct ioatdma_device *device)
892 struct ioat_chan_common *chan;
893 struct pci_dev *pdev = device->pdev;
894 struct device *dev = &pdev->dev;
895 struct msix_entry *msix;
900 if (!strcmp(ioat_interrupt_style, "msix"))
902 if (!strcmp(ioat_interrupt_style, "msix-single-vector"))
903 goto msix_single_vector;
904 if (!strcmp(ioat_interrupt_style, "msi"))
906 if (!strcmp(ioat_interrupt_style, "intx"))
908 dev_err(dev, "invalid ioat_interrupt_style %s\n", ioat_interrupt_style);
912 /* The number of MSI-X vectors should equal the number of channels */
913 msixcnt = device->common.chancnt;
914 for (i = 0; i < msixcnt; i++)
915 device->msix_entries[i].entry = i;
917 err = pci_enable_msix(pdev, device->msix_entries, msixcnt);
921 goto msix_single_vector;
923 for (i = 0; i < msixcnt; i++) {
924 msix = &device->msix_entries[i];
925 chan = ioat_chan_by_index(device, i);
926 err = devm_request_irq(dev, msix->vector,
927 ioat_dma_do_interrupt_msix, 0,
930 for (j = 0; j < i; j++) {
931 msix = &device->msix_entries[j];
932 chan = ioat_chan_by_index(device, j);
933 devm_free_irq(dev, msix->vector, chan);
935 goto msix_single_vector;
938 intrctrl |= IOAT_INTRCTRL_MSIX_VECTOR_CONTROL;
942 msix = &device->msix_entries[0];
944 err = pci_enable_msix(pdev, device->msix_entries, 1);
948 err = devm_request_irq(dev, msix->vector, ioat_dma_do_interrupt, 0,
949 "ioat-msix", device);
951 pci_disable_msix(pdev);
957 err = pci_enable_msi(pdev);
961 err = devm_request_irq(dev, pdev->irq, ioat_dma_do_interrupt, 0,
964 pci_disable_msi(pdev);
970 err = devm_request_irq(dev, pdev->irq, ioat_dma_do_interrupt,
971 IRQF_SHARED, "ioat-intx", device);
976 if (device->intr_quirk)
977 device->intr_quirk(device);
978 intrctrl |= IOAT_INTRCTRL_MASTER_INT_EN;
979 writeb(intrctrl, device->reg_base + IOAT_INTRCTRL_OFFSET);
983 /* Disable all interrupt generation */
984 writeb(0, device->reg_base + IOAT_INTRCTRL_OFFSET);
985 dev_err(dev, "no usable interrupts\n");
989 static void ioat_disable_interrupts(struct ioatdma_device *device)
991 /* Disable all interrupt generation */
992 writeb(0, device->reg_base + IOAT_INTRCTRL_OFFSET);
995 int __devinit ioat_probe(struct ioatdma_device *device)
998 struct dma_device *dma = &device->common;
999 struct pci_dev *pdev = device->pdev;
1000 struct device *dev = &pdev->dev;
1002 /* DMA coherent memory pool for DMA descriptor allocations */
1003 device->dma_pool = pci_pool_create("dma_desc_pool", pdev,
1004 sizeof(struct ioat_dma_descriptor),
1006 if (!device->dma_pool) {
1011 device->completion_pool = pci_pool_create("completion_pool", pdev,
1012 sizeof(u64), SMP_CACHE_BYTES,
1015 if (!device->completion_pool) {
1017 goto err_completion_pool;
1020 device->enumerate_channels(device);
1022 dma_cap_set(DMA_MEMCPY, dma->cap_mask);
1023 dma->dev = &pdev->dev;
1025 if (!dma->chancnt) {
1026 dev_err(dev, "channel enumeration error\n");
1027 goto err_setup_interrupts;
1030 err = ioat_dma_setup_interrupts(device);
1032 goto err_setup_interrupts;
1034 err = device->self_test(device);
1041 ioat_disable_interrupts(device);
1042 err_setup_interrupts:
1043 pci_pool_destroy(device->completion_pool);
1044 err_completion_pool:
1045 pci_pool_destroy(device->dma_pool);
1050 int __devinit ioat_register(struct ioatdma_device *device)
1052 int err = dma_async_device_register(&device->common);
1055 ioat_disable_interrupts(device);
1056 pci_pool_destroy(device->completion_pool);
1057 pci_pool_destroy(device->dma_pool);
1063 /* ioat1_intr_quirk - fix up dma ctrl register to enable / disable msi */
1064 static void ioat1_intr_quirk(struct ioatdma_device *device)
1066 struct pci_dev *pdev = device->pdev;
1069 pci_read_config_dword(pdev, IOAT_PCI_DMACTRL_OFFSET, &dmactrl);
1070 if (pdev->msi_enabled)
1071 dmactrl |= IOAT_PCI_DMACTRL_MSI_EN;
1073 dmactrl &= ~IOAT_PCI_DMACTRL_MSI_EN;
1074 pci_write_config_dword(pdev, IOAT_PCI_DMACTRL_OFFSET, dmactrl);
1077 static ssize_t ring_size_show(struct dma_chan *c, char *page)
1079 struct ioat_dma_chan *ioat = to_ioat_chan(c);
1081 return sprintf(page, "%d\n", ioat->desccount);
1083 static struct ioat_sysfs_entry ring_size_attr = __ATTR_RO(ring_size);
1085 static ssize_t ring_active_show(struct dma_chan *c, char *page)
1087 struct ioat_dma_chan *ioat = to_ioat_chan(c);
1089 return sprintf(page, "%d\n", ioat->active);
1091 static struct ioat_sysfs_entry ring_active_attr = __ATTR_RO(ring_active);
1093 static ssize_t cap_show(struct dma_chan *c, char *page)
1095 struct dma_device *dma = c->device;
1097 return sprintf(page, "copy%s%s%s%s%s%s\n",
1098 dma_has_cap(DMA_PQ, dma->cap_mask) ? " pq" : "",
1099 dma_has_cap(DMA_PQ_VAL, dma->cap_mask) ? " pq_val" : "",
1100 dma_has_cap(DMA_XOR, dma->cap_mask) ? " xor" : "",
1101 dma_has_cap(DMA_XOR_VAL, dma->cap_mask) ? " xor_val" : "",
1102 dma_has_cap(DMA_MEMSET, dma->cap_mask) ? " fill" : "",
1103 dma_has_cap(DMA_INTERRUPT, dma->cap_mask) ? " intr" : "");
1106 struct ioat_sysfs_entry ioat_cap_attr = __ATTR_RO(cap);
1108 static ssize_t version_show(struct dma_chan *c, char *page)
1110 struct dma_device *dma = c->device;
1111 struct ioatdma_device *device = to_ioatdma_device(dma);
1113 return sprintf(page, "%d.%d\n",
1114 device->version >> 4, device->version & 0xf);
1116 struct ioat_sysfs_entry ioat_version_attr = __ATTR_RO(version);
1118 static struct attribute *ioat1_attrs[] = {
1119 &ring_size_attr.attr,
1120 &ring_active_attr.attr,
1121 &ioat_cap_attr.attr,
1122 &ioat_version_attr.attr,
1127 ioat_attr_show(struct kobject *kobj, struct attribute *attr, char *page)
1129 struct ioat_sysfs_entry *entry;
1130 struct ioat_chan_common *chan;
1132 entry = container_of(attr, struct ioat_sysfs_entry, attr);
1133 chan = container_of(kobj, struct ioat_chan_common, kobj);
1137 return entry->show(&chan->common, page);
1140 const struct sysfs_ops ioat_sysfs_ops = {
1141 .show = ioat_attr_show,
1144 static struct kobj_type ioat1_ktype = {
1145 .sysfs_ops = &ioat_sysfs_ops,
1146 .default_attrs = ioat1_attrs,
1149 void ioat_kobject_add(struct ioatdma_device *device, struct kobj_type *type)
1151 struct dma_device *dma = &device->common;
1154 list_for_each_entry(c, &dma->channels, device_node) {
1155 struct ioat_chan_common *chan = to_chan_common(c);
1156 struct kobject *parent = &c->dev->device.kobj;
1159 err = kobject_init_and_add(&chan->kobj, type, parent, "quickdata");
1161 dev_warn(to_dev(chan),
1162 "sysfs init error (%d), continuing...\n", err);
1163 kobject_put(&chan->kobj);
1164 set_bit(IOAT_KOBJ_INIT_FAIL, &chan->state);
1169 void ioat_kobject_del(struct ioatdma_device *device)
1171 struct dma_device *dma = &device->common;
1174 list_for_each_entry(c, &dma->channels, device_node) {
1175 struct ioat_chan_common *chan = to_chan_common(c);
1177 if (!test_bit(IOAT_KOBJ_INIT_FAIL, &chan->state)) {
1178 kobject_del(&chan->kobj);
1179 kobject_put(&chan->kobj);
1184 int __devinit ioat1_dma_probe(struct ioatdma_device *device, int dca)
1186 struct pci_dev *pdev = device->pdev;
1187 struct dma_device *dma;
1190 device->intr_quirk = ioat1_intr_quirk;
1191 device->enumerate_channels = ioat1_enumerate_channels;
1192 device->self_test = ioat_dma_self_test;
1193 device->timer_fn = ioat1_timer_event;
1194 device->cleanup_fn = ioat1_cleanup_event;
1195 dma = &device->common;
1196 dma->device_prep_dma_memcpy = ioat1_dma_prep_memcpy;
1197 dma->device_issue_pending = ioat1_dma_memcpy_issue_pending;
1198 dma->device_alloc_chan_resources = ioat1_dma_alloc_chan_resources;
1199 dma->device_free_chan_resources = ioat1_dma_free_chan_resources;
1200 dma->device_tx_status = ioat_dma_tx_status;
1202 err = ioat_probe(device);
1205 ioat_set_tcp_copy_break(4096);
1206 err = ioat_register(device);
1209 ioat_kobject_add(device, &ioat1_ktype);
1212 device->dca = ioat_dca_init(pdev, device->reg_base);
1217 void __devexit ioat_dma_remove(struct ioatdma_device *device)
1219 struct dma_device *dma = &device->common;
1221 ioat_disable_interrupts(device);
1223 ioat_kobject_del(device);
1225 dma_async_device_unregister(dma);
1227 pci_pool_destroy(device->dma_pool);
1228 pci_pool_destroy(device->completion_pool);
1230 INIT_LIST_HEAD(&dma->channels);