1 // SPDX-License-Identifier: GPL-2.0+
3 // drivers/dma/imx-sdma.c
5 // This file contains a driver for the Freescale Smart DMA engine
7 // Copyright 2010 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
9 // Based on code from Freescale:
11 // Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved.
13 #include <linux/init.h>
14 #include <linux/iopoll.h>
15 #include <linux/module.h>
16 #include <linux/types.h>
17 #include <linux/bitops.h>
19 #include <linux/interrupt.h>
20 #include <linux/clk.h>
21 #include <linux/delay.h>
22 #include <linux/sched.h>
23 #include <linux/semaphore.h>
24 #include <linux/spinlock.h>
25 #include <linux/device.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/firmware.h>
28 #include <linux/slab.h>
29 #include <linux/platform_device.h>
30 #include <linux/dmaengine.h>
32 #include <linux/of_address.h>
33 #include <linux/of_device.h>
34 #include <linux/of_dma.h>
35 #include <linux/workqueue.h>
38 #include <linux/platform_data/dma-imx-sdma.h>
39 #include <linux/platform_data/dma-imx.h>
40 #include <linux/regmap.h>
41 #include <linux/mfd/syscon.h>
42 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
44 #include "dmaengine.h"
48 #define SDMA_H_C0PTR 0x000
49 #define SDMA_H_INTR 0x004
50 #define SDMA_H_STATSTOP 0x008
51 #define SDMA_H_START 0x00c
52 #define SDMA_H_EVTOVR 0x010
53 #define SDMA_H_DSPOVR 0x014
54 #define SDMA_H_HOSTOVR 0x018
55 #define SDMA_H_EVTPEND 0x01c
56 #define SDMA_H_DSPENBL 0x020
57 #define SDMA_H_RESET 0x024
58 #define SDMA_H_EVTERR 0x028
59 #define SDMA_H_INTRMSK 0x02c
60 #define SDMA_H_PSW 0x030
61 #define SDMA_H_EVTERRDBG 0x034
62 #define SDMA_H_CONFIG 0x038
63 #define SDMA_ONCE_ENB 0x040
64 #define SDMA_ONCE_DATA 0x044
65 #define SDMA_ONCE_INSTR 0x048
66 #define SDMA_ONCE_STAT 0x04c
67 #define SDMA_ONCE_CMD 0x050
68 #define SDMA_EVT_MIRROR 0x054
69 #define SDMA_ILLINSTADDR 0x058
70 #define SDMA_CHN0ADDR 0x05c
71 #define SDMA_ONCE_RTB 0x060
72 #define SDMA_XTRIG_CONF1 0x070
73 #define SDMA_XTRIG_CONF2 0x074
74 #define SDMA_CHNENBL0_IMX35 0x200
75 #define SDMA_CHNENBL0_IMX31 0x080
76 #define SDMA_CHNPRI_0 0x100
79 * Buffer descriptor status values.
90 * Data Node descriptor status values.
92 #define DND_END_OF_FRAME 0x80
93 #define DND_END_OF_XFER 0x40
95 #define DND_UNUSED 0x01
98 * IPCV2 descriptor status values.
100 #define BD_IPCV2_END_OF_FRAME 0x40
102 #define IPCV2_MAX_NODES 50
104 * Error bit set in the CCB status field by the SDMA,
105 * in setbd routine, in case of a transfer error
107 #define DATA_ERROR 0x10000000
110 * Buffer descriptor commands.
115 #define C0_SETCTX 0x07
116 #define C0_GETCTX 0x03
117 #define C0_SETDM 0x01
118 #define C0_SETPM 0x04
119 #define C0_GETDM 0x02
120 #define C0_GETPM 0x08
122 * Change endianness indicator in the BD command field
124 #define CHANGE_ENDIANNESS 0x80
127 * p_2_p watermark_level description
128 * Bits Name Description
129 * 0-7 Lower WML Lower watermark level
130 * 8 PS 1: Pad Swallowing
131 * 0: No Pad Swallowing
134 * 10 SPDIF If this bit is set both source
135 * and destination are on SPBA
136 * 11 Source Bit(SP) 1: Source on SPBA
138 * 12 Destination Bit(DP) 1: Destination on SPBA
139 * 0: Destination on AIPS
140 * 13-15 --------- MUST BE 0
141 * 16-23 Higher WML HWML
142 * 24-27 N Total number of samples after
143 * which Pad adding/Swallowing
144 * must be done. It must be odd.
145 * 28 Lower WML Event(LWE) SDMA events reg to check for
147 * 0: LWE in EVENTS register
148 * 1: LWE in EVENTS2 register
149 * 29 Higher WML Event(HWE) SDMA events reg to check for
151 * 0: HWE in EVENTS register
152 * 1: HWE in EVENTS2 register
153 * 30 --------- MUST BE 0
154 * 31 CONT 1: Amount of samples to be
155 * transferred is unknown and
156 * script will keep on
157 * transferring samples as long as
158 * both events are detected and
159 * script must be manually stopped
161 * 0: The amount of samples to be
162 * transferred is equal to the
163 * count field of mode word
165 #define SDMA_WATERMARK_LEVEL_LWML 0xFF
166 #define SDMA_WATERMARK_LEVEL_PS BIT(8)
167 #define SDMA_WATERMARK_LEVEL_PA BIT(9)
168 #define SDMA_WATERMARK_LEVEL_SPDIF BIT(10)
169 #define SDMA_WATERMARK_LEVEL_SP BIT(11)
170 #define SDMA_WATERMARK_LEVEL_DP BIT(12)
171 #define SDMA_WATERMARK_LEVEL_HWML (0xFF << 16)
172 #define SDMA_WATERMARK_LEVEL_LWE BIT(28)
173 #define SDMA_WATERMARK_LEVEL_HWE BIT(29)
174 #define SDMA_WATERMARK_LEVEL_CONT BIT(31)
176 #define SDMA_DMA_BUSWIDTHS (BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \
177 BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \
178 BIT(DMA_SLAVE_BUSWIDTH_4_BYTES))
180 #define SDMA_DMA_DIRECTIONS (BIT(DMA_DEV_TO_MEM) | \
181 BIT(DMA_MEM_TO_DEV) | \
185 * Mode/Count of data node descriptors - IPCv2
187 struct sdma_mode_count {
188 #define SDMA_BD_MAX_CNT 0xffff
189 u32 count : 16; /* size of the buffer pointed by this BD */
190 u32 status : 8; /* E,R,I,C,W,D status bits stored here */
191 u32 command : 8; /* command mostly used for channel 0 */
197 struct sdma_buffer_descriptor {
198 struct sdma_mode_count mode;
199 u32 buffer_addr; /* address of the buffer described */
200 u32 ext_buffer_addr; /* extended buffer address */
201 } __attribute__ ((packed));
204 * struct sdma_channel_control - Channel control Block
206 * @current_bd_ptr: current buffer descriptor processed
207 * @base_bd_ptr: first element of buffer descriptor array
208 * @unused: padding. The SDMA engine expects an array of 128 byte
211 struct sdma_channel_control {
215 } __attribute__ ((packed));
218 * struct sdma_state_registers - SDMA context for a channel
220 * @pc: program counter
222 * @t: test bit: status of arithmetic & test instruction
223 * @rpc: return program counter
225 * @sf: source fault while loading data
226 * @spc: loop start program counter
228 * @df: destination fault while storing data
229 * @epc: loop end program counter
232 struct sdma_state_registers {
244 } __attribute__ ((packed));
247 * struct sdma_context_data - sdma context specific to a channel
249 * @channel_state: channel state bits
250 * @gReg: general registers
251 * @mda: burst dma destination address register
252 * @msa: burst dma source address register
253 * @ms: burst dma status register
254 * @md: burst dma data register
255 * @pda: peripheral dma destination address register
256 * @psa: peripheral dma source address register
257 * @ps: peripheral dma status register
258 * @pd: peripheral dma data register
259 * @ca: CRC polynomial register
260 * @cs: CRC accumulator register
261 * @dda: dedicated core destination address register
262 * @dsa: dedicated core source address register
263 * @ds: dedicated core status register
264 * @dd: dedicated core data register
265 * @scratch0: 1st word of dedicated ram for context switch
266 * @scratch1: 2nd word of dedicated ram for context switch
267 * @scratch2: 3rd word of dedicated ram for context switch
268 * @scratch3: 4th word of dedicated ram for context switch
269 * @scratch4: 5th word of dedicated ram for context switch
270 * @scratch5: 6th word of dedicated ram for context switch
271 * @scratch6: 7th word of dedicated ram for context switch
272 * @scratch7: 8th word of dedicated ram for context switch
274 struct sdma_context_data {
275 struct sdma_state_registers channel_state;
299 } __attribute__ ((packed));
305 * struct sdma_desc - descriptor structor for one transfer
306 * @vd: descriptor for virt dma
307 * @num_bd: number of descriptors currently handling
308 * @bd_phys: physical address of bd
309 * @buf_tail: ID of the buffer that was processed
310 * @buf_ptail: ID of the previous buffer that was processed
311 * @period_len: period length, used in cyclic.
312 * @chn_real_count: the real count updated from bd->mode.count
313 * @chn_count: the transfer count set
314 * @sdmac: sdma_channel pointer
315 * @bd: pointer of allocate bd
318 struct virt_dma_desc vd;
321 unsigned int buf_tail;
322 unsigned int buf_ptail;
323 unsigned int period_len;
324 unsigned int chn_real_count;
325 unsigned int chn_count;
326 struct sdma_channel *sdmac;
327 struct sdma_buffer_descriptor *bd;
331 * struct sdma_channel - housekeeping for a SDMA channel
333 * @vc: virt_dma base structure
334 * @desc: sdma description including vd and other special member
335 * @sdma: pointer to the SDMA engine for this channel
336 * @channel: the channel number, matches dmaengine chan_id + 1
337 * @direction: transfer type. Needed for setting SDMA script
338 * @peripheral_type: Peripheral type. Needed for setting SDMA script
339 * @event_id0: aka dma request line
340 * @event_id1: for channels that use 2 events
341 * @word_size: peripheral access size
342 * @pc_from_device: script address for those device_2_memory
343 * @pc_to_device: script address for those memory_2_device
344 * @device_to_device: script address for those device_2_device
345 * @pc_to_pc: script address for those memory_2_memory
346 * @flags: loop mode or not
347 * @per_address: peripheral source or destination address in common case
348 * destination address in p_2_p case
349 * @per_address2: peripheral source address in p_2_p case
350 * @event_mask: event mask used in p_2_p script
351 * @watermark_level: value for gReg[7], some script will extend it from
352 * basic watermark such as p_2_p
353 * @shp_addr: value for gReg[6]
354 * @per_addr: value for gReg[2]
355 * @status: status of dma channel
356 * @data: specific sdma interface structure
357 * @bd_pool: dma_pool for bd
359 struct sdma_channel {
360 struct virt_dma_chan vc;
361 struct sdma_desc *desc;
362 struct sdma_engine *sdma;
363 unsigned int channel;
364 enum dma_transfer_direction direction;
365 enum sdma_peripheral_type peripheral_type;
366 unsigned int event_id0;
367 unsigned int event_id1;
368 enum dma_slave_buswidth word_size;
369 unsigned int pc_from_device, pc_to_device;
370 unsigned int device_to_device;
371 unsigned int pc_to_pc;
373 dma_addr_t per_address, per_address2;
374 unsigned long event_mask[2];
375 unsigned long watermark_level;
376 u32 shp_addr, per_addr;
377 enum dma_status status;
378 struct imx_dma_data data;
379 struct work_struct terminate_worker;
382 #define IMX_DMA_SG_LOOP BIT(0)
384 #define MAX_DMA_CHANNELS 32
385 #define MXC_SDMA_DEFAULT_PRIORITY 1
386 #define MXC_SDMA_MIN_PRIORITY 1
387 #define MXC_SDMA_MAX_PRIORITY 7
389 #define SDMA_FIRMWARE_MAGIC 0x414d4453
392 * struct sdma_firmware_header - Layout of the firmware image
395 * @version_major: increased whenever layout of struct
396 * sdma_script_start_addrs changes.
397 * @version_minor: firmware minor version (for binary compatible changes)
398 * @script_addrs_start: offset of struct sdma_script_start_addrs in this image
399 * @num_script_addrs: Number of script addresses in this image
400 * @ram_code_start: offset of SDMA ram image in this firmware image
401 * @ram_code_size: size of SDMA ram image
402 * @script_addrs: Stores the start address of the SDMA scripts
403 * (in SDMA memory space)
405 struct sdma_firmware_header {
409 u32 script_addrs_start;
410 u32 num_script_addrs;
415 struct sdma_driver_data {
418 struct sdma_script_start_addrs *script_addrs;
423 struct device_dma_parameters dma_parms;
424 struct sdma_channel channel[MAX_DMA_CHANNELS];
425 struct sdma_channel_control *channel_control;
427 struct sdma_context_data *context;
428 dma_addr_t context_phys;
429 struct dma_device dma_device;
432 spinlock_t channel_0_lock;
434 struct sdma_script_start_addrs *script_addrs;
435 const struct sdma_driver_data *drvdata;
440 struct sdma_buffer_descriptor *bd0;
443 static struct sdma_driver_data sdma_imx31 = {
444 .chnenbl0 = SDMA_CHNENBL0_IMX31,
448 static struct sdma_script_start_addrs sdma_script_imx25 = {
450 .uart_2_mcu_addr = 904,
451 .per_2_app_addr = 1255,
452 .mcu_2_app_addr = 834,
453 .uartsh_2_mcu_addr = 1120,
454 .per_2_shp_addr = 1329,
455 .mcu_2_shp_addr = 1048,
456 .ata_2_mcu_addr = 1560,
457 .mcu_2_ata_addr = 1479,
458 .app_2_per_addr = 1189,
459 .app_2_mcu_addr = 770,
460 .shp_2_per_addr = 1407,
461 .shp_2_mcu_addr = 979,
464 static struct sdma_driver_data sdma_imx25 = {
465 .chnenbl0 = SDMA_CHNENBL0_IMX35,
467 .script_addrs = &sdma_script_imx25,
470 static struct sdma_driver_data sdma_imx35 = {
471 .chnenbl0 = SDMA_CHNENBL0_IMX35,
475 static struct sdma_script_start_addrs sdma_script_imx51 = {
477 .uart_2_mcu_addr = 817,
478 .mcu_2_app_addr = 747,
479 .mcu_2_shp_addr = 961,
480 .ata_2_mcu_addr = 1473,
481 .mcu_2_ata_addr = 1392,
482 .app_2_per_addr = 1033,
483 .app_2_mcu_addr = 683,
484 .shp_2_per_addr = 1251,
485 .shp_2_mcu_addr = 892,
488 static struct sdma_driver_data sdma_imx51 = {
489 .chnenbl0 = SDMA_CHNENBL0_IMX35,
491 .script_addrs = &sdma_script_imx51,
494 static struct sdma_script_start_addrs sdma_script_imx53 = {
496 .app_2_mcu_addr = 683,
497 .mcu_2_app_addr = 747,
498 .uart_2_mcu_addr = 817,
499 .shp_2_mcu_addr = 891,
500 .mcu_2_shp_addr = 960,
501 .uartsh_2_mcu_addr = 1032,
502 .spdif_2_mcu_addr = 1100,
503 .mcu_2_spdif_addr = 1134,
504 .firi_2_mcu_addr = 1193,
505 .mcu_2_firi_addr = 1290,
508 static struct sdma_driver_data sdma_imx53 = {
509 .chnenbl0 = SDMA_CHNENBL0_IMX35,
511 .script_addrs = &sdma_script_imx53,
514 static struct sdma_script_start_addrs sdma_script_imx6q = {
516 .uart_2_mcu_addr = 817,
517 .mcu_2_app_addr = 747,
518 .per_2_per_addr = 6331,
519 .uartsh_2_mcu_addr = 1032,
520 .mcu_2_shp_addr = 960,
521 .app_2_mcu_addr = 683,
522 .shp_2_mcu_addr = 891,
523 .spdif_2_mcu_addr = 1100,
524 .mcu_2_spdif_addr = 1134,
527 static struct sdma_driver_data sdma_imx6q = {
528 .chnenbl0 = SDMA_CHNENBL0_IMX35,
530 .script_addrs = &sdma_script_imx6q,
533 static struct sdma_script_start_addrs sdma_script_imx7d = {
535 .uart_2_mcu_addr = 819,
536 .mcu_2_app_addr = 749,
537 .uartsh_2_mcu_addr = 1034,
538 .mcu_2_shp_addr = 962,
539 .app_2_mcu_addr = 685,
540 .shp_2_mcu_addr = 893,
541 .spdif_2_mcu_addr = 1102,
542 .mcu_2_spdif_addr = 1136,
545 static struct sdma_driver_data sdma_imx7d = {
546 .chnenbl0 = SDMA_CHNENBL0_IMX35,
548 .script_addrs = &sdma_script_imx7d,
551 static const struct platform_device_id sdma_devtypes[] = {
553 .name = "imx25-sdma",
554 .driver_data = (unsigned long)&sdma_imx25,
556 .name = "imx31-sdma",
557 .driver_data = (unsigned long)&sdma_imx31,
559 .name = "imx35-sdma",
560 .driver_data = (unsigned long)&sdma_imx35,
562 .name = "imx51-sdma",
563 .driver_data = (unsigned long)&sdma_imx51,
565 .name = "imx53-sdma",
566 .driver_data = (unsigned long)&sdma_imx53,
568 .name = "imx6q-sdma",
569 .driver_data = (unsigned long)&sdma_imx6q,
571 .name = "imx7d-sdma",
572 .driver_data = (unsigned long)&sdma_imx7d,
577 MODULE_DEVICE_TABLE(platform, sdma_devtypes);
579 static const struct of_device_id sdma_dt_ids[] = {
580 { .compatible = "fsl,imx6q-sdma", .data = &sdma_imx6q, },
581 { .compatible = "fsl,imx53-sdma", .data = &sdma_imx53, },
582 { .compatible = "fsl,imx51-sdma", .data = &sdma_imx51, },
583 { .compatible = "fsl,imx35-sdma", .data = &sdma_imx35, },
584 { .compatible = "fsl,imx31-sdma", .data = &sdma_imx31, },
585 { .compatible = "fsl,imx25-sdma", .data = &sdma_imx25, },
586 { .compatible = "fsl,imx7d-sdma", .data = &sdma_imx7d, },
589 MODULE_DEVICE_TABLE(of, sdma_dt_ids);
591 #define SDMA_H_CONFIG_DSPDMA BIT(12) /* indicates if the DSPDMA is used */
592 #define SDMA_H_CONFIG_RTD_PINS BIT(11) /* indicates if Real-Time Debug pins are enabled */
593 #define SDMA_H_CONFIG_ACR BIT(4) /* indicates if AHB freq /core freq = 2 or 1 */
594 #define SDMA_H_CONFIG_CSM (3) /* indicates which context switch mode is selected*/
596 static inline u32 chnenbl_ofs(struct sdma_engine *sdma, unsigned int event)
598 u32 chnenbl0 = sdma->drvdata->chnenbl0;
599 return chnenbl0 + event * 4;
602 static int sdma_config_ownership(struct sdma_channel *sdmac,
603 bool event_override, bool mcu_override, bool dsp_override)
605 struct sdma_engine *sdma = sdmac->sdma;
606 int channel = sdmac->channel;
607 unsigned long evt, mcu, dsp;
609 if (event_override && mcu_override && dsp_override)
612 evt = readl_relaxed(sdma->regs + SDMA_H_EVTOVR);
613 mcu = readl_relaxed(sdma->regs + SDMA_H_HOSTOVR);
614 dsp = readl_relaxed(sdma->regs + SDMA_H_DSPOVR);
617 __clear_bit(channel, &dsp);
619 __set_bit(channel, &dsp);
622 __clear_bit(channel, &evt);
624 __set_bit(channel, &evt);
627 __clear_bit(channel, &mcu);
629 __set_bit(channel, &mcu);
631 writel_relaxed(evt, sdma->regs + SDMA_H_EVTOVR);
632 writel_relaxed(mcu, sdma->regs + SDMA_H_HOSTOVR);
633 writel_relaxed(dsp, sdma->regs + SDMA_H_DSPOVR);
638 static void sdma_enable_channel(struct sdma_engine *sdma, int channel)
640 writel(BIT(channel), sdma->regs + SDMA_H_START);
644 * sdma_run_channel0 - run a channel and wait till it's done
646 static int sdma_run_channel0(struct sdma_engine *sdma)
651 sdma_enable_channel(sdma, 0);
653 ret = readl_relaxed_poll_timeout_atomic(sdma->regs + SDMA_H_STATSTOP,
654 reg, !(reg & 1), 1, 500);
656 dev_err(sdma->dev, "Timeout waiting for CH0 ready\n");
658 /* Set bits of CONFIG register with dynamic context switching */
659 if (readl(sdma->regs + SDMA_H_CONFIG) == 0)
660 writel_relaxed(SDMA_H_CONFIG_CSM, sdma->regs + SDMA_H_CONFIG);
665 static int sdma_load_script(struct sdma_engine *sdma, void *buf, int size,
668 struct sdma_buffer_descriptor *bd0 = sdma->bd0;
674 buf_virt = dma_alloc_coherent(NULL,
676 &buf_phys, GFP_KERNEL);
681 spin_lock_irqsave(&sdma->channel_0_lock, flags);
683 bd0->mode.command = C0_SETPM;
684 bd0->mode.status = BD_DONE | BD_INTR | BD_WRAP | BD_EXTD;
685 bd0->mode.count = size / 2;
686 bd0->buffer_addr = buf_phys;
687 bd0->ext_buffer_addr = address;
689 memcpy(buf_virt, buf, size);
691 ret = sdma_run_channel0(sdma);
693 spin_unlock_irqrestore(&sdma->channel_0_lock, flags);
695 dma_free_coherent(NULL, size, buf_virt, buf_phys);
700 static void sdma_event_enable(struct sdma_channel *sdmac, unsigned int event)
702 struct sdma_engine *sdma = sdmac->sdma;
703 int channel = sdmac->channel;
705 u32 chnenbl = chnenbl_ofs(sdma, event);
707 val = readl_relaxed(sdma->regs + chnenbl);
708 __set_bit(channel, &val);
709 writel_relaxed(val, sdma->regs + chnenbl);
712 static void sdma_event_disable(struct sdma_channel *sdmac, unsigned int event)
714 struct sdma_engine *sdma = sdmac->sdma;
715 int channel = sdmac->channel;
716 u32 chnenbl = chnenbl_ofs(sdma, event);
719 val = readl_relaxed(sdma->regs + chnenbl);
720 __clear_bit(channel, &val);
721 writel_relaxed(val, sdma->regs + chnenbl);
724 static struct sdma_desc *to_sdma_desc(struct dma_async_tx_descriptor *t)
726 return container_of(t, struct sdma_desc, vd.tx);
729 static void sdma_start_desc(struct sdma_channel *sdmac)
731 struct virt_dma_desc *vd = vchan_next_desc(&sdmac->vc);
732 struct sdma_desc *desc;
733 struct sdma_engine *sdma = sdmac->sdma;
734 int channel = sdmac->channel;
740 sdmac->desc = desc = to_sdma_desc(&vd->tx);
742 * Do not delete the node in desc_issued list in cyclic mode, otherwise
743 * the desc allocated will never be freed in vchan_dma_desc_free_list
745 if (!(sdmac->flags & IMX_DMA_SG_LOOP))
748 sdma->channel_control[channel].base_bd_ptr = desc->bd_phys;
749 sdma->channel_control[channel].current_bd_ptr = desc->bd_phys;
750 sdma_enable_channel(sdma, sdmac->channel);
753 static void sdma_update_channel_loop(struct sdma_channel *sdmac)
755 struct sdma_buffer_descriptor *bd;
757 enum dma_status old_status = sdmac->status;
760 * loop mode. Iterate over descriptors, re-setup them and
761 * call callback function.
763 while (sdmac->desc) {
764 struct sdma_desc *desc = sdmac->desc;
766 bd = &desc->bd[desc->buf_tail];
768 if (bd->mode.status & BD_DONE)
771 if (bd->mode.status & BD_RROR) {
772 bd->mode.status &= ~BD_RROR;
773 sdmac->status = DMA_ERROR;
778 * We use bd->mode.count to calculate the residue, since contains
779 * the number of bytes present in the current buffer descriptor.
782 desc->chn_real_count = bd->mode.count;
783 bd->mode.status |= BD_DONE;
784 bd->mode.count = desc->period_len;
785 desc->buf_ptail = desc->buf_tail;
786 desc->buf_tail = (desc->buf_tail + 1) % desc->num_bd;
789 * The callback is called from the interrupt context in order
790 * to reduce latency and to avoid the risk of altering the
791 * SDMA transaction status by the time the client tasklet is
794 spin_unlock(&sdmac->vc.lock);
795 dmaengine_desc_get_callback_invoke(&desc->vd.tx, NULL);
796 spin_lock(&sdmac->vc.lock);
799 sdmac->status = old_status;
803 static void mxc_sdma_handle_channel_normal(struct sdma_channel *data)
805 struct sdma_channel *sdmac = (struct sdma_channel *) data;
806 struct sdma_buffer_descriptor *bd;
809 sdmac->desc->chn_real_count = 0;
811 * non loop mode. Iterate over all descriptors, collect
812 * errors and call callback function
814 for (i = 0; i < sdmac->desc->num_bd; i++) {
815 bd = &sdmac->desc->bd[i];
817 if (bd->mode.status & (BD_DONE | BD_RROR))
819 sdmac->desc->chn_real_count += bd->mode.count;
823 sdmac->status = DMA_ERROR;
825 sdmac->status = DMA_COMPLETE;
828 static irqreturn_t sdma_int_handler(int irq, void *dev_id)
830 struct sdma_engine *sdma = dev_id;
833 stat = readl_relaxed(sdma->regs + SDMA_H_INTR);
834 writel_relaxed(stat, sdma->regs + SDMA_H_INTR);
835 /* channel 0 is special and not handled here, see run_channel0() */
839 int channel = fls(stat) - 1;
840 struct sdma_channel *sdmac = &sdma->channel[channel];
841 struct sdma_desc *desc;
843 spin_lock(&sdmac->vc.lock);
846 if (sdmac->flags & IMX_DMA_SG_LOOP) {
847 sdma_update_channel_loop(sdmac);
849 mxc_sdma_handle_channel_normal(sdmac);
850 vchan_cookie_complete(&desc->vd);
851 sdma_start_desc(sdmac);
855 spin_unlock(&sdmac->vc.lock);
856 __clear_bit(channel, &stat);
863 * sets the pc of SDMA script according to the peripheral type
865 static void sdma_get_pc(struct sdma_channel *sdmac,
866 enum sdma_peripheral_type peripheral_type)
868 struct sdma_engine *sdma = sdmac->sdma;
869 int per_2_emi = 0, emi_2_per = 0;
871 * These are needed once we start to support transfers between
872 * two peripherals or memory-to-memory transfers
874 int per_2_per = 0, emi_2_emi = 0;
876 sdmac->pc_from_device = 0;
877 sdmac->pc_to_device = 0;
878 sdmac->device_to_device = 0;
881 switch (peripheral_type) {
882 case IMX_DMATYPE_MEMORY:
883 emi_2_emi = sdma->script_addrs->ap_2_ap_addr;
885 case IMX_DMATYPE_DSP:
886 emi_2_per = sdma->script_addrs->bp_2_ap_addr;
887 per_2_emi = sdma->script_addrs->ap_2_bp_addr;
889 case IMX_DMATYPE_FIRI:
890 per_2_emi = sdma->script_addrs->firi_2_mcu_addr;
891 emi_2_per = sdma->script_addrs->mcu_2_firi_addr;
893 case IMX_DMATYPE_UART:
894 per_2_emi = sdma->script_addrs->uart_2_mcu_addr;
895 emi_2_per = sdma->script_addrs->mcu_2_app_addr;
897 case IMX_DMATYPE_UART_SP:
898 per_2_emi = sdma->script_addrs->uartsh_2_mcu_addr;
899 emi_2_per = sdma->script_addrs->mcu_2_shp_addr;
901 case IMX_DMATYPE_ATA:
902 per_2_emi = sdma->script_addrs->ata_2_mcu_addr;
903 emi_2_per = sdma->script_addrs->mcu_2_ata_addr;
905 case IMX_DMATYPE_CSPI:
906 case IMX_DMATYPE_EXT:
907 case IMX_DMATYPE_SSI:
908 case IMX_DMATYPE_SAI:
909 per_2_emi = sdma->script_addrs->app_2_mcu_addr;
910 emi_2_per = sdma->script_addrs->mcu_2_app_addr;
912 case IMX_DMATYPE_SSI_DUAL:
913 per_2_emi = sdma->script_addrs->ssish_2_mcu_addr;
914 emi_2_per = sdma->script_addrs->mcu_2_ssish_addr;
916 case IMX_DMATYPE_SSI_SP:
917 case IMX_DMATYPE_MMC:
918 case IMX_DMATYPE_SDHC:
919 case IMX_DMATYPE_CSPI_SP:
920 case IMX_DMATYPE_ESAI:
921 case IMX_DMATYPE_MSHC_SP:
922 per_2_emi = sdma->script_addrs->shp_2_mcu_addr;
923 emi_2_per = sdma->script_addrs->mcu_2_shp_addr;
925 case IMX_DMATYPE_ASRC:
926 per_2_emi = sdma->script_addrs->asrc_2_mcu_addr;
927 emi_2_per = sdma->script_addrs->asrc_2_mcu_addr;
928 per_2_per = sdma->script_addrs->per_2_per_addr;
930 case IMX_DMATYPE_ASRC_SP:
931 per_2_emi = sdma->script_addrs->shp_2_mcu_addr;
932 emi_2_per = sdma->script_addrs->mcu_2_shp_addr;
933 per_2_per = sdma->script_addrs->per_2_per_addr;
935 case IMX_DMATYPE_MSHC:
936 per_2_emi = sdma->script_addrs->mshc_2_mcu_addr;
937 emi_2_per = sdma->script_addrs->mcu_2_mshc_addr;
939 case IMX_DMATYPE_CCM:
940 per_2_emi = sdma->script_addrs->dptc_dvfs_addr;
942 case IMX_DMATYPE_SPDIF:
943 per_2_emi = sdma->script_addrs->spdif_2_mcu_addr;
944 emi_2_per = sdma->script_addrs->mcu_2_spdif_addr;
946 case IMX_DMATYPE_IPU_MEMORY:
947 emi_2_per = sdma->script_addrs->ext_mem_2_ipu_addr;
953 sdmac->pc_from_device = per_2_emi;
954 sdmac->pc_to_device = emi_2_per;
955 sdmac->device_to_device = per_2_per;
956 sdmac->pc_to_pc = emi_2_emi;
959 static int sdma_load_context(struct sdma_channel *sdmac)
961 struct sdma_engine *sdma = sdmac->sdma;
962 int channel = sdmac->channel;
964 struct sdma_context_data *context = sdma->context;
965 struct sdma_buffer_descriptor *bd0 = sdma->bd0;
969 if (sdmac->direction == DMA_DEV_TO_MEM)
970 load_address = sdmac->pc_from_device;
971 else if (sdmac->direction == DMA_DEV_TO_DEV)
972 load_address = sdmac->device_to_device;
973 else if (sdmac->direction == DMA_MEM_TO_MEM)
974 load_address = sdmac->pc_to_pc;
976 load_address = sdmac->pc_to_device;
978 if (load_address < 0)
981 dev_dbg(sdma->dev, "load_address = %d\n", load_address);
982 dev_dbg(sdma->dev, "wml = 0x%08x\n", (u32)sdmac->watermark_level);
983 dev_dbg(sdma->dev, "shp_addr = 0x%08x\n", sdmac->shp_addr);
984 dev_dbg(sdma->dev, "per_addr = 0x%08x\n", sdmac->per_addr);
985 dev_dbg(sdma->dev, "event_mask0 = 0x%08x\n", (u32)sdmac->event_mask[0]);
986 dev_dbg(sdma->dev, "event_mask1 = 0x%08x\n", (u32)sdmac->event_mask[1]);
988 spin_lock_irqsave(&sdma->channel_0_lock, flags);
990 memset(context, 0, sizeof(*context));
991 context->channel_state.pc = load_address;
993 /* Send by context the event mask,base address for peripheral
994 * and watermark level
996 context->gReg[0] = sdmac->event_mask[1];
997 context->gReg[1] = sdmac->event_mask[0];
998 context->gReg[2] = sdmac->per_addr;
999 context->gReg[6] = sdmac->shp_addr;
1000 context->gReg[7] = sdmac->watermark_level;
1002 bd0->mode.command = C0_SETDM;
1003 bd0->mode.status = BD_DONE | BD_INTR | BD_WRAP | BD_EXTD;
1004 bd0->mode.count = sizeof(*context) / 4;
1005 bd0->buffer_addr = sdma->context_phys;
1006 bd0->ext_buffer_addr = 2048 + (sizeof(*context) / 4) * channel;
1007 ret = sdma_run_channel0(sdma);
1009 spin_unlock_irqrestore(&sdma->channel_0_lock, flags);
1014 static struct sdma_channel *to_sdma_chan(struct dma_chan *chan)
1016 return container_of(chan, struct sdma_channel, vc.chan);
1019 static int sdma_disable_channel(struct dma_chan *chan)
1021 struct sdma_channel *sdmac = to_sdma_chan(chan);
1022 struct sdma_engine *sdma = sdmac->sdma;
1023 int channel = sdmac->channel;
1025 writel_relaxed(BIT(channel), sdma->regs + SDMA_H_STATSTOP);
1026 sdmac->status = DMA_ERROR;
1030 static void sdma_channel_terminate_work(struct work_struct *work)
1032 struct sdma_channel *sdmac = container_of(work, struct sdma_channel,
1034 unsigned long flags;
1038 * According to NXP R&D team a delay of one BD SDMA cost time
1039 * (maximum is 1ms) should be added after disable of the channel
1040 * bit, to ensure SDMA core has really been stopped after SDMA
1041 * clients call .device_terminate_all.
1043 usleep_range(1000, 2000);
1045 spin_lock_irqsave(&sdmac->vc.lock, flags);
1046 vchan_get_all_descriptors(&sdmac->vc, &head);
1048 spin_unlock_irqrestore(&sdmac->vc.lock, flags);
1049 vchan_dma_desc_free_list(&sdmac->vc, &head);
1052 static int sdma_disable_channel_async(struct dma_chan *chan)
1054 struct sdma_channel *sdmac = to_sdma_chan(chan);
1056 sdma_disable_channel(chan);
1059 schedule_work(&sdmac->terminate_worker);
1064 static void sdma_channel_synchronize(struct dma_chan *chan)
1066 struct sdma_channel *sdmac = to_sdma_chan(chan);
1068 vchan_synchronize(&sdmac->vc);
1070 flush_work(&sdmac->terminate_worker);
1073 static void sdma_set_watermarklevel_for_p2p(struct sdma_channel *sdmac)
1075 struct sdma_engine *sdma = sdmac->sdma;
1077 int lwml = sdmac->watermark_level & SDMA_WATERMARK_LEVEL_LWML;
1078 int hwml = (sdmac->watermark_level & SDMA_WATERMARK_LEVEL_HWML) >> 16;
1080 set_bit(sdmac->event_id0 % 32, &sdmac->event_mask[1]);
1081 set_bit(sdmac->event_id1 % 32, &sdmac->event_mask[0]);
1083 if (sdmac->event_id0 > 31)
1084 sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_LWE;
1086 if (sdmac->event_id1 > 31)
1087 sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_HWE;
1090 * If LWML(src_maxburst) > HWML(dst_maxburst), we need
1091 * swap LWML and HWML of INFO(A.3.2.5.1), also need swap
1092 * r0(event_mask[1]) and r1(event_mask[0]).
1095 sdmac->watermark_level &= ~(SDMA_WATERMARK_LEVEL_LWML |
1096 SDMA_WATERMARK_LEVEL_HWML);
1097 sdmac->watermark_level |= hwml;
1098 sdmac->watermark_level |= lwml << 16;
1099 swap(sdmac->event_mask[0], sdmac->event_mask[1]);
1102 if (sdmac->per_address2 >= sdma->spba_start_addr &&
1103 sdmac->per_address2 <= sdma->spba_end_addr)
1104 sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_SP;
1106 if (sdmac->per_address >= sdma->spba_start_addr &&
1107 sdmac->per_address <= sdma->spba_end_addr)
1108 sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_DP;
1110 sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_CONT;
1113 static int sdma_config_channel(struct dma_chan *chan)
1115 struct sdma_channel *sdmac = to_sdma_chan(chan);
1118 sdma_disable_channel(chan);
1120 sdmac->event_mask[0] = 0;
1121 sdmac->event_mask[1] = 0;
1122 sdmac->shp_addr = 0;
1123 sdmac->per_addr = 0;
1125 if (sdmac->event_id0) {
1126 if (sdmac->event_id0 >= sdmac->sdma->drvdata->num_events)
1128 sdma_event_enable(sdmac, sdmac->event_id0);
1131 if (sdmac->event_id1) {
1132 if (sdmac->event_id1 >= sdmac->sdma->drvdata->num_events)
1134 sdma_event_enable(sdmac, sdmac->event_id1);
1137 switch (sdmac->peripheral_type) {
1138 case IMX_DMATYPE_DSP:
1139 sdma_config_ownership(sdmac, false, true, true);
1141 case IMX_DMATYPE_MEMORY:
1142 sdma_config_ownership(sdmac, false, true, false);
1145 sdma_config_ownership(sdmac, true, true, false);
1149 sdma_get_pc(sdmac, sdmac->peripheral_type);
1151 if ((sdmac->peripheral_type != IMX_DMATYPE_MEMORY) &&
1152 (sdmac->peripheral_type != IMX_DMATYPE_DSP)) {
1153 /* Handle multiple event channels differently */
1154 if (sdmac->event_id1) {
1155 if (sdmac->peripheral_type == IMX_DMATYPE_ASRC_SP ||
1156 sdmac->peripheral_type == IMX_DMATYPE_ASRC)
1157 sdma_set_watermarklevel_for_p2p(sdmac);
1159 __set_bit(sdmac->event_id0, sdmac->event_mask);
1162 sdmac->shp_addr = sdmac->per_address;
1163 sdmac->per_addr = sdmac->per_address2;
1165 sdmac->watermark_level = 0; /* FIXME: M3_BASE_ADDRESS */
1168 ret = sdma_load_context(sdmac);
1173 static int sdma_set_channel_priority(struct sdma_channel *sdmac,
1174 unsigned int priority)
1176 struct sdma_engine *sdma = sdmac->sdma;
1177 int channel = sdmac->channel;
1179 if (priority < MXC_SDMA_MIN_PRIORITY
1180 || priority > MXC_SDMA_MAX_PRIORITY) {
1184 writel_relaxed(priority, sdma->regs + SDMA_CHNPRI_0 + 4 * channel);
1189 static int sdma_request_channel0(struct sdma_engine *sdma)
1193 sdma->bd0 = dma_zalloc_coherent(NULL, PAGE_SIZE, &sdma->bd0_phys,
1200 sdma->channel_control[0].base_bd_ptr = sdma->bd0_phys;
1201 sdma->channel_control[0].current_bd_ptr = sdma->bd0_phys;
1203 sdma_set_channel_priority(&sdma->channel[0], MXC_SDMA_DEFAULT_PRIORITY);
1211 static int sdma_alloc_bd(struct sdma_desc *desc)
1213 u32 bd_size = desc->num_bd * sizeof(struct sdma_buffer_descriptor);
1216 desc->bd = dma_zalloc_coherent(NULL, bd_size, &desc->bd_phys,
1226 static void sdma_free_bd(struct sdma_desc *desc)
1228 u32 bd_size = desc->num_bd * sizeof(struct sdma_buffer_descriptor);
1230 dma_free_coherent(NULL, bd_size, desc->bd, desc->bd_phys);
1233 static void sdma_desc_free(struct virt_dma_desc *vd)
1235 struct sdma_desc *desc = container_of(vd, struct sdma_desc, vd);
1241 static int sdma_alloc_chan_resources(struct dma_chan *chan)
1243 struct sdma_channel *sdmac = to_sdma_chan(chan);
1244 struct imx_dma_data *data = chan->private;
1245 struct imx_dma_data mem_data;
1249 * MEMCPY may never setup chan->private by filter function such as
1250 * dmatest, thus create 'struct imx_dma_data mem_data' for this case.
1251 * Please note in any other slave case, you have to setup chan->private
1252 * with 'struct imx_dma_data' in your own filter function if you want to
1253 * request dma channel by dma_request_channel() rather than
1254 * dma_request_slave_channel(). Othwise, 'MEMCPY in case?' will appear
1255 * to warn you to correct your filter function.
1258 dev_dbg(sdmac->sdma->dev, "MEMCPY in case?\n");
1259 mem_data.priority = 2;
1260 mem_data.peripheral_type = IMX_DMATYPE_MEMORY;
1261 mem_data.dma_request = 0;
1262 mem_data.dma_request2 = 0;
1265 sdma_get_pc(sdmac, IMX_DMATYPE_MEMORY);
1268 switch (data->priority) {
1272 case DMA_PRIO_MEDIUM:
1281 sdmac->peripheral_type = data->peripheral_type;
1282 sdmac->event_id0 = data->dma_request;
1283 sdmac->event_id1 = data->dma_request2;
1285 ret = clk_enable(sdmac->sdma->clk_ipg);
1288 ret = clk_enable(sdmac->sdma->clk_ahb);
1290 goto disable_clk_ipg;
1292 ret = sdma_set_channel_priority(sdmac, prio);
1294 goto disable_clk_ahb;
1299 clk_disable(sdmac->sdma->clk_ahb);
1301 clk_disable(sdmac->sdma->clk_ipg);
1305 static void sdma_free_chan_resources(struct dma_chan *chan)
1307 struct sdma_channel *sdmac = to_sdma_chan(chan);
1308 struct sdma_engine *sdma = sdmac->sdma;
1310 sdma_disable_channel_async(chan);
1312 sdma_channel_synchronize(chan);
1314 if (sdmac->event_id0)
1315 sdma_event_disable(sdmac, sdmac->event_id0);
1316 if (sdmac->event_id1)
1317 sdma_event_disable(sdmac, sdmac->event_id1);
1319 sdmac->event_id0 = 0;
1320 sdmac->event_id1 = 0;
1322 sdma_set_channel_priority(sdmac, 0);
1324 clk_disable(sdma->clk_ipg);
1325 clk_disable(sdma->clk_ahb);
1328 static struct sdma_desc *sdma_transfer_init(struct sdma_channel *sdmac,
1329 enum dma_transfer_direction direction, u32 bds)
1331 struct sdma_desc *desc;
1333 desc = kzalloc((sizeof(*desc)), GFP_NOWAIT);
1337 sdmac->status = DMA_IN_PROGRESS;
1338 sdmac->direction = direction;
1341 desc->chn_count = 0;
1342 desc->chn_real_count = 0;
1344 desc->buf_ptail = 0;
1345 desc->sdmac = sdmac;
1348 if (sdma_alloc_bd(desc))
1351 /* No slave_config called in MEMCPY case, so do here */
1352 if (direction == DMA_MEM_TO_MEM)
1353 sdma_config_ownership(sdmac, false, true, false);
1355 if (sdma_load_context(sdmac))
1366 static struct dma_async_tx_descriptor *sdma_prep_memcpy(
1367 struct dma_chan *chan, dma_addr_t dma_dst,
1368 dma_addr_t dma_src, size_t len, unsigned long flags)
1370 struct sdma_channel *sdmac = to_sdma_chan(chan);
1371 struct sdma_engine *sdma = sdmac->sdma;
1372 int channel = sdmac->channel;
1375 struct sdma_buffer_descriptor *bd;
1376 struct sdma_desc *desc;
1381 dev_dbg(sdma->dev, "memcpy: %pad->%pad, len=%zu, channel=%d.\n",
1382 &dma_src, &dma_dst, len, channel);
1384 desc = sdma_transfer_init(sdmac, DMA_MEM_TO_MEM,
1385 len / SDMA_BD_MAX_CNT + 1);
1390 count = min_t(size_t, len, SDMA_BD_MAX_CNT);
1392 bd->buffer_addr = dma_src;
1393 bd->ext_buffer_addr = dma_dst;
1394 bd->mode.count = count;
1395 desc->chn_count += count;
1396 bd->mode.command = 0;
1403 param = BD_DONE | BD_EXTD | BD_CONT;
1411 dev_dbg(sdma->dev, "entry %d: count: %zd dma: 0x%x %s%s\n",
1412 i, count, bd->buffer_addr,
1413 param & BD_WRAP ? "wrap" : "",
1414 param & BD_INTR ? " intr" : "");
1416 bd->mode.status = param;
1419 return vchan_tx_prep(&sdmac->vc, &desc->vd, flags);
1422 static struct dma_async_tx_descriptor *sdma_prep_slave_sg(
1423 struct dma_chan *chan, struct scatterlist *sgl,
1424 unsigned int sg_len, enum dma_transfer_direction direction,
1425 unsigned long flags, void *context)
1427 struct sdma_channel *sdmac = to_sdma_chan(chan);
1428 struct sdma_engine *sdma = sdmac->sdma;
1430 int channel = sdmac->channel;
1431 struct scatterlist *sg;
1432 struct sdma_desc *desc;
1434 desc = sdma_transfer_init(sdmac, direction, sg_len);
1438 dev_dbg(sdma->dev, "setting up %d entries for channel %d.\n",
1441 for_each_sg(sgl, sg, sg_len, i) {
1442 struct sdma_buffer_descriptor *bd = &desc->bd[i];
1445 bd->buffer_addr = sg->dma_address;
1447 count = sg_dma_len(sg);
1449 if (count > SDMA_BD_MAX_CNT) {
1450 dev_err(sdma->dev, "SDMA channel %d: maximum bytes for sg entry exceeded: %d > %d\n",
1451 channel, count, SDMA_BD_MAX_CNT);
1455 bd->mode.count = count;
1456 desc->chn_count += count;
1458 if (sdmac->word_size > DMA_SLAVE_BUSWIDTH_4_BYTES)
1461 switch (sdmac->word_size) {
1462 case DMA_SLAVE_BUSWIDTH_4_BYTES:
1463 bd->mode.command = 0;
1464 if (count & 3 || sg->dma_address & 3)
1467 case DMA_SLAVE_BUSWIDTH_2_BYTES:
1468 bd->mode.command = 2;
1469 if (count & 1 || sg->dma_address & 1)
1472 case DMA_SLAVE_BUSWIDTH_1_BYTE:
1473 bd->mode.command = 1;
1479 param = BD_DONE | BD_EXTD | BD_CONT;
1481 if (i + 1 == sg_len) {
1487 dev_dbg(sdma->dev, "entry %d: count: %d dma: %#llx %s%s\n",
1488 i, count, (u64)sg->dma_address,
1489 param & BD_WRAP ? "wrap" : "",
1490 param & BD_INTR ? " intr" : "");
1492 bd->mode.status = param;
1495 return vchan_tx_prep(&sdmac->vc, &desc->vd, flags);
1500 sdmac->status = DMA_ERROR;
1504 static struct dma_async_tx_descriptor *sdma_prep_dma_cyclic(
1505 struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len,
1506 size_t period_len, enum dma_transfer_direction direction,
1507 unsigned long flags)
1509 struct sdma_channel *sdmac = to_sdma_chan(chan);
1510 struct sdma_engine *sdma = sdmac->sdma;
1511 int num_periods = buf_len / period_len;
1512 int channel = sdmac->channel;
1514 struct sdma_desc *desc;
1516 dev_dbg(sdma->dev, "%s channel: %d\n", __func__, channel);
1518 desc = sdma_transfer_init(sdmac, direction, num_periods);
1522 desc->period_len = period_len;
1524 sdmac->flags |= IMX_DMA_SG_LOOP;
1526 if (period_len > SDMA_BD_MAX_CNT) {
1527 dev_err(sdma->dev, "SDMA channel %d: maximum period size exceeded: %zu > %d\n",
1528 channel, period_len, SDMA_BD_MAX_CNT);
1532 while (buf < buf_len) {
1533 struct sdma_buffer_descriptor *bd = &desc->bd[i];
1536 bd->buffer_addr = dma_addr;
1538 bd->mode.count = period_len;
1540 if (sdmac->word_size > DMA_SLAVE_BUSWIDTH_4_BYTES)
1542 if (sdmac->word_size == DMA_SLAVE_BUSWIDTH_4_BYTES)
1543 bd->mode.command = 0;
1545 bd->mode.command = sdmac->word_size;
1547 param = BD_DONE | BD_EXTD | BD_CONT | BD_INTR;
1548 if (i + 1 == num_periods)
1551 dev_dbg(sdma->dev, "entry %d: count: %zu dma: %#llx %s%s\n",
1552 i, period_len, (u64)dma_addr,
1553 param & BD_WRAP ? "wrap" : "",
1554 param & BD_INTR ? " intr" : "");
1556 bd->mode.status = param;
1558 dma_addr += period_len;
1564 return vchan_tx_prep(&sdmac->vc, &desc->vd, flags);
1569 sdmac->status = DMA_ERROR;
1573 static int sdma_config(struct dma_chan *chan,
1574 struct dma_slave_config *dmaengine_cfg)
1576 struct sdma_channel *sdmac = to_sdma_chan(chan);
1578 if (dmaengine_cfg->direction == DMA_DEV_TO_MEM) {
1579 sdmac->per_address = dmaengine_cfg->src_addr;
1580 sdmac->watermark_level = dmaengine_cfg->src_maxburst *
1581 dmaengine_cfg->src_addr_width;
1582 sdmac->word_size = dmaengine_cfg->src_addr_width;
1583 } else if (dmaengine_cfg->direction == DMA_DEV_TO_DEV) {
1584 sdmac->per_address2 = dmaengine_cfg->src_addr;
1585 sdmac->per_address = dmaengine_cfg->dst_addr;
1586 sdmac->watermark_level = dmaengine_cfg->src_maxburst &
1587 SDMA_WATERMARK_LEVEL_LWML;
1588 sdmac->watermark_level |= (dmaengine_cfg->dst_maxburst << 16) &
1589 SDMA_WATERMARK_LEVEL_HWML;
1590 sdmac->word_size = dmaengine_cfg->dst_addr_width;
1592 sdmac->per_address = dmaengine_cfg->dst_addr;
1593 sdmac->watermark_level = dmaengine_cfg->dst_maxburst *
1594 dmaengine_cfg->dst_addr_width;
1595 sdmac->word_size = dmaengine_cfg->dst_addr_width;
1597 sdmac->direction = dmaengine_cfg->direction;
1598 return sdma_config_channel(chan);
1601 static enum dma_status sdma_tx_status(struct dma_chan *chan,
1602 dma_cookie_t cookie,
1603 struct dma_tx_state *txstate)
1605 struct sdma_channel *sdmac = to_sdma_chan(chan);
1606 struct sdma_desc *desc;
1608 struct virt_dma_desc *vd;
1609 enum dma_status ret;
1610 unsigned long flags;
1612 ret = dma_cookie_status(chan, cookie, txstate);
1613 if (ret == DMA_COMPLETE || !txstate)
1616 spin_lock_irqsave(&sdmac->vc.lock, flags);
1617 vd = vchan_find_desc(&sdmac->vc, cookie);
1619 desc = to_sdma_desc(&vd->tx);
1620 if (sdmac->flags & IMX_DMA_SG_LOOP)
1621 residue = (desc->num_bd - desc->buf_ptail) *
1622 desc->period_len - desc->chn_real_count;
1624 residue = desc->chn_count - desc->chn_real_count;
1625 } else if (sdmac->desc && sdmac->desc->vd.tx.cookie == cookie) {
1626 residue = sdmac->desc->chn_count - sdmac->desc->chn_real_count;
1630 spin_unlock_irqrestore(&sdmac->vc.lock, flags);
1632 dma_set_tx_state(txstate, chan->completed_cookie, chan->cookie,
1635 return sdmac->status;
1638 static void sdma_issue_pending(struct dma_chan *chan)
1640 struct sdma_channel *sdmac = to_sdma_chan(chan);
1641 unsigned long flags;
1643 spin_lock_irqsave(&sdmac->vc.lock, flags);
1644 if (vchan_issue_pending(&sdmac->vc) && !sdmac->desc)
1645 sdma_start_desc(sdmac);
1646 spin_unlock_irqrestore(&sdmac->vc.lock, flags);
1649 #define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1 34
1650 #define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V2 38
1651 #define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V3 41
1652 #define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V4 42
1654 static void sdma_add_scripts(struct sdma_engine *sdma,
1655 const struct sdma_script_start_addrs *addr)
1657 s32 *addr_arr = (u32 *)addr;
1658 s32 *saddr_arr = (u32 *)sdma->script_addrs;
1661 /* use the default firmware in ROM if missing external firmware */
1662 if (!sdma->script_number)
1663 sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1;
1665 for (i = 0; i < sdma->script_number; i++)
1666 if (addr_arr[i] > 0)
1667 saddr_arr[i] = addr_arr[i];
1670 static void sdma_load_firmware(const struct firmware *fw, void *context)
1672 struct sdma_engine *sdma = context;
1673 const struct sdma_firmware_header *header;
1674 const struct sdma_script_start_addrs *addr;
1675 unsigned short *ram_code;
1678 dev_info(sdma->dev, "external firmware not found, using ROM firmware\n");
1679 /* In this case we just use the ROM firmware. */
1683 if (fw->size < sizeof(*header))
1686 header = (struct sdma_firmware_header *)fw->data;
1688 if (header->magic != SDMA_FIRMWARE_MAGIC)
1690 if (header->ram_code_start + header->ram_code_size > fw->size)
1692 switch (header->version_major) {
1694 sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1;
1697 sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V2;
1700 sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V3;
1703 sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V4;
1706 dev_err(sdma->dev, "unknown firmware version\n");
1710 addr = (void *)header + header->script_addrs_start;
1711 ram_code = (void *)header + header->ram_code_start;
1713 clk_enable(sdma->clk_ipg);
1714 clk_enable(sdma->clk_ahb);
1715 /* download the RAM image for SDMA */
1716 sdma_load_script(sdma, ram_code,
1717 header->ram_code_size,
1718 addr->ram_code_start_addr);
1719 clk_disable(sdma->clk_ipg);
1720 clk_disable(sdma->clk_ahb);
1722 sdma_add_scripts(sdma, addr);
1724 dev_info(sdma->dev, "loaded firmware %d.%d\n",
1725 header->version_major,
1726 header->version_minor);
1729 release_firmware(fw);
1732 #define EVENT_REMAP_CELLS 3
1734 static int sdma_event_remap(struct sdma_engine *sdma)
1736 struct device_node *np = sdma->dev->of_node;
1737 struct device_node *gpr_np = of_parse_phandle(np, "gpr", 0);
1738 struct property *event_remap;
1740 char propname[] = "fsl,sdma-event-remap";
1741 u32 reg, val, shift, num_map, i;
1744 if (IS_ERR(np) || IS_ERR(gpr_np))
1747 event_remap = of_find_property(np, propname, NULL);
1748 num_map = event_remap ? (event_remap->length / sizeof(u32)) : 0;
1750 dev_dbg(sdma->dev, "no event needs to be remapped\n");
1752 } else if (num_map % EVENT_REMAP_CELLS) {
1753 dev_err(sdma->dev, "the property %s must modulo %d\n",
1754 propname, EVENT_REMAP_CELLS);
1759 gpr = syscon_node_to_regmap(gpr_np);
1761 dev_err(sdma->dev, "failed to get gpr regmap\n");
1766 for (i = 0; i < num_map; i += EVENT_REMAP_CELLS) {
1767 ret = of_property_read_u32_index(np, propname, i, ®);
1769 dev_err(sdma->dev, "failed to read property %s index %d\n",
1774 ret = of_property_read_u32_index(np, propname, i + 1, &shift);
1776 dev_err(sdma->dev, "failed to read property %s index %d\n",
1781 ret = of_property_read_u32_index(np, propname, i + 2, &val);
1783 dev_err(sdma->dev, "failed to read property %s index %d\n",
1788 regmap_update_bits(gpr, reg, BIT(shift), val << shift);
1792 if (!IS_ERR(gpr_np))
1793 of_node_put(gpr_np);
1798 static int sdma_get_firmware(struct sdma_engine *sdma,
1799 const char *fw_name)
1803 ret = request_firmware_nowait(THIS_MODULE,
1804 FW_ACTION_HOTPLUG, fw_name, sdma->dev,
1805 GFP_KERNEL, sdma, sdma_load_firmware);
1810 static int sdma_init(struct sdma_engine *sdma)
1813 dma_addr_t ccb_phys;
1815 ret = clk_enable(sdma->clk_ipg);
1818 ret = clk_enable(sdma->clk_ahb);
1820 goto disable_clk_ipg;
1822 /* Be sure SDMA has not started yet */
1823 writel_relaxed(0, sdma->regs + SDMA_H_C0PTR);
1825 sdma->channel_control = dma_alloc_coherent(NULL,
1826 MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control) +
1827 sizeof(struct sdma_context_data),
1828 &ccb_phys, GFP_KERNEL);
1830 if (!sdma->channel_control) {
1835 sdma->context = (void *)sdma->channel_control +
1836 MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control);
1837 sdma->context_phys = ccb_phys +
1838 MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control);
1840 /* Zero-out the CCB structures array just allocated */
1841 memset(sdma->channel_control, 0,
1842 MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control));
1844 /* disable all channels */
1845 for (i = 0; i < sdma->drvdata->num_events; i++)
1846 writel_relaxed(0, sdma->regs + chnenbl_ofs(sdma, i));
1848 /* All channels have priority 0 */
1849 for (i = 0; i < MAX_DMA_CHANNELS; i++)
1850 writel_relaxed(0, sdma->regs + SDMA_CHNPRI_0 + i * 4);
1852 ret = sdma_request_channel0(sdma);
1856 sdma_config_ownership(&sdma->channel[0], false, true, false);
1858 /* Set Command Channel (Channel Zero) */
1859 writel_relaxed(0x4050, sdma->regs + SDMA_CHN0ADDR);
1861 /* Set bits of CONFIG register but with static context switching */
1862 /* FIXME: Check whether to set ACR bit depending on clock ratios */
1863 writel_relaxed(0, sdma->regs + SDMA_H_CONFIG);
1865 writel_relaxed(ccb_phys, sdma->regs + SDMA_H_C0PTR);
1867 /* Initializes channel's priorities */
1868 sdma_set_channel_priority(&sdma->channel[0], 7);
1870 clk_disable(sdma->clk_ipg);
1871 clk_disable(sdma->clk_ahb);
1876 clk_disable(sdma->clk_ahb);
1878 clk_disable(sdma->clk_ipg);
1879 dev_err(sdma->dev, "initialisation failed with %d\n", ret);
1883 static bool sdma_filter_fn(struct dma_chan *chan, void *fn_param)
1885 struct sdma_channel *sdmac = to_sdma_chan(chan);
1886 struct imx_dma_data *data = fn_param;
1888 if (!imx_dma_is_general_purpose(chan))
1891 sdmac->data = *data;
1892 chan->private = &sdmac->data;
1897 static struct dma_chan *sdma_xlate(struct of_phandle_args *dma_spec,
1898 struct of_dma *ofdma)
1900 struct sdma_engine *sdma = ofdma->of_dma_data;
1901 dma_cap_mask_t mask = sdma->dma_device.cap_mask;
1902 struct imx_dma_data data;
1904 if (dma_spec->args_count != 3)
1907 data.dma_request = dma_spec->args[0];
1908 data.peripheral_type = dma_spec->args[1];
1909 data.priority = dma_spec->args[2];
1911 * init dma_request2 to zero, which is not used by the dts.
1912 * For P2P, dma_request2 is init from dma_request_channel(),
1913 * chan->private will point to the imx_dma_data, and in
1914 * device_alloc_chan_resources(), imx_dma_data.dma_request2 will
1915 * be set to sdmac->event_id1.
1917 data.dma_request2 = 0;
1919 return dma_request_channel(mask, sdma_filter_fn, &data);
1922 static int sdma_probe(struct platform_device *pdev)
1924 const struct of_device_id *of_id =
1925 of_match_device(sdma_dt_ids, &pdev->dev);
1926 struct device_node *np = pdev->dev.of_node;
1927 struct device_node *spba_bus;
1928 const char *fw_name;
1931 struct resource *iores;
1932 struct resource spba_res;
1933 struct sdma_platform_data *pdata = dev_get_platdata(&pdev->dev);
1935 struct sdma_engine *sdma;
1937 const struct sdma_driver_data *drvdata = NULL;
1940 drvdata = of_id->data;
1941 else if (pdev->id_entry)
1942 drvdata = (void *)pdev->id_entry->driver_data;
1945 dev_err(&pdev->dev, "unable to find driver data\n");
1949 ret = dma_coerce_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
1953 sdma = devm_kzalloc(&pdev->dev, sizeof(*sdma), GFP_KERNEL);
1957 spin_lock_init(&sdma->channel_0_lock);
1959 sdma->dev = &pdev->dev;
1960 sdma->drvdata = drvdata;
1962 irq = platform_get_irq(pdev, 0);
1966 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1967 sdma->regs = devm_ioremap_resource(&pdev->dev, iores);
1968 if (IS_ERR(sdma->regs))
1969 return PTR_ERR(sdma->regs);
1971 sdma->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
1972 if (IS_ERR(sdma->clk_ipg))
1973 return PTR_ERR(sdma->clk_ipg);
1975 sdma->clk_ahb = devm_clk_get(&pdev->dev, "ahb");
1976 if (IS_ERR(sdma->clk_ahb))
1977 return PTR_ERR(sdma->clk_ahb);
1979 ret = clk_prepare(sdma->clk_ipg);
1983 ret = clk_prepare(sdma->clk_ahb);
1987 ret = devm_request_irq(&pdev->dev, irq, sdma_int_handler, 0, "sdma",
1994 sdma->script_addrs = kzalloc(sizeof(*sdma->script_addrs), GFP_KERNEL);
1995 if (!sdma->script_addrs) {
2000 /* initially no scripts available */
2001 saddr_arr = (s32 *)sdma->script_addrs;
2002 for (i = 0; i < SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1; i++)
2003 saddr_arr[i] = -EINVAL;
2005 dma_cap_set(DMA_SLAVE, sdma->dma_device.cap_mask);
2006 dma_cap_set(DMA_CYCLIC, sdma->dma_device.cap_mask);
2007 dma_cap_set(DMA_MEMCPY, sdma->dma_device.cap_mask);
2009 INIT_LIST_HEAD(&sdma->dma_device.channels);
2010 /* Initialize channel parameters */
2011 for (i = 0; i < MAX_DMA_CHANNELS; i++) {
2012 struct sdma_channel *sdmac = &sdma->channel[i];
2017 sdmac->vc.desc_free = sdma_desc_free;
2018 INIT_WORK(&sdmac->terminate_worker,
2019 sdma_channel_terminate_work);
2021 * Add the channel to the DMAC list. Do not add channel 0 though
2022 * because we need it internally in the SDMA driver. This also means
2023 * that channel 0 in dmaengine counting matches sdma channel 1.
2026 vchan_init(&sdmac->vc, &sdma->dma_device);
2029 ret = sdma_init(sdma);
2033 ret = sdma_event_remap(sdma);
2037 if (sdma->drvdata->script_addrs)
2038 sdma_add_scripts(sdma, sdma->drvdata->script_addrs);
2039 if (pdata && pdata->script_addrs)
2040 sdma_add_scripts(sdma, pdata->script_addrs);
2043 ret = sdma_get_firmware(sdma, pdata->fw_name);
2045 dev_warn(&pdev->dev, "failed to get firmware from platform data\n");
2048 * Because that device tree does not encode ROM script address,
2049 * the RAM script in firmware is mandatory for device tree
2050 * probe, otherwise it fails.
2052 ret = of_property_read_string(np, "fsl,sdma-ram-script-name",
2055 dev_warn(&pdev->dev, "failed to get firmware name\n");
2057 ret = sdma_get_firmware(sdma, fw_name);
2059 dev_warn(&pdev->dev, "failed to get firmware from device tree\n");
2063 sdma->dma_device.dev = &pdev->dev;
2065 sdma->dma_device.device_alloc_chan_resources = sdma_alloc_chan_resources;
2066 sdma->dma_device.device_free_chan_resources = sdma_free_chan_resources;
2067 sdma->dma_device.device_tx_status = sdma_tx_status;
2068 sdma->dma_device.device_prep_slave_sg = sdma_prep_slave_sg;
2069 sdma->dma_device.device_prep_dma_cyclic = sdma_prep_dma_cyclic;
2070 sdma->dma_device.device_config = sdma_config;
2071 sdma->dma_device.device_terminate_all = sdma_disable_channel_async;
2072 sdma->dma_device.device_synchronize = sdma_channel_synchronize;
2073 sdma->dma_device.src_addr_widths = SDMA_DMA_BUSWIDTHS;
2074 sdma->dma_device.dst_addr_widths = SDMA_DMA_BUSWIDTHS;
2075 sdma->dma_device.directions = SDMA_DMA_DIRECTIONS;
2076 sdma->dma_device.residue_granularity = DMA_RESIDUE_GRANULARITY_SEGMENT;
2077 sdma->dma_device.device_prep_dma_memcpy = sdma_prep_memcpy;
2078 sdma->dma_device.device_issue_pending = sdma_issue_pending;
2079 sdma->dma_device.dev->dma_parms = &sdma->dma_parms;
2080 dma_set_max_seg_size(sdma->dma_device.dev, SDMA_BD_MAX_CNT);
2082 platform_set_drvdata(pdev, sdma);
2084 ret = dma_async_device_register(&sdma->dma_device);
2086 dev_err(&pdev->dev, "unable to register\n");
2091 ret = of_dma_controller_register(np, sdma_xlate, sdma);
2093 dev_err(&pdev->dev, "failed to register controller\n");
2097 spba_bus = of_find_compatible_node(NULL, NULL, "fsl,spba-bus");
2098 ret = of_address_to_resource(spba_bus, 0, &spba_res);
2100 sdma->spba_start_addr = spba_res.start;
2101 sdma->spba_end_addr = spba_res.end;
2103 of_node_put(spba_bus);
2109 dma_async_device_unregister(&sdma->dma_device);
2111 kfree(sdma->script_addrs);
2113 clk_unprepare(sdma->clk_ahb);
2115 clk_unprepare(sdma->clk_ipg);
2119 static int sdma_remove(struct platform_device *pdev)
2121 struct sdma_engine *sdma = platform_get_drvdata(pdev);
2124 devm_free_irq(&pdev->dev, sdma->irq, sdma);
2125 dma_async_device_unregister(&sdma->dma_device);
2126 kfree(sdma->script_addrs);
2127 clk_unprepare(sdma->clk_ahb);
2128 clk_unprepare(sdma->clk_ipg);
2129 /* Kill the tasklet */
2130 for (i = 0; i < MAX_DMA_CHANNELS; i++) {
2131 struct sdma_channel *sdmac = &sdma->channel[i];
2133 tasklet_kill(&sdmac->vc.task);
2134 sdma_free_chan_resources(&sdmac->vc.chan);
2137 platform_set_drvdata(pdev, NULL);
2141 static struct platform_driver sdma_driver = {
2144 .of_match_table = sdma_dt_ids,
2146 .id_table = sdma_devtypes,
2147 .remove = sdma_remove,
2148 .probe = sdma_probe,
2151 module_platform_driver(sdma_driver);
2153 MODULE_AUTHOR("Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>");
2154 MODULE_DESCRIPTION("i.MX SDMA driver");
2155 #if IS_ENABLED(CONFIG_SOC_IMX6Q)
2156 MODULE_FIRMWARE("imx/sdma/sdma-imx6q.bin");
2158 #if IS_ENABLED(CONFIG_SOC_IMX7D)
2159 MODULE_FIRMWARE("imx/sdma/sdma-imx7d.bin");
2161 MODULE_LICENSE("GPL");