drivers/dma/imx-dma.c

   1 /*
   2  * drivers/dma/imx-dma.c
   3  *
   4  * This file contains a driver for the Freescale i.MX DMA engine
   5  * found on i.MX1/21/27
   6  *
   7  * Copyright 2010 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
   8  * Copyright 2012 Javier Martin, Vista Silicon <javier.martin@vista-silicon.com>
   9  *
  10  * The code contained herein is licensed under the GNU General Public
  11  * License. You may obtain a copy of the GNU General Public License
  12  * Version 2 or later at the following locations:
  13  *
  14  * http://www.opensource.org/licenses/gpl-license.html
  15  * http://www.gnu.org/copyleft/gpl.html
  16  */
  17 #include <linux/init.h>
  18 #include <linux/types.h>
  19 #include <linux/mm.h>
  20 #include <linux/interrupt.h>
  21 #include <linux/spinlock.h>
  22 #include <linux/device.h>
  23 #include <linux/dma-mapping.h>
  24 #include <linux/slab.h>
  25 #include <linux/platform_device.h>
  26 #include <linux/clk.h>
  27 #include <linux/dmaengine.h>
  28 #include <linux/module.h>
  29
  30 #include <asm/irq.h>
  31 #include <mach/dma.h>
  32 #include <mach/hardware.h>
  33
  34 #include "dmaengine.h"
  35 #define IMXDMA_MAX_CHAN_DESCRIPTORS     16
  36 #define IMX_DMA_CHANNELS  16
  37
  38 #define IMX_DMA_2D_SLOTS        2
  39 #define IMX_DMA_2D_SLOT_A       0
  40 #define IMX_DMA_2D_SLOT_B       1
  41
  42 #define IMX_DMA_LENGTH_LOOP     ((unsigned int)-1)
  43 #define IMX_DMA_MEMSIZE_32      (0 << 4)
  44 #define IMX_DMA_MEMSIZE_8       (1 << 4)
  45 #define IMX_DMA_MEMSIZE_16      (2 << 4)
  46 #define IMX_DMA_TYPE_LINEAR     (0 << 10)
  47 #define IMX_DMA_TYPE_2D         (1 << 10)
  48 #define IMX_DMA_TYPE_FIFO       (2 << 10)
  49
  50 #define IMX_DMA_ERR_BURST     (1 << 0)
  51 #define IMX_DMA_ERR_REQUEST   (1 << 1)
  52 #define IMX_DMA_ERR_TRANSFER  (1 << 2)
  53 #define IMX_DMA_ERR_BUFFER    (1 << 3)
  54 #define IMX_DMA_ERR_TIMEOUT   (1 << 4)
  55
  56 #define DMA_DCR     0x00                /* Control Register */
  57 #define DMA_DISR    0x04                /* Interrupt status Register */
  58 #define DMA_DIMR    0x08                /* Interrupt mask Register */
  59 #define DMA_DBTOSR  0x0c                /* Burst timeout status Register */
  60 #define DMA_DRTOSR  0x10                /* Request timeout Register */
  61 #define DMA_DSESR   0x14                /* Transfer Error Status Register */
  62 #define DMA_DBOSR   0x18                /* Buffer overflow status Register */
  63 #define DMA_DBTOCR  0x1c                /* Burst timeout control Register */
  64 #define DMA_WSRA    0x40                /* W-Size Register A */
  65 #define DMA_XSRA    0x44                /* X-Size Register A */
  66 #define DMA_YSRA    0x48                /* Y-Size Register A */
  67 #define DMA_WSRB    0x4c                /* W-Size Register B */
  68 #define DMA_XSRB    0x50                /* X-Size Register B */
  69 #define DMA_YSRB    0x54                /* Y-Size Register B */
  70 #define DMA_SAR(x)  (0x80 + ((x) << 6)) /* Source Address Registers */
  71 #define DMA_DAR(x)  (0x84 + ((x) << 6)) /* Destination Address Registers */
  72 #define DMA_CNTR(x) (0x88 + ((x) << 6)) /* Count Registers */
  73 #define DMA_CCR(x)  (0x8c + ((x) << 6)) /* Control Registers */
  74 #define DMA_RSSR(x) (0x90 + ((x) << 6)) /* Request source select Registers */
  75 #define DMA_BLR(x)  (0x94 + ((x) << 6)) /* Burst length Registers */
  76 #define DMA_RTOR(x) (0x98 + ((x) << 6)) /* Request timeout Registers */
  77 #define DMA_BUCR(x) (0x98 + ((x) << 6)) /* Bus Utilization Registers */
  78 #define DMA_CCNR(x) (0x9C + ((x) << 6)) /* Channel counter Registers */
  79
  80 #define DCR_DRST           (1<<1)
  81 #define DCR_DEN            (1<<0)
  82 #define DBTOCR_EN          (1<<15)
  83 #define DBTOCR_CNT(x)      ((x) & 0x7fff)
  84 #define CNTR_CNT(x)        ((x) & 0xffffff)
  85 #define CCR_ACRPT          (1<<14)
  86 #define CCR_DMOD_LINEAR    (0x0 << 12)
  87 #define CCR_DMOD_2D        (0x1 << 12)
  88 #define CCR_DMOD_FIFO      (0x2 << 12)
  89 #define CCR_DMOD_EOBFIFO   (0x3 << 12)
  90 #define CCR_SMOD_LINEAR    (0x0 << 10)
  91 #define CCR_SMOD_2D        (0x1 << 10)
  92 #define CCR_SMOD_FIFO      (0x2 << 10)
  93 #define CCR_SMOD_EOBFIFO   (0x3 << 10)
  94 #define CCR_MDIR_DEC       (1<<9)
  95 #define CCR_MSEL_B         (1<<8)
  96 #define CCR_DSIZ_32        (0x0 << 6)
  97 #define CCR_DSIZ_8         (0x1 << 6)
  98 #define CCR_DSIZ_16        (0x2 << 6)
  99 #define CCR_SSIZ_32        (0x0 << 4)
 100 #define CCR_SSIZ_8         (0x1 << 4)
 101 #define CCR_SSIZ_16        (0x2 << 4)
 102 #define CCR_REN            (1<<3)
 103 #define CCR_RPT            (1<<2)
 104 #define CCR_FRC            (1<<1)
 105 #define CCR_CEN            (1<<0)
 106 #define RTOR_EN            (1<<15)
 107 #define RTOR_CLK           (1<<14)
 108 #define RTOR_PSC           (1<<13)
 109
 110 enum  imxdma_prep_type {
 111         IMXDMA_DESC_MEMCPY,
 112         IMXDMA_DESC_INTERLEAVED,
 113         IMXDMA_DESC_SLAVE_SG,
 114         IMXDMA_DESC_CYCLIC,
 115 };
 116
 117 struct imx_dma_2d_config {
 118         u16             xsr;
 119         u16             ysr;
 120         u16             wsr;
 121         int             count;
 122 };
 123
 124 struct imxdma_desc {
 125         struct list_head                node;
 126         struct dma_async_tx_descriptor  desc;
 127         enum dma_status                 status;
 128         dma_addr_t                      src;
 129         dma_addr_t                      dest;
 130         size_t                          len;
 131         enum dma_transfer_direction     direction;
 132         enum imxdma_prep_type           type;
 133         /* For memcpy and interleaved */
 134         unsigned int                    config_port;
 135         unsigned int                    config_mem;
 136         /* For interleaved transfers */
 137         unsigned int                    x;
 138         unsigned int                    y;
 139         unsigned int                    w;
 140         /* For slave sg and cyclic */
 141         struct scatterlist              *sg;
 142         unsigned int                    sgcount;
 143 };
 144
 145 struct imxdma_channel {
 146         int                             hw_chaining;
 147         struct timer_list               watchdog;
 148         struct imxdma_engine            *imxdma;
 149         unsigned int                    channel;
 150
 151         struct tasklet_struct           dma_tasklet;
 152         struct list_head                ld_free;
 153         struct list_head                ld_queue;
 154         struct list_head                ld_active;
 155         int                             descs_allocated;
 156         enum dma_slave_buswidth         word_size;
 157         dma_addr_t                      per_address;
 158         u32                             watermark_level;
 159         struct dma_chan                 chan;
 160         struct dma_async_tx_descriptor  desc;
 161         enum dma_status                 status;
 162         int                             dma_request;
 163         struct scatterlist              *sg_list;
 164         u32                             ccr_from_device;
 165         u32                             ccr_to_device;
 166         bool                            enabled_2d;
 167         int                             slot_2d;
 168 };
 169
 170 struct imxdma_engine {
 171         struct device                   *dev;
 172         struct device_dma_parameters    dma_parms;
 173         struct dma_device               dma_device;
 174         void __iomem                    *base;
 175         struct clk                      *dma_clk;
 176         spinlock_t                      lock;
 177         struct imx_dma_2d_config        slots_2d[IMX_DMA_2D_SLOTS];
 178         struct imxdma_channel           channel[IMX_DMA_CHANNELS];
 179 };
 180
 181 static struct imxdma_channel *to_imxdma_chan(struct dma_chan *chan)
 182 {
 183         return container_of(chan, struct imxdma_channel, chan);
 184 }
 185
 186 static inline bool imxdma_chan_is_doing_cyclic(struct imxdma_channel *imxdmac)
 187 {
 188         struct imxdma_desc *desc;
 189
 190         if (!list_empty(&imxdmac->ld_active)) {
 191                 desc = list_first_entry(&imxdmac->ld_active, struct imxdma_desc,
 192                                         node);
 193                 if (desc->type == IMXDMA_DESC_CYCLIC)
 194                         return true;
 195         }
 196         return false;
 197 }
 198
 199
 200
 201 static void imx_dmav1_writel(struct imxdma_engine *imxdma, unsigned val,
 202                              unsigned offset)
 203 {
 204         __raw_writel(val, imxdma->base + offset);
 205 }
 206
 207 static unsigned imx_dmav1_readl(struct imxdma_engine *imxdma, unsigned offset)
 208 {
 209         return __raw_readl(imxdma->base + offset);
 210 }
 211
 212 static int imxdma_hw_chain(struct imxdma_channel *imxdmac)
 213 {
 214         if (cpu_is_mx27())
 215                 return imxdmac->hw_chaining;
 216         else
 217                 return 0;
 218 }
 219
 220 /*
 221  * imxdma_sg_next - prepare next chunk for scatter-gather DMA emulation
 222  */
 223 static inline int imxdma_sg_next(struct imxdma_desc *d)
 224 {
 225         struct imxdma_channel *imxdmac = to_imxdma_chan(d->desc.chan);
 226         struct imxdma_engine *imxdma = imxdmac->imxdma;
 227         struct scatterlist *sg = d->sg;
 228         unsigned long now;
 229
 230         now = min(d->len, sg->length);
 231         if (d->len != IMX_DMA_LENGTH_LOOP)
 232                 d->len -= now;
 233
 234         if (d->direction == DMA_DEV_TO_MEM)
 235                 imx_dmav1_writel(imxdma, sg->dma_address,
 236                                  DMA_DAR(imxdmac->channel));
 237         else
 238                 imx_dmav1_writel(imxdma, sg->dma_address,
 239                                  DMA_SAR(imxdmac->channel));
 240
 241         imx_dmav1_writel(imxdma, now, DMA_CNTR(imxdmac->channel));
 242
 243         dev_dbg(imxdma->dev, " %s channel: %d dst 0x%08x, src 0x%08x, "
 244                 "size 0x%08x\n", __func__, imxdmac->channel,
 245                  imx_dmav1_readl(imxdma, DMA_DAR(imxdmac->channel)),
 246                  imx_dmav1_readl(imxdma, DMA_SAR(imxdmac->channel)),
 247                  imx_dmav1_readl(imxdma, DMA_CNTR(imxdmac->channel)));
 248
 249         return now;
 250 }
 251
 252 static void imxdma_enable_hw(struct imxdma_desc *d)
 253 {
 254         struct imxdma_channel *imxdmac = to_imxdma_chan(d->desc.chan);
 255         struct imxdma_engine *imxdma = imxdmac->imxdma;
 256         int channel = imxdmac->channel;
 257         unsigned long flags;
 258
 259         dev_dbg(imxdma->dev, "%s channel %d\n", __func__, channel);
 260
 261         local_irq_save(flags);
 262
 263         imx_dmav1_writel(imxdma, 1 << channel, DMA_DISR);
 264         imx_dmav1_writel(imxdma, imx_dmav1_readl(imxdma, DMA_DIMR) &
 265                          ~(1 << channel), DMA_DIMR);
 266         imx_dmav1_writel(imxdma, imx_dmav1_readl(imxdma, DMA_CCR(channel)) |
 267                          CCR_CEN | CCR_ACRPT, DMA_CCR(channel));
 268
 269         if ((cpu_is_mx21() || cpu_is_mx27()) &&
 270                         d->sg && imxdma_hw_chain(imxdmac)) {
 271                 d->sg = sg_next(d->sg);
 272                 if (d->sg) {
 273                         u32 tmp;
 274                         imxdma_sg_next(d);
 275                         tmp = imx_dmav1_readl(imxdma, DMA_CCR(channel));
 276                         imx_dmav1_writel(imxdma, tmp | CCR_RPT | CCR_ACRPT,
 277                                          DMA_CCR(channel));
 278                 }
 279         }
 280
 281         local_irq_restore(flags);
 282 }
 283
 284 static void imxdma_disable_hw(struct imxdma_channel *imxdmac)
 285 {
 286         struct imxdma_engine *imxdma = imxdmac->imxdma;
 287         int channel = imxdmac->channel;
 288         unsigned long flags;
 289
 290         dev_dbg(imxdma->dev, "%s channel %d\n", __func__, channel);
 291
 292         if (imxdma_hw_chain(imxdmac))
 293                 del_timer(&imxdmac->watchdog);
 294
 295         local_irq_save(flags);
 296         imx_dmav1_writel(imxdma, imx_dmav1_readl(imxdma, DMA_DIMR) |
 297                          (1 << channel), DMA_DIMR);
 298         imx_dmav1_writel(imxdma, imx_dmav1_readl(imxdma, DMA_CCR(channel)) &
 299                          ~CCR_CEN, DMA_CCR(channel));
 300         imx_dmav1_writel(imxdma, 1 << channel, DMA_DISR);
 301         local_irq_restore(flags);
 302 }
 303
 304 static void imxdma_watchdog(unsigned long data)
 305 {
 306         struct imxdma_channel *imxdmac = (struct imxdma_channel *)data;
 307         struct imxdma_engine *imxdma = imxdmac->imxdma;
 308         int channel = imxdmac->channel;
 309
 310         imx_dmav1_writel(imxdma, 0, DMA_CCR(channel));
 311
 312         /* Tasklet watchdog error handler */
 313         tasklet_schedule(&imxdmac->dma_tasklet);
 314         dev_dbg(imxdma->dev, "channel %d: watchdog timeout!\n",
 315                 imxdmac->channel);
 316 }
 317
 318 static irqreturn_t imxdma_err_handler(int irq, void *dev_id)
 319 {
 320         struct imxdma_engine *imxdma = dev_id;
 321         unsigned int err_mask;
 322         int i, disr;
 323         int errcode;
 324
 325         disr = imx_dmav1_readl(imxdma, DMA_DISR);
 326
 327         err_mask = imx_dmav1_readl(imxdma, DMA_DBTOSR) |
 328                    imx_dmav1_readl(imxdma, DMA_DRTOSR) |
 329                    imx_dmav1_readl(imxdma, DMA_DSESR)  |
 330                    imx_dmav1_readl(imxdma, DMA_DBOSR);
 331
 332         if (!err_mask)
 333                 return IRQ_HANDLED;
 334
 335         imx_dmav1_writel(imxdma, disr & err_mask, DMA_DISR);
 336
 337         for (i = 0; i < IMX_DMA_CHANNELS; i++) {
 338                 if (!(err_mask & (1 << i)))
 339                         continue;
 340                 errcode = 0;
 341
 342                 if (imx_dmav1_readl(imxdma, DMA_DBTOSR) & (1 << i)) {
 343                         imx_dmav1_writel(imxdma, 1 << i, DMA_DBTOSR);
 344                         errcode |= IMX_DMA_ERR_BURST;
 345                 }
 346                 if (imx_dmav1_readl(imxdma, DMA_DRTOSR) & (1 << i)) {
 347                         imx_dmav1_writel(imxdma, 1 << i, DMA_DRTOSR);
 348                         errcode |= IMX_DMA_ERR_REQUEST;
 349                 }
 350                 if (imx_dmav1_readl(imxdma, DMA_DSESR) & (1 << i)) {
 351                         imx_dmav1_writel(imxdma, 1 << i, DMA_DSESR);
 352                         errcode |= IMX_DMA_ERR_TRANSFER;
 353                 }
 354                 if (imx_dmav1_readl(imxdma, DMA_DBOSR) & (1 << i)) {
 355                         imx_dmav1_writel(imxdma, 1 << i, DMA_DBOSR);
 356                         errcode |= IMX_DMA_ERR_BUFFER;
 357                 }
 358                 /* Tasklet error handler */
 359                 tasklet_schedule(&imxdma->channel[i].dma_tasklet);
 360
 361                 printk(KERN_WARNING
 362                        "DMA timeout on channel %d -%s%s%s%s\n", i,
 363                        errcode & IMX_DMA_ERR_BURST ?    " burst" : "",
 364                        errcode & IMX_DMA_ERR_REQUEST ?  " request" : "",
 365                        errcode & IMX_DMA_ERR_TRANSFER ? " transfer" : "",
 366                        errcode & IMX_DMA_ERR_BUFFER ?   " buffer" : "");
 367         }
 368         return IRQ_HANDLED;
 369 }
 370
 371 static void dma_irq_handle_channel(struct imxdma_channel *imxdmac)
 372 {
 373         struct imxdma_engine *imxdma = imxdmac->imxdma;
 374         int chno = imxdmac->channel;
 375         struct imxdma_desc *desc;
 376
 377         spin_lock(&imxdma->lock);
 378         if (list_empty(&imxdmac->ld_active)) {
 379                 spin_unlock(&imxdma->lock);
 380                 goto out;
 381         }
 382
 383         desc = list_first_entry(&imxdmac->ld_active,
 384                                 struct imxdma_desc,
 385                                 node);
 386         spin_unlock(&imxdma->lock);
 387
 388         if (desc->sg) {
 389                 u32 tmp;
 390                 desc->sg = sg_next(desc->sg);
 391
 392                 if (desc->sg) {
 393                         imxdma_sg_next(desc);
 394
 395                         tmp = imx_dmav1_readl(imxdma, DMA_CCR(chno));
 396
 397                         if (imxdma_hw_chain(imxdmac)) {
 398                                 /* FIXME: The timeout should probably be
 399                                  * configurable
 400                                  */
 401                                 mod_timer(&imxdmac->watchdog,
 402                                         jiffies + msecs_to_jiffies(500));
 403
 404                                 tmp |= CCR_CEN | CCR_RPT | CCR_ACRPT;
 405                                 imx_dmav1_writel(imxdma, tmp, DMA_CCR(chno));
 406                         } else {
 407                                 imx_dmav1_writel(imxdma, tmp & ~CCR_CEN,
 408                                                  DMA_CCR(chno));
 409                                 tmp |= CCR_CEN;
 410                         }
 411
 412                         imx_dmav1_writel(imxdma, tmp, DMA_CCR(chno));
 413
 414                         if (imxdma_chan_is_doing_cyclic(imxdmac))
 415                                 /* Tasklet progression */
 416                                 tasklet_schedule(&imxdmac->dma_tasklet);
 417
 418                         return;
 419                 }
 420
 421                 if (imxdma_hw_chain(imxdmac)) {
 422                         del_timer(&imxdmac->watchdog);
 423                         return;
 424                 }
 425         }
 426
 427 out:
 428         imx_dmav1_writel(imxdma, 0, DMA_CCR(chno));
 429         /* Tasklet irq */
 430         tasklet_schedule(&imxdmac->dma_tasklet);
 431 }
 432
 433 static irqreturn_t dma_irq_handler(int irq, void *dev_id)
 434 {
 435         struct imxdma_engine *imxdma = dev_id;
 436         int i, disr;
 437
 438         if (cpu_is_mx21() || cpu_is_mx27())
 439                 imxdma_err_handler(irq, dev_id);
 440
 441         disr = imx_dmav1_readl(imxdma, DMA_DISR);
 442
 443         dev_dbg(imxdma->dev, "%s called, disr=0x%08x\n", __func__, disr);
 444
 445         imx_dmav1_writel(imxdma, disr, DMA_DISR);
 446         for (i = 0; i < IMX_DMA_CHANNELS; i++) {
 447                 if (disr & (1 << i))
 448                         dma_irq_handle_channel(&imxdma->channel[i]);
 449         }
 450
 451         return IRQ_HANDLED;
 452 }
 453
 454 static int imxdma_xfer_desc(struct imxdma_desc *d)
 455 {
 456         struct imxdma_channel *imxdmac = to_imxdma_chan(d->desc.chan);
 457         struct imxdma_engine *imxdma = imxdmac->imxdma;
 458         unsigned long flags;
 459         int slot = -1;
 460         int i;
 461
 462         /* Configure and enable */
 463         switch (d->type) {
 464         case IMXDMA_DESC_INTERLEAVED:
 465                 /* Try to get a free 2D slot */
 466                 spin_lock_irqsave(&imxdma->lock, flags);
 467                 for (i = 0; i < IMX_DMA_2D_SLOTS; i++) {
 468                         if ((imxdma->slots_2d[i].count > 0) &&
 469                         ((imxdma->slots_2d[i].xsr != d->x) ||
 470                         (imxdma->slots_2d[i].ysr != d->y) ||
 471                         (imxdma->slots_2d[i].wsr != d->w)))
 472                                 continue;
 473                         slot = i;
 474                         break;
 475                 }
 476                 if (slot < 0)
 477                         return -EBUSY;
 478
 479                 imxdma->slots_2d[slot].xsr = d->x;
 480                 imxdma->slots_2d[slot].ysr = d->y;
 481                 imxdma->slots_2d[slot].wsr = d->w;
 482                 imxdma->slots_2d[slot].count++;
 483
 484                 imxdmac->slot_2d = slot;
 485                 imxdmac->enabled_2d = true;
 486                 spin_unlock_irqrestore(&imxdma->lock, flags);
 487
 488                 if (slot == IMX_DMA_2D_SLOT_A) {
 489                         d->config_mem &= ~CCR_MSEL_B;
 490                         d->config_port &= ~CCR_MSEL_B;
 491                         imx_dmav1_writel(imxdma, d->x, DMA_XSRA);
 492                         imx_dmav1_writel(imxdma, d->y, DMA_YSRA);
 493                         imx_dmav1_writel(imxdma, d->w, DMA_WSRA);
 494                 } else {
 495                         d->config_mem |= CCR_MSEL_B;
 496                         d->config_port |= CCR_MSEL_B;
 497                         imx_dmav1_writel(imxdma, d->x, DMA_XSRB);
 498                         imx_dmav1_writel(imxdma, d->y, DMA_YSRB);
 499                         imx_dmav1_writel(imxdma, d->w, DMA_WSRB);
 500                 }
 501                 /*
 502                  * We fall-through here intentionally, since a 2D transfer is
 503                  * similar to MEMCPY just adding the 2D slot configuration.
 504                  */
 505         case IMXDMA_DESC_MEMCPY:
 506                 imx_dmav1_writel(imxdma, d->src, DMA_SAR(imxdmac->channel));
 507                 imx_dmav1_writel(imxdma, d->dest, DMA_DAR(imxdmac->channel));
 508                 imx_dmav1_writel(imxdma, d->config_mem | (d->config_port << 2),
 509                          DMA_CCR(imxdmac->channel));
 510
 511                 imx_dmav1_writel(imxdma, d->len, DMA_CNTR(imxdmac->channel));
 512
 513                 dev_dbg(imxdma->dev, "%s channel: %d dest=0x%08x src=0x%08x "
 514                         "dma_length=%d\n", __func__, imxdmac->channel,
 515                         d->dest, d->src, d->len);
 516
 517                 break;
 518         /* Cyclic transfer is the same as slave_sg with special sg configuration. */
 519         case IMXDMA_DESC_CYCLIC:
 520         case IMXDMA_DESC_SLAVE_SG:
 521                 if (d->direction == DMA_DEV_TO_MEM) {
 522                         imx_dmav1_writel(imxdma, imxdmac->per_address,
 523                                          DMA_SAR(imxdmac->channel));
 524                         imx_dmav1_writel(imxdma, imxdmac->ccr_from_device,
 525                                          DMA_CCR(imxdmac->channel));
 526
 527                         dev_dbg(imxdma->dev, "%s channel: %d sg=%p sgcount=%d "
 528                                 "total length=%d dev_addr=0x%08x (dev2mem)\n",
 529                                 __func__, imxdmac->channel, d->sg, d->sgcount,
 530                                 d->len, imxdmac->per_address);
 531                 } else if (d->direction == DMA_MEM_TO_DEV) {
 532                         imx_dmav1_writel(imxdma, imxdmac->per_address,
 533                                          DMA_DAR(imxdmac->channel));
 534                         imx_dmav1_writel(imxdma, imxdmac->ccr_to_device,
 535                                          DMA_CCR(imxdmac->channel));
 536
 537                         dev_dbg(imxdma->dev, "%s channel: %d sg=%p sgcount=%d "
 538                                 "total length=%d dev_addr=0x%08x (mem2dev)\n",
 539                                 __func__, imxdmac->channel, d->sg, d->sgcount,
 540                                 d->len, imxdmac->per_address);
 541                 } else {
 542                         dev_err(imxdma->dev, "%s channel: %d bad dma mode\n",
 543                                 __func__, imxdmac->channel);
 544                         return -EINVAL;
 545                 }
 546
 547                 imxdma_sg_next(d);
 548
 549                 break;
 550         default:
 551                 return -EINVAL;
 552         }
 553         imxdma_enable_hw(d);
 554         return 0;
 555 }
 556
 557 static void imxdma_tasklet(unsigned long data)
 558 {
 559         struct imxdma_channel *imxdmac = (void *)data;
 560         struct imxdma_engine *imxdma = imxdmac->imxdma;
 561         struct imxdma_desc *desc;
 562
 563         spin_lock(&imxdma->lock);
 564
 565         if (list_empty(&imxdmac->ld_active)) {
 566                 /* Someone might have called terminate all */
 567                 goto out;
 568         }
 569         desc = list_first_entry(&imxdmac->ld_active, struct imxdma_desc, node);
 570
 571         if (desc->desc.callback)
 572                 desc->desc.callback(desc->desc.callback_param);
 573
 574         dma_cookie_complete(&desc->desc);
 575
 576         /* If we are dealing with a cyclic descriptor keep it on ld_active */
 577         if (imxdma_chan_is_doing_cyclic(imxdmac))
 578                 goto out;
 579
 580         /* Free 2D slot if it was an interleaved transfer */
 581         if (imxdmac->enabled_2d) {
 582                 imxdma->slots_2d[imxdmac->slot_2d].count--;
 583                 imxdmac->enabled_2d = false;
 584         }
 585
 586         list_move_tail(imxdmac->ld_active.next, &imxdmac->ld_free);
 587
 588         if (!list_empty(&imxdmac->ld_queue)) {
 589                 desc = list_first_entry(&imxdmac->ld_queue, struct imxdma_desc,
 590                                         node);
 591                 list_move_tail(imxdmac->ld_queue.next, &imxdmac->ld_active);
 592                 if (imxdma_xfer_desc(desc) < 0)
 593                         dev_warn(imxdma->dev, "%s: channel: %d couldn't xfer desc\n",
 594                                  __func__, imxdmac->channel);
 595         }
 596 out:
 597         spin_unlock(&imxdma->lock);
 598 }
 599
 600 static int imxdma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
 601                 unsigned long arg)
 602 {
 603         struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
 604         struct dma_slave_config *dmaengine_cfg = (void *)arg;
 605         struct imxdma_engine *imxdma = imxdmac->imxdma;
 606         unsigned long flags;
 607         unsigned int mode = 0;
 608
 609         switch (cmd) {
 610         case DMA_TERMINATE_ALL:
 611                 imxdma_disable_hw(imxdmac);
 612
 613                 spin_lock_irqsave(&imxdma->lock, flags);
 614                 list_splice_tail_init(&imxdmac->ld_active, &imxdmac->ld_free);
 615                 list_splice_tail_init(&imxdmac->ld_queue, &imxdmac->ld_free);
 616                 spin_unlock_irqrestore(&imxdma->lock, flags);
 617                 return 0;
 618         case DMA_SLAVE_CONFIG:
 619                 if (dmaengine_cfg->direction == DMA_DEV_TO_MEM) {
 620                         imxdmac->per_address = dmaengine_cfg->src_addr;
 621                         imxdmac->watermark_level = dmaengine_cfg->src_maxburst;
 622                         imxdmac->word_size = dmaengine_cfg->src_addr_width;
 623                 } else {
 624                         imxdmac->per_address = dmaengine_cfg->dst_addr;
 625                         imxdmac->watermark_level = dmaengine_cfg->dst_maxburst;
 626                         imxdmac->word_size = dmaengine_cfg->dst_addr_width;
 627                 }
 628
 629                 switch (imxdmac->word_size) {
 630                 case DMA_SLAVE_BUSWIDTH_1_BYTE:
 631                         mode = IMX_DMA_MEMSIZE_8;
 632                         break;
 633                 case DMA_SLAVE_BUSWIDTH_2_BYTES:
 634                         mode = IMX_DMA_MEMSIZE_16;
 635                         break;
 636                 default:
 637                 case DMA_SLAVE_BUSWIDTH_4_BYTES:
 638                         mode = IMX_DMA_MEMSIZE_32;
 639                         break;
 640                 }
 641
 642                 imxdmac->hw_chaining = 1;
 643                 if (!imxdma_hw_chain(imxdmac))
 644                         return -EINVAL;
 645                 imxdmac->ccr_from_device = (mode | IMX_DMA_TYPE_FIFO) |
 646                         ((IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR) << 2) |
 647                         CCR_REN;
 648                 imxdmac->ccr_to_device =
 649                         (IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR) |
 650                         ((mode | IMX_DMA_TYPE_FIFO) << 2) | CCR_REN;
 651                 imx_dmav1_writel(imxdma, imxdmac->dma_request,
 652                                  DMA_RSSR(imxdmac->channel));
 653
 654                 /* Set burst length */
 655                 imx_dmav1_writel(imxdma, imxdmac->watermark_level *
 656                                 imxdmac->word_size, DMA_BLR(imxdmac->channel));
 657
 658                 return 0;
 659         default:
 660                 return -ENOSYS;
 661         }
 662
 663         return -EINVAL;
 664 }
 665
 666 static enum dma_status imxdma_tx_status(struct dma_chan *chan,
 667                                             dma_cookie_t cookie,
 668                                             struct dma_tx_state *txstate)
 669 {
 670         return dma_cookie_status(chan, cookie, txstate);
 671 }
 672
 673 static dma_cookie_t imxdma_tx_submit(struct dma_async_tx_descriptor *tx)
 674 {
 675         struct imxdma_channel *imxdmac = to_imxdma_chan(tx->chan);
 676         struct imxdma_engine *imxdma = imxdmac->imxdma;
 677         dma_cookie_t cookie;
 678         unsigned long flags;
 679
 680         spin_lock_irqsave(&imxdma->lock, flags);
 681         list_move_tail(imxdmac->ld_free.next, &imxdmac->ld_queue);
 682         cookie = dma_cookie_assign(tx);
 683         spin_unlock_irqrestore(&imxdma->lock, flags);
 684
 685         return cookie;
 686 }
 687
 688 static int imxdma_alloc_chan_resources(struct dma_chan *chan)
 689 {
 690         struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
 691         struct imx_dma_data *data = chan->private;
 692
 693         if (data != NULL)
 694                 imxdmac->dma_request = data->dma_request;
 695
 696         while (imxdmac->descs_allocated < IMXDMA_MAX_CHAN_DESCRIPTORS) {
 697                 struct imxdma_desc *desc;
 698
 699                 desc = kzalloc(sizeof(*desc), GFP_KERNEL);
 700                 if (!desc)
 701                         break;
 702                 __memzero(&desc->desc, sizeof(struct dma_async_tx_descriptor));
 703                 dma_async_tx_descriptor_init(&desc->desc, chan);
 704                 desc->desc.tx_submit = imxdma_tx_submit;
 705                 /* txd.flags will be overwritten in prep funcs */
 706                 desc->desc.flags = DMA_CTRL_ACK;
 707                 desc->status = DMA_SUCCESS;
 708
 709                 list_add_tail(&desc->node, &imxdmac->ld_free);
 710                 imxdmac->descs_allocated++;
 711         }
 712
 713         if (!imxdmac->descs_allocated)
 714                 return -ENOMEM;
 715
 716         return imxdmac->descs_allocated;
 717 }
 718
 719 static void imxdma_free_chan_resources(struct dma_chan *chan)
 720 {
 721         struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
 722         struct imxdma_engine *imxdma = imxdmac->imxdma;
 723         struct imxdma_desc *desc, *_desc;
 724         unsigned long flags;
 725
 726         spin_lock_irqsave(&imxdma->lock, flags);
 727
 728         imxdma_disable_hw(imxdmac);
 729         list_splice_tail_init(&imxdmac->ld_active, &imxdmac->ld_free);
 730         list_splice_tail_init(&imxdmac->ld_queue, &imxdmac->ld_free);
 731
 732         spin_unlock_irqrestore(&imxdma->lock, flags);
 733
 734         list_for_each_entry_safe(desc, _desc, &imxdmac->ld_free, node) {
 735                 kfree(desc);
 736                 imxdmac->descs_allocated--;
 737         }
 738         INIT_LIST_HEAD(&imxdmac->ld_free);
 739
 740         if (imxdmac->sg_list) {
 741                 kfree(imxdmac->sg_list);
 742                 imxdmac->sg_list = NULL;
 743         }
 744 }
 745
 746 static struct dma_async_tx_descriptor *imxdma_prep_slave_sg(
 747                 struct dma_chan *chan, struct scatterlist *sgl,
 748                 unsigned int sg_len, enum dma_transfer_direction direction,
 749                 unsigned long flags, void *context)
 750 {
 751         struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
 752         struct scatterlist *sg;
 753         int i, dma_length = 0;
 754         struct imxdma_desc *desc;
 755
 756         if (list_empty(&imxdmac->ld_free) ||
 757             imxdma_chan_is_doing_cyclic(imxdmac))
 758                 return NULL;
 759
 760         desc = list_first_entry(&imxdmac->ld_free, struct imxdma_desc, node);
 761
 762         for_each_sg(sgl, sg, sg_len, i) {
 763                 dma_length += sg->length;
 764         }
 765
 766         switch (imxdmac->word_size) {
 767         case DMA_SLAVE_BUSWIDTH_4_BYTES:
 768                 if (sgl->length & 3 || sgl->dma_address & 3)
 769                         return NULL;
 770                 break;
 771         case DMA_SLAVE_BUSWIDTH_2_BYTES:
 772                 if (sgl->length & 1 || sgl->dma_address & 1)
 773                         return NULL;
 774                 break;
 775         case DMA_SLAVE_BUSWIDTH_1_BYTE:
 776                 break;
 777         default:
 778                 return NULL;
 779         }
 780
 781         desc->type = IMXDMA_DESC_SLAVE_SG;
 782         desc->sg = sgl;
 783         desc->sgcount = sg_len;
 784         desc->len = dma_length;
 785         desc->direction = direction;
 786         if (direction == DMA_DEV_TO_MEM) {
 787                 desc->src = imxdmac->per_address;
 788         } else {
 789                 desc->dest = imxdmac->per_address;
 790         }
 791         desc->desc.callback = NULL;
 792         desc->desc.callback_param = NULL;
 793
 794         return &desc->desc;
 795 }
 796
 797 static struct dma_async_tx_descriptor *imxdma_prep_dma_cyclic(
 798                 struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len,
 799                 size_t period_len, enum dma_transfer_direction direction,
 800                 void *context)
 801 {
 802         struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
 803         struct imxdma_engine *imxdma = imxdmac->imxdma;
 804         struct imxdma_desc *desc;
 805         int i;
 806         unsigned int periods = buf_len / period_len;
 807
 808         dev_dbg(imxdma->dev, "%s channel: %d buf_len=%d period_len=%d\n",
 809                         __func__, imxdmac->channel, buf_len, period_len);
 810
 811         if (list_empty(&imxdmac->ld_free) ||
 812             imxdma_chan_is_doing_cyclic(imxdmac))
 813                 return NULL;
 814
 815         desc = list_first_entry(&imxdmac->ld_free, struct imxdma_desc, node);
 816
 817         if (imxdmac->sg_list)
 818                 kfree(imxdmac->sg_list);
 819
 820         imxdmac->sg_list = kcalloc(periods + 1,
 821                         sizeof(struct scatterlist), GFP_KERNEL);
 822         if (!imxdmac->sg_list)
 823                 return NULL;
 824
 825         sg_init_table(imxdmac->sg_list, periods);
 826
 827         for (i = 0; i < periods; i++) {
 828                 imxdmac->sg_list[i].page_link = 0;
 829                 imxdmac->sg_list[i].offset = 0;
 830                 imxdmac->sg_list[i].dma_address = dma_addr;
 831                 imxdmac->sg_list[i].length = period_len;
 832                 dma_addr += period_len;
 833         }
 834
 835         /* close the loop */
 836         imxdmac->sg_list[periods].offset = 0;
 837         imxdmac->sg_list[periods].length = 0;
 838         imxdmac->sg_list[periods].page_link =
 839                 ((unsigned long)imxdmac->sg_list | 0x01) & ~0x02;
 840
 841         desc->type = IMXDMA_DESC_CYCLIC;
 842         desc->sg = imxdmac->sg_list;
 843         desc->sgcount = periods;
 844         desc->len = IMX_DMA_LENGTH_LOOP;
 845         desc->direction = direction;
 846         if (direction == DMA_DEV_TO_MEM) {
 847                 desc->src = imxdmac->per_address;
 848         } else {
 849                 desc->dest = imxdmac->per_address;
 850         }
 851         desc->desc.callback = NULL;
 852         desc->desc.callback_param = NULL;
 853
 854         return &desc->desc;
 855 }
 856
 857 static struct dma_async_tx_descriptor *imxdma_prep_dma_memcpy(
 858         struct dma_chan *chan, dma_addr_t dest,
 859         dma_addr_t src, size_t len, unsigned long flags)
 860 {
 861         struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
 862         struct imxdma_engine *imxdma = imxdmac->imxdma;
 863         struct imxdma_desc *desc;
 864
 865         dev_dbg(imxdma->dev, "%s channel: %d src=0x%x dst=0x%x len=%d\n",
 866                         __func__, imxdmac->channel, src, dest, len);
 867
 868         if (list_empty(&imxdmac->ld_free) ||
 869             imxdma_chan_is_doing_cyclic(imxdmac))
 870                 return NULL;
 871
 872         desc = list_first_entry(&imxdmac->ld_free, struct imxdma_desc, node);
 873
 874         desc->type = IMXDMA_DESC_MEMCPY;
 875         desc->src = src;
 876         desc->dest = dest;
 877         desc->len = len;
 878         desc->direction = DMA_MEM_TO_MEM;
 879         desc->config_port = IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR;
 880         desc->config_mem = IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR;
 881         desc->desc.callback = NULL;
 882         desc->desc.callback_param = NULL;
 883
 884         return &desc->desc;
 885 }
 886
 887 static struct dma_async_tx_descriptor *imxdma_prep_dma_interleaved(
 888         struct dma_chan *chan, struct dma_interleaved_template *xt,
 889         unsigned long flags)
 890 {
 891         struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
 892         struct imxdma_engine *imxdma = imxdmac->imxdma;
 893         struct imxdma_desc *desc;
 894
 895         dev_dbg(imxdma->dev, "%s channel: %d src_start=0x%x dst_start=0x%x\n"
 896                 "   src_sgl=%s dst_sgl=%s numf=%d frame_size=%d\n", __func__,
 897                 imxdmac->channel, xt->src_start, xt->dst_start,
 898                 xt->src_sgl ? "true" : "false", xt->dst_sgl ? "true" : "false",
 899                 xt->numf, xt->frame_size);
 900
 901         if (list_empty(&imxdmac->ld_free) ||
 902             imxdma_chan_is_doing_cyclic(imxdmac))
 903                 return NULL;
 904
 905         if (xt->frame_size != 1 || xt->numf <= 0 || xt->dir != DMA_MEM_TO_MEM)
 906                 return NULL;
 907
 908         desc = list_first_entry(&imxdmac->ld_free, struct imxdma_desc, node);
 909
 910         desc->type = IMXDMA_DESC_INTERLEAVED;
 911         desc->src = xt->src_start;
 912         desc->dest = xt->dst_start;
 913         desc->x = xt->sgl[0].size;
 914         desc->y = xt->numf;
 915         desc->w = xt->sgl[0].icg + desc->x;
 916         desc->len = desc->x * desc->y;
 917         desc->direction = DMA_MEM_TO_MEM;
 918         desc->config_port = IMX_DMA_MEMSIZE_32;
 919         desc->config_mem = IMX_DMA_MEMSIZE_32;
 920         if (xt->src_sgl)
 921                 desc->config_mem |= IMX_DMA_TYPE_2D;
 922         if (xt->dst_sgl)
 923                 desc->config_port |= IMX_DMA_TYPE_2D;
 924         desc->desc.callback = NULL;
 925         desc->desc.callback_param = NULL;
 926
 927         return &desc->desc;
 928 }
 929
 930 static void imxdma_issue_pending(struct dma_chan *chan)
 931 {
 932         struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
 933         struct imxdma_engine *imxdma = imxdmac->imxdma;
 934         struct imxdma_desc *desc;
 935         unsigned long flags;
 936
 937         spin_lock_irqsave(&imxdma->lock, flags);
 938         if (list_empty(&imxdmac->ld_active) &&
 939             !list_empty(&imxdmac->ld_queue)) {
 940                 desc = list_first_entry(&imxdmac->ld_queue,
 941                                         struct imxdma_desc, node);
 942
 943                 if (imxdma_xfer_desc(desc) < 0) {
 944                         dev_warn(imxdma->dev,
 945                                  "%s: channel: %d couldn't issue DMA xfer\n",
 946                                  __func__, imxdmac->channel);
 947                 } else {
 948                         list_move_tail(imxdmac->ld_queue.next,
 949                                        &imxdmac->ld_active);
 950                 }
 951         }
 952         spin_unlock_irqrestore(&imxdma->lock, flags);
 953 }
 954
 955 static int __init imxdma_probe(struct platform_device *pdev)
 956         {
 957         struct imxdma_engine *imxdma;
 958         int ret, i;
 959
 960
 961         imxdma = kzalloc(sizeof(*imxdma), GFP_KERNEL);
 962         if (!imxdma)
 963                 return -ENOMEM;
 964
 965         if (cpu_is_mx1()) {
 966                 imxdma->base = MX1_IO_ADDRESS(MX1_DMA_BASE_ADDR);
 967         } else if (cpu_is_mx21()) {
 968                 imxdma->base = MX21_IO_ADDRESS(MX21_DMA_BASE_ADDR);
 969         } else if (cpu_is_mx27()) {
 970                 imxdma->base = MX27_IO_ADDRESS(MX27_DMA_BASE_ADDR);
 971         } else {
 972                 kfree(imxdma);
 973                 return 0;
 974         }
 975
 976         imxdma->dma_clk = clk_get(NULL, "dma");
 977         if (IS_ERR(imxdma->dma_clk))
 978                 return PTR_ERR(imxdma->dma_clk);
 979         clk_enable(imxdma->dma_clk);
 980
 981         /* reset DMA module */
 982         imx_dmav1_writel(imxdma, DCR_DRST, DMA_DCR);
 983
 984         if (cpu_is_mx1()) {
 985                 ret = request_irq(MX1_DMA_INT, dma_irq_handler, 0, "DMA", imxdma);
 986                 if (ret) {
 987                         dev_warn(imxdma->dev, "Can't register IRQ for DMA\n");
 988                         kfree(imxdma);
 989                         return ret;
 990                 }
 991
 992                 ret = request_irq(MX1_DMA_ERR, imxdma_err_handler, 0, "DMA", imxdma);
 993                 if (ret) {
 994                         dev_warn(imxdma->dev, "Can't register ERRIRQ for DMA\n");
 995                         free_irq(MX1_DMA_INT, NULL);
 996                         kfree(imxdma);
 997                         return ret;
 998                 }
 999         }
1000
1001         /* enable DMA module */
1002         imx_dmav1_writel(imxdma, DCR_DEN, DMA_DCR);
1003
1004         /* clear all interrupts */
1005         imx_dmav1_writel(imxdma, (1 << IMX_DMA_CHANNELS) - 1, DMA_DISR);
1006
1007         /* disable interrupts */
1008         imx_dmav1_writel(imxdma, (1 << IMX_DMA_CHANNELS) - 1, DMA_DIMR);
1009
1010         INIT_LIST_HEAD(&imxdma->dma_device.channels);
1011
1012         dma_cap_set(DMA_SLAVE, imxdma->dma_device.cap_mask);
1013         dma_cap_set(DMA_CYCLIC, imxdma->dma_device.cap_mask);
1014         dma_cap_set(DMA_MEMCPY, imxdma->dma_device.cap_mask);
1015         dma_cap_set(DMA_INTERLEAVE, imxdma->dma_device.cap_mask);
1016
1017         /* Initialize 2D global parameters */
1018         for (i = 0; i < IMX_DMA_2D_SLOTS; i++)
1019                 imxdma->slots_2d[i].count = 0;
1020
1021         spin_lock_init(&imxdma->lock);
1022
1023         /* Initialize channel parameters */
1024         for (i = 0; i < IMX_DMA_CHANNELS; i++) {
1025                 struct imxdma_channel *imxdmac = &imxdma->channel[i];
1026
1027                 if (cpu_is_mx21() || cpu_is_mx27()) {
1028                         ret = request_irq(MX2x_INT_DMACH0 + i,
1029                                         dma_irq_handler, 0, "DMA", imxdma);
1030                         if (ret) {
1031                                 dev_warn(imxdma->dev, "Can't register IRQ %d "
1032                                          "for DMA channel %d\n",
1033                                          MX2x_INT_DMACH0 + i, i);
1034                                 goto err_init;
1035                         }
1036                         init_timer(&imxdmac->watchdog);
1037                         imxdmac->watchdog.function = &imxdma_watchdog;
1038                         imxdmac->watchdog.data = (unsigned long)imxdmac;
1039                 }
1040
1041                 imxdmac->imxdma = imxdma;
1042
1043                 INIT_LIST_HEAD(&imxdmac->ld_queue);
1044                 INIT_LIST_HEAD(&imxdmac->ld_free);
1045                 INIT_LIST_HEAD(&imxdmac->ld_active);
1046
1047                 tasklet_init(&imxdmac->dma_tasklet, imxdma_tasklet,
1048                              (unsigned long)imxdmac);
1049                 imxdmac->chan.device = &imxdma->dma_device;
1050                 dma_cookie_init(&imxdmac->chan);
1051                 imxdmac->channel = i;
1052
1053                 /* Add the channel to the DMAC list */
1054                 list_add_tail(&imxdmac->chan.device_node,
1055                               &imxdma->dma_device.channels);
1056         }
1057
1058         imxdma->dev = &pdev->dev;
1059         imxdma->dma_device.dev = &pdev->dev;
1060
1061         imxdma->dma_device.device_alloc_chan_resources = imxdma_alloc_chan_resources;
1062         imxdma->dma_device.device_free_chan_resources = imxdma_free_chan_resources;
1063         imxdma->dma_device.device_tx_status = imxdma_tx_status;
1064         imxdma->dma_device.device_prep_slave_sg = imxdma_prep_slave_sg;
1065         imxdma->dma_device.device_prep_dma_cyclic = imxdma_prep_dma_cyclic;
1066         imxdma->dma_device.device_prep_dma_memcpy = imxdma_prep_dma_memcpy;
1067         imxdma->dma_device.device_prep_interleaved_dma = imxdma_prep_dma_interleaved;
1068         imxdma->dma_device.device_control = imxdma_control;
1069         imxdma->dma_device.device_issue_pending = imxdma_issue_pending;
1070
1071         platform_set_drvdata(pdev, imxdma);
1072
1073         imxdma->dma_device.copy_align = 2; /* 2^2 = 4 bytes alignment */
1074         imxdma->dma_device.dev->dma_parms = &imxdma->dma_parms;
1075         dma_set_max_seg_size(imxdma->dma_device.dev, 0xffffff);
1076
1077         ret = dma_async_device_register(&imxdma->dma_device);
1078         if (ret) {
1079                 dev_err(&pdev->dev, "unable to register\n");
1080                 goto err_init;
1081         }
1082
1083         return 0;
1084
1085 err_init:
1086
1087         if (cpu_is_mx21() || cpu_is_mx27()) {
1088                 while (--i >= 0)
1089                         free_irq(MX2x_INT_DMACH0 + i, NULL);
1090         } else if cpu_is_mx1() {
1091                 free_irq(MX1_DMA_INT, NULL);
1092                 free_irq(MX1_DMA_ERR, NULL);
1093         }
1094
1095         kfree(imxdma);
1096         return ret;
1097 }
1098
1099 static int __exit imxdma_remove(struct platform_device *pdev)
1100 {
1101         struct imxdma_engine *imxdma = platform_get_drvdata(pdev);
1102         int i;
1103
1104         dma_async_device_unregister(&imxdma->dma_device);
1105
1106         if (cpu_is_mx21() || cpu_is_mx27()) {
1107                 for (i = 0; i < IMX_DMA_CHANNELS; i++)
1108                         free_irq(MX2x_INT_DMACH0 + i, NULL);
1109         } else if cpu_is_mx1() {
1110                 free_irq(MX1_DMA_INT, NULL);
1111                 free_irq(MX1_DMA_ERR, NULL);
1112         }
1113
1114         kfree(imxdma);
1115
1116         return 0;
1117 }
1118
1119 static struct platform_driver imxdma_driver = {
1120         .driver         = {
1121                 .name   = "imx-dma",
1122         },
1123         .remove         = __exit_p(imxdma_remove),
1124 };
1125
1126 static int __init imxdma_module_init(void)
1127 {
1128         return platform_driver_probe(&imxdma_driver, imxdma_probe);
1129 }
1130 subsys_initcall(imxdma_module_init);
1131
1132 MODULE_AUTHOR("Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>");
1133 MODULE_DESCRIPTION("i.MX dma driver");
1134 MODULE_LICENSE("GPL");