drivers/dma/imx-dma.c

   1 /*
   2  * drivers/dma/imx-dma.c
   3  *
   4  * This file contains a driver for the Freescale i.MX DMA engine
   5  * found on i.MX1/21/27
   6  *
   7  * Copyright 2010 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
   8  *
   9  * The code contained herein is licensed under the GNU General Public
  10  * License. You may obtain a copy of the GNU General Public License
  11  * Version 2 or later at the following locations:
  12  *
  13  * http://www.opensource.org/licenses/gpl-license.html
  14  * http://www.gnu.org/copyleft/gpl.html
  15  */
  16 #include <linux/init.h>
  17 #include <linux/module.h>
  18 #include <linux/types.h>
  19 #include <linux/mm.h>
  20 #include <linux/interrupt.h>
  21 #include <linux/spinlock.h>
  22 #include <linux/device.h>
  23 #include <linux/dma-mapping.h>
  24 #include <linux/slab.h>
  25 #include <linux/platform_device.h>
  26 #include <linux/dmaengine.h>
  27 #include <linux/module.h>
  28
  29 #include <asm/irq.h>
  30 #include <mach/dma-v1.h>
  31 #include <mach/hardware.h>
  32
  33 #include "dmaengine.h"
  34
  35 struct imxdma_channel {
  36         struct imxdma_engine            *imxdma;
  37         unsigned int                    channel;
  38         unsigned int                    imxdma_channel;
  39
  40         enum dma_slave_buswidth         word_size;
  41         dma_addr_t                      per_address;
  42         u32                             watermark_level;
  43         struct dma_chan                 chan;
  44         spinlock_t                      lock;
  45         struct dma_async_tx_descriptor  desc;
  46         enum dma_status                 status;
  47         int                             dma_request;
  48         struct scatterlist              *sg_list;
  49 };
  50
  51 #define MAX_DMA_CHANNELS 8
  52
  53 struct imxdma_engine {
  54         struct device                   *dev;
  55         struct device_dma_parameters    dma_parms;
  56         struct dma_device               dma_device;
  57         struct imxdma_channel           channel[MAX_DMA_CHANNELS];
  58 };
  59
  60 static struct imxdma_channel *to_imxdma_chan(struct dma_chan *chan)
  61 {
  62         return container_of(chan, struct imxdma_channel, chan);
  63 }
  64
  65 static void imxdma_handle(struct imxdma_channel *imxdmac)
  66 {
  67         if (imxdmac->desc.callback)
  68                 imxdmac->desc.callback(imxdmac->desc.callback_param);
  69         imxdmac->chan.completed_cookie = imxdmac->desc.cookie;
  70 }
  71
  72 static void imxdma_irq_handler(int channel, void *data)
  73 {
  74         struct imxdma_channel *imxdmac = data;
  75
  76         imxdmac->status = DMA_SUCCESS;
  77         imxdma_handle(imxdmac);
  78 }
  79
  80 static void imxdma_err_handler(int channel, void *data, int error)
  81 {
  82         struct imxdma_channel *imxdmac = data;
  83
  84         imxdmac->status = DMA_ERROR;
  85         imxdma_handle(imxdmac);
  86 }
  87
  88 static void imxdma_progression(int channel, void *data,
  89                 struct scatterlist *sg)
  90 {
  91         struct imxdma_channel *imxdmac = data;
  92
  93         imxdmac->status = DMA_SUCCESS;
  94         imxdma_handle(imxdmac);
  95 }
  96
  97 static int imxdma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
  98                 unsigned long arg)
  99 {
 100         struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
 101         struct dma_slave_config *dmaengine_cfg = (void *)arg;
 102         int ret;
 103         unsigned int mode = 0;
 104
 105         switch (cmd) {
 106         case DMA_TERMINATE_ALL:
 107                 imxdmac->status = DMA_ERROR;
 108                 imx_dma_disable(imxdmac->imxdma_channel);
 109                 return 0;
 110         case DMA_SLAVE_CONFIG:
 111                 if (dmaengine_cfg->direction == DMA_DEV_TO_MEM) {
 112                         imxdmac->per_address = dmaengine_cfg->src_addr;
 113                         imxdmac->watermark_level = dmaengine_cfg->src_maxburst;
 114                         imxdmac->word_size = dmaengine_cfg->src_addr_width;
 115                 } else {
 116                         imxdmac->per_address = dmaengine_cfg->dst_addr;
 117                         imxdmac->watermark_level = dmaengine_cfg->dst_maxburst;
 118                         imxdmac->word_size = dmaengine_cfg->dst_addr_width;
 119                 }
 120
 121                 switch (imxdmac->word_size) {
 122                 case DMA_SLAVE_BUSWIDTH_1_BYTE:
 123                         mode = IMX_DMA_MEMSIZE_8;
 124                         break;
 125                 case DMA_SLAVE_BUSWIDTH_2_BYTES:
 126                         mode = IMX_DMA_MEMSIZE_16;
 127                         break;
 128                 default:
 129                 case DMA_SLAVE_BUSWIDTH_4_BYTES:
 130                         mode = IMX_DMA_MEMSIZE_32;
 131                         break;
 132                 }
 133                 ret = imx_dma_config_channel(imxdmac->imxdma_channel,
 134                                 mode | IMX_DMA_TYPE_FIFO,
 135                                 IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR,
 136                                 imxdmac->dma_request, 1);
 137
 138                 if (ret)
 139                         return ret;
 140
 141                 imx_dma_config_burstlen(imxdmac->imxdma_channel,
 142                                 imxdmac->watermark_level * imxdmac->word_size);
 143
 144                 return 0;
 145         default:
 146                 return -ENOSYS;
 147         }
 148
 149         return -EINVAL;
 150 }
 151
 152 static enum dma_status imxdma_tx_status(struct dma_chan *chan,
 153                                             dma_cookie_t cookie,
 154                                             struct dma_tx_state *txstate)
 155 {
 156         struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
 157         dma_cookie_t last_used;
 158         enum dma_status ret;
 159
 160         last_used = chan->cookie;
 161
 162         ret = dma_async_is_complete(cookie, chan->completed_cookie, last_used);
 163         dma_set_tx_state(txstate, chan->completed_cookie, last_used, 0);
 164
 165         return ret;
 166 }
 167
 168 static dma_cookie_t imxdma_tx_submit(struct dma_async_tx_descriptor *tx)
 169 {
 170         struct imxdma_channel *imxdmac = to_imxdma_chan(tx->chan);
 171         dma_cookie_t cookie;
 172
 173         spin_lock_irq(&imxdmac->lock);
 174
 175         cookie = dma_cookie_assign(tx);
 176
 177         spin_unlock_irq(&imxdmac->lock);
 178
 179         return cookie;
 180 }
 181
 182 static int imxdma_alloc_chan_resources(struct dma_chan *chan)
 183 {
 184         struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
 185         struct imx_dma_data *data = chan->private;
 186
 187         imxdmac->dma_request = data->dma_request;
 188
 189         dma_async_tx_descriptor_init(&imxdmac->desc, chan);
 190         imxdmac->desc.tx_submit = imxdma_tx_submit;
 191         /* txd.flags will be overwritten in prep funcs */
 192         imxdmac->desc.flags = DMA_CTRL_ACK;
 193
 194         imxdmac->status = DMA_SUCCESS;
 195
 196         return 0;
 197 }
 198
 199 static void imxdma_free_chan_resources(struct dma_chan *chan)
 200 {
 201         struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
 202
 203         imx_dma_disable(imxdmac->imxdma_channel);
 204
 205         if (imxdmac->sg_list) {
 206                 kfree(imxdmac->sg_list);
 207                 imxdmac->sg_list = NULL;
 208         }
 209 }
 210
 211 static struct dma_async_tx_descriptor *imxdma_prep_slave_sg(
 212                 struct dma_chan *chan, struct scatterlist *sgl,
 213                 unsigned int sg_len, enum dma_transfer_direction direction,
 214                 unsigned long flags)
 215 {
 216         struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
 217         struct scatterlist *sg;
 218         int i, ret, dma_length = 0;
 219         unsigned int dmamode;
 220
 221         if (imxdmac->status == DMA_IN_PROGRESS)
 222                 return NULL;
 223
 224         imxdmac->status = DMA_IN_PROGRESS;
 225
 226         for_each_sg(sgl, sg, sg_len, i) {
 227                 dma_length += sg->length;
 228         }
 229
 230         if (direction == DMA_DEV_TO_MEM)
 231                 dmamode = DMA_MODE_READ;
 232         else
 233                 dmamode = DMA_MODE_WRITE;
 234
 235         switch (imxdmac->word_size) {
 236         case DMA_SLAVE_BUSWIDTH_4_BYTES:
 237                 if (sgl->length & 3 || sgl->dma_address & 3)
 238                         return NULL;
 239                 break;
 240         case DMA_SLAVE_BUSWIDTH_2_BYTES:
 241                 if (sgl->length & 1 || sgl->dma_address & 1)
 242                         return NULL;
 243                 break;
 244         case DMA_SLAVE_BUSWIDTH_1_BYTE:
 245                 break;
 246         default:
 247                 return NULL;
 248         }
 249
 250         ret = imx_dma_setup_sg(imxdmac->imxdma_channel, sgl, sg_len,
 251                  dma_length, imxdmac->per_address, dmamode);
 252         if (ret)
 253                 return NULL;
 254
 255         return &imxdmac->desc;
 256 }
 257
 258 static struct dma_async_tx_descriptor *imxdma_prep_dma_cyclic(
 259                 struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len,
 260                 size_t period_len, enum dma_transfer_direction direction)
 261 {
 262         struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
 263         struct imxdma_engine *imxdma = imxdmac->imxdma;
 264         int i, ret;
 265         unsigned int periods = buf_len / period_len;
 266         unsigned int dmamode;
 267
 268         dev_dbg(imxdma->dev, "%s channel: %d buf_len=%d period_len=%d\n",
 269                         __func__, imxdmac->channel, buf_len, period_len);
 270
 271         if (imxdmac->status == DMA_IN_PROGRESS)
 272                 return NULL;
 273         imxdmac->status = DMA_IN_PROGRESS;
 274
 275         ret = imx_dma_setup_progression_handler(imxdmac->imxdma_channel,
 276                         imxdma_progression);
 277         if (ret) {
 278                 dev_err(imxdma->dev, "Failed to setup the DMA handler\n");
 279                 return NULL;
 280         }
 281
 282         if (imxdmac->sg_list)
 283                 kfree(imxdmac->sg_list);
 284
 285         imxdmac->sg_list = kcalloc(periods + 1,
 286                         sizeof(struct scatterlist), GFP_KERNEL);
 287         if (!imxdmac->sg_list)
 288                 return NULL;
 289
 290         sg_init_table(imxdmac->sg_list, periods);
 291
 292         for (i = 0; i < periods; i++) {
 293                 imxdmac->sg_list[i].page_link = 0;
 294                 imxdmac->sg_list[i].offset = 0;
 295                 imxdmac->sg_list[i].dma_address = dma_addr;
 296                 imxdmac->sg_list[i].length = period_len;
 297                 dma_addr += period_len;
 298         }
 299
 300         /* close the loop */
 301         imxdmac->sg_list[periods].offset = 0;
 302         imxdmac->sg_list[periods].length = 0;
 303         imxdmac->sg_list[periods].page_link =
 304                 ((unsigned long)imxdmac->sg_list | 0x01) & ~0x02;
 305
 306         if (direction == DMA_DEV_TO_MEM)
 307                 dmamode = DMA_MODE_READ;
 308         else
 309                 dmamode = DMA_MODE_WRITE;
 310
 311         ret = imx_dma_setup_sg(imxdmac->imxdma_channel, imxdmac->sg_list, periods,
 312                  IMX_DMA_LENGTH_LOOP, imxdmac->per_address, dmamode);
 313         if (ret)
 314                 return NULL;
 315
 316         return &imxdmac->desc;
 317 }
 318
 319 static void imxdma_issue_pending(struct dma_chan *chan)
 320 {
 321         struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
 322
 323         if (imxdmac->status == DMA_IN_PROGRESS)
 324                 imx_dma_enable(imxdmac->imxdma_channel);
 325 }
 326
 327 static int __init imxdma_probe(struct platform_device *pdev)
 328 {
 329         struct imxdma_engine *imxdma;
 330         int ret, i;
 331
 332         imxdma = kzalloc(sizeof(*imxdma), GFP_KERNEL);
 333         if (!imxdma)
 334                 return -ENOMEM;
 335
 336         INIT_LIST_HEAD(&imxdma->dma_device.channels);
 337
 338         dma_cap_set(DMA_SLAVE, imxdma->dma_device.cap_mask);
 339         dma_cap_set(DMA_CYCLIC, imxdma->dma_device.cap_mask);
 340
 341         /* Initialize channel parameters */
 342         for (i = 0; i < MAX_DMA_CHANNELS; i++) {
 343                 struct imxdma_channel *imxdmac = &imxdma->channel[i];
 344
 345                 imxdmac->imxdma_channel = imx_dma_request_by_prio("dmaengine",
 346                                 DMA_PRIO_MEDIUM);
 347                 if ((int)imxdmac->channel < 0) {
 348                         ret = -ENODEV;
 349                         goto err_init;
 350                 }
 351
 352                 imx_dma_setup_handlers(imxdmac->imxdma_channel,
 353                        imxdma_irq_handler, imxdma_err_handler, imxdmac);
 354
 355                 imxdmac->imxdma = imxdma;
 356                 spin_lock_init(&imxdmac->lock);
 357
 358                 imxdmac->chan.device = &imxdma->dma_device;
 359                 imxdmac->channel = i;
 360
 361                 /* Add the channel to the DMAC list */
 362                 list_add_tail(&imxdmac->chan.device_node, &imxdma->dma_device.channels);
 363         }
 364
 365         imxdma->dev = &pdev->dev;
 366         imxdma->dma_device.dev = &pdev->dev;
 367
 368         imxdma->dma_device.device_alloc_chan_resources = imxdma_alloc_chan_resources;
 369         imxdma->dma_device.device_free_chan_resources = imxdma_free_chan_resources;
 370         imxdma->dma_device.device_tx_status = imxdma_tx_status;
 371         imxdma->dma_device.device_prep_slave_sg = imxdma_prep_slave_sg;
 372         imxdma->dma_device.device_prep_dma_cyclic = imxdma_prep_dma_cyclic;
 373         imxdma->dma_device.device_control = imxdma_control;
 374         imxdma->dma_device.device_issue_pending = imxdma_issue_pending;
 375
 376         platform_set_drvdata(pdev, imxdma);
 377
 378         imxdma->dma_device.dev->dma_parms = &imxdma->dma_parms;
 379         dma_set_max_seg_size(imxdma->dma_device.dev, 0xffffff);
 380
 381         ret = dma_async_device_register(&imxdma->dma_device);
 382         if (ret) {
 383                 dev_err(&pdev->dev, "unable to register\n");
 384                 goto err_init;
 385         }
 386
 387         return 0;
 388
 389 err_init:
 390         while (--i >= 0) {
 391                 struct imxdma_channel *imxdmac = &imxdma->channel[i];
 392                 imx_dma_free(imxdmac->imxdma_channel);
 393         }
 394
 395         kfree(imxdma);
 396         return ret;
 397 }
 398
 399 static int __exit imxdma_remove(struct platform_device *pdev)
 400 {
 401         struct imxdma_engine *imxdma = platform_get_drvdata(pdev);
 402         int i;
 403
 404         dma_async_device_unregister(&imxdma->dma_device);
 405
 406         for (i = 0; i < MAX_DMA_CHANNELS; i++) {
 407                 struct imxdma_channel *imxdmac = &imxdma->channel[i];
 408
 409                  imx_dma_free(imxdmac->imxdma_channel);
 410         }
 411
 412         kfree(imxdma);
 413
 414         return 0;
 415 }
 416
 417 static struct platform_driver imxdma_driver = {
 418         .driver         = {
 419                 .name   = "imx-dma",
 420         },
 421         .remove         = __exit_p(imxdma_remove),
 422 };
 423
 424 static int __init imxdma_module_init(void)
 425 {
 426         return platform_driver_probe(&imxdma_driver, imxdma_probe);
 427 }
 428 subsys_initcall(imxdma_module_init);
 429
 430 MODULE_AUTHOR("Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>");
 431 MODULE_DESCRIPTION("i.MX dma driver");
 432 MODULE_LICENSE("GPL");