1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright(c) 2019 Intel Corporation. All rights rsvd. */
3 #ifndef _IDXD_REGISTERS_H_
4 #define _IDXD_REGISTERS_H_
7 #define PCI_DEVICE_ID_INTEL_DSA_SPR0 0x0b25
9 #define IDXD_MMIO_BAR 0
11 #define IDXD_PORTAL_SIZE 0x4000
13 /* MMIO Device BAR0 Registers */
14 #define IDXD_VER_OFFSET 0x00
15 #define IDXD_VER_MAJOR_MASK 0xf0
16 #define IDXD_VER_MINOR_MASK 0x0f
17 #define GET_IDXD_VER_MAJOR(x) (((x) & IDXD_VER_MAJOR_MASK) >> 4)
18 #define GET_IDXD_VER_MINOR(x) ((x) & IDXD_VER_MINOR_MASK)
24 u64 cache_control_mem:1;
25 u64 cache_control_cache:1;
32 u64 max_batch_shift:4;
35 u64 max_descs_per_engine:8;
40 #define IDXD_GENCAP_OFFSET 0x10
58 #define IDXD_WQCAP_OFFSET 0x20
59 #define IDXD_WQCFG_MIN 5
71 #define IDXD_GRPCAP_OFFSET 0x30
73 union engine_cap_reg {
81 #define IDXD_ENGCAP_OFFSET 0x38
83 #define IDXD_OPCAP_NOOP 0x0001
84 #define IDXD_OPCAP_BATCH 0x0002
85 #define IDXD_OPCAP_MEMMOVE 0x0008
90 #define IDXD_OPCAP_OFFSET 0x40
92 #define IDXD_TABLE_OFFSET 0x60
105 #define IDXD_GENCFG_OFFSET 0x80
116 #define IDXD_GENCTRL_OFFSET 0x88
119 u32 softerr_int_en:1;
125 #define IDXD_GENSTATS_OFFSET 0x90
135 enum idxd_device_status_state {
136 IDXD_DEVICE_STATE_DISABLED = 0,
137 IDXD_DEVICE_STATE_ENABLED,
138 IDXD_DEVICE_STATE_DRAIN,
139 IDXD_DEVICE_STATE_HALT,
142 enum idxd_device_reset_type {
143 IDXD_DEVICE_RESET_SOFTWARE = 0,
144 IDXD_DEVICE_RESET_FLR,
145 IDXD_DEVICE_RESET_WARM,
146 IDXD_DEVICE_RESET_COLD,
149 #define IDXD_INTCAUSE_OFFSET 0x98
150 #define IDXD_INTC_ERR 0x01
151 #define IDXD_INTC_CMD 0x02
152 #define IDXD_INTC_OCCUPY 0x04
153 #define IDXD_INTC_PERFMON_OVFL 0x08
155 #define IDXD_CMD_OFFSET 0xa0
156 union idxd_command_reg {
167 IDXD_CMD_ENABLE_DEVICE = 1,
168 IDXD_CMD_DISABLE_DEVICE,
171 IDXD_CMD_RESET_DEVICE,
177 IDXD_CMD_DRAIN_PASID,
178 IDXD_CMD_ABORT_PASID,
179 IDXD_CMD_REQUEST_INT_HANDLE,
182 #define IDXD_CMDSTS_OFFSET 0xa8
192 #define IDXD_CMDSTS_ACTIVE 0x80000000
194 enum idxd_cmdsts_err {
195 IDXD_CMDSTS_SUCCESS = 0,
196 IDXD_CMDSTS_INVAL_CMD,
197 IDXD_CMDSTS_INVAL_WQIDX,
199 /* enable device errors */
200 IDXD_CMDSTS_ERR_DEV_ENABLED = 0x10,
201 IDXD_CMDSTS_ERR_CONFIG,
202 IDXD_CMDSTS_ERR_BUSMASTER_EN,
203 IDXD_CMDSTS_ERR_PASID_INVAL,
204 IDXD_CMDSTS_ERR_WQ_SIZE_ERANGE,
205 IDXD_CMDSTS_ERR_GRP_CONFIG,
206 IDXD_CMDSTS_ERR_GRP_CONFIG2,
207 IDXD_CMDSTS_ERR_GRP_CONFIG3,
208 IDXD_CMDSTS_ERR_GRP_CONFIG4,
209 /* enable wq errors */
210 IDXD_CMDSTS_ERR_DEV_NOTEN = 0x20,
211 IDXD_CMDSTS_ERR_WQ_ENABLED,
212 IDXD_CMDSTS_ERR_WQ_SIZE,
213 IDXD_CMDSTS_ERR_WQ_PRIOR,
214 IDXD_CMDSTS_ERR_WQ_MODE,
215 IDXD_CMDSTS_ERR_BOF_EN,
216 IDXD_CMDSTS_ERR_PASID_EN,
217 IDXD_CMDSTS_ERR_MAX_BATCH_SIZE,
218 IDXD_CMDSTS_ERR_MAX_XFER_SIZE,
219 /* disable device errors */
220 IDXD_CMDSTS_ERR_DIS_DEV_EN = 0x31,
221 /* disable WQ, drain WQ, abort WQ, reset WQ */
222 IDXD_CMDSTS_ERR_DEV_NOT_EN,
223 /* request interrupt handle */
224 IDXD_CMDSTS_ERR_INVAL_INT_IDX = 0x41,
225 IDXD_CMDSTS_ERR_NO_HANDLE,
228 #define IDXD_SWERR_OFFSET 0xc0
229 #define IDXD_SWERR_VALID 0x00000001
230 #define IDXD_SWERR_OVERFLOW 0x00000002
231 #define IDXD_SWERR_ACK (IDXD_SWERR_VALID | IDXD_SWERR_OVERFLOW)
251 u64 invalid_flags:32;
276 u32 use_token_limit:1;
277 u32 tokens_reserved:8;
279 u32 tokens_allowed:8;
288 union group_flags flags;
302 u32 mode:1; /* shared or dedicated */
303 u32 bof:1; /* block on fault */
312 u32 max_xfer_shift:5;
313 u32 max_batch_shift:4;
318 u16 occupancy_table_sel:1;
323 u16 occupancy_int_en:1;
339 #define WQCFG_PASID_IDX 2
342 * This macro calculates the offset into the WQCFG register
343 * idxd - struct idxd *
345 * ofs - the index of the 32b dword for the config register
347 * The WQCFG register block is divided into groups per each wq. The n index
348 * allows us to move to the register group that's for that particular wq.
349 * Each register is 32bits. The ofs gives us the number of register to access.
351 #define WQCFG_OFFSET(_idxd_dev, n, ofs) \
353 typeof(_idxd_dev) __idxd_dev = (_idxd_dev); \
354 (__idxd_dev)->wqcfg_offset + (n) * (__idxd_dev)->wqcfg_size + sizeof(u32) * (ofs); \
357 #define WQCFG_STRIDES(_idxd_dev) ((_idxd_dev)->wqcfg_size / sizeof(u32))