drivers/dma/idxd/init.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /* Copyright(c) 2019 Intel Corporation. All rights rsvd. */
   3 #include <linux/init.h>
   4 #include <linux/kernel.h>
   5 #include <linux/module.h>
   6 #include <linux/slab.h>
   7 #include <linux/pci.h>
   8 #include <linux/interrupt.h>
   9 #include <linux/delay.h>
  10 #include <linux/dma-mapping.h>
  11 #include <linux/workqueue.h>
  12 #include <linux/fs.h>
  13 #include <linux/io-64-nonatomic-lo-hi.h>
  14 #include <linux/device.h>
  15 #include <linux/idr.h>
  16 #include <linux/iommu.h>
  17 #include <uapi/linux/idxd.h>
  18 #include <linux/dmaengine.h>
  19 #include "../dmaengine.h"
  20 #include "registers.h"
  21 #include "idxd.h"
  22 #include "perfmon.h"
  23
  24 MODULE_VERSION(IDXD_DRIVER_VERSION);
  25 MODULE_LICENSE("GPL v2");
  26 MODULE_AUTHOR("Intel Corporation");
  27 MODULE_IMPORT_NS(IDXD);
  28
  29 static bool sva = true;
  30 module_param(sva, bool, 0644);
  31 MODULE_PARM_DESC(sva, "Toggle SVA support on/off");
  32
  33 bool tc_override;
  34 module_param(tc_override, bool, 0644);
  35 MODULE_PARM_DESC(tc_override, "Override traffic class defaults");
  36
  37 #define DRV_NAME "idxd"
  38
  39 bool support_enqcmd;
  40 DEFINE_IDA(idxd_ida);
  41
  42 static struct idxd_driver_data idxd_driver_data[] = {
  43         [IDXD_TYPE_DSA] = {
  44                 .name_prefix = "dsa",
  45                 .type = IDXD_TYPE_DSA,
  46                 .compl_size = sizeof(struct dsa_completion_record),
  47                 .align = 32,
  48                 .dev_type = &dsa_device_type,
  49         },
  50         [IDXD_TYPE_IAX] = {
  51                 .name_prefix = "iax",
  52                 .type = IDXD_TYPE_IAX,
  53                 .compl_size = sizeof(struct iax_completion_record),
  54                 .align = 64,
  55                 .dev_type = &iax_device_type,
  56         },
  57 };
  58
  59 static struct pci_device_id idxd_pci_tbl[] = {
  60         /* DSA ver 1.0 platforms */
  61         { PCI_DEVICE_DATA(INTEL, DSA_SPR0, &idxd_driver_data[IDXD_TYPE_DSA]) },
  62
  63         /* IAX ver 1.0 platforms */
  64         { PCI_DEVICE_DATA(INTEL, IAX_SPR0, &idxd_driver_data[IDXD_TYPE_IAX]) },
  65         { 0, }
  66 };
  67 MODULE_DEVICE_TABLE(pci, idxd_pci_tbl);
  68
  69 static int idxd_setup_interrupts(struct idxd_device *idxd)
  70 {
  71         struct pci_dev *pdev = idxd->pdev;
  72         struct device *dev = &pdev->dev;
  73         struct idxd_irq_entry *ie;
  74         int i, msixcnt;
  75         int rc = 0;
  76
  77         msixcnt = pci_msix_vec_count(pdev);
  78         if (msixcnt < 0) {
  79                 dev_err(dev, "Not MSI-X interrupt capable.\n");
  80                 return -ENOSPC;
  81         }
  82         idxd->irq_cnt = msixcnt;
  83
  84         rc = pci_alloc_irq_vectors(pdev, msixcnt, msixcnt, PCI_IRQ_MSIX);
  85         if (rc != msixcnt) {
  86                 dev_err(dev, "Failed enabling %d MSIX entries: %d\n", msixcnt, rc);
  87                 return -ENOSPC;
  88         }
  89         dev_dbg(dev, "Enabled %d msix vectors\n", msixcnt);
  90
  91
  92         ie = idxd_get_ie(idxd, 0);
  93         ie->vector = pci_irq_vector(pdev, 0);
  94         rc = request_threaded_irq(ie->vector, NULL, idxd_misc_thread, 0, "idxd-misc", ie);
  95         if (rc < 0) {
  96                 dev_err(dev, "Failed to allocate misc interrupt.\n");
  97                 goto err_misc_irq;
  98         }
  99         dev_dbg(dev, "Requested idxd-misc handler on msix vector %d\n", ie->vector);
 100
 101         for (i = 0; i < idxd->max_wqs; i++) {
 102                 int msix_idx = i + 1;
 103
 104                 ie = idxd_get_ie(idxd, msix_idx);
 105                 ie->id = msix_idx;
 106                 ie->int_handle = INVALID_INT_HANDLE;
 107                 ie->pasid = INVALID_IOASID;
 108
 109                 spin_lock_init(&ie->list_lock);
 110                 init_llist_head(&ie->pending_llist);
 111                 INIT_LIST_HEAD(&ie->work_list);
 112         }
 113
 114         idxd_unmask_error_interrupts(idxd);
 115         return 0;
 116
 117  err_misc_irq:
 118         idxd_mask_error_interrupts(idxd);
 119         pci_free_irq_vectors(pdev);
 120         dev_err(dev, "No usable interrupts\n");
 121         return rc;
 122 }
 123
 124 static void idxd_cleanup_interrupts(struct idxd_device *idxd)
 125 {
 126         struct pci_dev *pdev = idxd->pdev;
 127         struct idxd_irq_entry *ie;
 128         int msixcnt;
 129
 130         msixcnt = pci_msix_vec_count(pdev);
 131         if (msixcnt <= 0)
 132                 return;
 133
 134         ie = idxd_get_ie(idxd, 0);
 135         idxd_mask_error_interrupts(idxd);
 136         free_irq(ie->vector, ie);
 137         pci_free_irq_vectors(pdev);
 138 }
 139
 140 static int idxd_setup_wqs(struct idxd_device *idxd)
 141 {
 142         struct device *dev = &idxd->pdev->dev;
 143         struct idxd_wq *wq;
 144         struct device *conf_dev;
 145         int i, rc;
 146
 147         idxd->wqs = kcalloc_node(idxd->max_wqs, sizeof(struct idxd_wq *),
 148                                  GFP_KERNEL, dev_to_node(dev));
 149         if (!idxd->wqs)
 150                 return -ENOMEM;
 151
 152         idxd->wq_enable_map = bitmap_zalloc_node(idxd->max_wqs, GFP_KERNEL, dev_to_node(dev));
 153         if (!idxd->wq_enable_map) {
 154                 kfree(idxd->wqs);
 155                 return -ENOMEM;
 156         }
 157
 158         for (i = 0; i < idxd->max_wqs; i++) {
 159                 wq = kzalloc_node(sizeof(*wq), GFP_KERNEL, dev_to_node(dev));
 160                 if (!wq) {
 161                         rc = -ENOMEM;
 162                         goto err;
 163                 }
 164
 165                 idxd_dev_set_type(&wq->idxd_dev, IDXD_DEV_WQ);
 166                 conf_dev = wq_confdev(wq);
 167                 wq->id = i;
 168                 wq->idxd = idxd;
 169                 device_initialize(wq_confdev(wq));
 170                 conf_dev->parent = idxd_confdev(idxd);
 171                 conf_dev->bus = &dsa_bus_type;
 172                 conf_dev->type = &idxd_wq_device_type;
 173                 rc = dev_set_name(conf_dev, "wq%d.%d", idxd->id, wq->id);
 174                 if (rc < 0) {
 175                         put_device(conf_dev);
 176                         goto err;
 177                 }
 178
 179                 mutex_init(&wq->wq_lock);
 180                 init_waitqueue_head(&wq->err_queue);
 181                 init_completion(&wq->wq_dead);
 182                 init_completion(&wq->wq_resurrect);
 183                 wq->max_xfer_bytes = WQ_DEFAULT_MAX_XFER;
 184                 idxd_wq_set_max_batch_size(idxd->data->type, wq, WQ_DEFAULT_MAX_BATCH);
 185                 wq->enqcmds_retries = IDXD_ENQCMDS_RETRIES;
 186                 wq->wqcfg = kzalloc_node(idxd->wqcfg_size, GFP_KERNEL, dev_to_node(dev));
 187                 if (!wq->wqcfg) {
 188                         put_device(conf_dev);
 189                         rc = -ENOMEM;
 190                         goto err;
 191                 }
 192
 193                 if (idxd->hw.wq_cap.op_config) {
 194                         wq->opcap_bmap = bitmap_zalloc(IDXD_MAX_OPCAP_BITS, GFP_KERNEL);
 195                         if (!wq->opcap_bmap) {
 196                                 put_device(conf_dev);
 197                                 rc = -ENOMEM;
 198                                 goto err;
 199                         }
 200                         bitmap_copy(wq->opcap_bmap, idxd->opcap_bmap, IDXD_MAX_OPCAP_BITS);
 201                 }
 202                 idxd->wqs[i] = wq;
 203         }
 204
 205         return 0;
 206
 207  err:
 208         while (--i >= 0) {
 209                 wq = idxd->wqs[i];
 210                 conf_dev = wq_confdev(wq);
 211                 put_device(conf_dev);
 212         }
 213         return rc;
 214 }
 215
 216 static int idxd_setup_engines(struct idxd_device *idxd)
 217 {
 218         struct idxd_engine *engine;
 219         struct device *dev = &idxd->pdev->dev;
 220         struct device *conf_dev;
 221         int i, rc;
 222
 223         idxd->engines = kcalloc_node(idxd->max_engines, sizeof(struct idxd_engine *),
 224                                      GFP_KERNEL, dev_to_node(dev));
 225         if (!idxd->engines)
 226                 return -ENOMEM;
 227
 228         for (i = 0; i < idxd->max_engines; i++) {
 229                 engine = kzalloc_node(sizeof(*engine), GFP_KERNEL, dev_to_node(dev));
 230                 if (!engine) {
 231                         rc = -ENOMEM;
 232                         goto err;
 233                 }
 234
 235                 idxd_dev_set_type(&engine->idxd_dev, IDXD_DEV_ENGINE);
 236                 conf_dev = engine_confdev(engine);
 237                 engine->id = i;
 238                 engine->idxd = idxd;
 239                 device_initialize(conf_dev);
 240                 conf_dev->parent = idxd_confdev(idxd);
 241                 conf_dev->bus = &dsa_bus_type;
 242                 conf_dev->type = &idxd_engine_device_type;
 243                 rc = dev_set_name(conf_dev, "engine%d.%d", idxd->id, engine->id);
 244                 if (rc < 0) {
 245                         put_device(conf_dev);
 246                         goto err;
 247                 }
 248
 249                 idxd->engines[i] = engine;
 250         }
 251
 252         return 0;
 253
 254  err:
 255         while (--i >= 0) {
 256                 engine = idxd->engines[i];
 257                 conf_dev = engine_confdev(engine);
 258                 put_device(conf_dev);
 259         }
 260         return rc;
 261 }
 262
 263 static int idxd_setup_groups(struct idxd_device *idxd)
 264 {
 265         struct device *dev = &idxd->pdev->dev;
 266         struct device *conf_dev;
 267         struct idxd_group *group;
 268         int i, rc;
 269
 270         idxd->groups = kcalloc_node(idxd->max_groups, sizeof(struct idxd_group *),
 271                                     GFP_KERNEL, dev_to_node(dev));
 272         if (!idxd->groups)
 273                 return -ENOMEM;
 274
 275         for (i = 0; i < idxd->max_groups; i++) {
 276                 group = kzalloc_node(sizeof(*group), GFP_KERNEL, dev_to_node(dev));
 277                 if (!group) {
 278                         rc = -ENOMEM;
 279                         goto err;
 280                 }
 281
 282                 idxd_dev_set_type(&group->idxd_dev, IDXD_DEV_GROUP);
 283                 conf_dev = group_confdev(group);
 284                 group->id = i;
 285                 group->idxd = idxd;
 286                 device_initialize(conf_dev);
 287                 conf_dev->parent = idxd_confdev(idxd);
 288                 conf_dev->bus = &dsa_bus_type;
 289                 conf_dev->type = &idxd_group_device_type;
 290                 rc = dev_set_name(conf_dev, "group%d.%d", idxd->id, group->id);
 291                 if (rc < 0) {
 292                         put_device(conf_dev);
 293                         goto err;
 294                 }
 295
 296                 idxd->groups[i] = group;
 297                 if (idxd->hw.version <= DEVICE_VERSION_2 && !tc_override) {
 298                         group->tc_a = 1;
 299                         group->tc_b = 1;
 300                 } else {
 301                         group->tc_a = -1;
 302                         group->tc_b = -1;
 303                 }
 304                 /*
 305                  * The default value is the same as the value of
 306                  * total read buffers in GRPCAP.
 307                  */
 308                 group->rdbufs_allowed = idxd->max_rdbufs;
 309         }
 310
 311         return 0;
 312
 313  err:
 314         while (--i >= 0) {
 315                 group = idxd->groups[i];
 316                 put_device(group_confdev(group));
 317         }
 318         return rc;
 319 }
 320
 321 static void idxd_cleanup_internals(struct idxd_device *idxd)
 322 {
 323         int i;
 324
 325         for (i = 0; i < idxd->max_groups; i++)
 326                 put_device(group_confdev(idxd->groups[i]));
 327         for (i = 0; i < idxd->max_engines; i++)
 328                 put_device(engine_confdev(idxd->engines[i]));
 329         for (i = 0; i < idxd->max_wqs; i++)
 330                 put_device(wq_confdev(idxd->wqs[i]));
 331         destroy_workqueue(idxd->wq);
 332 }
 333
 334 static int idxd_init_evl(struct idxd_device *idxd)
 335 {
 336         struct device *dev = &idxd->pdev->dev;
 337         struct idxd_evl *evl;
 338
 339         if (idxd->hw.gen_cap.evl_support == 0)
 340                 return 0;
 341
 342         evl = kzalloc_node(sizeof(*evl), GFP_KERNEL, dev_to_node(dev));
 343         if (!evl)
 344                 return -ENOMEM;
 345
 346         spin_lock_init(&evl->lock);
 347         evl->size = IDXD_EVL_SIZE_MIN;
 348
 349         idxd->evl_cache = kmem_cache_create(dev_name(idxd_confdev(idxd)),
 350                                             sizeof(struct idxd_evl_fault) + evl_ent_size(idxd),
 351                                             0, 0, NULL);
 352         if (!idxd->evl_cache) {
 353                 kfree(evl);
 354                 return -ENOMEM;
 355         }
 356
 357         idxd->evl = evl;
 358         return 0;
 359 }
 360
 361 static int idxd_setup_internals(struct idxd_device *idxd)
 362 {
 363         struct device *dev = &idxd->pdev->dev;
 364         int rc, i;
 365
 366         init_waitqueue_head(&idxd->cmd_waitq);
 367
 368         rc = idxd_setup_wqs(idxd);
 369         if (rc < 0)
 370                 goto err_wqs;
 371
 372         rc = idxd_setup_engines(idxd);
 373         if (rc < 0)
 374                 goto err_engine;
 375
 376         rc = idxd_setup_groups(idxd);
 377         if (rc < 0)
 378                 goto err_group;
 379
 380         idxd->wq = create_workqueue(dev_name(dev));
 381         if (!idxd->wq) {
 382                 rc = -ENOMEM;
 383                 goto err_wkq_create;
 384         }
 385
 386         rc = idxd_init_evl(idxd);
 387         if (rc < 0)
 388                 goto err_evl;
 389
 390         return 0;
 391
 392  err_evl:
 393         destroy_workqueue(idxd->wq);
 394  err_wkq_create:
 395         for (i = 0; i < idxd->max_groups; i++)
 396                 put_device(group_confdev(idxd->groups[i]));
 397  err_group:
 398         for (i = 0; i < idxd->max_engines; i++)
 399                 put_device(engine_confdev(idxd->engines[i]));
 400  err_engine:
 401         for (i = 0; i < idxd->max_wqs; i++)
 402                 put_device(wq_confdev(idxd->wqs[i]));
 403  err_wqs:
 404         return rc;
 405 }
 406
 407 static void idxd_read_table_offsets(struct idxd_device *idxd)
 408 {
 409         union offsets_reg offsets;
 410         struct device *dev = &idxd->pdev->dev;
 411
 412         offsets.bits[0] = ioread64(idxd->reg_base + IDXD_TABLE_OFFSET);
 413         offsets.bits[1] = ioread64(idxd->reg_base + IDXD_TABLE_OFFSET + sizeof(u64));
 414         idxd->grpcfg_offset = offsets.grpcfg * IDXD_TABLE_MULT;
 415         dev_dbg(dev, "IDXD Group Config Offset: %#x\n", idxd->grpcfg_offset);
 416         idxd->wqcfg_offset = offsets.wqcfg * IDXD_TABLE_MULT;
 417         dev_dbg(dev, "IDXD Work Queue Config Offset: %#x\n", idxd->wqcfg_offset);
 418         idxd->msix_perm_offset = offsets.msix_perm * IDXD_TABLE_MULT;
 419         dev_dbg(dev, "IDXD MSIX Permission Offset: %#x\n", idxd->msix_perm_offset);
 420         idxd->perfmon_offset = offsets.perfmon * IDXD_TABLE_MULT;
 421         dev_dbg(dev, "IDXD Perfmon Offset: %#x\n", idxd->perfmon_offset);
 422 }
 423
 424 void multi_u64_to_bmap(unsigned long *bmap, u64 *val, int count)
 425 {
 426         int i, j, nr;
 427
 428         for (i = 0, nr = 0; i < count; i++) {
 429                 for (j = 0; j < BITS_PER_LONG_LONG; j++) {
 430                         if (val[i] & BIT(j))
 431                                 set_bit(nr, bmap);
 432                         nr++;
 433                 }
 434         }
 435 }
 436
 437 static void idxd_read_caps(struct idxd_device *idxd)
 438 {
 439         struct device *dev = &idxd->pdev->dev;
 440         int i;
 441
 442         /* reading generic capabilities */
 443         idxd->hw.gen_cap.bits = ioread64(idxd->reg_base + IDXD_GENCAP_OFFSET);
 444         dev_dbg(dev, "gen_cap: %#llx\n", idxd->hw.gen_cap.bits);
 445
 446         if (idxd->hw.gen_cap.cmd_cap) {
 447                 idxd->hw.cmd_cap = ioread32(idxd->reg_base + IDXD_CMDCAP_OFFSET);
 448                 dev_dbg(dev, "cmd_cap: %#x\n", idxd->hw.cmd_cap);
 449         }
 450
 451         /* reading command capabilities */
 452         if (idxd->hw.cmd_cap & BIT(IDXD_CMD_REQUEST_INT_HANDLE))
 453                 idxd->request_int_handles = true;
 454
 455         idxd->max_xfer_bytes = 1ULL << idxd->hw.gen_cap.max_xfer_shift;
 456         dev_dbg(dev, "max xfer size: %llu bytes\n", idxd->max_xfer_bytes);
 457         idxd_set_max_batch_size(idxd->data->type, idxd, 1U << idxd->hw.gen_cap.max_batch_shift);
 458         dev_dbg(dev, "max batch size: %u\n", idxd->max_batch_size);
 459         if (idxd->hw.gen_cap.config_en)
 460                 set_bit(IDXD_FLAG_CONFIGURABLE, &idxd->flags);
 461
 462         /* reading group capabilities */
 463         idxd->hw.group_cap.bits =
 464                 ioread64(idxd->reg_base + IDXD_GRPCAP_OFFSET);
 465         dev_dbg(dev, "group_cap: %#llx\n", idxd->hw.group_cap.bits);
 466         idxd->max_groups = idxd->hw.group_cap.num_groups;
 467         dev_dbg(dev, "max groups: %u\n", idxd->max_groups);
 468         idxd->max_rdbufs = idxd->hw.group_cap.total_rdbufs;
 469         dev_dbg(dev, "max read buffers: %u\n", idxd->max_rdbufs);
 470         idxd->nr_rdbufs = idxd->max_rdbufs;
 471
 472         /* read engine capabilities */
 473         idxd->hw.engine_cap.bits =
 474                 ioread64(idxd->reg_base + IDXD_ENGCAP_OFFSET);
 475         dev_dbg(dev, "engine_cap: %#llx\n", idxd->hw.engine_cap.bits);
 476         idxd->max_engines = idxd->hw.engine_cap.num_engines;
 477         dev_dbg(dev, "max engines: %u\n", idxd->max_engines);
 478
 479         /* read workqueue capabilities */
 480         idxd->hw.wq_cap.bits = ioread64(idxd->reg_base + IDXD_WQCAP_OFFSET);
 481         dev_dbg(dev, "wq_cap: %#llx\n", idxd->hw.wq_cap.bits);
 482         idxd->max_wq_size = idxd->hw.wq_cap.total_wq_size;
 483         dev_dbg(dev, "total workqueue size: %u\n", idxd->max_wq_size);
 484         idxd->max_wqs = idxd->hw.wq_cap.num_wqs;
 485         dev_dbg(dev, "max workqueues: %u\n", idxd->max_wqs);
 486         idxd->wqcfg_size = 1 << (idxd->hw.wq_cap.wqcfg_size + IDXD_WQCFG_MIN);
 487         dev_dbg(dev, "wqcfg size: %u\n", idxd->wqcfg_size);
 488
 489         /* reading operation capabilities */
 490         for (i = 0; i < 4; i++) {
 491                 idxd->hw.opcap.bits[i] = ioread64(idxd->reg_base +
 492                                 IDXD_OPCAP_OFFSET + i * sizeof(u64));
 493                 dev_dbg(dev, "opcap[%d]: %#llx\n", i, idxd->hw.opcap.bits[i]);
 494         }
 495         multi_u64_to_bmap(idxd->opcap_bmap, &idxd->hw.opcap.bits[0], 4);
 496
 497         /* read iaa cap */
 498         if (idxd->data->type == IDXD_TYPE_IAX && idxd->hw.version >= DEVICE_VERSION_2)
 499                 idxd->hw.iaa_cap.bits = ioread64(idxd->reg_base + IDXD_IAACAP_OFFSET);
 500 }
 501
 502 static struct idxd_device *idxd_alloc(struct pci_dev *pdev, struct idxd_driver_data *data)
 503 {
 504         struct device *dev = &pdev->dev;
 505         struct device *conf_dev;
 506         struct idxd_device *idxd;
 507         int rc;
 508
 509         idxd = kzalloc_node(sizeof(*idxd), GFP_KERNEL, dev_to_node(dev));
 510         if (!idxd)
 511                 return NULL;
 512
 513         conf_dev = idxd_confdev(idxd);
 514         idxd->pdev = pdev;
 515         idxd->data = data;
 516         idxd_dev_set_type(&idxd->idxd_dev, idxd->data->type);
 517         idxd->id = ida_alloc(&idxd_ida, GFP_KERNEL);
 518         if (idxd->id < 0)
 519                 return NULL;
 520
 521         idxd->opcap_bmap = bitmap_zalloc_node(IDXD_MAX_OPCAP_BITS, GFP_KERNEL, dev_to_node(dev));
 522         if (!idxd->opcap_bmap) {
 523                 ida_free(&idxd_ida, idxd->id);
 524                 return NULL;
 525         }
 526
 527         device_initialize(conf_dev);
 528         conf_dev->parent = dev;
 529         conf_dev->bus = &dsa_bus_type;
 530         conf_dev->type = idxd->data->dev_type;
 531         rc = dev_set_name(conf_dev, "%s%d", idxd->data->name_prefix, idxd->id);
 532         if (rc < 0) {
 533                 put_device(conf_dev);
 534                 return NULL;
 535         }
 536
 537         spin_lock_init(&idxd->dev_lock);
 538         spin_lock_init(&idxd->cmd_lock);
 539
 540         return idxd;
 541 }
 542
 543 static int idxd_enable_system_pasid(struct idxd_device *idxd)
 544 {
 545         return -EOPNOTSUPP;
 546 }
 547
 548 static void idxd_disable_system_pasid(struct idxd_device *idxd)
 549 {
 550
 551         iommu_sva_unbind_device(idxd->sva);
 552         idxd->sva = NULL;
 553 }
 554
 555 static int idxd_probe(struct idxd_device *idxd)
 556 {
 557         struct pci_dev *pdev = idxd->pdev;
 558         struct device *dev = &pdev->dev;
 559         int rc;
 560
 561         dev_dbg(dev, "%s entered and resetting device\n", __func__);
 562         rc = idxd_device_init_reset(idxd);
 563         if (rc < 0)
 564                 return rc;
 565
 566         dev_dbg(dev, "IDXD reset complete\n");
 567
 568         if (IS_ENABLED(CONFIG_INTEL_IDXD_SVM) && sva) {
 569                 if (iommu_dev_enable_feature(dev, IOMMU_DEV_FEAT_SVA)) {
 570                         dev_warn(dev, "Unable to turn on user SVA feature.\n");
 571                 } else {
 572                         set_bit(IDXD_FLAG_USER_PASID_ENABLED, &idxd->flags);
 573
 574                         if (idxd_enable_system_pasid(idxd))
 575                                 dev_warn(dev, "No in-kernel DMA with PASID.\n");
 576                         else
 577                                 set_bit(IDXD_FLAG_PASID_ENABLED, &idxd->flags);
 578                 }
 579         } else if (!sva) {
 580                 dev_warn(dev, "User forced SVA off via module param.\n");
 581         }
 582
 583         idxd_read_caps(idxd);
 584         idxd_read_table_offsets(idxd);
 585
 586         rc = idxd_setup_internals(idxd);
 587         if (rc)
 588                 goto err;
 589
 590         /* If the configs are readonly, then load them from device */
 591         if (!test_bit(IDXD_FLAG_CONFIGURABLE, &idxd->flags)) {
 592                 dev_dbg(dev, "Loading RO device config\n");
 593                 rc = idxd_device_load_config(idxd);
 594                 if (rc < 0)
 595                         goto err_config;
 596         }
 597
 598         rc = idxd_setup_interrupts(idxd);
 599         if (rc)
 600                 goto err_config;
 601
 602         idxd->major = idxd_cdev_get_major(idxd);
 603
 604         rc = perfmon_pmu_init(idxd);
 605         if (rc < 0)
 606                 dev_warn(dev, "Failed to initialize perfmon. No PMU support: %d\n", rc);
 607
 608         dev_dbg(dev, "IDXD device %d probed successfully\n", idxd->id);
 609         return 0;
 610
 611  err_config:
 612         idxd_cleanup_internals(idxd);
 613  err:
 614         if (device_pasid_enabled(idxd))
 615                 idxd_disable_system_pasid(idxd);
 616         if (device_user_pasid_enabled(idxd))
 617                 iommu_dev_disable_feature(dev, IOMMU_DEV_FEAT_SVA);
 618         return rc;
 619 }
 620
 621 static void idxd_cleanup(struct idxd_device *idxd)
 622 {
 623         struct device *dev = &idxd->pdev->dev;
 624
 625         perfmon_pmu_remove(idxd);
 626         idxd_cleanup_interrupts(idxd);
 627         idxd_cleanup_internals(idxd);
 628         if (device_pasid_enabled(idxd))
 629                 idxd_disable_system_pasid(idxd);
 630         if (device_user_pasid_enabled(idxd))
 631                 iommu_dev_disable_feature(dev, IOMMU_DEV_FEAT_SVA);
 632 }
 633
 634 static int idxd_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
 635 {
 636         struct device *dev = &pdev->dev;
 637         struct idxd_device *idxd;
 638         struct idxd_driver_data *data = (struct idxd_driver_data *)id->driver_data;
 639         int rc;
 640
 641         rc = pci_enable_device(pdev);
 642         if (rc)
 643                 return rc;
 644
 645         dev_dbg(dev, "Alloc IDXD context\n");
 646         idxd = idxd_alloc(pdev, data);
 647         if (!idxd) {
 648                 rc = -ENOMEM;
 649                 goto err_idxd_alloc;
 650         }
 651
 652         dev_dbg(dev, "Mapping BARs\n");
 653         idxd->reg_base = pci_iomap(pdev, IDXD_MMIO_BAR, 0);
 654         if (!idxd->reg_base) {
 655                 rc = -ENOMEM;
 656                 goto err_iomap;
 657         }
 658
 659         dev_dbg(dev, "Set DMA masks\n");
 660         rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
 661         if (rc)
 662                 goto err;
 663
 664         dev_dbg(dev, "Set PCI master\n");
 665         pci_set_master(pdev);
 666         pci_set_drvdata(pdev, idxd);
 667
 668         idxd->hw.version = ioread32(idxd->reg_base + IDXD_VER_OFFSET);
 669         rc = idxd_probe(idxd);
 670         if (rc) {
 671                 dev_err(dev, "Intel(R) IDXD DMA Engine init failed\n");
 672                 goto err;
 673         }
 674
 675         rc = idxd_register_devices(idxd);
 676         if (rc) {
 677                 dev_err(dev, "IDXD sysfs setup failed\n");
 678                 goto err_dev_register;
 679         }
 680
 681         rc = idxd_device_init_debugfs(idxd);
 682         if (rc)
 683                 dev_warn(dev, "IDXD debugfs failed to setup\n");
 684
 685         dev_info(&pdev->dev, "Intel(R) Accelerator Device (v%x)\n",
 686                  idxd->hw.version);
 687
 688         return 0;
 689
 690  err_dev_register:
 691         idxd_cleanup(idxd);
 692  err:
 693         pci_iounmap(pdev, idxd->reg_base);
 694  err_iomap:
 695         put_device(idxd_confdev(idxd));
 696  err_idxd_alloc:
 697         pci_disable_device(pdev);
 698         return rc;
 699 }
 700
 701 void idxd_wqs_quiesce(struct idxd_device *idxd)
 702 {
 703         struct idxd_wq *wq;
 704         int i;
 705
 706         for (i = 0; i < idxd->max_wqs; i++) {
 707                 wq = idxd->wqs[i];
 708                 if (wq->state == IDXD_WQ_ENABLED && wq->type == IDXD_WQT_KERNEL)
 709                         idxd_wq_quiesce(wq);
 710         }
 711 }
 712
 713 static void idxd_shutdown(struct pci_dev *pdev)
 714 {
 715         struct idxd_device *idxd = pci_get_drvdata(pdev);
 716         struct idxd_irq_entry *irq_entry;
 717         int rc;
 718
 719         rc = idxd_device_disable(idxd);
 720         if (rc)
 721                 dev_err(&pdev->dev, "Disabling device failed\n");
 722
 723         irq_entry = &idxd->ie;
 724         synchronize_irq(irq_entry->vector);
 725         idxd_mask_error_interrupts(idxd);
 726         flush_workqueue(idxd->wq);
 727 }
 728
 729 static void idxd_remove(struct pci_dev *pdev)
 730 {
 731         struct idxd_device *idxd = pci_get_drvdata(pdev);
 732         struct idxd_irq_entry *irq_entry;
 733
 734         idxd_unregister_devices(idxd);
 735         /*
 736          * When ->release() is called for the idxd->conf_dev, it frees all the memory related
 737          * to the idxd context. The driver still needs those bits in order to do the rest of
 738          * the cleanup. However, we do need to unbound the idxd sub-driver. So take a ref
 739          * on the device here to hold off the freeing while allowing the idxd sub-driver
 740          * to unbind.
 741          */
 742         get_device(idxd_confdev(idxd));
 743         device_unregister(idxd_confdev(idxd));
 744         idxd_shutdown(pdev);
 745         if (device_pasid_enabled(idxd))
 746                 idxd_disable_system_pasid(idxd);
 747         idxd_device_remove_debugfs(idxd);
 748
 749         irq_entry = idxd_get_ie(idxd, 0);
 750         free_irq(irq_entry->vector, irq_entry);
 751         pci_free_irq_vectors(pdev);
 752         pci_iounmap(pdev, idxd->reg_base);
 753         if (device_user_pasid_enabled(idxd))
 754                 iommu_dev_disable_feature(&pdev->dev, IOMMU_DEV_FEAT_SVA);
 755         pci_disable_device(pdev);
 756         destroy_workqueue(idxd->wq);
 757         perfmon_pmu_remove(idxd);
 758         put_device(idxd_confdev(idxd));
 759 }
 760
 761 static struct pci_driver idxd_pci_driver = {
 762         .name           = DRV_NAME,
 763         .id_table       = idxd_pci_tbl,
 764         .probe          = idxd_pci_probe,
 765         .remove         = idxd_remove,
 766         .shutdown       = idxd_shutdown,
 767 };
 768
 769 static int __init idxd_init_module(void)
 770 {
 771         int err;
 772
 773         /*
 774          * If the CPU does not support MOVDIR64B or ENQCMDS, there's no point in
 775          * enumerating the device. We can not utilize it.
 776          */
 777         if (!cpu_feature_enabled(X86_FEATURE_MOVDIR64B)) {
 778                 pr_warn("idxd driver failed to load without MOVDIR64B.\n");
 779                 return -ENODEV;
 780         }
 781
 782         if (!cpu_feature_enabled(X86_FEATURE_ENQCMD))
 783                 pr_warn("Platform does not have ENQCMD(S) support.\n");
 784         else
 785                 support_enqcmd = true;
 786
 787         perfmon_init();
 788
 789         err = idxd_driver_register(&idxd_drv);
 790         if (err < 0)
 791                 goto err_idxd_driver_register;
 792
 793         err = idxd_driver_register(&idxd_dmaengine_drv);
 794         if (err < 0)
 795                 goto err_idxd_dmaengine_driver_register;
 796
 797         err = idxd_driver_register(&idxd_user_drv);
 798         if (err < 0)
 799                 goto err_idxd_user_driver_register;
 800
 801         err = idxd_cdev_register();
 802         if (err)
 803                 goto err_cdev_register;
 804
 805         err = idxd_init_debugfs();
 806         if (err)
 807                 goto err_debugfs;
 808
 809         err = pci_register_driver(&idxd_pci_driver);
 810         if (err)
 811                 goto err_pci_register;
 812
 813         return 0;
 814
 815 err_pci_register:
 816         idxd_remove_debugfs();
 817 err_debugfs:
 818         idxd_cdev_remove();
 819 err_cdev_register:
 820         idxd_driver_unregister(&idxd_user_drv);
 821 err_idxd_user_driver_register:
 822         idxd_driver_unregister(&idxd_dmaengine_drv);
 823 err_idxd_dmaengine_driver_register:
 824         idxd_driver_unregister(&idxd_drv);
 825 err_idxd_driver_register:
 826         return err;
 827 }
 828 module_init(idxd_init_module);
 829
 830 static void __exit idxd_exit_module(void)
 831 {
 832         idxd_driver_unregister(&idxd_user_drv);
 833         idxd_driver_unregister(&idxd_dmaengine_drv);
 834         idxd_driver_unregister(&idxd_drv);
 835         pci_unregister_driver(&idxd_pci_driver);
 836         idxd_cdev_remove();
 837         perfmon_exit();
 838         idxd_remove_debugfs();
 839 }
 840 module_exit(idxd_exit_module);