1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2013-2014 Freescale Semiconductor, Inc.
4 * Copyright 2018 Angelo Dureghello <angelo@sysam.it>
6 #ifndef _FSL_EDMA_COMMON_H_
7 #define _FSL_EDMA_COMMON_H_
9 #include <linux/dma-direction.h>
10 #include <linux/platform_device.h>
13 #define EDMA_CR_EDBG BIT(1)
14 #define EDMA_CR_ERCA BIT(2)
15 #define EDMA_CR_ERGA BIT(3)
16 #define EDMA_CR_HOE BIT(4)
17 #define EDMA_CR_HALT BIT(5)
18 #define EDMA_CR_CLM BIT(6)
19 #define EDMA_CR_EMLM BIT(7)
20 #define EDMA_CR_ECX BIT(16)
21 #define EDMA_CR_CX BIT(17)
23 #define EDMA_SEEI_SEEI(x) ((x) & GENMASK(4, 0))
24 #define EDMA_CEEI_CEEI(x) ((x) & GENMASK(4, 0))
25 #define EDMA_CINT_CINT(x) ((x) & GENMASK(4, 0))
26 #define EDMA_CERR_CERR(x) ((x) & GENMASK(4, 0))
28 #define EDMA_TCD_ATTR_DSIZE(x) (((x) & GENMASK(2, 0)))
29 #define EDMA_TCD_ATTR_DMOD(x) (((x) & GENMASK(4, 0)) << 3)
30 #define EDMA_TCD_ATTR_SSIZE(x) (((x) & GENMASK(2, 0)) << 8)
31 #define EDMA_TCD_ATTR_SMOD(x) (((x) & GENMASK(4, 0)) << 11)
33 #define EDMA_TCD_CITER_CITER(x) ((x) & GENMASK(14, 0))
34 #define EDMA_TCD_BITER_BITER(x) ((x) & GENMASK(14, 0))
36 #define EDMA_TCD_CSR_START BIT(0)
37 #define EDMA_TCD_CSR_INT_MAJOR BIT(1)
38 #define EDMA_TCD_CSR_INT_HALF BIT(2)
39 #define EDMA_TCD_CSR_D_REQ BIT(3)
40 #define EDMA_TCD_CSR_E_SG BIT(4)
41 #define EDMA_TCD_CSR_E_LINK BIT(5)
42 #define EDMA_TCD_CSR_ACTIVE BIT(6)
43 #define EDMA_TCD_CSR_DONE BIT(7)
45 #define EDMA_V3_TCD_NBYTES_MLOFF_NBYTES(x) ((x) & GENMASK(9, 0))
46 #define EDMA_V3_TCD_NBYTES_MLOFF(x) (x << 10)
47 #define EDMA_V3_TCD_NBYTES_DMLOE (1 << 30)
48 #define EDMA_V3_TCD_NBYTES_SMLOE (1 << 31)
50 #define EDMAMUX_CHCFG_DIS 0x0
51 #define EDMAMUX_CHCFG_ENBL 0x80
52 #define EDMAMUX_CHCFG_SOURCE(n) ((n) & 0x3F)
56 #define EDMA_TCD 0x1000
58 #define FSL_EDMA_BUSWIDTHS (BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \
59 BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \
60 BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) | \
61 BIT(DMA_SLAVE_BUSWIDTH_8_BYTES))
63 #define EDMA_V3_CH_SBR_RD BIT(22)
64 #define EDMA_V3_CH_SBR_WR BIT(21)
65 #define EDMA_V3_CH_CSR_ERQ BIT(0)
66 #define EDMA_V3_CH_CSR_EARQ BIT(1)
67 #define EDMA_V3_CH_CSR_EEI BIT(2)
68 #define EDMA_V3_CH_CSR_DONE BIT(30)
69 #define EDMA_V3_CH_CSR_ACTIVE BIT(31)
71 enum fsl_edma_pm_state {
76 struct fsl_edma_hw_tcd {
90 struct fsl_edma3_ch_reg {
97 __le32 ch_mattr; /* edma4, reserved for edma3 */
99 struct fsl_edma_hw_tcd tcd;
103 * These are iomem pointers, for both v32 and v64.
109 void __iomem *erql; /* aka erq on v32 */
111 void __iomem *eeil; /* aka eei on v32 */
126 struct fsl_edma_sw_tcd {
128 struct fsl_edma_hw_tcd *vtcd;
131 struct fsl_edma_chan {
132 struct virt_dma_chan vchan;
133 enum dma_status status;
134 enum fsl_edma_pm_state pm_state;
137 struct fsl_edma_engine *edma;
138 struct fsl_edma_desc *edesc;
139 struct dma_slave_config cfg;
142 struct dma_pool *tcd_pool;
143 dma_addr_t dma_dev_addr;
145 enum dma_data_direction dma_dir;
147 struct fsl_edma_hw_tcd __iomem *tcd;
149 struct work_struct issue_worker;
150 struct platform_device *pdev;
151 struct device *pd_dev;
162 struct fsl_edma_desc {
163 struct virt_dma_desc vdesc;
164 struct fsl_edma_chan *echan;
166 enum dma_transfer_direction dirn;
168 struct fsl_edma_sw_tcd tcd[];
171 #define FSL_EDMA_DRV_HAS_DMACLK BIT(0)
172 #define FSL_EDMA_DRV_MUX_SWAP BIT(1)
173 #define FSL_EDMA_DRV_CONFIG32 BIT(2)
174 #define FSL_EDMA_DRV_WRAP_IO BIT(3)
175 #define FSL_EDMA_DRV_EDMA64 BIT(4)
176 #define FSL_EDMA_DRV_HAS_PD BIT(5)
177 #define FSL_EDMA_DRV_HAS_CHCLK BIT(6)
178 #define FSL_EDMA_DRV_HAS_CHMUX BIT(7)
179 /* imx8 QM audio edma remote local swapped */
180 #define FSL_EDMA_DRV_QUIRK_SWAPPED BIT(8)
181 /* control and status register is in tcd address space, edma3 reg layout */
182 #define FSL_EDMA_DRV_SPLIT_REG BIT(9)
183 #define FSL_EDMA_DRV_BUS_8BYTE BIT(10)
184 #define FSL_EDMA_DRV_DEV_TO_DEV BIT(11)
185 #define FSL_EDMA_DRV_ALIGN_64BYTE BIT(12)
187 #define FSL_EDMA_DRV_EDMA3 (FSL_EDMA_DRV_SPLIT_REG | \
188 FSL_EDMA_DRV_BUS_8BYTE | \
189 FSL_EDMA_DRV_DEV_TO_DEV | \
190 FSL_EDMA_DRV_ALIGN_64BYTE)
192 struct fsl_edma_drvdata {
193 u32 dmamuxs; /* only used before v3 */
197 int (*setup_irq)(struct platform_device *pdev,
198 struct fsl_edma_engine *fsl_edma);
201 struct fsl_edma_engine {
202 struct dma_device dma_dev;
203 void __iomem *membase;
204 void __iomem *muxbase[DMAMUX_NR];
205 struct clk *muxclk[DMAMUX_NR];
208 struct mutex fsl_edma_mutex;
209 const struct fsl_edma_drvdata *drvdata;
214 struct edma_regs regs;
216 struct fsl_edma_chan chans[];
219 #define edma_read_tcdreg(chan, __name) \
220 (sizeof(chan->tcd->__name) == sizeof(u32) ? \
221 edma_readl(chan->edma, &chan->tcd->__name) : \
222 edma_readw(chan->edma, &chan->tcd->__name))
224 #define edma_write_tcdreg(chan, val, __name) \
225 (sizeof(chan->tcd->__name) == sizeof(u32) ? \
226 edma_writel(chan->edma, (u32 __force)val, &chan->tcd->__name) : \
227 edma_writew(chan->edma, (u16 __force)val, &chan->tcd->__name))
229 #define edma_readl_chreg(chan, __name) \
230 edma_readl(chan->edma, \
231 (void __iomem *)&(container_of(chan->tcd, struct fsl_edma3_ch_reg, tcd)->__name))
233 #define edma_writel_chreg(chan, val, __name) \
234 edma_writel(chan->edma, val, \
235 (void __iomem *)&(container_of(chan->tcd, struct fsl_edma3_ch_reg, tcd)->__name))
238 * R/W functions for big- or little-endian registers:
239 * The eDMA controller's endian is independent of the CPU core's endian.
240 * For the big-endian IP module, the offset for 8-bit or 16-bit registers
241 * should also be swapped opposite to that in little-endian IP.
243 static inline u32 edma_readl(struct fsl_edma_engine *edma, void __iomem *addr)
245 if (edma->big_endian)
246 return ioread32be(addr);
248 return ioread32(addr);
251 static inline u16 edma_readw(struct fsl_edma_engine *edma, void __iomem *addr)
253 if (edma->big_endian)
254 return ioread16be(addr);
256 return ioread16(addr);
259 static inline void edma_writeb(struct fsl_edma_engine *edma,
260 u8 val, void __iomem *addr)
262 /* swap the reg offset for these in big-endian mode */
263 if (edma->big_endian)
264 iowrite8(val, (void __iomem *)((unsigned long)addr ^ 0x3));
269 static inline void edma_writew(struct fsl_edma_engine *edma,
270 u16 val, void __iomem *addr)
272 /* swap the reg offset for these in big-endian mode */
273 if (edma->big_endian)
274 iowrite16be(val, (void __iomem *)((unsigned long)addr ^ 0x2));
276 iowrite16(val, addr);
279 static inline void edma_writel(struct fsl_edma_engine *edma,
280 u32 val, void __iomem *addr)
282 if (edma->big_endian)
283 iowrite32be(val, addr);
285 iowrite32(val, addr);
288 static inline struct fsl_edma_chan *to_fsl_edma_chan(struct dma_chan *chan)
290 return container_of(chan, struct fsl_edma_chan, vchan.chan);
293 static inline u32 fsl_edma_drvflags(struct fsl_edma_chan *fsl_chan)
295 return fsl_chan->edma->drvdata->flags;
298 static inline struct fsl_edma_desc *to_fsl_edma_desc(struct virt_dma_desc *vd)
300 return container_of(vd, struct fsl_edma_desc, vdesc);
303 static inline void fsl_edma_err_chan_handler(struct fsl_edma_chan *fsl_chan)
305 fsl_chan->status = DMA_ERROR;
306 fsl_chan->idle = true;
309 void fsl_edma_tx_chan_handler(struct fsl_edma_chan *fsl_chan);
310 void fsl_edma_disable_request(struct fsl_edma_chan *fsl_chan);
311 void fsl_edma_chan_mux(struct fsl_edma_chan *fsl_chan,
312 unsigned int slot, bool enable);
313 void fsl_edma_free_desc(struct virt_dma_desc *vdesc);
314 int fsl_edma_terminate_all(struct dma_chan *chan);
315 int fsl_edma_pause(struct dma_chan *chan);
316 int fsl_edma_resume(struct dma_chan *chan);
317 int fsl_edma_slave_config(struct dma_chan *chan,
318 struct dma_slave_config *cfg);
319 enum dma_status fsl_edma_tx_status(struct dma_chan *chan,
320 dma_cookie_t cookie, struct dma_tx_state *txstate);
321 struct dma_async_tx_descriptor *fsl_edma_prep_dma_cyclic(
322 struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len,
323 size_t period_len, enum dma_transfer_direction direction,
324 unsigned long flags);
325 struct dma_async_tx_descriptor *fsl_edma_prep_slave_sg(
326 struct dma_chan *chan, struct scatterlist *sgl,
327 unsigned int sg_len, enum dma_transfer_direction direction,
328 unsigned long flags, void *context);
329 struct dma_async_tx_descriptor *fsl_edma_prep_memcpy(
330 struct dma_chan *chan, dma_addr_t dma_dst, dma_addr_t dma_src,
331 size_t len, unsigned long flags);
332 void fsl_edma_xfer_desc(struct fsl_edma_chan *fsl_chan);
333 void fsl_edma_issue_pending(struct dma_chan *chan);
334 int fsl_edma_alloc_chan_resources(struct dma_chan *chan);
335 void fsl_edma_free_chan_resources(struct dma_chan *chan);
336 void fsl_edma_cleanup_vchan(struct dma_device *dmadev);
337 void fsl_edma_setup_regs(struct fsl_edma_engine *edma);
339 #endif /* _FSL_EDMA_COMMON_H_ */