2 * Core driver for the Synopsys DesignWare DMA Controller
4 * Copyright (C) 2007-2008 Atmel Corporation
5 * Copyright (C) 2010-2011 ST Microelectronics
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
12 #include <linux/bitops.h>
13 #include <linux/clk.h>
14 #include <linux/delay.h>
15 #include <linux/dmaengine.h>
16 #include <linux/dma-mapping.h>
17 #include <linux/dmapool.h>
18 #include <linux/init.h>
19 #include <linux/interrupt.h>
23 #include <linux/module.h>
24 #include <linux/platform_device.h>
25 #include <linux/slab.h>
27 #include "dw_dmac_regs.h"
28 #include "dmaengine.h"
31 * This supports the Synopsys "DesignWare AHB Central DMA Controller",
32 * (DW_ahb_dmac) which is used with various AMBA 2.0 systems (not all
33 * of which use ARM any more). See the "Databook" from Synopsys for
34 * information beyond what licensees probably provide.
36 * The driver has currently been tested only with the Atmel AT32AP7000,
37 * which does not support descriptor writeback.
40 static inline unsigned int dwc_get_dms(struct dw_dma_slave *slave)
42 return slave ? slave->dst_master : 0;
45 static inline unsigned int dwc_get_sms(struct dw_dma_slave *slave)
47 return slave ? slave->src_master : 1;
53 static inline unsigned int dwc_get_master(struct dma_chan *chan, int master)
55 struct dw_dma *dw = to_dw_dma(chan->device);
56 struct dw_dma_slave *dws = chan->private;
59 if (master == SRC_MASTER)
64 return min_t(unsigned int, dw->nr_masters - 1, m);
67 #define DWC_DEFAULT_CTLLO(_chan) ({ \
68 struct dw_dma_chan *_dwc = to_dw_dma_chan(_chan); \
69 struct dma_slave_config *_sconfig = &_dwc->dma_sconfig; \
70 bool _is_slave = is_slave_direction(_dwc->direction); \
71 int _dms = dwc_get_master(_chan, DST_MASTER); \
72 int _sms = dwc_get_master(_chan, SRC_MASTER); \
73 u8 _smsize = _is_slave ? _sconfig->src_maxburst : \
75 u8 _dmsize = _is_slave ? _sconfig->dst_maxburst : \
78 (DWC_CTLL_DST_MSIZE(_dmsize) \
79 | DWC_CTLL_SRC_MSIZE(_smsize) \
82 | DWC_CTLL_DMS(_dms) \
83 | DWC_CTLL_SMS(_sms)); \
87 * Number of descriptors to allocate for each channel. This should be
88 * made configurable somehow; preferably, the clients (at least the
89 * ones using slave transfers) should be able to give us a hint.
91 #define NR_DESCS_PER_CHANNEL 64
93 static inline unsigned int dwc_get_data_width(struct dma_chan *chan, int master)
95 struct dw_dma *dw = to_dw_dma(chan->device);
97 return dw->data_width[dwc_get_master(chan, master)];
100 /*----------------------------------------------------------------------*/
102 static struct device *chan2dev(struct dma_chan *chan)
104 return &chan->dev->device;
106 static struct device *chan2parent(struct dma_chan *chan)
108 return chan->dev->device.parent;
111 static struct dw_desc *dwc_first_active(struct dw_dma_chan *dwc)
113 return to_dw_desc(dwc->active_list.next);
116 static struct dw_desc *dwc_desc_get(struct dw_dma_chan *dwc)
118 struct dw_desc *desc, *_desc;
119 struct dw_desc *ret = NULL;
123 spin_lock_irqsave(&dwc->lock, flags);
124 list_for_each_entry_safe(desc, _desc, &dwc->free_list, desc_node) {
126 if (async_tx_test_ack(&desc->txd)) {
127 list_del(&desc->desc_node);
131 dev_dbg(chan2dev(&dwc->chan), "desc %p not ACKed\n", desc);
133 spin_unlock_irqrestore(&dwc->lock, flags);
135 dev_vdbg(chan2dev(&dwc->chan), "scanned %u descriptors on freelist\n", i);
141 * Move a descriptor, including any children, to the free list.
142 * `desc' must not be on any lists.
144 static void dwc_desc_put(struct dw_dma_chan *dwc, struct dw_desc *desc)
149 struct dw_desc *child;
151 spin_lock_irqsave(&dwc->lock, flags);
152 list_for_each_entry(child, &desc->tx_list, desc_node)
153 dev_vdbg(chan2dev(&dwc->chan),
154 "moving child desc %p to freelist\n",
156 list_splice_init(&desc->tx_list, &dwc->free_list);
157 dev_vdbg(chan2dev(&dwc->chan), "moving desc %p to freelist\n", desc);
158 list_add(&desc->desc_node, &dwc->free_list);
159 spin_unlock_irqrestore(&dwc->lock, flags);
163 static void dwc_initialize(struct dw_dma_chan *dwc)
165 struct dw_dma *dw = to_dw_dma(dwc->chan.device);
166 struct dw_dma_slave *dws = dwc->chan.private;
167 u32 cfghi = DWC_CFGH_FIFO_MODE;
168 u32 cfglo = DWC_CFGL_CH_PRIOR(dwc->priority);
170 if (dwc->initialized == true)
175 * We need controller-specific data to set up slave
178 BUG_ON(!dws->dma_dev || dws->dma_dev != dw->dma.dev);
181 cfglo |= dws->cfg_lo & ~DWC_CFGL_CH_PRIOR_MASK;
183 if (dwc->direction == DMA_MEM_TO_DEV)
184 cfghi = DWC_CFGH_DST_PER(dwc->dma_sconfig.slave_id);
185 else if (dwc->direction == DMA_DEV_TO_MEM)
186 cfghi = DWC_CFGH_SRC_PER(dwc->dma_sconfig.slave_id);
189 channel_writel(dwc, CFG_LO, cfglo);
190 channel_writel(dwc, CFG_HI, cfghi);
192 /* Enable interrupts */
193 channel_set_bit(dw, MASK.XFER, dwc->mask);
194 channel_set_bit(dw, MASK.ERROR, dwc->mask);
196 dwc->initialized = true;
199 /*----------------------------------------------------------------------*/
201 static inline unsigned int dwc_fast_fls(unsigned long long v)
204 * We can be a lot more clever here, but this should take care
205 * of the most common optimization.
216 static inline void dwc_dump_chan_regs(struct dw_dma_chan *dwc)
218 dev_err(chan2dev(&dwc->chan),
219 " SAR: 0x%x DAR: 0x%x LLP: 0x%x CTL: 0x%x:%08x\n",
220 channel_readl(dwc, SAR),
221 channel_readl(dwc, DAR),
222 channel_readl(dwc, LLP),
223 channel_readl(dwc, CTL_HI),
224 channel_readl(dwc, CTL_LO));
227 static inline void dwc_chan_disable(struct dw_dma *dw, struct dw_dma_chan *dwc)
229 channel_clear_bit(dw, CH_EN, dwc->mask);
230 while (dma_readl(dw, CH_EN) & dwc->mask)
234 /*----------------------------------------------------------------------*/
236 /* Perform single block transfer */
237 static inline void dwc_do_single_block(struct dw_dma_chan *dwc,
238 struct dw_desc *desc)
240 struct dw_dma *dw = to_dw_dma(dwc->chan.device);
243 /* Software emulation of LLP mode relies on interrupts to continue
244 * multi block transfer. */
245 ctllo = desc->lli.ctllo | DWC_CTLL_INT_EN;
247 channel_writel(dwc, SAR, desc->lli.sar);
248 channel_writel(dwc, DAR, desc->lli.dar);
249 channel_writel(dwc, CTL_LO, ctllo);
250 channel_writel(dwc, CTL_HI, desc->lli.ctlhi);
251 channel_set_bit(dw, CH_EN, dwc->mask);
253 /* Move pointer to next descriptor */
254 dwc->tx_node_active = dwc->tx_node_active->next;
257 /* Called with dwc->lock held and bh disabled */
258 static void dwc_dostart(struct dw_dma_chan *dwc, struct dw_desc *first)
260 struct dw_dma *dw = to_dw_dma(dwc->chan.device);
261 unsigned long was_soft_llp;
263 /* ASSERT: channel is idle */
264 if (dma_readl(dw, CH_EN) & dwc->mask) {
265 dev_err(chan2dev(&dwc->chan),
266 "BUG: Attempted to start non-idle channel\n");
267 dwc_dump_chan_regs(dwc);
269 /* The tasklet will hopefully advance the queue... */
274 was_soft_llp = test_and_set_bit(DW_DMA_IS_SOFT_LLP,
277 dev_err(chan2dev(&dwc->chan),
278 "BUG: Attempted to start new LLP transfer "
279 "inside ongoing one\n");
285 dwc->tx_node_active = &first->tx_list;
287 /* Submit first block */
288 dwc_do_single_block(dwc, first);
295 channel_writel(dwc, LLP, first->txd.phys);
296 channel_writel(dwc, CTL_LO,
297 DWC_CTLL_LLP_D_EN | DWC_CTLL_LLP_S_EN);
298 channel_writel(dwc, CTL_HI, 0);
299 channel_set_bit(dw, CH_EN, dwc->mask);
302 /*----------------------------------------------------------------------*/
305 dwc_descriptor_complete(struct dw_dma_chan *dwc, struct dw_desc *desc,
306 bool callback_required)
308 dma_async_tx_callback callback = NULL;
310 struct dma_async_tx_descriptor *txd = &desc->txd;
311 struct dw_desc *child;
314 dev_vdbg(chan2dev(&dwc->chan), "descriptor %u complete\n", txd->cookie);
316 spin_lock_irqsave(&dwc->lock, flags);
317 dma_cookie_complete(txd);
318 if (callback_required) {
319 callback = txd->callback;
320 param = txd->callback_param;
324 list_for_each_entry(child, &desc->tx_list, desc_node)
325 async_tx_ack(&child->txd);
326 async_tx_ack(&desc->txd);
328 list_splice_init(&desc->tx_list, &dwc->free_list);
329 list_move(&desc->desc_node, &dwc->free_list);
331 if (!is_slave_direction(dwc->direction)) {
332 struct device *parent = chan2parent(&dwc->chan);
333 if (!(txd->flags & DMA_COMPL_SKIP_DEST_UNMAP)) {
334 if (txd->flags & DMA_COMPL_DEST_UNMAP_SINGLE)
335 dma_unmap_single(parent, desc->lli.dar,
336 desc->total_len, DMA_FROM_DEVICE);
338 dma_unmap_page(parent, desc->lli.dar,
339 desc->total_len, DMA_FROM_DEVICE);
341 if (!(txd->flags & DMA_COMPL_SKIP_SRC_UNMAP)) {
342 if (txd->flags & DMA_COMPL_SRC_UNMAP_SINGLE)
343 dma_unmap_single(parent, desc->lli.sar,
344 desc->total_len, DMA_TO_DEVICE);
346 dma_unmap_page(parent, desc->lli.sar,
347 desc->total_len, DMA_TO_DEVICE);
351 spin_unlock_irqrestore(&dwc->lock, flags);
357 static void dwc_complete_all(struct dw_dma *dw, struct dw_dma_chan *dwc)
359 struct dw_desc *desc, *_desc;
363 spin_lock_irqsave(&dwc->lock, flags);
364 if (dma_readl(dw, CH_EN) & dwc->mask) {
365 dev_err(chan2dev(&dwc->chan),
366 "BUG: XFER bit set, but channel not idle!\n");
368 /* Try to continue after resetting the channel... */
369 dwc_chan_disable(dw, dwc);
373 * Submit queued descriptors ASAP, i.e. before we go through
374 * the completed ones.
376 list_splice_init(&dwc->active_list, &list);
377 if (!list_empty(&dwc->queue)) {
378 list_move(dwc->queue.next, &dwc->active_list);
379 dwc_dostart(dwc, dwc_first_active(dwc));
382 spin_unlock_irqrestore(&dwc->lock, flags);
384 list_for_each_entry_safe(desc, _desc, &list, desc_node)
385 dwc_descriptor_complete(dwc, desc, true);
388 static void dwc_scan_descriptors(struct dw_dma *dw, struct dw_dma_chan *dwc)
391 struct dw_desc *desc, *_desc;
392 struct dw_desc *child;
396 spin_lock_irqsave(&dwc->lock, flags);
397 llp = channel_readl(dwc, LLP);
398 status_xfer = dma_readl(dw, RAW.XFER);
400 if (status_xfer & dwc->mask) {
401 /* Everything we've submitted is done */
402 dma_writel(dw, CLEAR.XFER, dwc->mask);
404 if (test_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags)) {
405 struct list_head *head, *active = dwc->tx_node_active;
408 * We are inside first active descriptor.
409 * Otherwise something is really wrong.
411 desc = dwc_first_active(dwc);
413 head = &desc->tx_list;
414 if (active != head) {
415 child = to_dw_desc(active);
417 /* Submit next block */
418 dwc_do_single_block(dwc, child);
420 spin_unlock_irqrestore(&dwc->lock, flags);
424 /* We are done here */
425 clear_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags);
427 spin_unlock_irqrestore(&dwc->lock, flags);
429 dwc_complete_all(dw, dwc);
433 if (list_empty(&dwc->active_list)) {
434 spin_unlock_irqrestore(&dwc->lock, flags);
438 if (test_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags)) {
439 dev_vdbg(chan2dev(&dwc->chan), "%s: soft LLP mode\n", __func__);
440 spin_unlock_irqrestore(&dwc->lock, flags);
444 dev_vdbg(chan2dev(&dwc->chan), "%s: llp=0x%llx\n", __func__,
445 (unsigned long long)llp);
447 list_for_each_entry_safe(desc, _desc, &dwc->active_list, desc_node) {
448 /* check first descriptors addr */
449 if (desc->txd.phys == llp) {
450 spin_unlock_irqrestore(&dwc->lock, flags);
454 /* check first descriptors llp */
455 if (desc->lli.llp == llp) {
456 /* This one is currently in progress */
457 spin_unlock_irqrestore(&dwc->lock, flags);
461 list_for_each_entry(child, &desc->tx_list, desc_node)
462 if (child->lli.llp == llp) {
463 /* Currently in progress */
464 spin_unlock_irqrestore(&dwc->lock, flags);
469 * No descriptors so far seem to be in progress, i.e.
470 * this one must be done.
472 spin_unlock_irqrestore(&dwc->lock, flags);
473 dwc_descriptor_complete(dwc, desc, true);
474 spin_lock_irqsave(&dwc->lock, flags);
477 dev_err(chan2dev(&dwc->chan),
478 "BUG: All descriptors done, but channel not idle!\n");
480 /* Try to continue after resetting the channel... */
481 dwc_chan_disable(dw, dwc);
483 if (!list_empty(&dwc->queue)) {
484 list_move(dwc->queue.next, &dwc->active_list);
485 dwc_dostart(dwc, dwc_first_active(dwc));
487 spin_unlock_irqrestore(&dwc->lock, flags);
490 static inline void dwc_dump_lli(struct dw_dma_chan *dwc, struct dw_lli *lli)
492 dev_crit(chan2dev(&dwc->chan), " desc: s0x%x d0x%x l0x%x c0x%x:%x\n",
493 lli->sar, lli->dar, lli->llp, lli->ctlhi, lli->ctllo);
496 static void dwc_handle_error(struct dw_dma *dw, struct dw_dma_chan *dwc)
498 struct dw_desc *bad_desc;
499 struct dw_desc *child;
502 dwc_scan_descriptors(dw, dwc);
504 spin_lock_irqsave(&dwc->lock, flags);
507 * The descriptor currently at the head of the active list is
508 * borked. Since we don't have any way to report errors, we'll
509 * just have to scream loudly and try to carry on.
511 bad_desc = dwc_first_active(dwc);
512 list_del_init(&bad_desc->desc_node);
513 list_move(dwc->queue.next, dwc->active_list.prev);
515 /* Clear the error flag and try to restart the controller */
516 dma_writel(dw, CLEAR.ERROR, dwc->mask);
517 if (!list_empty(&dwc->active_list))
518 dwc_dostart(dwc, dwc_first_active(dwc));
521 * WARN may seem harsh, but since this only happens
522 * when someone submits a bad physical address in a
523 * descriptor, we should consider ourselves lucky that the
524 * controller flagged an error instead of scribbling over
525 * random memory locations.
527 dev_WARN(chan2dev(&dwc->chan), "Bad descriptor submitted for DMA!\n"
528 " cookie: %d\n", bad_desc->txd.cookie);
529 dwc_dump_lli(dwc, &bad_desc->lli);
530 list_for_each_entry(child, &bad_desc->tx_list, desc_node)
531 dwc_dump_lli(dwc, &child->lli);
533 spin_unlock_irqrestore(&dwc->lock, flags);
535 /* Pretend the descriptor completed successfully */
536 dwc_descriptor_complete(dwc, bad_desc, true);
539 /* --------------------- Cyclic DMA API extensions -------------------- */
541 inline dma_addr_t dw_dma_get_src_addr(struct dma_chan *chan)
543 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
544 return channel_readl(dwc, SAR);
546 EXPORT_SYMBOL(dw_dma_get_src_addr);
548 inline dma_addr_t dw_dma_get_dst_addr(struct dma_chan *chan)
550 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
551 return channel_readl(dwc, DAR);
553 EXPORT_SYMBOL(dw_dma_get_dst_addr);
555 /* called with dwc->lock held and all DMAC interrupts disabled */
556 static void dwc_handle_cyclic(struct dw_dma *dw, struct dw_dma_chan *dwc,
557 u32 status_err, u32 status_xfer)
562 void (*callback)(void *param);
563 void *callback_param;
565 dev_vdbg(chan2dev(&dwc->chan), "new cyclic period llp 0x%08x\n",
566 channel_readl(dwc, LLP));
568 callback = dwc->cdesc->period_callback;
569 callback_param = dwc->cdesc->period_callback_param;
572 callback(callback_param);
576 * Error and transfer complete are highly unlikely, and will most
577 * likely be due to a configuration error by the user.
579 if (unlikely(status_err & dwc->mask) ||
580 unlikely(status_xfer & dwc->mask)) {
583 dev_err(chan2dev(&dwc->chan), "cyclic DMA unexpected %s "
584 "interrupt, stopping DMA transfer\n",
585 status_xfer ? "xfer" : "error");
587 spin_lock_irqsave(&dwc->lock, flags);
589 dwc_dump_chan_regs(dwc);
591 dwc_chan_disable(dw, dwc);
593 /* make sure DMA does not restart by loading a new list */
594 channel_writel(dwc, LLP, 0);
595 channel_writel(dwc, CTL_LO, 0);
596 channel_writel(dwc, CTL_HI, 0);
598 dma_writel(dw, CLEAR.ERROR, dwc->mask);
599 dma_writel(dw, CLEAR.XFER, dwc->mask);
601 for (i = 0; i < dwc->cdesc->periods; i++)
602 dwc_dump_lli(dwc, &dwc->cdesc->desc[i]->lli);
604 spin_unlock_irqrestore(&dwc->lock, flags);
608 /* ------------------------------------------------------------------------- */
610 static void dw_dma_tasklet(unsigned long data)
612 struct dw_dma *dw = (struct dw_dma *)data;
613 struct dw_dma_chan *dwc;
618 status_xfer = dma_readl(dw, RAW.XFER);
619 status_err = dma_readl(dw, RAW.ERROR);
621 dev_vdbg(dw->dma.dev, "%s: status_err=%x\n", __func__, status_err);
623 for (i = 0; i < dw->dma.chancnt; i++) {
625 if (test_bit(DW_DMA_IS_CYCLIC, &dwc->flags))
626 dwc_handle_cyclic(dw, dwc, status_err, status_xfer);
627 else if (status_err & (1 << i))
628 dwc_handle_error(dw, dwc);
629 else if (status_xfer & (1 << i))
630 dwc_scan_descriptors(dw, dwc);
634 * Re-enable interrupts.
636 channel_set_bit(dw, MASK.XFER, dw->all_chan_mask);
637 channel_set_bit(dw, MASK.ERROR, dw->all_chan_mask);
640 static irqreturn_t dw_dma_interrupt(int irq, void *dev_id)
642 struct dw_dma *dw = dev_id;
645 dev_vdbg(dw->dma.dev, "%s: status=0x%x\n", __func__,
646 dma_readl(dw, STATUS_INT));
649 * Just disable the interrupts. We'll turn them back on in the
652 channel_clear_bit(dw, MASK.XFER, dw->all_chan_mask);
653 channel_clear_bit(dw, MASK.ERROR, dw->all_chan_mask);
655 status = dma_readl(dw, STATUS_INT);
658 "BUG: Unexpected interrupts pending: 0x%x\n",
662 channel_clear_bit(dw, MASK.XFER, (1 << 8) - 1);
663 channel_clear_bit(dw, MASK.SRC_TRAN, (1 << 8) - 1);
664 channel_clear_bit(dw, MASK.DST_TRAN, (1 << 8) - 1);
665 channel_clear_bit(dw, MASK.ERROR, (1 << 8) - 1);
668 tasklet_schedule(&dw->tasklet);
673 /*----------------------------------------------------------------------*/
675 static dma_cookie_t dwc_tx_submit(struct dma_async_tx_descriptor *tx)
677 struct dw_desc *desc = txd_to_dw_desc(tx);
678 struct dw_dma_chan *dwc = to_dw_dma_chan(tx->chan);
682 spin_lock_irqsave(&dwc->lock, flags);
683 cookie = dma_cookie_assign(tx);
686 * REVISIT: We should attempt to chain as many descriptors as
687 * possible, perhaps even appending to those already submitted
688 * for DMA. But this is hard to do in a race-free manner.
690 if (list_empty(&dwc->active_list)) {
691 dev_vdbg(chan2dev(tx->chan), "%s: started %u\n", __func__,
693 list_add_tail(&desc->desc_node, &dwc->active_list);
694 dwc_dostart(dwc, dwc_first_active(dwc));
696 dev_vdbg(chan2dev(tx->chan), "%s: queued %u\n", __func__,
699 list_add_tail(&desc->desc_node, &dwc->queue);
702 spin_unlock_irqrestore(&dwc->lock, flags);
707 static struct dma_async_tx_descriptor *
708 dwc_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
709 size_t len, unsigned long flags)
711 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
712 struct dw_desc *desc;
713 struct dw_desc *first;
714 struct dw_desc *prev;
717 unsigned int src_width;
718 unsigned int dst_width;
719 unsigned int data_width;
722 dev_vdbg(chan2dev(chan),
723 "%s: d0x%llx s0x%llx l0x%zx f0x%lx\n", __func__,
724 (unsigned long long)dest, (unsigned long long)src,
727 if (unlikely(!len)) {
728 dev_dbg(chan2dev(chan), "%s: length is zero!\n", __func__);
732 dwc->direction = DMA_MEM_TO_MEM;
734 data_width = min_t(unsigned int, dwc_get_data_width(chan, SRC_MASTER),
735 dwc_get_data_width(chan, DST_MASTER));
737 src_width = dst_width = min_t(unsigned int, data_width,
738 dwc_fast_fls(src | dest | len));
740 ctllo = DWC_DEFAULT_CTLLO(chan)
741 | DWC_CTLL_DST_WIDTH(dst_width)
742 | DWC_CTLL_SRC_WIDTH(src_width)
748 for (offset = 0; offset < len; offset += xfer_count << src_width) {
749 xfer_count = min_t(size_t, (len - offset) >> src_width,
752 desc = dwc_desc_get(dwc);
756 desc->lli.sar = src + offset;
757 desc->lli.dar = dest + offset;
758 desc->lli.ctllo = ctllo;
759 desc->lli.ctlhi = xfer_count;
764 prev->lli.llp = desc->txd.phys;
765 list_add_tail(&desc->desc_node,
771 if (flags & DMA_PREP_INTERRUPT)
772 /* Trigger interrupt after last block */
773 prev->lli.ctllo |= DWC_CTLL_INT_EN;
776 first->txd.flags = flags;
777 first->total_len = len;
782 dwc_desc_put(dwc, first);
786 static struct dma_async_tx_descriptor *
787 dwc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
788 unsigned int sg_len, enum dma_transfer_direction direction,
789 unsigned long flags, void *context)
791 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
792 struct dma_slave_config *sconfig = &dwc->dma_sconfig;
793 struct dw_desc *prev;
794 struct dw_desc *first;
797 unsigned int reg_width;
798 unsigned int mem_width;
799 unsigned int data_width;
801 struct scatterlist *sg;
802 size_t total_len = 0;
804 dev_vdbg(chan2dev(chan), "%s\n", __func__);
806 if (unlikely(!is_slave_direction(direction) || !sg_len))
809 dwc->direction = direction;
815 reg_width = __fls(sconfig->dst_addr_width);
816 reg = sconfig->dst_addr;
817 ctllo = (DWC_DEFAULT_CTLLO(chan)
818 | DWC_CTLL_DST_WIDTH(reg_width)
822 ctllo |= sconfig->device_fc ? DWC_CTLL_FC(DW_DMA_FC_P_M2P) :
823 DWC_CTLL_FC(DW_DMA_FC_D_M2P);
825 data_width = dwc_get_data_width(chan, SRC_MASTER);
827 for_each_sg(sgl, sg, sg_len, i) {
828 struct dw_desc *desc;
831 mem = sg_dma_address(sg);
832 len = sg_dma_len(sg);
834 mem_width = min_t(unsigned int,
835 data_width, dwc_fast_fls(mem | len));
837 slave_sg_todev_fill_desc:
838 desc = dwc_desc_get(dwc);
840 dev_err(chan2dev(chan),
841 "not enough descriptors available\n");
847 desc->lli.ctllo = ctllo | DWC_CTLL_SRC_WIDTH(mem_width);
848 if ((len >> mem_width) > dwc->block_size) {
849 dlen = dwc->block_size << mem_width;
857 desc->lli.ctlhi = dlen >> mem_width;
862 prev->lli.llp = desc->txd.phys;
863 list_add_tail(&desc->desc_node,
870 goto slave_sg_todev_fill_desc;
874 reg_width = __fls(sconfig->src_addr_width);
875 reg = sconfig->src_addr;
876 ctllo = (DWC_DEFAULT_CTLLO(chan)
877 | DWC_CTLL_SRC_WIDTH(reg_width)
881 ctllo |= sconfig->device_fc ? DWC_CTLL_FC(DW_DMA_FC_P_P2M) :
882 DWC_CTLL_FC(DW_DMA_FC_D_P2M);
884 data_width = dwc_get_data_width(chan, DST_MASTER);
886 for_each_sg(sgl, sg, sg_len, i) {
887 struct dw_desc *desc;
890 mem = sg_dma_address(sg);
891 len = sg_dma_len(sg);
893 mem_width = min_t(unsigned int,
894 data_width, dwc_fast_fls(mem | len));
896 slave_sg_fromdev_fill_desc:
897 desc = dwc_desc_get(dwc);
899 dev_err(chan2dev(chan),
900 "not enough descriptors available\n");
906 desc->lli.ctllo = ctllo | DWC_CTLL_DST_WIDTH(mem_width);
907 if ((len >> reg_width) > dwc->block_size) {
908 dlen = dwc->block_size << reg_width;
915 desc->lli.ctlhi = dlen >> reg_width;
920 prev->lli.llp = desc->txd.phys;
921 list_add_tail(&desc->desc_node,
928 goto slave_sg_fromdev_fill_desc;
935 if (flags & DMA_PREP_INTERRUPT)
936 /* Trigger interrupt after last block */
937 prev->lli.ctllo |= DWC_CTLL_INT_EN;
940 first->total_len = total_len;
945 dwc_desc_put(dwc, first);
950 * Fix sconfig's burst size according to dw_dmac. We need to convert them as:
951 * 1 -> 0, 4 -> 1, 8 -> 2, 16 -> 3.
953 * NOTE: burst size 2 is not supported by controller.
955 * This can be done by finding least significant bit set: n & (n - 1)
957 static inline void convert_burst(u32 *maxburst)
960 *maxburst = fls(*maxburst) - 2;
966 set_runtime_config(struct dma_chan *chan, struct dma_slave_config *sconfig)
968 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
970 /* Check if chan will be configured for slave transfers */
971 if (!is_slave_direction(sconfig->direction))
974 memcpy(&dwc->dma_sconfig, sconfig, sizeof(*sconfig));
975 dwc->direction = sconfig->direction;
977 convert_burst(&dwc->dma_sconfig.src_maxburst);
978 convert_burst(&dwc->dma_sconfig.dst_maxburst);
983 static inline void dwc_chan_pause(struct dw_dma_chan *dwc)
985 u32 cfglo = channel_readl(dwc, CFG_LO);
987 channel_writel(dwc, CFG_LO, cfglo | DWC_CFGL_CH_SUSP);
988 while (!(channel_readl(dwc, CFG_LO) & DWC_CFGL_FIFO_EMPTY))
994 static inline void dwc_chan_resume(struct dw_dma_chan *dwc)
996 u32 cfglo = channel_readl(dwc, CFG_LO);
998 channel_writel(dwc, CFG_LO, cfglo & ~DWC_CFGL_CH_SUSP);
1000 dwc->paused = false;
1003 static int dwc_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
1006 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
1007 struct dw_dma *dw = to_dw_dma(chan->device);
1008 struct dw_desc *desc, *_desc;
1009 unsigned long flags;
1012 if (cmd == DMA_PAUSE) {
1013 spin_lock_irqsave(&dwc->lock, flags);
1015 dwc_chan_pause(dwc);
1017 spin_unlock_irqrestore(&dwc->lock, flags);
1018 } else if (cmd == DMA_RESUME) {
1022 spin_lock_irqsave(&dwc->lock, flags);
1024 dwc_chan_resume(dwc);
1026 spin_unlock_irqrestore(&dwc->lock, flags);
1027 } else if (cmd == DMA_TERMINATE_ALL) {
1028 spin_lock_irqsave(&dwc->lock, flags);
1030 clear_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags);
1032 dwc_chan_disable(dw, dwc);
1034 dwc_chan_resume(dwc);
1036 /* active_list entries will end up before queued entries */
1037 list_splice_init(&dwc->queue, &list);
1038 list_splice_init(&dwc->active_list, &list);
1040 spin_unlock_irqrestore(&dwc->lock, flags);
1042 /* Flush all pending and queued descriptors */
1043 list_for_each_entry_safe(desc, _desc, &list, desc_node)
1044 dwc_descriptor_complete(dwc, desc, false);
1045 } else if (cmd == DMA_SLAVE_CONFIG) {
1046 return set_runtime_config(chan, (struct dma_slave_config *)arg);
1054 static enum dma_status
1055 dwc_tx_status(struct dma_chan *chan,
1056 dma_cookie_t cookie,
1057 struct dma_tx_state *txstate)
1059 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
1060 enum dma_status ret;
1062 ret = dma_cookie_status(chan, cookie, txstate);
1063 if (ret != DMA_SUCCESS) {
1064 dwc_scan_descriptors(to_dw_dma(chan->device), dwc);
1066 ret = dma_cookie_status(chan, cookie, txstate);
1069 if (ret != DMA_SUCCESS)
1070 dma_set_residue(txstate, dwc_first_active(dwc)->len);
1078 static void dwc_issue_pending(struct dma_chan *chan)
1080 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
1082 if (!list_empty(&dwc->queue))
1083 dwc_scan_descriptors(to_dw_dma(chan->device), dwc);
1086 static int dwc_alloc_chan_resources(struct dma_chan *chan)
1088 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
1089 struct dw_dma *dw = to_dw_dma(chan->device);
1090 struct dw_desc *desc;
1092 unsigned long flags;
1094 dev_vdbg(chan2dev(chan), "%s\n", __func__);
1096 /* ASSERT: channel is idle */
1097 if (dma_readl(dw, CH_EN) & dwc->mask) {
1098 dev_dbg(chan2dev(chan), "DMA channel not idle?\n");
1102 dma_cookie_init(chan);
1105 * NOTE: some controllers may have additional features that we
1106 * need to initialize here, like "scatter-gather" (which
1107 * doesn't mean what you think it means), and status writeback.
1110 spin_lock_irqsave(&dwc->lock, flags);
1111 i = dwc->descs_allocated;
1112 while (dwc->descs_allocated < NR_DESCS_PER_CHANNEL) {
1115 spin_unlock_irqrestore(&dwc->lock, flags);
1117 desc = dma_pool_alloc(dw->desc_pool, GFP_ATOMIC, &phys);
1119 goto err_desc_alloc;
1121 memset(desc, 0, sizeof(struct dw_desc));
1123 INIT_LIST_HEAD(&desc->tx_list);
1124 dma_async_tx_descriptor_init(&desc->txd, chan);
1125 desc->txd.tx_submit = dwc_tx_submit;
1126 desc->txd.flags = DMA_CTRL_ACK;
1127 desc->txd.phys = phys;
1129 dwc_desc_put(dwc, desc);
1131 spin_lock_irqsave(&dwc->lock, flags);
1132 i = ++dwc->descs_allocated;
1135 spin_unlock_irqrestore(&dwc->lock, flags);
1137 dev_dbg(chan2dev(chan), "%s: allocated %d descriptors\n", __func__, i);
1142 dev_info(chan2dev(chan), "only allocated %d descriptors\n", i);
1147 static void dwc_free_chan_resources(struct dma_chan *chan)
1149 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
1150 struct dw_dma *dw = to_dw_dma(chan->device);
1151 struct dw_desc *desc, *_desc;
1152 unsigned long flags;
1155 dev_dbg(chan2dev(chan), "%s: descs allocated=%u\n", __func__,
1156 dwc->descs_allocated);
1158 /* ASSERT: channel is idle */
1159 BUG_ON(!list_empty(&dwc->active_list));
1160 BUG_ON(!list_empty(&dwc->queue));
1161 BUG_ON(dma_readl(to_dw_dma(chan->device), CH_EN) & dwc->mask);
1163 spin_lock_irqsave(&dwc->lock, flags);
1164 list_splice_init(&dwc->free_list, &list);
1165 dwc->descs_allocated = 0;
1166 dwc->initialized = false;
1168 /* Disable interrupts */
1169 channel_clear_bit(dw, MASK.XFER, dwc->mask);
1170 channel_clear_bit(dw, MASK.ERROR, dwc->mask);
1172 spin_unlock_irqrestore(&dwc->lock, flags);
1174 list_for_each_entry_safe(desc, _desc, &list, desc_node) {
1175 dev_vdbg(chan2dev(chan), " freeing descriptor %p\n", desc);
1176 dma_pool_free(dw->desc_pool, desc, desc->txd.phys);
1179 dev_vdbg(chan2dev(chan), "%s: done\n", __func__);
1182 bool dw_dma_generic_filter(struct dma_chan *chan, void *param)
1184 struct dw_dma *dw = to_dw_dma(chan->device);
1185 static struct dw_dma *last_dw;
1186 static char *last_bus_id;
1190 * dmaengine framework calls this routine for all channels of all dma
1191 * controller, until true is returned. If 'param' bus_id is not
1192 * registered with a dma controller (dw), then there is no need of
1193 * running below function for all channels of dw.
1195 * This block of code does this by saving the parameters of last
1196 * failure. If dw and param are same, i.e. trying on same dw with
1197 * different channel, return false.
1199 if ((last_dw == dw) && (last_bus_id == param))
1203 * - If dw_dma's platform data is not filled with slave info, then all
1204 * dma controllers are fine for transfer.
1205 * - Or if param is NULL
1207 if (!dw->sd || !param)
1210 while (++i < dw->sd_count) {
1211 if (!strcmp(dw->sd[i].bus_id, param)) {
1212 chan->private = &dw->sd[i];
1221 last_bus_id = param;
1224 EXPORT_SYMBOL(dw_dma_generic_filter);
1226 /* --------------------- Cyclic DMA API extensions -------------------- */
1229 * dw_dma_cyclic_start - start the cyclic DMA transfer
1230 * @chan: the DMA channel to start
1232 * Must be called with soft interrupts disabled. Returns zero on success or
1233 * -errno on failure.
1235 int dw_dma_cyclic_start(struct dma_chan *chan)
1237 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
1238 struct dw_dma *dw = to_dw_dma(dwc->chan.device);
1239 unsigned long flags;
1241 if (!test_bit(DW_DMA_IS_CYCLIC, &dwc->flags)) {
1242 dev_err(chan2dev(&dwc->chan), "missing prep for cyclic DMA\n");
1246 spin_lock_irqsave(&dwc->lock, flags);
1248 /* assert channel is idle */
1249 if (dma_readl(dw, CH_EN) & dwc->mask) {
1250 dev_err(chan2dev(&dwc->chan),
1251 "BUG: Attempted to start non-idle channel\n");
1252 dwc_dump_chan_regs(dwc);
1253 spin_unlock_irqrestore(&dwc->lock, flags);
1257 dma_writel(dw, CLEAR.ERROR, dwc->mask);
1258 dma_writel(dw, CLEAR.XFER, dwc->mask);
1260 /* setup DMAC channel registers */
1261 channel_writel(dwc, LLP, dwc->cdesc->desc[0]->txd.phys);
1262 channel_writel(dwc, CTL_LO, DWC_CTLL_LLP_D_EN | DWC_CTLL_LLP_S_EN);
1263 channel_writel(dwc, CTL_HI, 0);
1265 channel_set_bit(dw, CH_EN, dwc->mask);
1267 spin_unlock_irqrestore(&dwc->lock, flags);
1271 EXPORT_SYMBOL(dw_dma_cyclic_start);
1274 * dw_dma_cyclic_stop - stop the cyclic DMA transfer
1275 * @chan: the DMA channel to stop
1277 * Must be called with soft interrupts disabled.
1279 void dw_dma_cyclic_stop(struct dma_chan *chan)
1281 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
1282 struct dw_dma *dw = to_dw_dma(dwc->chan.device);
1283 unsigned long flags;
1285 spin_lock_irqsave(&dwc->lock, flags);
1287 dwc_chan_disable(dw, dwc);
1289 spin_unlock_irqrestore(&dwc->lock, flags);
1291 EXPORT_SYMBOL(dw_dma_cyclic_stop);
1294 * dw_dma_cyclic_prep - prepare the cyclic DMA transfer
1295 * @chan: the DMA channel to prepare
1296 * @buf_addr: physical DMA address where the buffer starts
1297 * @buf_len: total number of bytes for the entire buffer
1298 * @period_len: number of bytes for each period
1299 * @direction: transfer direction, to or from device
1301 * Must be called before trying to start the transfer. Returns a valid struct
1302 * dw_cyclic_desc if successful or an ERR_PTR(-errno) if not successful.
1304 struct dw_cyclic_desc *dw_dma_cyclic_prep(struct dma_chan *chan,
1305 dma_addr_t buf_addr, size_t buf_len, size_t period_len,
1306 enum dma_transfer_direction direction)
1308 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
1309 struct dma_slave_config *sconfig = &dwc->dma_sconfig;
1310 struct dw_cyclic_desc *cdesc;
1311 struct dw_cyclic_desc *retval = NULL;
1312 struct dw_desc *desc;
1313 struct dw_desc *last = NULL;
1314 unsigned long was_cyclic;
1315 unsigned int reg_width;
1316 unsigned int periods;
1318 unsigned long flags;
1320 spin_lock_irqsave(&dwc->lock, flags);
1322 spin_unlock_irqrestore(&dwc->lock, flags);
1323 dev_dbg(chan2dev(&dwc->chan),
1324 "channel doesn't support LLP transfers\n");
1325 return ERR_PTR(-EINVAL);
1328 if (!list_empty(&dwc->queue) || !list_empty(&dwc->active_list)) {
1329 spin_unlock_irqrestore(&dwc->lock, flags);
1330 dev_dbg(chan2dev(&dwc->chan),
1331 "queue and/or active list are not empty\n");
1332 return ERR_PTR(-EBUSY);
1335 was_cyclic = test_and_set_bit(DW_DMA_IS_CYCLIC, &dwc->flags);
1336 spin_unlock_irqrestore(&dwc->lock, flags);
1338 dev_dbg(chan2dev(&dwc->chan),
1339 "channel already prepared for cyclic DMA\n");
1340 return ERR_PTR(-EBUSY);
1343 retval = ERR_PTR(-EINVAL);
1345 if (unlikely(!is_slave_direction(direction)))
1348 dwc->direction = direction;
1350 if (direction == DMA_MEM_TO_DEV)
1351 reg_width = __ffs(sconfig->dst_addr_width);
1353 reg_width = __ffs(sconfig->src_addr_width);
1355 periods = buf_len / period_len;
1357 /* Check for too big/unaligned periods and unaligned DMA buffer. */
1358 if (period_len > (dwc->block_size << reg_width))
1360 if (unlikely(period_len & ((1 << reg_width) - 1)))
1362 if (unlikely(buf_addr & ((1 << reg_width) - 1)))
1365 retval = ERR_PTR(-ENOMEM);
1367 if (periods > NR_DESCS_PER_CHANNEL)
1370 cdesc = kzalloc(sizeof(struct dw_cyclic_desc), GFP_KERNEL);
1374 cdesc->desc = kzalloc(sizeof(struct dw_desc *) * periods, GFP_KERNEL);
1378 for (i = 0; i < periods; i++) {
1379 desc = dwc_desc_get(dwc);
1381 goto out_err_desc_get;
1383 switch (direction) {
1384 case DMA_MEM_TO_DEV:
1385 desc->lli.dar = sconfig->dst_addr;
1386 desc->lli.sar = buf_addr + (period_len * i);
1387 desc->lli.ctllo = (DWC_DEFAULT_CTLLO(chan)
1388 | DWC_CTLL_DST_WIDTH(reg_width)
1389 | DWC_CTLL_SRC_WIDTH(reg_width)
1394 desc->lli.ctllo |= sconfig->device_fc ?
1395 DWC_CTLL_FC(DW_DMA_FC_P_M2P) :
1396 DWC_CTLL_FC(DW_DMA_FC_D_M2P);
1399 case DMA_DEV_TO_MEM:
1400 desc->lli.dar = buf_addr + (period_len * i);
1401 desc->lli.sar = sconfig->src_addr;
1402 desc->lli.ctllo = (DWC_DEFAULT_CTLLO(chan)
1403 | DWC_CTLL_SRC_WIDTH(reg_width)
1404 | DWC_CTLL_DST_WIDTH(reg_width)
1409 desc->lli.ctllo |= sconfig->device_fc ?
1410 DWC_CTLL_FC(DW_DMA_FC_P_P2M) :
1411 DWC_CTLL_FC(DW_DMA_FC_D_P2M);
1418 desc->lli.ctlhi = (period_len >> reg_width);
1419 cdesc->desc[i] = desc;
1422 last->lli.llp = desc->txd.phys;
1427 /* lets make a cyclic list */
1428 last->lli.llp = cdesc->desc[0]->txd.phys;
1430 dev_dbg(chan2dev(&dwc->chan), "cyclic prepared buf 0x%llx len %zu "
1431 "period %zu periods %d\n", (unsigned long long)buf_addr,
1432 buf_len, period_len, periods);
1434 cdesc->periods = periods;
1441 dwc_desc_put(dwc, cdesc->desc[i]);
1445 clear_bit(DW_DMA_IS_CYCLIC, &dwc->flags);
1446 return (struct dw_cyclic_desc *)retval;
1448 EXPORT_SYMBOL(dw_dma_cyclic_prep);
1451 * dw_dma_cyclic_free - free a prepared cyclic DMA transfer
1452 * @chan: the DMA channel to free
1454 void dw_dma_cyclic_free(struct dma_chan *chan)
1456 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
1457 struct dw_dma *dw = to_dw_dma(dwc->chan.device);
1458 struct dw_cyclic_desc *cdesc = dwc->cdesc;
1460 unsigned long flags;
1462 dev_dbg(chan2dev(&dwc->chan), "%s\n", __func__);
1467 spin_lock_irqsave(&dwc->lock, flags);
1469 dwc_chan_disable(dw, dwc);
1471 dma_writel(dw, CLEAR.ERROR, dwc->mask);
1472 dma_writel(dw, CLEAR.XFER, dwc->mask);
1474 spin_unlock_irqrestore(&dwc->lock, flags);
1476 for (i = 0; i < cdesc->periods; i++)
1477 dwc_desc_put(dwc, cdesc->desc[i]);
1482 clear_bit(DW_DMA_IS_CYCLIC, &dwc->flags);
1484 EXPORT_SYMBOL(dw_dma_cyclic_free);
1486 /*----------------------------------------------------------------------*/
1488 static void dw_dma_off(struct dw_dma *dw)
1492 dma_writel(dw, CFG, 0);
1494 channel_clear_bit(dw, MASK.XFER, dw->all_chan_mask);
1495 channel_clear_bit(dw, MASK.SRC_TRAN, dw->all_chan_mask);
1496 channel_clear_bit(dw, MASK.DST_TRAN, dw->all_chan_mask);
1497 channel_clear_bit(dw, MASK.ERROR, dw->all_chan_mask);
1499 while (dma_readl(dw, CFG) & DW_CFG_DMA_EN)
1502 for (i = 0; i < dw->dma.chancnt; i++)
1503 dw->chan[i].initialized = false;
1507 static struct dw_dma_platform_data *
1508 dw_dma_parse_dt(struct platform_device *pdev)
1510 struct device_node *sn, *cn, *np = pdev->dev.of_node;
1511 struct dw_dma_platform_data *pdata;
1512 struct dw_dma_slave *sd;
1516 dev_err(&pdev->dev, "Missing DT data\n");
1520 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
1524 if (of_property_read_u32(np, "nr_channels", &pdata->nr_channels))
1527 if (of_property_read_bool(np, "is_private"))
1528 pdata->is_private = true;
1530 if (!of_property_read_u32(np, "chan_allocation_order", &tmp))
1531 pdata->chan_allocation_order = (unsigned char)tmp;
1533 if (!of_property_read_u32(np, "chan_priority", &tmp))
1534 pdata->chan_priority = tmp;
1536 if (!of_property_read_u32(np, "block_size", &tmp))
1537 pdata->block_size = tmp;
1539 if (!of_property_read_u32(np, "nr_masters", &tmp)) {
1543 pdata->nr_masters = tmp;
1546 if (!of_property_read_u32_array(np, "data_width", arr,
1548 for (tmp = 0; tmp < pdata->nr_masters; tmp++)
1549 pdata->data_width[tmp] = arr[tmp];
1551 /* parse slave data */
1552 sn = of_find_node_by_name(np, "slave_info");
1556 /* calculate number of slaves */
1557 tmp = of_get_child_count(sn);
1561 sd = devm_kzalloc(&pdev->dev, sizeof(*sd) * tmp, GFP_KERNEL);
1566 pdata->sd_count = tmp;
1568 for_each_child_of_node(sn, cn) {
1569 sd->dma_dev = &pdev->dev;
1570 of_property_read_string(cn, "bus_id", &sd->bus_id);
1571 of_property_read_u32(cn, "cfg_hi", &sd->cfg_hi);
1572 of_property_read_u32(cn, "cfg_lo", &sd->cfg_lo);
1573 if (!of_property_read_u32(cn, "src_master", &tmp))
1574 sd->src_master = tmp;
1576 if (!of_property_read_u32(cn, "dst_master", &tmp))
1577 sd->dst_master = tmp;
1584 static inline struct dw_dma_platform_data *
1585 dw_dma_parse_dt(struct platform_device *pdev)
1591 static int dw_probe(struct platform_device *pdev)
1593 struct dw_dma_platform_data *pdata;
1594 struct resource *io;
1599 unsigned int dw_params;
1600 unsigned int nr_channels;
1601 unsigned int max_blk_size = 0;
1606 io = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1610 irq = platform_get_irq(pdev, 0);
1614 regs = devm_request_and_ioremap(&pdev->dev, io);
1618 dw_params = dma_read_byaddr(regs, DW_PARAMS);
1619 autocfg = dw_params >> DW_PARAMS_EN & 0x1;
1621 dev_dbg(&pdev->dev, "DW_PARAMS: 0x%08x\n", dw_params);
1623 pdata = dev_get_platdata(&pdev->dev);
1625 pdata = dw_dma_parse_dt(pdev);
1627 if (!pdata && autocfg) {
1628 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
1632 /* Fill platform data with the default values */
1633 pdata->is_private = true;
1634 pdata->chan_allocation_order = CHAN_ALLOCATION_ASCENDING;
1635 pdata->chan_priority = CHAN_PRIORITY_ASCENDING;
1636 } else if (!pdata || pdata->nr_channels > DW_DMA_MAX_NR_CHANNELS)
1640 nr_channels = (dw_params >> DW_PARAMS_NR_CHAN & 0x7) + 1;
1642 nr_channels = pdata->nr_channels;
1644 size = sizeof(struct dw_dma) + nr_channels * sizeof(struct dw_dma_chan);
1645 dw = devm_kzalloc(&pdev->dev, size, GFP_KERNEL);
1649 dw->clk = devm_clk_get(&pdev->dev, "hclk");
1650 if (IS_ERR(dw->clk))
1651 return PTR_ERR(dw->clk);
1652 clk_prepare_enable(dw->clk);
1656 dw->sd_count = pdata->sd_count;
1658 /* get hardware configuration parameters */
1660 max_blk_size = dma_readl(dw, MAX_BLK_SIZE);
1662 dw->nr_masters = (dw_params >> DW_PARAMS_NR_MASTER & 3) + 1;
1663 for (i = 0; i < dw->nr_masters; i++) {
1665 (dw_params >> DW_PARAMS_DATA_WIDTH(i) & 3) + 2;
1668 dw->nr_masters = pdata->nr_masters;
1669 memcpy(dw->data_width, pdata->data_width, 4);
1672 /* Calculate all channel mask before DMA setup */
1673 dw->all_chan_mask = (1 << nr_channels) - 1;
1675 /* force dma off, just in case */
1678 /* disable BLOCK interrupts as well */
1679 channel_clear_bit(dw, MASK.BLOCK, dw->all_chan_mask);
1681 err = devm_request_irq(&pdev->dev, irq, dw_dma_interrupt, 0,
1686 platform_set_drvdata(pdev, dw);
1688 /* create a pool of consistent memory blocks for hardware descriptors */
1689 dw->desc_pool = dmam_pool_create("dw_dmac_desc_pool", &pdev->dev,
1690 sizeof(struct dw_desc), 4, 0);
1691 if (!dw->desc_pool) {
1692 dev_err(&pdev->dev, "No memory for descriptors dma pool\n");
1696 tasklet_init(&dw->tasklet, dw_dma_tasklet, (unsigned long)dw);
1698 INIT_LIST_HEAD(&dw->dma.channels);
1699 for (i = 0; i < nr_channels; i++) {
1700 struct dw_dma_chan *dwc = &dw->chan[i];
1701 int r = nr_channels - i - 1;
1703 dwc->chan.device = &dw->dma;
1704 dma_cookie_init(&dwc->chan);
1705 if (pdata->chan_allocation_order == CHAN_ALLOCATION_ASCENDING)
1706 list_add_tail(&dwc->chan.device_node,
1709 list_add(&dwc->chan.device_node, &dw->dma.channels);
1711 /* 7 is highest priority & 0 is lowest. */
1712 if (pdata->chan_priority == CHAN_PRIORITY_ASCENDING)
1717 dwc->ch_regs = &__dw_regs(dw)->CHAN[i];
1718 spin_lock_init(&dwc->lock);
1721 INIT_LIST_HEAD(&dwc->active_list);
1722 INIT_LIST_HEAD(&dwc->queue);
1723 INIT_LIST_HEAD(&dwc->free_list);
1725 channel_clear_bit(dw, CH_EN, dwc->mask);
1727 dwc->direction = DMA_TRANS_NONE;
1729 /* hardware configuration */
1731 unsigned int dwc_params;
1733 dwc_params = dma_read_byaddr(regs + r * sizeof(u32),
1736 dev_dbg(&pdev->dev, "DWC_PARAMS[%d]: 0x%08x\n", i,
1739 /* Decode maximum block size for given channel. The
1740 * stored 4 bit value represents blocks from 0x00 for 3
1741 * up to 0x0a for 4095. */
1743 (4 << ((max_blk_size >> 4 * i) & 0xf)) - 1;
1745 (dwc_params >> DWC_PARAMS_MBLK_EN & 0x1) == 0;
1747 dwc->block_size = pdata->block_size;
1749 /* Check if channel supports multi block transfer */
1750 channel_writel(dwc, LLP, 0xfffffffc);
1752 (channel_readl(dwc, LLP) & 0xfffffffc) == 0;
1753 channel_writel(dwc, LLP, 0);
1757 /* Clear all interrupts on all channels. */
1758 dma_writel(dw, CLEAR.XFER, dw->all_chan_mask);
1759 dma_writel(dw, CLEAR.BLOCK, dw->all_chan_mask);
1760 dma_writel(dw, CLEAR.SRC_TRAN, dw->all_chan_mask);
1761 dma_writel(dw, CLEAR.DST_TRAN, dw->all_chan_mask);
1762 dma_writel(dw, CLEAR.ERROR, dw->all_chan_mask);
1764 dma_cap_set(DMA_MEMCPY, dw->dma.cap_mask);
1765 dma_cap_set(DMA_SLAVE, dw->dma.cap_mask);
1766 if (pdata->is_private)
1767 dma_cap_set(DMA_PRIVATE, dw->dma.cap_mask);
1768 dw->dma.dev = &pdev->dev;
1769 dw->dma.device_alloc_chan_resources = dwc_alloc_chan_resources;
1770 dw->dma.device_free_chan_resources = dwc_free_chan_resources;
1772 dw->dma.device_prep_dma_memcpy = dwc_prep_dma_memcpy;
1774 dw->dma.device_prep_slave_sg = dwc_prep_slave_sg;
1775 dw->dma.device_control = dwc_control;
1777 dw->dma.device_tx_status = dwc_tx_status;
1778 dw->dma.device_issue_pending = dwc_issue_pending;
1780 dma_writel(dw, CFG, DW_CFG_DMA_EN);
1782 dev_info(&pdev->dev, "DesignWare DMA Controller, %d channels\n",
1785 dma_async_device_register(&dw->dma);
1790 static int __devexit dw_remove(struct platform_device *pdev)
1792 struct dw_dma *dw = platform_get_drvdata(pdev);
1793 struct dw_dma_chan *dwc, *_dwc;
1796 dma_async_device_unregister(&dw->dma);
1798 tasklet_kill(&dw->tasklet);
1800 list_for_each_entry_safe(dwc, _dwc, &dw->dma.channels,
1802 list_del(&dwc->chan.device_node);
1803 channel_clear_bit(dw, CH_EN, dwc->mask);
1809 static void dw_shutdown(struct platform_device *pdev)
1811 struct dw_dma *dw = platform_get_drvdata(pdev);
1814 clk_disable_unprepare(dw->clk);
1817 static int dw_suspend_noirq(struct device *dev)
1819 struct platform_device *pdev = to_platform_device(dev);
1820 struct dw_dma *dw = platform_get_drvdata(pdev);
1823 clk_disable_unprepare(dw->clk);
1828 static int dw_resume_noirq(struct device *dev)
1830 struct platform_device *pdev = to_platform_device(dev);
1831 struct dw_dma *dw = platform_get_drvdata(pdev);
1833 clk_prepare_enable(dw->clk);
1834 dma_writel(dw, CFG, DW_CFG_DMA_EN);
1839 static const struct dev_pm_ops dw_dev_pm_ops = {
1840 .suspend_noirq = dw_suspend_noirq,
1841 .resume_noirq = dw_resume_noirq,
1842 .freeze_noirq = dw_suspend_noirq,
1843 .thaw_noirq = dw_resume_noirq,
1844 .restore_noirq = dw_resume_noirq,
1845 .poweroff_noirq = dw_suspend_noirq,
1849 static const struct of_device_id dw_dma_id_table[] = {
1850 { .compatible = "snps,dma-spear1340" },
1853 MODULE_DEVICE_TABLE(of, dw_dma_id_table);
1856 static struct platform_driver dw_driver = {
1858 .remove = dw_remove,
1859 .shutdown = dw_shutdown,
1862 .pm = &dw_dev_pm_ops,
1863 .of_match_table = of_match_ptr(dw_dma_id_table),
1867 static int __init dw_init(void)
1869 return platform_driver_register(&dw_driver);
1871 subsys_initcall(dw_init);
1873 static void __exit dw_exit(void)
1875 platform_driver_unregister(&dw_driver);
1877 module_exit(dw_exit);
1879 MODULE_LICENSE("GPL v2");
1880 MODULE_DESCRIPTION("Synopsys DesignWare DMA Controller driver");
1881 MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
1882 MODULE_AUTHOR("Viresh Kumar <viresh.linux@gmail.com>");