2 * Core driver for the Synopsys DesignWare DMA Controller
4 * Copyright (C) 2007-2008 Atmel Corporation
5 * Copyright (C) 2010-2011 ST Microelectronics
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
12 #include <linux/bitops.h>
13 #include <linux/clk.h>
14 #include <linux/delay.h>
15 #include <linux/dmaengine.h>
16 #include <linux/dma-mapping.h>
17 #include <linux/dmapool.h>
18 #include <linux/err.h>
19 #include <linux/init.h>
20 #include <linux/interrupt.h>
24 #include <linux/module.h>
25 #include <linux/platform_device.h>
26 #include <linux/slab.h>
28 #include "dw_dmac_regs.h"
29 #include "dmaengine.h"
32 * This supports the Synopsys "DesignWare AHB Central DMA Controller",
33 * (DW_ahb_dmac) which is used with various AMBA 2.0 systems (not all
34 * of which use ARM any more). See the "Databook" from Synopsys for
35 * information beyond what licensees probably provide.
37 * The driver has currently been tested only with the Atmel AT32AP7000,
38 * which does not support descriptor writeback.
41 static inline unsigned int dwc_get_dms(struct dw_dma_slave *slave)
43 return slave ? slave->dst_master : 0;
46 static inline unsigned int dwc_get_sms(struct dw_dma_slave *slave)
48 return slave ? slave->src_master : 1;
54 static inline unsigned int dwc_get_master(struct dma_chan *chan, int master)
56 struct dw_dma *dw = to_dw_dma(chan->device);
57 struct dw_dma_slave *dws = chan->private;
60 if (master == SRC_MASTER)
65 return min_t(unsigned int, dw->nr_masters - 1, m);
68 #define DWC_DEFAULT_CTLLO(_chan) ({ \
69 struct dw_dma_chan *_dwc = to_dw_dma_chan(_chan); \
70 struct dma_slave_config *_sconfig = &_dwc->dma_sconfig; \
71 bool _is_slave = is_slave_direction(_dwc->direction); \
72 int _dms = dwc_get_master(_chan, DST_MASTER); \
73 int _sms = dwc_get_master(_chan, SRC_MASTER); \
74 u8 _smsize = _is_slave ? _sconfig->src_maxburst : \
76 u8 _dmsize = _is_slave ? _sconfig->dst_maxburst : \
79 (DWC_CTLL_DST_MSIZE(_dmsize) \
80 | DWC_CTLL_SRC_MSIZE(_smsize) \
83 | DWC_CTLL_DMS(_dms) \
84 | DWC_CTLL_SMS(_sms)); \
88 * Number of descriptors to allocate for each channel. This should be
89 * made configurable somehow; preferably, the clients (at least the
90 * ones using slave transfers) should be able to give us a hint.
92 #define NR_DESCS_PER_CHANNEL 64
94 static inline unsigned int dwc_get_data_width(struct dma_chan *chan, int master)
96 struct dw_dma *dw = to_dw_dma(chan->device);
98 return dw->data_width[dwc_get_master(chan, master)];
101 /*----------------------------------------------------------------------*/
103 static struct device *chan2dev(struct dma_chan *chan)
105 return &chan->dev->device;
107 static struct device *chan2parent(struct dma_chan *chan)
109 return chan->dev->device.parent;
112 static struct dw_desc *dwc_first_active(struct dw_dma_chan *dwc)
114 return to_dw_desc(dwc->active_list.next);
117 static struct dw_desc *dwc_desc_get(struct dw_dma_chan *dwc)
119 struct dw_desc *desc, *_desc;
120 struct dw_desc *ret = NULL;
124 spin_lock_irqsave(&dwc->lock, flags);
125 list_for_each_entry_safe(desc, _desc, &dwc->free_list, desc_node) {
127 if (async_tx_test_ack(&desc->txd)) {
128 list_del(&desc->desc_node);
132 dev_dbg(chan2dev(&dwc->chan), "desc %p not ACKed\n", desc);
134 spin_unlock_irqrestore(&dwc->lock, flags);
136 dev_vdbg(chan2dev(&dwc->chan), "scanned %u descriptors on freelist\n", i);
142 * Move a descriptor, including any children, to the free list.
143 * `desc' must not be on any lists.
145 static void dwc_desc_put(struct dw_dma_chan *dwc, struct dw_desc *desc)
150 struct dw_desc *child;
152 spin_lock_irqsave(&dwc->lock, flags);
153 list_for_each_entry(child, &desc->tx_list, desc_node)
154 dev_vdbg(chan2dev(&dwc->chan),
155 "moving child desc %p to freelist\n",
157 list_splice_init(&desc->tx_list, &dwc->free_list);
158 dev_vdbg(chan2dev(&dwc->chan), "moving desc %p to freelist\n", desc);
159 list_add(&desc->desc_node, &dwc->free_list);
160 spin_unlock_irqrestore(&dwc->lock, flags);
164 static void dwc_initialize(struct dw_dma_chan *dwc)
166 struct dw_dma *dw = to_dw_dma(dwc->chan.device);
167 struct dw_dma_slave *dws = dwc->chan.private;
168 u32 cfghi = DWC_CFGH_FIFO_MODE;
169 u32 cfglo = DWC_CFGL_CH_PRIOR(dwc->priority);
171 if (dwc->initialized == true)
176 * We need controller-specific data to set up slave
179 BUG_ON(!dws->dma_dev || dws->dma_dev != dw->dma.dev);
182 cfglo |= dws->cfg_lo & ~DWC_CFGL_CH_PRIOR_MASK;
184 if (dwc->direction == DMA_MEM_TO_DEV)
185 cfghi = DWC_CFGH_DST_PER(dwc->dma_sconfig.slave_id);
186 else if (dwc->direction == DMA_DEV_TO_MEM)
187 cfghi = DWC_CFGH_SRC_PER(dwc->dma_sconfig.slave_id);
190 channel_writel(dwc, CFG_LO, cfglo);
191 channel_writel(dwc, CFG_HI, cfghi);
193 /* Enable interrupts */
194 channel_set_bit(dw, MASK.XFER, dwc->mask);
195 channel_set_bit(dw, MASK.ERROR, dwc->mask);
197 dwc->initialized = true;
200 /*----------------------------------------------------------------------*/
202 static inline unsigned int dwc_fast_fls(unsigned long long v)
205 * We can be a lot more clever here, but this should take care
206 * of the most common optimization.
217 static inline void dwc_dump_chan_regs(struct dw_dma_chan *dwc)
219 dev_err(chan2dev(&dwc->chan),
220 " SAR: 0x%x DAR: 0x%x LLP: 0x%x CTL: 0x%x:%08x\n",
221 channel_readl(dwc, SAR),
222 channel_readl(dwc, DAR),
223 channel_readl(dwc, LLP),
224 channel_readl(dwc, CTL_HI),
225 channel_readl(dwc, CTL_LO));
228 static inline void dwc_chan_disable(struct dw_dma *dw, struct dw_dma_chan *dwc)
230 channel_clear_bit(dw, CH_EN, dwc->mask);
231 while (dma_readl(dw, CH_EN) & dwc->mask)
235 /*----------------------------------------------------------------------*/
237 /* Perform single block transfer */
238 static inline void dwc_do_single_block(struct dw_dma_chan *dwc,
239 struct dw_desc *desc)
241 struct dw_dma *dw = to_dw_dma(dwc->chan.device);
244 /* Software emulation of LLP mode relies on interrupts to continue
245 * multi block transfer. */
246 ctllo = desc->lli.ctllo | DWC_CTLL_INT_EN;
248 channel_writel(dwc, SAR, desc->lli.sar);
249 channel_writel(dwc, DAR, desc->lli.dar);
250 channel_writel(dwc, CTL_LO, ctllo);
251 channel_writel(dwc, CTL_HI, desc->lli.ctlhi);
252 channel_set_bit(dw, CH_EN, dwc->mask);
254 /* Move pointer to next descriptor */
255 dwc->tx_node_active = dwc->tx_node_active->next;
258 /* Called with dwc->lock held and bh disabled */
259 static void dwc_dostart(struct dw_dma_chan *dwc, struct dw_desc *first)
261 struct dw_dma *dw = to_dw_dma(dwc->chan.device);
262 unsigned long was_soft_llp;
264 /* ASSERT: channel is idle */
265 if (dma_readl(dw, CH_EN) & dwc->mask) {
266 dev_err(chan2dev(&dwc->chan),
267 "BUG: Attempted to start non-idle channel\n");
268 dwc_dump_chan_regs(dwc);
270 /* The tasklet will hopefully advance the queue... */
275 was_soft_llp = test_and_set_bit(DW_DMA_IS_SOFT_LLP,
278 dev_err(chan2dev(&dwc->chan),
279 "BUG: Attempted to start new LLP transfer "
280 "inside ongoing one\n");
286 dwc->residue = first->total_len;
287 dwc->tx_node_active = &first->tx_list;
289 /* Submit first block */
290 dwc_do_single_block(dwc, first);
297 channel_writel(dwc, LLP, first->txd.phys);
298 channel_writel(dwc, CTL_LO,
299 DWC_CTLL_LLP_D_EN | DWC_CTLL_LLP_S_EN);
300 channel_writel(dwc, CTL_HI, 0);
301 channel_set_bit(dw, CH_EN, dwc->mask);
304 /*----------------------------------------------------------------------*/
307 dwc_descriptor_complete(struct dw_dma_chan *dwc, struct dw_desc *desc,
308 bool callback_required)
310 dma_async_tx_callback callback = NULL;
312 struct dma_async_tx_descriptor *txd = &desc->txd;
313 struct dw_desc *child;
316 dev_vdbg(chan2dev(&dwc->chan), "descriptor %u complete\n", txd->cookie);
318 spin_lock_irqsave(&dwc->lock, flags);
319 dma_cookie_complete(txd);
320 if (callback_required) {
321 callback = txd->callback;
322 param = txd->callback_param;
326 list_for_each_entry(child, &desc->tx_list, desc_node)
327 async_tx_ack(&child->txd);
328 async_tx_ack(&desc->txd);
330 list_splice_init(&desc->tx_list, &dwc->free_list);
331 list_move(&desc->desc_node, &dwc->free_list);
333 if (!is_slave_direction(dwc->direction)) {
334 struct device *parent = chan2parent(&dwc->chan);
335 if (!(txd->flags & DMA_COMPL_SKIP_DEST_UNMAP)) {
336 if (txd->flags & DMA_COMPL_DEST_UNMAP_SINGLE)
337 dma_unmap_single(parent, desc->lli.dar,
338 desc->total_len, DMA_FROM_DEVICE);
340 dma_unmap_page(parent, desc->lli.dar,
341 desc->total_len, DMA_FROM_DEVICE);
343 if (!(txd->flags & DMA_COMPL_SKIP_SRC_UNMAP)) {
344 if (txd->flags & DMA_COMPL_SRC_UNMAP_SINGLE)
345 dma_unmap_single(parent, desc->lli.sar,
346 desc->total_len, DMA_TO_DEVICE);
348 dma_unmap_page(parent, desc->lli.sar,
349 desc->total_len, DMA_TO_DEVICE);
353 spin_unlock_irqrestore(&dwc->lock, flags);
359 static void dwc_complete_all(struct dw_dma *dw, struct dw_dma_chan *dwc)
361 struct dw_desc *desc, *_desc;
365 spin_lock_irqsave(&dwc->lock, flags);
366 if (dma_readl(dw, CH_EN) & dwc->mask) {
367 dev_err(chan2dev(&dwc->chan),
368 "BUG: XFER bit set, but channel not idle!\n");
370 /* Try to continue after resetting the channel... */
371 dwc_chan_disable(dw, dwc);
375 * Submit queued descriptors ASAP, i.e. before we go through
376 * the completed ones.
378 list_splice_init(&dwc->active_list, &list);
379 if (!list_empty(&dwc->queue)) {
380 list_move(dwc->queue.next, &dwc->active_list);
381 dwc_dostart(dwc, dwc_first_active(dwc));
384 spin_unlock_irqrestore(&dwc->lock, flags);
386 list_for_each_entry_safe(desc, _desc, &list, desc_node)
387 dwc_descriptor_complete(dwc, desc, true);
390 /* Returns how many bytes were already received from source */
391 static inline u32 dwc_get_sent(struct dw_dma_chan *dwc)
393 u32 ctlhi = channel_readl(dwc, CTL_HI);
394 u32 ctllo = channel_readl(dwc, CTL_LO);
396 return (ctlhi & DWC_CTLH_BLOCK_TS_MASK) * (1 << (ctllo >> 4 & 7));
399 static void dwc_scan_descriptors(struct dw_dma *dw, struct dw_dma_chan *dwc)
402 struct dw_desc *desc, *_desc;
403 struct dw_desc *child;
407 spin_lock_irqsave(&dwc->lock, flags);
408 llp = channel_readl(dwc, LLP);
409 status_xfer = dma_readl(dw, RAW.XFER);
411 if (status_xfer & dwc->mask) {
412 /* Everything we've submitted is done */
413 dma_writel(dw, CLEAR.XFER, dwc->mask);
415 if (test_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags)) {
416 struct list_head *head, *active = dwc->tx_node_active;
419 * We are inside first active descriptor.
420 * Otherwise something is really wrong.
422 desc = dwc_first_active(dwc);
424 head = &desc->tx_list;
425 if (active != head) {
426 /* Update desc to reflect last sent one */
427 if (active != head->next)
428 desc = to_dw_desc(active->prev);
430 dwc->residue -= desc->len;
432 child = to_dw_desc(active);
434 /* Submit next block */
435 dwc_do_single_block(dwc, child);
437 spin_unlock_irqrestore(&dwc->lock, flags);
441 /* We are done here */
442 clear_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags);
447 spin_unlock_irqrestore(&dwc->lock, flags);
449 dwc_complete_all(dw, dwc);
453 if (list_empty(&dwc->active_list)) {
455 spin_unlock_irqrestore(&dwc->lock, flags);
459 if (test_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags)) {
460 dev_vdbg(chan2dev(&dwc->chan), "%s: soft LLP mode\n", __func__);
461 spin_unlock_irqrestore(&dwc->lock, flags);
465 dev_vdbg(chan2dev(&dwc->chan), "%s: llp=0x%llx\n", __func__,
466 (unsigned long long)llp);
468 list_for_each_entry_safe(desc, _desc, &dwc->active_list, desc_node) {
469 /* initial residue value */
470 dwc->residue = desc->total_len;
472 /* check first descriptors addr */
473 if (desc->txd.phys == llp) {
474 spin_unlock_irqrestore(&dwc->lock, flags);
478 /* check first descriptors llp */
479 if (desc->lli.llp == llp) {
480 /* This one is currently in progress */
481 dwc->residue -= dwc_get_sent(dwc);
482 spin_unlock_irqrestore(&dwc->lock, flags);
486 dwc->residue -= desc->len;
487 list_for_each_entry(child, &desc->tx_list, desc_node) {
488 if (child->lli.llp == llp) {
489 /* Currently in progress */
490 dwc->residue -= dwc_get_sent(dwc);
491 spin_unlock_irqrestore(&dwc->lock, flags);
494 dwc->residue -= child->len;
498 * No descriptors so far seem to be in progress, i.e.
499 * this one must be done.
501 spin_unlock_irqrestore(&dwc->lock, flags);
502 dwc_descriptor_complete(dwc, desc, true);
503 spin_lock_irqsave(&dwc->lock, flags);
506 dev_err(chan2dev(&dwc->chan),
507 "BUG: All descriptors done, but channel not idle!\n");
509 /* Try to continue after resetting the channel... */
510 dwc_chan_disable(dw, dwc);
512 if (!list_empty(&dwc->queue)) {
513 list_move(dwc->queue.next, &dwc->active_list);
514 dwc_dostart(dwc, dwc_first_active(dwc));
516 spin_unlock_irqrestore(&dwc->lock, flags);
519 static inline void dwc_dump_lli(struct dw_dma_chan *dwc, struct dw_lli *lli)
521 dev_crit(chan2dev(&dwc->chan), " desc: s0x%x d0x%x l0x%x c0x%x:%x\n",
522 lli->sar, lli->dar, lli->llp, lli->ctlhi, lli->ctllo);
525 static void dwc_handle_error(struct dw_dma *dw, struct dw_dma_chan *dwc)
527 struct dw_desc *bad_desc;
528 struct dw_desc *child;
531 dwc_scan_descriptors(dw, dwc);
533 spin_lock_irqsave(&dwc->lock, flags);
536 * The descriptor currently at the head of the active list is
537 * borked. Since we don't have any way to report errors, we'll
538 * just have to scream loudly and try to carry on.
540 bad_desc = dwc_first_active(dwc);
541 list_del_init(&bad_desc->desc_node);
542 list_move(dwc->queue.next, dwc->active_list.prev);
544 /* Clear the error flag and try to restart the controller */
545 dma_writel(dw, CLEAR.ERROR, dwc->mask);
546 if (!list_empty(&dwc->active_list))
547 dwc_dostart(dwc, dwc_first_active(dwc));
550 * WARN may seem harsh, but since this only happens
551 * when someone submits a bad physical address in a
552 * descriptor, we should consider ourselves lucky that the
553 * controller flagged an error instead of scribbling over
554 * random memory locations.
556 dev_WARN(chan2dev(&dwc->chan), "Bad descriptor submitted for DMA!\n"
557 " cookie: %d\n", bad_desc->txd.cookie);
558 dwc_dump_lli(dwc, &bad_desc->lli);
559 list_for_each_entry(child, &bad_desc->tx_list, desc_node)
560 dwc_dump_lli(dwc, &child->lli);
562 spin_unlock_irqrestore(&dwc->lock, flags);
564 /* Pretend the descriptor completed successfully */
565 dwc_descriptor_complete(dwc, bad_desc, true);
568 /* --------------------- Cyclic DMA API extensions -------------------- */
570 inline dma_addr_t dw_dma_get_src_addr(struct dma_chan *chan)
572 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
573 return channel_readl(dwc, SAR);
575 EXPORT_SYMBOL(dw_dma_get_src_addr);
577 inline dma_addr_t dw_dma_get_dst_addr(struct dma_chan *chan)
579 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
580 return channel_readl(dwc, DAR);
582 EXPORT_SYMBOL(dw_dma_get_dst_addr);
584 /* called with dwc->lock held and all DMAC interrupts disabled */
585 static void dwc_handle_cyclic(struct dw_dma *dw, struct dw_dma_chan *dwc,
586 u32 status_err, u32 status_xfer)
591 void (*callback)(void *param);
592 void *callback_param;
594 dev_vdbg(chan2dev(&dwc->chan), "new cyclic period llp 0x%08x\n",
595 channel_readl(dwc, LLP));
597 callback = dwc->cdesc->period_callback;
598 callback_param = dwc->cdesc->period_callback_param;
601 callback(callback_param);
605 * Error and transfer complete are highly unlikely, and will most
606 * likely be due to a configuration error by the user.
608 if (unlikely(status_err & dwc->mask) ||
609 unlikely(status_xfer & dwc->mask)) {
612 dev_err(chan2dev(&dwc->chan), "cyclic DMA unexpected %s "
613 "interrupt, stopping DMA transfer\n",
614 status_xfer ? "xfer" : "error");
616 spin_lock_irqsave(&dwc->lock, flags);
618 dwc_dump_chan_regs(dwc);
620 dwc_chan_disable(dw, dwc);
622 /* make sure DMA does not restart by loading a new list */
623 channel_writel(dwc, LLP, 0);
624 channel_writel(dwc, CTL_LO, 0);
625 channel_writel(dwc, CTL_HI, 0);
627 dma_writel(dw, CLEAR.ERROR, dwc->mask);
628 dma_writel(dw, CLEAR.XFER, dwc->mask);
630 for (i = 0; i < dwc->cdesc->periods; i++)
631 dwc_dump_lli(dwc, &dwc->cdesc->desc[i]->lli);
633 spin_unlock_irqrestore(&dwc->lock, flags);
637 /* ------------------------------------------------------------------------- */
639 static void dw_dma_tasklet(unsigned long data)
641 struct dw_dma *dw = (struct dw_dma *)data;
642 struct dw_dma_chan *dwc;
647 status_xfer = dma_readl(dw, RAW.XFER);
648 status_err = dma_readl(dw, RAW.ERROR);
650 dev_vdbg(dw->dma.dev, "%s: status_err=%x\n", __func__, status_err);
652 for (i = 0; i < dw->dma.chancnt; i++) {
654 if (test_bit(DW_DMA_IS_CYCLIC, &dwc->flags))
655 dwc_handle_cyclic(dw, dwc, status_err, status_xfer);
656 else if (status_err & (1 << i))
657 dwc_handle_error(dw, dwc);
658 else if (status_xfer & (1 << i))
659 dwc_scan_descriptors(dw, dwc);
663 * Re-enable interrupts.
665 channel_set_bit(dw, MASK.XFER, dw->all_chan_mask);
666 channel_set_bit(dw, MASK.ERROR, dw->all_chan_mask);
669 static irqreturn_t dw_dma_interrupt(int irq, void *dev_id)
671 struct dw_dma *dw = dev_id;
674 dev_vdbg(dw->dma.dev, "%s: status=0x%x\n", __func__,
675 dma_readl(dw, STATUS_INT));
678 * Just disable the interrupts. We'll turn them back on in the
681 channel_clear_bit(dw, MASK.XFER, dw->all_chan_mask);
682 channel_clear_bit(dw, MASK.ERROR, dw->all_chan_mask);
684 status = dma_readl(dw, STATUS_INT);
687 "BUG: Unexpected interrupts pending: 0x%x\n",
691 channel_clear_bit(dw, MASK.XFER, (1 << 8) - 1);
692 channel_clear_bit(dw, MASK.SRC_TRAN, (1 << 8) - 1);
693 channel_clear_bit(dw, MASK.DST_TRAN, (1 << 8) - 1);
694 channel_clear_bit(dw, MASK.ERROR, (1 << 8) - 1);
697 tasklet_schedule(&dw->tasklet);
702 /*----------------------------------------------------------------------*/
704 static dma_cookie_t dwc_tx_submit(struct dma_async_tx_descriptor *tx)
706 struct dw_desc *desc = txd_to_dw_desc(tx);
707 struct dw_dma_chan *dwc = to_dw_dma_chan(tx->chan);
711 spin_lock_irqsave(&dwc->lock, flags);
712 cookie = dma_cookie_assign(tx);
715 * REVISIT: We should attempt to chain as many descriptors as
716 * possible, perhaps even appending to those already submitted
717 * for DMA. But this is hard to do in a race-free manner.
719 if (list_empty(&dwc->active_list)) {
720 dev_vdbg(chan2dev(tx->chan), "%s: started %u\n", __func__,
722 list_add_tail(&desc->desc_node, &dwc->active_list);
723 dwc_dostart(dwc, dwc_first_active(dwc));
725 dev_vdbg(chan2dev(tx->chan), "%s: queued %u\n", __func__,
728 list_add_tail(&desc->desc_node, &dwc->queue);
731 spin_unlock_irqrestore(&dwc->lock, flags);
736 static struct dma_async_tx_descriptor *
737 dwc_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
738 size_t len, unsigned long flags)
740 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
741 struct dw_desc *desc;
742 struct dw_desc *first;
743 struct dw_desc *prev;
746 unsigned int src_width;
747 unsigned int dst_width;
748 unsigned int data_width;
751 dev_vdbg(chan2dev(chan),
752 "%s: d0x%llx s0x%llx l0x%zx f0x%lx\n", __func__,
753 (unsigned long long)dest, (unsigned long long)src,
756 if (unlikely(!len)) {
757 dev_dbg(chan2dev(chan), "%s: length is zero!\n", __func__);
761 dwc->direction = DMA_MEM_TO_MEM;
763 data_width = min_t(unsigned int, dwc_get_data_width(chan, SRC_MASTER),
764 dwc_get_data_width(chan, DST_MASTER));
766 src_width = dst_width = min_t(unsigned int, data_width,
767 dwc_fast_fls(src | dest | len));
769 ctllo = DWC_DEFAULT_CTLLO(chan)
770 | DWC_CTLL_DST_WIDTH(dst_width)
771 | DWC_CTLL_SRC_WIDTH(src_width)
777 for (offset = 0; offset < len; offset += xfer_count << src_width) {
778 xfer_count = min_t(size_t, (len - offset) >> src_width,
781 desc = dwc_desc_get(dwc);
785 desc->lli.sar = src + offset;
786 desc->lli.dar = dest + offset;
787 desc->lli.ctllo = ctllo;
788 desc->lli.ctlhi = xfer_count;
789 desc->len = xfer_count << src_width;
794 prev->lli.llp = desc->txd.phys;
795 list_add_tail(&desc->desc_node,
801 if (flags & DMA_PREP_INTERRUPT)
802 /* Trigger interrupt after last block */
803 prev->lli.ctllo |= DWC_CTLL_INT_EN;
806 first->txd.flags = flags;
807 first->total_len = len;
812 dwc_desc_put(dwc, first);
816 static struct dma_async_tx_descriptor *
817 dwc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
818 unsigned int sg_len, enum dma_transfer_direction direction,
819 unsigned long flags, void *context)
821 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
822 struct dma_slave_config *sconfig = &dwc->dma_sconfig;
823 struct dw_desc *prev;
824 struct dw_desc *first;
827 unsigned int reg_width;
828 unsigned int mem_width;
829 unsigned int data_width;
831 struct scatterlist *sg;
832 size_t total_len = 0;
834 dev_vdbg(chan2dev(chan), "%s\n", __func__);
836 if (unlikely(!is_slave_direction(direction) || !sg_len))
839 dwc->direction = direction;
845 reg_width = __fls(sconfig->dst_addr_width);
846 reg = sconfig->dst_addr;
847 ctllo = (DWC_DEFAULT_CTLLO(chan)
848 | DWC_CTLL_DST_WIDTH(reg_width)
852 ctllo |= sconfig->device_fc ? DWC_CTLL_FC(DW_DMA_FC_P_M2P) :
853 DWC_CTLL_FC(DW_DMA_FC_D_M2P);
855 data_width = dwc_get_data_width(chan, SRC_MASTER);
857 for_each_sg(sgl, sg, sg_len, i) {
858 struct dw_desc *desc;
861 mem = sg_dma_address(sg);
862 len = sg_dma_len(sg);
864 mem_width = min_t(unsigned int,
865 data_width, dwc_fast_fls(mem | len));
867 slave_sg_todev_fill_desc:
868 desc = dwc_desc_get(dwc);
870 dev_err(chan2dev(chan),
871 "not enough descriptors available\n");
877 desc->lli.ctllo = ctllo | DWC_CTLL_SRC_WIDTH(mem_width);
878 if ((len >> mem_width) > dwc->block_size) {
879 dlen = dwc->block_size << mem_width;
887 desc->lli.ctlhi = dlen >> mem_width;
893 prev->lli.llp = desc->txd.phys;
894 list_add_tail(&desc->desc_node,
901 goto slave_sg_todev_fill_desc;
905 reg_width = __fls(sconfig->src_addr_width);
906 reg = sconfig->src_addr;
907 ctllo = (DWC_DEFAULT_CTLLO(chan)
908 | DWC_CTLL_SRC_WIDTH(reg_width)
912 ctllo |= sconfig->device_fc ? DWC_CTLL_FC(DW_DMA_FC_P_P2M) :
913 DWC_CTLL_FC(DW_DMA_FC_D_P2M);
915 data_width = dwc_get_data_width(chan, DST_MASTER);
917 for_each_sg(sgl, sg, sg_len, i) {
918 struct dw_desc *desc;
921 mem = sg_dma_address(sg);
922 len = sg_dma_len(sg);
924 mem_width = min_t(unsigned int,
925 data_width, dwc_fast_fls(mem | len));
927 slave_sg_fromdev_fill_desc:
928 desc = dwc_desc_get(dwc);
930 dev_err(chan2dev(chan),
931 "not enough descriptors available\n");
937 desc->lli.ctllo = ctllo | DWC_CTLL_DST_WIDTH(mem_width);
938 if ((len >> reg_width) > dwc->block_size) {
939 dlen = dwc->block_size << reg_width;
946 desc->lli.ctlhi = dlen >> reg_width;
952 prev->lli.llp = desc->txd.phys;
953 list_add_tail(&desc->desc_node,
960 goto slave_sg_fromdev_fill_desc;
967 if (flags & DMA_PREP_INTERRUPT)
968 /* Trigger interrupt after last block */
969 prev->lli.ctllo |= DWC_CTLL_INT_EN;
972 first->total_len = total_len;
977 dwc_desc_put(dwc, first);
982 * Fix sconfig's burst size according to dw_dmac. We need to convert them as:
983 * 1 -> 0, 4 -> 1, 8 -> 2, 16 -> 3.
985 * NOTE: burst size 2 is not supported by controller.
987 * This can be done by finding least significant bit set: n & (n - 1)
989 static inline void convert_burst(u32 *maxburst)
992 *maxburst = fls(*maxburst) - 2;
998 set_runtime_config(struct dma_chan *chan, struct dma_slave_config *sconfig)
1000 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
1002 /* Check if chan will be configured for slave transfers */
1003 if (!is_slave_direction(sconfig->direction))
1006 memcpy(&dwc->dma_sconfig, sconfig, sizeof(*sconfig));
1007 dwc->direction = sconfig->direction;
1009 convert_burst(&dwc->dma_sconfig.src_maxburst);
1010 convert_burst(&dwc->dma_sconfig.dst_maxburst);
1015 static inline void dwc_chan_pause(struct dw_dma_chan *dwc)
1017 u32 cfglo = channel_readl(dwc, CFG_LO);
1019 channel_writel(dwc, CFG_LO, cfglo | DWC_CFGL_CH_SUSP);
1020 while (!(channel_readl(dwc, CFG_LO) & DWC_CFGL_FIFO_EMPTY))
1026 static inline void dwc_chan_resume(struct dw_dma_chan *dwc)
1028 u32 cfglo = channel_readl(dwc, CFG_LO);
1030 channel_writel(dwc, CFG_LO, cfglo & ~DWC_CFGL_CH_SUSP);
1032 dwc->paused = false;
1035 static int dwc_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
1038 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
1039 struct dw_dma *dw = to_dw_dma(chan->device);
1040 struct dw_desc *desc, *_desc;
1041 unsigned long flags;
1044 if (cmd == DMA_PAUSE) {
1045 spin_lock_irqsave(&dwc->lock, flags);
1047 dwc_chan_pause(dwc);
1049 spin_unlock_irqrestore(&dwc->lock, flags);
1050 } else if (cmd == DMA_RESUME) {
1054 spin_lock_irqsave(&dwc->lock, flags);
1056 dwc_chan_resume(dwc);
1058 spin_unlock_irqrestore(&dwc->lock, flags);
1059 } else if (cmd == DMA_TERMINATE_ALL) {
1060 spin_lock_irqsave(&dwc->lock, flags);
1062 clear_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags);
1064 dwc_chan_disable(dw, dwc);
1066 dwc_chan_resume(dwc);
1068 /* active_list entries will end up before queued entries */
1069 list_splice_init(&dwc->queue, &list);
1070 list_splice_init(&dwc->active_list, &list);
1072 spin_unlock_irqrestore(&dwc->lock, flags);
1074 /* Flush all pending and queued descriptors */
1075 list_for_each_entry_safe(desc, _desc, &list, desc_node)
1076 dwc_descriptor_complete(dwc, desc, false);
1077 } else if (cmd == DMA_SLAVE_CONFIG) {
1078 return set_runtime_config(chan, (struct dma_slave_config *)arg);
1086 static inline u32 dwc_get_residue(struct dw_dma_chan *dwc)
1088 unsigned long flags;
1091 spin_lock_irqsave(&dwc->lock, flags);
1093 residue = dwc->residue;
1094 if (test_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags) && residue)
1095 residue -= dwc_get_sent(dwc);
1097 spin_unlock_irqrestore(&dwc->lock, flags);
1101 static enum dma_status
1102 dwc_tx_status(struct dma_chan *chan,
1103 dma_cookie_t cookie,
1104 struct dma_tx_state *txstate)
1106 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
1107 enum dma_status ret;
1109 ret = dma_cookie_status(chan, cookie, txstate);
1110 if (ret != DMA_SUCCESS) {
1111 dwc_scan_descriptors(to_dw_dma(chan->device), dwc);
1113 ret = dma_cookie_status(chan, cookie, txstate);
1116 if (ret != DMA_SUCCESS)
1117 dma_set_residue(txstate, dwc_get_residue(dwc));
1125 static void dwc_issue_pending(struct dma_chan *chan)
1127 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
1129 if (!list_empty(&dwc->queue))
1130 dwc_scan_descriptors(to_dw_dma(chan->device), dwc);
1133 static int dwc_alloc_chan_resources(struct dma_chan *chan)
1135 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
1136 struct dw_dma *dw = to_dw_dma(chan->device);
1137 struct dw_desc *desc;
1139 unsigned long flags;
1141 dev_vdbg(chan2dev(chan), "%s\n", __func__);
1143 /* ASSERT: channel is idle */
1144 if (dma_readl(dw, CH_EN) & dwc->mask) {
1145 dev_dbg(chan2dev(chan), "DMA channel not idle?\n");
1149 dma_cookie_init(chan);
1152 * NOTE: some controllers may have additional features that we
1153 * need to initialize here, like "scatter-gather" (which
1154 * doesn't mean what you think it means), and status writeback.
1157 spin_lock_irqsave(&dwc->lock, flags);
1158 i = dwc->descs_allocated;
1159 while (dwc->descs_allocated < NR_DESCS_PER_CHANNEL) {
1162 spin_unlock_irqrestore(&dwc->lock, flags);
1164 desc = dma_pool_alloc(dw->desc_pool, GFP_ATOMIC, &phys);
1166 goto err_desc_alloc;
1168 memset(desc, 0, sizeof(struct dw_desc));
1170 INIT_LIST_HEAD(&desc->tx_list);
1171 dma_async_tx_descriptor_init(&desc->txd, chan);
1172 desc->txd.tx_submit = dwc_tx_submit;
1173 desc->txd.flags = DMA_CTRL_ACK;
1174 desc->txd.phys = phys;
1176 dwc_desc_put(dwc, desc);
1178 spin_lock_irqsave(&dwc->lock, flags);
1179 i = ++dwc->descs_allocated;
1182 spin_unlock_irqrestore(&dwc->lock, flags);
1184 dev_dbg(chan2dev(chan), "%s: allocated %d descriptors\n", __func__, i);
1189 dev_info(chan2dev(chan), "only allocated %d descriptors\n", i);
1194 static void dwc_free_chan_resources(struct dma_chan *chan)
1196 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
1197 struct dw_dma *dw = to_dw_dma(chan->device);
1198 struct dw_desc *desc, *_desc;
1199 unsigned long flags;
1202 dev_dbg(chan2dev(chan), "%s: descs allocated=%u\n", __func__,
1203 dwc->descs_allocated);
1205 /* ASSERT: channel is idle */
1206 BUG_ON(!list_empty(&dwc->active_list));
1207 BUG_ON(!list_empty(&dwc->queue));
1208 BUG_ON(dma_readl(to_dw_dma(chan->device), CH_EN) & dwc->mask);
1210 spin_lock_irqsave(&dwc->lock, flags);
1211 list_splice_init(&dwc->free_list, &list);
1212 dwc->descs_allocated = 0;
1213 dwc->initialized = false;
1215 /* Disable interrupts */
1216 channel_clear_bit(dw, MASK.XFER, dwc->mask);
1217 channel_clear_bit(dw, MASK.ERROR, dwc->mask);
1219 spin_unlock_irqrestore(&dwc->lock, flags);
1221 list_for_each_entry_safe(desc, _desc, &list, desc_node) {
1222 dev_vdbg(chan2dev(chan), " freeing descriptor %p\n", desc);
1223 dma_pool_free(dw->desc_pool, desc, desc->txd.phys);
1226 dev_vdbg(chan2dev(chan), "%s: done\n", __func__);
1229 bool dw_dma_generic_filter(struct dma_chan *chan, void *param)
1231 struct dw_dma *dw = to_dw_dma(chan->device);
1232 static struct dw_dma *last_dw;
1233 static char *last_bus_id;
1237 * dmaengine framework calls this routine for all channels of all dma
1238 * controller, until true is returned. If 'param' bus_id is not
1239 * registered with a dma controller (dw), then there is no need of
1240 * running below function for all channels of dw.
1242 * This block of code does this by saving the parameters of last
1243 * failure. If dw and param are same, i.e. trying on same dw with
1244 * different channel, return false.
1246 if ((last_dw == dw) && (last_bus_id == param))
1250 * - If dw_dma's platform data is not filled with slave info, then all
1251 * dma controllers are fine for transfer.
1252 * - Or if param is NULL
1254 if (!dw->sd || !param)
1257 while (++i < dw->sd_count) {
1258 if (!strcmp(dw->sd[i].bus_id, param)) {
1259 chan->private = &dw->sd[i];
1268 last_bus_id = param;
1271 EXPORT_SYMBOL(dw_dma_generic_filter);
1273 /* --------------------- Cyclic DMA API extensions -------------------- */
1276 * dw_dma_cyclic_start - start the cyclic DMA transfer
1277 * @chan: the DMA channel to start
1279 * Must be called with soft interrupts disabled. Returns zero on success or
1280 * -errno on failure.
1282 int dw_dma_cyclic_start(struct dma_chan *chan)
1284 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
1285 struct dw_dma *dw = to_dw_dma(dwc->chan.device);
1286 unsigned long flags;
1288 if (!test_bit(DW_DMA_IS_CYCLIC, &dwc->flags)) {
1289 dev_err(chan2dev(&dwc->chan), "missing prep for cyclic DMA\n");
1293 spin_lock_irqsave(&dwc->lock, flags);
1295 /* assert channel is idle */
1296 if (dma_readl(dw, CH_EN) & dwc->mask) {
1297 dev_err(chan2dev(&dwc->chan),
1298 "BUG: Attempted to start non-idle channel\n");
1299 dwc_dump_chan_regs(dwc);
1300 spin_unlock_irqrestore(&dwc->lock, flags);
1304 dma_writel(dw, CLEAR.ERROR, dwc->mask);
1305 dma_writel(dw, CLEAR.XFER, dwc->mask);
1307 /* setup DMAC channel registers */
1308 channel_writel(dwc, LLP, dwc->cdesc->desc[0]->txd.phys);
1309 channel_writel(dwc, CTL_LO, DWC_CTLL_LLP_D_EN | DWC_CTLL_LLP_S_EN);
1310 channel_writel(dwc, CTL_HI, 0);
1312 channel_set_bit(dw, CH_EN, dwc->mask);
1314 spin_unlock_irqrestore(&dwc->lock, flags);
1318 EXPORT_SYMBOL(dw_dma_cyclic_start);
1321 * dw_dma_cyclic_stop - stop the cyclic DMA transfer
1322 * @chan: the DMA channel to stop
1324 * Must be called with soft interrupts disabled.
1326 void dw_dma_cyclic_stop(struct dma_chan *chan)
1328 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
1329 struct dw_dma *dw = to_dw_dma(dwc->chan.device);
1330 unsigned long flags;
1332 spin_lock_irqsave(&dwc->lock, flags);
1334 dwc_chan_disable(dw, dwc);
1336 spin_unlock_irqrestore(&dwc->lock, flags);
1338 EXPORT_SYMBOL(dw_dma_cyclic_stop);
1341 * dw_dma_cyclic_prep - prepare the cyclic DMA transfer
1342 * @chan: the DMA channel to prepare
1343 * @buf_addr: physical DMA address where the buffer starts
1344 * @buf_len: total number of bytes for the entire buffer
1345 * @period_len: number of bytes for each period
1346 * @direction: transfer direction, to or from device
1348 * Must be called before trying to start the transfer. Returns a valid struct
1349 * dw_cyclic_desc if successful or an ERR_PTR(-errno) if not successful.
1351 struct dw_cyclic_desc *dw_dma_cyclic_prep(struct dma_chan *chan,
1352 dma_addr_t buf_addr, size_t buf_len, size_t period_len,
1353 enum dma_transfer_direction direction)
1355 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
1356 struct dma_slave_config *sconfig = &dwc->dma_sconfig;
1357 struct dw_cyclic_desc *cdesc;
1358 struct dw_cyclic_desc *retval = NULL;
1359 struct dw_desc *desc;
1360 struct dw_desc *last = NULL;
1361 unsigned long was_cyclic;
1362 unsigned int reg_width;
1363 unsigned int periods;
1365 unsigned long flags;
1367 spin_lock_irqsave(&dwc->lock, flags);
1369 spin_unlock_irqrestore(&dwc->lock, flags);
1370 dev_dbg(chan2dev(&dwc->chan),
1371 "channel doesn't support LLP transfers\n");
1372 return ERR_PTR(-EINVAL);
1375 if (!list_empty(&dwc->queue) || !list_empty(&dwc->active_list)) {
1376 spin_unlock_irqrestore(&dwc->lock, flags);
1377 dev_dbg(chan2dev(&dwc->chan),
1378 "queue and/or active list are not empty\n");
1379 return ERR_PTR(-EBUSY);
1382 was_cyclic = test_and_set_bit(DW_DMA_IS_CYCLIC, &dwc->flags);
1383 spin_unlock_irqrestore(&dwc->lock, flags);
1385 dev_dbg(chan2dev(&dwc->chan),
1386 "channel already prepared for cyclic DMA\n");
1387 return ERR_PTR(-EBUSY);
1390 retval = ERR_PTR(-EINVAL);
1392 if (unlikely(!is_slave_direction(direction)))
1395 dwc->direction = direction;
1397 if (direction == DMA_MEM_TO_DEV)
1398 reg_width = __ffs(sconfig->dst_addr_width);
1400 reg_width = __ffs(sconfig->src_addr_width);
1402 periods = buf_len / period_len;
1404 /* Check for too big/unaligned periods and unaligned DMA buffer. */
1405 if (period_len > (dwc->block_size << reg_width))
1407 if (unlikely(period_len & ((1 << reg_width) - 1)))
1409 if (unlikely(buf_addr & ((1 << reg_width) - 1)))
1412 retval = ERR_PTR(-ENOMEM);
1414 if (periods > NR_DESCS_PER_CHANNEL)
1417 cdesc = kzalloc(sizeof(struct dw_cyclic_desc), GFP_KERNEL);
1421 cdesc->desc = kzalloc(sizeof(struct dw_desc *) * periods, GFP_KERNEL);
1425 for (i = 0; i < periods; i++) {
1426 desc = dwc_desc_get(dwc);
1428 goto out_err_desc_get;
1430 switch (direction) {
1431 case DMA_MEM_TO_DEV:
1432 desc->lli.dar = sconfig->dst_addr;
1433 desc->lli.sar = buf_addr + (period_len * i);
1434 desc->lli.ctllo = (DWC_DEFAULT_CTLLO(chan)
1435 | DWC_CTLL_DST_WIDTH(reg_width)
1436 | DWC_CTLL_SRC_WIDTH(reg_width)
1441 desc->lli.ctllo |= sconfig->device_fc ?
1442 DWC_CTLL_FC(DW_DMA_FC_P_M2P) :
1443 DWC_CTLL_FC(DW_DMA_FC_D_M2P);
1446 case DMA_DEV_TO_MEM:
1447 desc->lli.dar = buf_addr + (period_len * i);
1448 desc->lli.sar = sconfig->src_addr;
1449 desc->lli.ctllo = (DWC_DEFAULT_CTLLO(chan)
1450 | DWC_CTLL_SRC_WIDTH(reg_width)
1451 | DWC_CTLL_DST_WIDTH(reg_width)
1456 desc->lli.ctllo |= sconfig->device_fc ?
1457 DWC_CTLL_FC(DW_DMA_FC_P_P2M) :
1458 DWC_CTLL_FC(DW_DMA_FC_D_P2M);
1465 desc->lli.ctlhi = (period_len >> reg_width);
1466 cdesc->desc[i] = desc;
1469 last->lli.llp = desc->txd.phys;
1474 /* lets make a cyclic list */
1475 last->lli.llp = cdesc->desc[0]->txd.phys;
1477 dev_dbg(chan2dev(&dwc->chan), "cyclic prepared buf 0x%llx len %zu "
1478 "period %zu periods %d\n", (unsigned long long)buf_addr,
1479 buf_len, period_len, periods);
1481 cdesc->periods = periods;
1488 dwc_desc_put(dwc, cdesc->desc[i]);
1492 clear_bit(DW_DMA_IS_CYCLIC, &dwc->flags);
1493 return (struct dw_cyclic_desc *)retval;
1495 EXPORT_SYMBOL(dw_dma_cyclic_prep);
1498 * dw_dma_cyclic_free - free a prepared cyclic DMA transfer
1499 * @chan: the DMA channel to free
1501 void dw_dma_cyclic_free(struct dma_chan *chan)
1503 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
1504 struct dw_dma *dw = to_dw_dma(dwc->chan.device);
1505 struct dw_cyclic_desc *cdesc = dwc->cdesc;
1507 unsigned long flags;
1509 dev_dbg(chan2dev(&dwc->chan), "%s\n", __func__);
1514 spin_lock_irqsave(&dwc->lock, flags);
1516 dwc_chan_disable(dw, dwc);
1518 dma_writel(dw, CLEAR.ERROR, dwc->mask);
1519 dma_writel(dw, CLEAR.XFER, dwc->mask);
1521 spin_unlock_irqrestore(&dwc->lock, flags);
1523 for (i = 0; i < cdesc->periods; i++)
1524 dwc_desc_put(dwc, cdesc->desc[i]);
1529 clear_bit(DW_DMA_IS_CYCLIC, &dwc->flags);
1531 EXPORT_SYMBOL(dw_dma_cyclic_free);
1533 /*----------------------------------------------------------------------*/
1535 static void dw_dma_off(struct dw_dma *dw)
1539 dma_writel(dw, CFG, 0);
1541 channel_clear_bit(dw, MASK.XFER, dw->all_chan_mask);
1542 channel_clear_bit(dw, MASK.SRC_TRAN, dw->all_chan_mask);
1543 channel_clear_bit(dw, MASK.DST_TRAN, dw->all_chan_mask);
1544 channel_clear_bit(dw, MASK.ERROR, dw->all_chan_mask);
1546 while (dma_readl(dw, CFG) & DW_CFG_DMA_EN)
1549 for (i = 0; i < dw->dma.chancnt; i++)
1550 dw->chan[i].initialized = false;
1554 static struct dw_dma_platform_data *
1555 dw_dma_parse_dt(struct platform_device *pdev)
1557 struct device_node *sn, *cn, *np = pdev->dev.of_node;
1558 struct dw_dma_platform_data *pdata;
1559 struct dw_dma_slave *sd;
1563 dev_err(&pdev->dev, "Missing DT data\n");
1567 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
1571 if (of_property_read_u32(np, "nr_channels", &pdata->nr_channels))
1574 if (of_property_read_bool(np, "is_private"))
1575 pdata->is_private = true;
1577 if (!of_property_read_u32(np, "chan_allocation_order", &tmp))
1578 pdata->chan_allocation_order = (unsigned char)tmp;
1580 if (!of_property_read_u32(np, "chan_priority", &tmp))
1581 pdata->chan_priority = tmp;
1583 if (!of_property_read_u32(np, "block_size", &tmp))
1584 pdata->block_size = tmp;
1586 if (!of_property_read_u32(np, "nr_masters", &tmp)) {
1590 pdata->nr_masters = tmp;
1593 if (!of_property_read_u32_array(np, "data_width", arr,
1595 for (tmp = 0; tmp < pdata->nr_masters; tmp++)
1596 pdata->data_width[tmp] = arr[tmp];
1598 /* parse slave data */
1599 sn = of_find_node_by_name(np, "slave_info");
1603 /* calculate number of slaves */
1604 tmp = of_get_child_count(sn);
1608 sd = devm_kzalloc(&pdev->dev, sizeof(*sd) * tmp, GFP_KERNEL);
1613 pdata->sd_count = tmp;
1615 for_each_child_of_node(sn, cn) {
1616 sd->dma_dev = &pdev->dev;
1617 of_property_read_string(cn, "bus_id", &sd->bus_id);
1618 of_property_read_u32(cn, "cfg_hi", &sd->cfg_hi);
1619 of_property_read_u32(cn, "cfg_lo", &sd->cfg_lo);
1620 if (!of_property_read_u32(cn, "src_master", &tmp))
1621 sd->src_master = tmp;
1623 if (!of_property_read_u32(cn, "dst_master", &tmp))
1624 sd->dst_master = tmp;
1631 static inline struct dw_dma_platform_data *
1632 dw_dma_parse_dt(struct platform_device *pdev)
1638 static int dw_probe(struct platform_device *pdev)
1640 struct dw_dma_platform_data *pdata;
1641 struct resource *io;
1646 unsigned int dw_params;
1647 unsigned int nr_channels;
1648 unsigned int max_blk_size = 0;
1653 io = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1657 irq = platform_get_irq(pdev, 0);
1661 regs = devm_ioremap_resource(&pdev->dev, io);
1663 return PTR_ERR(regs);
1665 /* Apply default dma_mask if needed */
1666 if (!pdev->dev.dma_mask) {
1667 pdev->dev.dma_mask = &pdev->dev.coherent_dma_mask;
1668 pdev->dev.coherent_dma_mask = DMA_BIT_MASK(32);
1671 dw_params = dma_read_byaddr(regs, DW_PARAMS);
1672 autocfg = dw_params >> DW_PARAMS_EN & 0x1;
1674 dev_dbg(&pdev->dev, "DW_PARAMS: 0x%08x\n", dw_params);
1676 pdata = dev_get_platdata(&pdev->dev);
1678 pdata = dw_dma_parse_dt(pdev);
1680 if (!pdata && autocfg) {
1681 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
1685 /* Fill platform data with the default values */
1686 pdata->is_private = true;
1687 pdata->chan_allocation_order = CHAN_ALLOCATION_ASCENDING;
1688 pdata->chan_priority = CHAN_PRIORITY_ASCENDING;
1689 } else if (!pdata || pdata->nr_channels > DW_DMA_MAX_NR_CHANNELS)
1693 nr_channels = (dw_params >> DW_PARAMS_NR_CHAN & 0x7) + 1;
1695 nr_channels = pdata->nr_channels;
1697 size = sizeof(struct dw_dma) + nr_channels * sizeof(struct dw_dma_chan);
1698 dw = devm_kzalloc(&pdev->dev, size, GFP_KERNEL);
1702 dw->clk = devm_clk_get(&pdev->dev, "hclk");
1703 if (IS_ERR(dw->clk))
1704 return PTR_ERR(dw->clk);
1705 clk_prepare_enable(dw->clk);
1709 dw->sd_count = pdata->sd_count;
1711 /* get hardware configuration parameters */
1713 max_blk_size = dma_readl(dw, MAX_BLK_SIZE);
1715 dw->nr_masters = (dw_params >> DW_PARAMS_NR_MASTER & 3) + 1;
1716 for (i = 0; i < dw->nr_masters; i++) {
1718 (dw_params >> DW_PARAMS_DATA_WIDTH(i) & 3) + 2;
1721 dw->nr_masters = pdata->nr_masters;
1722 memcpy(dw->data_width, pdata->data_width, 4);
1725 /* Calculate all channel mask before DMA setup */
1726 dw->all_chan_mask = (1 << nr_channels) - 1;
1728 /* force dma off, just in case */
1731 /* disable BLOCK interrupts as well */
1732 channel_clear_bit(dw, MASK.BLOCK, dw->all_chan_mask);
1734 err = devm_request_irq(&pdev->dev, irq, dw_dma_interrupt, 0,
1739 platform_set_drvdata(pdev, dw);
1741 /* create a pool of consistent memory blocks for hardware descriptors */
1742 dw->desc_pool = dmam_pool_create("dw_dmac_desc_pool", &pdev->dev,
1743 sizeof(struct dw_desc), 4, 0);
1744 if (!dw->desc_pool) {
1745 dev_err(&pdev->dev, "No memory for descriptors dma pool\n");
1749 tasklet_init(&dw->tasklet, dw_dma_tasklet, (unsigned long)dw);
1751 INIT_LIST_HEAD(&dw->dma.channels);
1752 for (i = 0; i < nr_channels; i++) {
1753 struct dw_dma_chan *dwc = &dw->chan[i];
1754 int r = nr_channels - i - 1;
1756 dwc->chan.device = &dw->dma;
1757 dma_cookie_init(&dwc->chan);
1758 if (pdata->chan_allocation_order == CHAN_ALLOCATION_ASCENDING)
1759 list_add_tail(&dwc->chan.device_node,
1762 list_add(&dwc->chan.device_node, &dw->dma.channels);
1764 /* 7 is highest priority & 0 is lowest. */
1765 if (pdata->chan_priority == CHAN_PRIORITY_ASCENDING)
1770 dwc->ch_regs = &__dw_regs(dw)->CHAN[i];
1771 spin_lock_init(&dwc->lock);
1774 INIT_LIST_HEAD(&dwc->active_list);
1775 INIT_LIST_HEAD(&dwc->queue);
1776 INIT_LIST_HEAD(&dwc->free_list);
1778 channel_clear_bit(dw, CH_EN, dwc->mask);
1780 dwc->direction = DMA_TRANS_NONE;
1782 /* hardware configuration */
1784 unsigned int dwc_params;
1786 dwc_params = dma_read_byaddr(regs + r * sizeof(u32),
1789 dev_dbg(&pdev->dev, "DWC_PARAMS[%d]: 0x%08x\n", i,
1792 /* Decode maximum block size for given channel. The
1793 * stored 4 bit value represents blocks from 0x00 for 3
1794 * up to 0x0a for 4095. */
1796 (4 << ((max_blk_size >> 4 * i) & 0xf)) - 1;
1798 (dwc_params >> DWC_PARAMS_MBLK_EN & 0x1) == 0;
1800 dwc->block_size = pdata->block_size;
1802 /* Check if channel supports multi block transfer */
1803 channel_writel(dwc, LLP, 0xfffffffc);
1805 (channel_readl(dwc, LLP) & 0xfffffffc) == 0;
1806 channel_writel(dwc, LLP, 0);
1810 /* Clear all interrupts on all channels. */
1811 dma_writel(dw, CLEAR.XFER, dw->all_chan_mask);
1812 dma_writel(dw, CLEAR.BLOCK, dw->all_chan_mask);
1813 dma_writel(dw, CLEAR.SRC_TRAN, dw->all_chan_mask);
1814 dma_writel(dw, CLEAR.DST_TRAN, dw->all_chan_mask);
1815 dma_writel(dw, CLEAR.ERROR, dw->all_chan_mask);
1817 dma_cap_set(DMA_MEMCPY, dw->dma.cap_mask);
1818 dma_cap_set(DMA_SLAVE, dw->dma.cap_mask);
1819 if (pdata->is_private)
1820 dma_cap_set(DMA_PRIVATE, dw->dma.cap_mask);
1821 dw->dma.dev = &pdev->dev;
1822 dw->dma.device_alloc_chan_resources = dwc_alloc_chan_resources;
1823 dw->dma.device_free_chan_resources = dwc_free_chan_resources;
1825 dw->dma.device_prep_dma_memcpy = dwc_prep_dma_memcpy;
1827 dw->dma.device_prep_slave_sg = dwc_prep_slave_sg;
1828 dw->dma.device_control = dwc_control;
1830 dw->dma.device_tx_status = dwc_tx_status;
1831 dw->dma.device_issue_pending = dwc_issue_pending;
1833 dma_writel(dw, CFG, DW_CFG_DMA_EN);
1835 dev_info(&pdev->dev, "DesignWare DMA Controller, %d channels\n",
1838 dma_async_device_register(&dw->dma);
1843 static int dw_remove(struct platform_device *pdev)
1845 struct dw_dma *dw = platform_get_drvdata(pdev);
1846 struct dw_dma_chan *dwc, *_dwc;
1849 dma_async_device_unregister(&dw->dma);
1851 tasklet_kill(&dw->tasklet);
1853 list_for_each_entry_safe(dwc, _dwc, &dw->dma.channels,
1855 list_del(&dwc->chan.device_node);
1856 channel_clear_bit(dw, CH_EN, dwc->mask);
1862 static void dw_shutdown(struct platform_device *pdev)
1864 struct dw_dma *dw = platform_get_drvdata(pdev);
1867 clk_disable_unprepare(dw->clk);
1870 static int dw_suspend_noirq(struct device *dev)
1872 struct platform_device *pdev = to_platform_device(dev);
1873 struct dw_dma *dw = platform_get_drvdata(pdev);
1876 clk_disable_unprepare(dw->clk);
1881 static int dw_resume_noirq(struct device *dev)
1883 struct platform_device *pdev = to_platform_device(dev);
1884 struct dw_dma *dw = platform_get_drvdata(pdev);
1886 clk_prepare_enable(dw->clk);
1887 dma_writel(dw, CFG, DW_CFG_DMA_EN);
1892 static const struct dev_pm_ops dw_dev_pm_ops = {
1893 .suspend_noirq = dw_suspend_noirq,
1894 .resume_noirq = dw_resume_noirq,
1895 .freeze_noirq = dw_suspend_noirq,
1896 .thaw_noirq = dw_resume_noirq,
1897 .restore_noirq = dw_resume_noirq,
1898 .poweroff_noirq = dw_suspend_noirq,
1902 static const struct of_device_id dw_dma_id_table[] = {
1903 { .compatible = "snps,dma-spear1340" },
1906 MODULE_DEVICE_TABLE(of, dw_dma_id_table);
1909 static const struct platform_device_id dw_dma_ids[] = {
1914 static struct platform_driver dw_driver = {
1916 .remove = dw_remove,
1917 .shutdown = dw_shutdown,
1920 .pm = &dw_dev_pm_ops,
1921 .of_match_table = of_match_ptr(dw_dma_id_table),
1923 .id_table = dw_dma_ids,
1926 static int __init dw_init(void)
1928 return platform_driver_register(&dw_driver);
1930 subsys_initcall(dw_init);
1932 static void __exit dw_exit(void)
1934 platform_driver_unregister(&dw_driver);
1936 module_exit(dw_exit);
1938 MODULE_LICENSE("GPL v2");
1939 MODULE_DESCRIPTION("Synopsys DesignWare DMA Controller driver");
1940 MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
1941 MODULE_AUTHOR("Viresh Kumar <viresh.linux@gmail.com>");