1 // SPDX-License-Identifier: GPL-2.0
2 // (C) 2017-2018 Synopsys, Inc. (www.synopsys.com)
5 * Synopsys DesignWare AXI DMA Controller driver.
7 * Author: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
10 #include <linux/bitops.h>
11 #include <linux/delay.h>
12 #include <linux/device.h>
13 #include <linux/dmaengine.h>
14 #include <linux/dmapool.h>
15 #include <linux/dma-mapping.h>
16 #include <linux/err.h>
17 #include <linux/interrupt.h>
19 #include <linux/iopoll.h>
20 #include <linux/io-64-nonatomic-lo-hi.h>
21 #include <linux/kernel.h>
22 #include <linux/module.h>
24 #include <linux/of_dma.h>
25 #include <linux/platform_device.h>
26 #include <linux/pm_runtime.h>
27 #include <linux/property.h>
28 #include <linux/slab.h>
29 #include <linux/types.h>
31 #include "dw-axi-dmac.h"
32 #include "../dmaengine.h"
33 #include "../virt-dma.h"
36 * The set of bus widths supported by the DMA controller. DW AXI DMAC supports
37 * master data bus width up to 512 bits (for both AXI master interfaces), but
38 * it depends on IP block configuration.
40 #define AXI_DMA_BUSWIDTHS \
41 (DMA_SLAVE_BUSWIDTH_1_BYTE | \
42 DMA_SLAVE_BUSWIDTH_2_BYTES | \
43 DMA_SLAVE_BUSWIDTH_4_BYTES | \
44 DMA_SLAVE_BUSWIDTH_8_BYTES | \
45 DMA_SLAVE_BUSWIDTH_16_BYTES | \
46 DMA_SLAVE_BUSWIDTH_32_BYTES | \
47 DMA_SLAVE_BUSWIDTH_64_BYTES)
50 axi_dma_iowrite32(struct axi_dma_chip *chip, u32 reg, u32 val)
52 iowrite32(val, chip->regs + reg);
55 static inline u32 axi_dma_ioread32(struct axi_dma_chip *chip, u32 reg)
57 return ioread32(chip->regs + reg);
61 axi_chan_iowrite32(struct axi_dma_chan *chan, u32 reg, u32 val)
63 iowrite32(val, chan->chan_regs + reg);
66 static inline u32 axi_chan_ioread32(struct axi_dma_chan *chan, u32 reg)
68 return ioread32(chan->chan_regs + reg);
72 axi_chan_iowrite64(struct axi_dma_chan *chan, u32 reg, u64 val)
75 * We split one 64 bit write for two 32 bit write as some HW doesn't
76 * support 64 bit access.
78 iowrite32(lower_32_bits(val), chan->chan_regs + reg);
79 iowrite32(upper_32_bits(val), chan->chan_regs + reg + 4);
82 static inline void axi_chan_config_write(struct axi_dma_chan *chan,
83 struct axi_dma_chan_config *config)
87 cfg_lo = (config->dst_multblk_type << CH_CFG_L_DST_MULTBLK_TYPE_POS |
88 config->src_multblk_type << CH_CFG_L_SRC_MULTBLK_TYPE_POS);
89 if (chan->chip->dw->hdata->reg_map_8_channels) {
90 cfg_hi = config->tt_fc << CH_CFG_H_TT_FC_POS |
91 config->hs_sel_src << CH_CFG_H_HS_SEL_SRC_POS |
92 config->hs_sel_dst << CH_CFG_H_HS_SEL_DST_POS |
93 config->src_per << CH_CFG_H_SRC_PER_POS |
94 config->dst_per << CH_CFG_H_DST_PER_POS |
95 config->prior << CH_CFG_H_PRIORITY_POS;
97 cfg_lo |= config->src_per << CH_CFG2_L_SRC_PER_POS |
98 config->dst_per << CH_CFG2_L_DST_PER_POS;
99 cfg_hi = config->tt_fc << CH_CFG2_H_TT_FC_POS |
100 config->hs_sel_src << CH_CFG2_H_HS_SEL_SRC_POS |
101 config->hs_sel_dst << CH_CFG2_H_HS_SEL_DST_POS |
102 config->prior << CH_CFG2_H_PRIORITY_POS;
104 axi_chan_iowrite32(chan, CH_CFG_L, cfg_lo);
105 axi_chan_iowrite32(chan, CH_CFG_H, cfg_hi);
108 static inline void axi_dma_disable(struct axi_dma_chip *chip)
112 val = axi_dma_ioread32(chip, DMAC_CFG);
113 val &= ~DMAC_EN_MASK;
114 axi_dma_iowrite32(chip, DMAC_CFG, val);
117 static inline void axi_dma_enable(struct axi_dma_chip *chip)
121 val = axi_dma_ioread32(chip, DMAC_CFG);
123 axi_dma_iowrite32(chip, DMAC_CFG, val);
126 static inline void axi_dma_irq_disable(struct axi_dma_chip *chip)
130 val = axi_dma_ioread32(chip, DMAC_CFG);
132 axi_dma_iowrite32(chip, DMAC_CFG, val);
135 static inline void axi_dma_irq_enable(struct axi_dma_chip *chip)
139 val = axi_dma_ioread32(chip, DMAC_CFG);
141 axi_dma_iowrite32(chip, DMAC_CFG, val);
144 static inline void axi_chan_irq_disable(struct axi_dma_chan *chan, u32 irq_mask)
148 if (likely(irq_mask == DWAXIDMAC_IRQ_ALL)) {
149 axi_chan_iowrite32(chan, CH_INTSTATUS_ENA, DWAXIDMAC_IRQ_NONE);
151 val = axi_chan_ioread32(chan, CH_INTSTATUS_ENA);
153 axi_chan_iowrite32(chan, CH_INTSTATUS_ENA, val);
157 static inline void axi_chan_irq_set(struct axi_dma_chan *chan, u32 irq_mask)
159 axi_chan_iowrite32(chan, CH_INTSTATUS_ENA, irq_mask);
162 static inline void axi_chan_irq_sig_set(struct axi_dma_chan *chan, u32 irq_mask)
164 axi_chan_iowrite32(chan, CH_INTSIGNAL_ENA, irq_mask);
167 static inline void axi_chan_irq_clear(struct axi_dma_chan *chan, u32 irq_mask)
169 axi_chan_iowrite32(chan, CH_INTCLEAR, irq_mask);
172 static inline u32 axi_chan_irq_read(struct axi_dma_chan *chan)
174 return axi_chan_ioread32(chan, CH_INTSTATUS);
177 static inline void axi_chan_disable(struct axi_dma_chan *chan)
181 val = axi_dma_ioread32(chan->chip, DMAC_CHEN);
182 val &= ~(BIT(chan->id) << DMAC_CHAN_EN_SHIFT);
183 if (chan->chip->dw->hdata->reg_map_8_channels)
184 val |= BIT(chan->id) << DMAC_CHAN_EN_WE_SHIFT;
186 val |= BIT(chan->id) << DMAC_CHAN_EN2_WE_SHIFT;
187 axi_dma_iowrite32(chan->chip, DMAC_CHEN, val);
190 static inline void axi_chan_enable(struct axi_dma_chan *chan)
194 val = axi_dma_ioread32(chan->chip, DMAC_CHEN);
195 if (chan->chip->dw->hdata->reg_map_8_channels)
196 val |= BIT(chan->id) << DMAC_CHAN_EN_SHIFT |
197 BIT(chan->id) << DMAC_CHAN_EN_WE_SHIFT;
199 val |= BIT(chan->id) << DMAC_CHAN_EN_SHIFT |
200 BIT(chan->id) << DMAC_CHAN_EN2_WE_SHIFT;
201 axi_dma_iowrite32(chan->chip, DMAC_CHEN, val);
204 static inline bool axi_chan_is_hw_enable(struct axi_dma_chan *chan)
208 val = axi_dma_ioread32(chan->chip, DMAC_CHEN);
210 return !!(val & (BIT(chan->id) << DMAC_CHAN_EN_SHIFT));
213 static void axi_dma_hw_init(struct axi_dma_chip *chip)
218 for (i = 0; i < chip->dw->hdata->nr_channels; i++) {
219 axi_chan_irq_disable(&chip->dw->chan[i], DWAXIDMAC_IRQ_ALL);
220 axi_chan_disable(&chip->dw->chan[i]);
222 ret = dma_set_mask_and_coherent(chip->dev, DMA_BIT_MASK(64));
224 dev_warn(chip->dev, "Unable to set coherent mask\n");
227 static u32 axi_chan_get_xfer_width(struct axi_dma_chan *chan, dma_addr_t src,
228 dma_addr_t dst, size_t len)
230 u32 max_width = chan->chip->dw->hdata->m_data_width;
232 return __ffs(src | dst | len | BIT(max_width));
235 static inline const char *axi_chan_name(struct axi_dma_chan *chan)
237 return dma_chan_name(&chan->vc.chan);
240 static struct axi_dma_desc *axi_desc_alloc(u32 num)
242 struct axi_dma_desc *desc;
244 desc = kzalloc(sizeof(*desc), GFP_NOWAIT);
248 desc->hw_desc = kcalloc(num, sizeof(*desc->hw_desc), GFP_NOWAIT);
249 if (!desc->hw_desc) {
257 static struct axi_dma_lli *axi_desc_get(struct axi_dma_chan *chan,
260 struct axi_dma_lli *lli;
263 lli = dma_pool_zalloc(chan->desc_pool, GFP_NOWAIT, &phys);
264 if (unlikely(!lli)) {
265 dev_err(chan2dev(chan), "%s: not enough descriptors available\n",
266 axi_chan_name(chan));
270 atomic_inc(&chan->descs_allocated);
276 static void axi_desc_put(struct axi_dma_desc *desc)
278 struct axi_dma_chan *chan = desc->chan;
279 int count = atomic_read(&chan->descs_allocated);
280 struct axi_dma_hw_desc *hw_desc;
283 for (descs_put = 0; descs_put < count; descs_put++) {
284 hw_desc = &desc->hw_desc[descs_put];
285 dma_pool_free(chan->desc_pool, hw_desc->lli, hw_desc->llp);
288 kfree(desc->hw_desc);
290 atomic_sub(descs_put, &chan->descs_allocated);
291 dev_vdbg(chan2dev(chan), "%s: %d descs put, %d still allocated\n",
292 axi_chan_name(chan), descs_put,
293 atomic_read(&chan->descs_allocated));
296 static void vchan_desc_put(struct virt_dma_desc *vdesc)
298 axi_desc_put(vd_to_axi_desc(vdesc));
301 static enum dma_status
302 dma_chan_tx_status(struct dma_chan *dchan, dma_cookie_t cookie,
303 struct dma_tx_state *txstate)
305 struct axi_dma_chan *chan = dchan_to_axi_dma_chan(dchan);
306 struct virt_dma_desc *vdesc;
307 enum dma_status status;
308 u32 completed_length;
310 u32 completed_blocks;
315 status = dma_cookie_status(dchan, cookie, txstate);
316 if (status == DMA_COMPLETE || !txstate)
319 spin_lock_irqsave(&chan->vc.lock, flags);
321 vdesc = vchan_find_desc(&chan->vc, cookie);
323 length = vd_to_axi_desc(vdesc)->length;
324 completed_blocks = vd_to_axi_desc(vdesc)->completed_blocks;
325 len = vd_to_axi_desc(vdesc)->hw_desc[0].len;
326 completed_length = completed_blocks * len;
327 bytes = length - completed_length;
330 spin_unlock_irqrestore(&chan->vc.lock, flags);
331 dma_set_residue(txstate, bytes);
336 static void write_desc_llp(struct axi_dma_hw_desc *desc, dma_addr_t adr)
338 desc->lli->llp = cpu_to_le64(adr);
341 static void write_chan_llp(struct axi_dma_chan *chan, dma_addr_t adr)
343 axi_chan_iowrite64(chan, CH_LLP, adr);
346 static void dw_axi_dma_set_byte_halfword(struct axi_dma_chan *chan, bool set)
348 u32 offset = DMAC_APB_BYTE_WR_CH_EN;
351 if (!chan->chip->apb_regs) {
352 dev_dbg(chan->chip->dev, "apb_regs not initialized\n");
356 reg_width = __ffs(chan->config.dst_addr_width);
357 if (reg_width == DWAXIDMAC_TRANS_WIDTH_16)
358 offset = DMAC_APB_HALFWORD_WR_CH_EN;
360 val = ioread32(chan->chip->apb_regs + offset);
363 val |= BIT(chan->id);
365 val &= ~BIT(chan->id);
367 iowrite32(val, chan->chip->apb_regs + offset);
369 /* Called in chan locked context */
370 static void axi_chan_block_xfer_start(struct axi_dma_chan *chan,
371 struct axi_dma_desc *first)
373 u32 priority = chan->chip->dw->hdata->priority[chan->id];
374 struct axi_dma_chan_config config = {};
376 u8 lms = 0; /* Select AXI0 master for LLI fetching */
378 if (unlikely(axi_chan_is_hw_enable(chan))) {
379 dev_err(chan2dev(chan), "%s is non-idle!\n",
380 axi_chan_name(chan));
385 axi_dma_enable(chan->chip);
387 config.dst_multblk_type = DWAXIDMAC_MBLK_TYPE_LL;
388 config.src_multblk_type = DWAXIDMAC_MBLK_TYPE_LL;
389 config.tt_fc = DWAXIDMAC_TT_FC_MEM_TO_MEM_DMAC;
390 config.prior = priority;
391 config.hs_sel_dst = DWAXIDMAC_HS_SEL_HW;
392 config.hs_sel_src = DWAXIDMAC_HS_SEL_HW;
393 switch (chan->direction) {
395 dw_axi_dma_set_byte_halfword(chan, true);
396 config.tt_fc = chan->config.device_fc ?
397 DWAXIDMAC_TT_FC_MEM_TO_PER_DST :
398 DWAXIDMAC_TT_FC_MEM_TO_PER_DMAC;
399 if (chan->chip->apb_regs)
400 config.dst_per = chan->id;
402 config.dst_per = chan->hw_handshake_num;
405 config.tt_fc = chan->config.device_fc ?
406 DWAXIDMAC_TT_FC_PER_TO_MEM_SRC :
407 DWAXIDMAC_TT_FC_PER_TO_MEM_DMAC;
408 if (chan->chip->apb_regs)
409 config.src_per = chan->id;
411 config.src_per = chan->hw_handshake_num;
416 axi_chan_config_write(chan, &config);
418 write_chan_llp(chan, first->hw_desc[0].llp | lms);
420 irq_mask = DWAXIDMAC_IRQ_DMA_TRF | DWAXIDMAC_IRQ_ALL_ERR;
421 axi_chan_irq_sig_set(chan, irq_mask);
423 /* Generate 'suspend' status but don't generate interrupt */
424 irq_mask |= DWAXIDMAC_IRQ_SUSPENDED;
425 axi_chan_irq_set(chan, irq_mask);
427 axi_chan_enable(chan);
430 static void axi_chan_start_first_queued(struct axi_dma_chan *chan)
432 struct axi_dma_desc *desc;
433 struct virt_dma_desc *vd;
435 vd = vchan_next_desc(&chan->vc);
439 desc = vd_to_axi_desc(vd);
440 dev_vdbg(chan2dev(chan), "%s: started %u\n", axi_chan_name(chan),
442 axi_chan_block_xfer_start(chan, desc);
445 static void dma_chan_issue_pending(struct dma_chan *dchan)
447 struct axi_dma_chan *chan = dchan_to_axi_dma_chan(dchan);
450 spin_lock_irqsave(&chan->vc.lock, flags);
451 if (vchan_issue_pending(&chan->vc))
452 axi_chan_start_first_queued(chan);
453 spin_unlock_irqrestore(&chan->vc.lock, flags);
456 static void dw_axi_dma_synchronize(struct dma_chan *dchan)
458 struct axi_dma_chan *chan = dchan_to_axi_dma_chan(dchan);
460 vchan_synchronize(&chan->vc);
463 static int dma_chan_alloc_chan_resources(struct dma_chan *dchan)
465 struct axi_dma_chan *chan = dchan_to_axi_dma_chan(dchan);
467 /* ASSERT: channel is idle */
468 if (axi_chan_is_hw_enable(chan)) {
469 dev_err(chan2dev(chan), "%s is non-idle!\n",
470 axi_chan_name(chan));
474 /* LLI address must be aligned to a 64-byte boundary */
475 chan->desc_pool = dma_pool_create(dev_name(chan2dev(chan)),
477 sizeof(struct axi_dma_lli),
479 if (!chan->desc_pool) {
480 dev_err(chan2dev(chan), "No memory for descriptors\n");
483 dev_vdbg(dchan2dev(dchan), "%s: allocating\n", axi_chan_name(chan));
485 pm_runtime_get(chan->chip->dev);
490 static void dma_chan_free_chan_resources(struct dma_chan *dchan)
492 struct axi_dma_chan *chan = dchan_to_axi_dma_chan(dchan);
494 /* ASSERT: channel is idle */
495 if (axi_chan_is_hw_enable(chan))
496 dev_err(dchan2dev(dchan), "%s is non-idle!\n",
497 axi_chan_name(chan));
499 axi_chan_disable(chan);
500 axi_chan_irq_disable(chan, DWAXIDMAC_IRQ_ALL);
502 vchan_free_chan_resources(&chan->vc);
504 dma_pool_destroy(chan->desc_pool);
505 chan->desc_pool = NULL;
506 dev_vdbg(dchan2dev(dchan),
507 "%s: free resources, descriptor still allocated: %u\n",
508 axi_chan_name(chan), atomic_read(&chan->descs_allocated));
510 pm_runtime_put(chan->chip->dev);
513 static void dw_axi_dma_set_hw_channel(struct axi_dma_chan *chan, bool set)
515 struct axi_dma_chip *chip = chan->chip;
516 unsigned long reg_value, val;
518 if (!chip->apb_regs) {
519 dev_err(chip->dev, "apb_regs not initialized\n");
524 * An unused DMA channel has a default value of 0x3F.
525 * Lock the DMA channel by assign a handshake number to the channel.
526 * Unlock the DMA channel by assign 0x3F to the channel.
529 val = chan->hw_handshake_num;
531 val = UNUSED_CHANNEL;
533 reg_value = lo_hi_readq(chip->apb_regs + DMAC_APB_HW_HS_SEL_0);
535 /* Channel is already allocated, set handshake as per channel ID */
536 /* 64 bit write should handle for 8 channels */
538 reg_value &= ~(DMA_APB_HS_SEL_MASK <<
539 (chan->id * DMA_APB_HS_SEL_BIT_SIZE));
540 reg_value |= (val << (chan->id * DMA_APB_HS_SEL_BIT_SIZE));
541 lo_hi_writeq(reg_value, chip->apb_regs + DMAC_APB_HW_HS_SEL_0);
547 * If DW_axi_dmac sees CHx_CTL.ShadowReg_Or_LLI_Last bit of the fetched LLI
548 * as 1, it understands that the current block is the final block in the
549 * transfer and completes the DMA transfer operation at the end of current
552 static void set_desc_last(struct axi_dma_hw_desc *desc)
556 val = le32_to_cpu(desc->lli->ctl_hi);
557 val |= CH_CTL_H_LLI_LAST;
558 desc->lli->ctl_hi = cpu_to_le32(val);
561 static void write_desc_sar(struct axi_dma_hw_desc *desc, dma_addr_t adr)
563 desc->lli->sar = cpu_to_le64(adr);
566 static void write_desc_dar(struct axi_dma_hw_desc *desc, dma_addr_t adr)
568 desc->lli->dar = cpu_to_le64(adr);
571 static void set_desc_src_master(struct axi_dma_hw_desc *desc)
575 /* Select AXI0 for source master */
576 val = le32_to_cpu(desc->lli->ctl_lo);
577 val &= ~CH_CTL_L_SRC_MAST;
578 desc->lli->ctl_lo = cpu_to_le32(val);
581 static void set_desc_dest_master(struct axi_dma_hw_desc *hw_desc,
582 struct axi_dma_desc *desc)
586 /* Select AXI1 for source master if available */
587 val = le32_to_cpu(hw_desc->lli->ctl_lo);
588 if (desc->chan->chip->dw->hdata->nr_masters > 1)
589 val |= CH_CTL_L_DST_MAST;
591 val &= ~CH_CTL_L_DST_MAST;
593 hw_desc->lli->ctl_lo = cpu_to_le32(val);
596 static int dw_axi_dma_set_hw_desc(struct axi_dma_chan *chan,
597 struct axi_dma_hw_desc *hw_desc,
598 dma_addr_t mem_addr, size_t len)
600 unsigned int data_width = BIT(chan->chip->dw->hdata->m_data_width);
601 unsigned int reg_width;
602 unsigned int mem_width;
603 dma_addr_t device_addr;
609 axi_block_ts = chan->chip->dw->hdata->block_size[chan->id];
611 mem_width = __ffs(data_width | mem_addr | len);
612 if (mem_width > DWAXIDMAC_TRANS_WIDTH_32)
613 mem_width = DWAXIDMAC_TRANS_WIDTH_32;
615 if (!IS_ALIGNED(mem_addr, 4)) {
616 dev_err(chan->chip->dev, "invalid buffer alignment\n");
620 switch (chan->direction) {
622 reg_width = __ffs(chan->config.dst_addr_width);
623 device_addr = chan->config.dst_addr;
624 ctllo = reg_width << CH_CTL_L_DST_WIDTH_POS |
625 mem_width << CH_CTL_L_SRC_WIDTH_POS |
626 DWAXIDMAC_CH_CTL_L_NOINC << CH_CTL_L_DST_INC_POS |
627 DWAXIDMAC_CH_CTL_L_INC << CH_CTL_L_SRC_INC_POS;
628 block_ts = len >> mem_width;
631 reg_width = __ffs(chan->config.src_addr_width);
632 device_addr = chan->config.src_addr;
633 ctllo = reg_width << CH_CTL_L_SRC_WIDTH_POS |
634 mem_width << CH_CTL_L_DST_WIDTH_POS |
635 DWAXIDMAC_CH_CTL_L_INC << CH_CTL_L_DST_INC_POS |
636 DWAXIDMAC_CH_CTL_L_NOINC << CH_CTL_L_SRC_INC_POS;
637 block_ts = len >> reg_width;
643 if (block_ts > axi_block_ts)
646 hw_desc->lli = axi_desc_get(chan, &hw_desc->llp);
647 if (unlikely(!hw_desc->lli))
650 ctlhi = CH_CTL_H_LLI_VALID;
652 if (chan->chip->dw->hdata->restrict_axi_burst_len) {
653 burst_len = chan->chip->dw->hdata->axi_rw_burst_len;
654 ctlhi |= CH_CTL_H_ARLEN_EN | CH_CTL_H_AWLEN_EN |
655 burst_len << CH_CTL_H_ARLEN_POS |
656 burst_len << CH_CTL_H_AWLEN_POS;
659 hw_desc->lli->ctl_hi = cpu_to_le32(ctlhi);
661 if (chan->direction == DMA_MEM_TO_DEV) {
662 write_desc_sar(hw_desc, mem_addr);
663 write_desc_dar(hw_desc, device_addr);
665 write_desc_sar(hw_desc, device_addr);
666 write_desc_dar(hw_desc, mem_addr);
669 hw_desc->lli->block_ts_lo = cpu_to_le32(block_ts - 1);
671 ctllo |= DWAXIDMAC_BURST_TRANS_LEN_4 << CH_CTL_L_DST_MSIZE_POS |
672 DWAXIDMAC_BURST_TRANS_LEN_4 << CH_CTL_L_SRC_MSIZE_POS;
673 hw_desc->lli->ctl_lo = cpu_to_le32(ctllo);
675 set_desc_src_master(hw_desc);
681 static size_t calculate_block_len(struct axi_dma_chan *chan,
682 dma_addr_t dma_addr, size_t buf_len,
683 enum dma_transfer_direction direction)
685 u32 data_width, reg_width, mem_width;
686 size_t axi_block_ts, block_len;
688 axi_block_ts = chan->chip->dw->hdata->block_size[chan->id];
692 data_width = BIT(chan->chip->dw->hdata->m_data_width);
693 mem_width = __ffs(data_width | dma_addr | buf_len);
694 if (mem_width > DWAXIDMAC_TRANS_WIDTH_32)
695 mem_width = DWAXIDMAC_TRANS_WIDTH_32;
697 block_len = axi_block_ts << mem_width;
700 reg_width = __ffs(chan->config.src_addr_width);
701 block_len = axi_block_ts << reg_width;
710 static struct dma_async_tx_descriptor *
711 dw_axi_dma_chan_prep_cyclic(struct dma_chan *dchan, dma_addr_t dma_addr,
712 size_t buf_len, size_t period_len,
713 enum dma_transfer_direction direction,
716 struct axi_dma_chan *chan = dchan_to_axi_dma_chan(dchan);
717 struct axi_dma_hw_desc *hw_desc = NULL;
718 struct axi_dma_desc *desc = NULL;
719 dma_addr_t src_addr = dma_addr;
720 u32 num_periods, num_segments;
721 size_t axi_block_len;
727 u8 lms = 0; /* Select AXI0 master for LLI fetching */
729 num_periods = buf_len / period_len;
731 axi_block_len = calculate_block_len(chan, dma_addr, buf_len, direction);
732 if (axi_block_len == 0)
735 num_segments = DIV_ROUND_UP(period_len, axi_block_len);
736 segment_len = DIV_ROUND_UP(period_len, num_segments);
738 total_segments = num_periods * num_segments;
740 desc = axi_desc_alloc(total_segments);
744 chan->direction = direction;
748 desc->period_len = period_len;
750 for (i = 0; i < total_segments; i++) {
751 hw_desc = &desc->hw_desc[i];
753 status = dw_axi_dma_set_hw_desc(chan, hw_desc, src_addr,
758 desc->length += hw_desc->len;
759 /* Set end-of-link to the linked descriptor, so that cyclic
760 * callback function can be triggered during interrupt.
762 set_desc_last(hw_desc);
764 src_addr += segment_len;
767 llp = desc->hw_desc[0].llp;
769 /* Managed transfer list */
771 hw_desc = &desc->hw_desc[--total_segments];
772 write_desc_llp(hw_desc, llp | lms);
774 } while (total_segments);
776 dw_axi_dma_set_hw_channel(chan, true);
778 return vchan_tx_prep(&chan->vc, &desc->vd, flags);
787 static struct dma_async_tx_descriptor *
788 dw_axi_dma_chan_prep_slave_sg(struct dma_chan *dchan, struct scatterlist *sgl,
790 enum dma_transfer_direction direction,
791 unsigned long flags, void *context)
793 struct axi_dma_chan *chan = dchan_to_axi_dma_chan(dchan);
794 struct axi_dma_hw_desc *hw_desc = NULL;
795 struct axi_dma_desc *desc = NULL;
796 u32 num_segments, segment_len;
797 unsigned int loop = 0;
798 struct scatterlist *sg;
799 size_t axi_block_len;
800 u32 len, num_sgs = 0;
805 u8 lms = 0; /* Select AXI0 master for LLI fetching */
807 if (unlikely(!is_slave_direction(direction) || !sg_len))
810 mem = sg_dma_address(sgl);
811 len = sg_dma_len(sgl);
813 axi_block_len = calculate_block_len(chan, mem, len, direction);
814 if (axi_block_len == 0)
817 for_each_sg(sgl, sg, sg_len, i)
818 num_sgs += DIV_ROUND_UP(sg_dma_len(sg), axi_block_len);
820 desc = axi_desc_alloc(num_sgs);
826 chan->direction = direction;
828 for_each_sg(sgl, sg, sg_len, i) {
829 mem = sg_dma_address(sg);
830 len = sg_dma_len(sg);
831 num_segments = DIV_ROUND_UP(sg_dma_len(sg), axi_block_len);
832 segment_len = DIV_ROUND_UP(sg_dma_len(sg), num_segments);
835 hw_desc = &desc->hw_desc[loop++];
836 status = dw_axi_dma_set_hw_desc(chan, hw_desc, mem, segment_len);
840 desc->length += hw_desc->len;
843 } while (len >= segment_len);
846 /* Set end-of-link to the last link descriptor of list */
847 set_desc_last(&desc->hw_desc[num_sgs - 1]);
849 /* Managed transfer list */
851 hw_desc = &desc->hw_desc[--num_sgs];
852 write_desc_llp(hw_desc, llp | lms);
856 dw_axi_dma_set_hw_channel(chan, true);
858 return vchan_tx_prep(&chan->vc, &desc->vd, flags);
867 static struct dma_async_tx_descriptor *
868 dma_chan_prep_dma_memcpy(struct dma_chan *dchan, dma_addr_t dst_adr,
869 dma_addr_t src_adr, size_t len, unsigned long flags)
871 struct axi_dma_chan *chan = dchan_to_axi_dma_chan(dchan);
872 size_t block_ts, max_block_ts, xfer_len;
873 struct axi_dma_hw_desc *hw_desc = NULL;
874 struct axi_dma_desc *desc = NULL;
875 u32 xfer_width, reg, num;
877 u8 lms = 0; /* Select AXI0 master for LLI fetching */
879 dev_dbg(chan2dev(chan), "%s: memcpy: src: %pad dst: %pad length: %zd flags: %#lx",
880 axi_chan_name(chan), &src_adr, &dst_adr, len, flags);
882 max_block_ts = chan->chip->dw->hdata->block_size[chan->id];
883 xfer_width = axi_chan_get_xfer_width(chan, src_adr, dst_adr, len);
884 num = DIV_ROUND_UP(len, max_block_ts << xfer_width);
885 desc = axi_desc_alloc(num);
895 hw_desc = &desc->hw_desc[num];
897 * Take care for the alignment.
898 * Actually source and destination widths can be different, but
899 * make them same to be simpler.
901 xfer_width = axi_chan_get_xfer_width(chan, src_adr, dst_adr, xfer_len);
904 * block_ts indicates the total number of data of width
905 * to be transferred in a DMA block transfer.
906 * BLOCK_TS register should be set to block_ts - 1
908 block_ts = xfer_len >> xfer_width;
909 if (block_ts > max_block_ts) {
910 block_ts = max_block_ts;
911 xfer_len = max_block_ts << xfer_width;
914 hw_desc->lli = axi_desc_get(chan, &hw_desc->llp);
915 if (unlikely(!hw_desc->lli))
918 write_desc_sar(hw_desc, src_adr);
919 write_desc_dar(hw_desc, dst_adr);
920 hw_desc->lli->block_ts_lo = cpu_to_le32(block_ts - 1);
922 reg = CH_CTL_H_LLI_VALID;
923 if (chan->chip->dw->hdata->restrict_axi_burst_len) {
924 u32 burst_len = chan->chip->dw->hdata->axi_rw_burst_len;
926 reg |= (CH_CTL_H_ARLEN_EN |
927 burst_len << CH_CTL_H_ARLEN_POS |
929 burst_len << CH_CTL_H_AWLEN_POS);
931 hw_desc->lli->ctl_hi = cpu_to_le32(reg);
933 reg = (DWAXIDMAC_BURST_TRANS_LEN_4 << CH_CTL_L_DST_MSIZE_POS |
934 DWAXIDMAC_BURST_TRANS_LEN_4 << CH_CTL_L_SRC_MSIZE_POS |
935 xfer_width << CH_CTL_L_DST_WIDTH_POS |
936 xfer_width << CH_CTL_L_SRC_WIDTH_POS |
937 DWAXIDMAC_CH_CTL_L_INC << CH_CTL_L_DST_INC_POS |
938 DWAXIDMAC_CH_CTL_L_INC << CH_CTL_L_SRC_INC_POS);
939 hw_desc->lli->ctl_lo = cpu_to_le32(reg);
941 set_desc_src_master(hw_desc);
942 set_desc_dest_master(hw_desc, desc);
944 hw_desc->len = xfer_len;
945 desc->length += hw_desc->len;
946 /* update the length and addresses for the next loop cycle */
953 /* Set end-of-link to the last link descriptor of list */
954 set_desc_last(&desc->hw_desc[num - 1]);
955 /* Managed transfer list */
957 hw_desc = &desc->hw_desc[--num];
958 write_desc_llp(hw_desc, llp | lms);
962 return vchan_tx_prep(&chan->vc, &desc->vd, flags);
970 static int dw_axi_dma_chan_slave_config(struct dma_chan *dchan,
971 struct dma_slave_config *config)
973 struct axi_dma_chan *chan = dchan_to_axi_dma_chan(dchan);
975 memcpy(&chan->config, config, sizeof(*config));
980 static void axi_chan_dump_lli(struct axi_dma_chan *chan,
981 struct axi_dma_hw_desc *desc)
984 dev_err(dchan2dev(&chan->vc.chan), "NULL LLI\n");
988 dev_err(dchan2dev(&chan->vc.chan),
989 "SAR: 0x%llx DAR: 0x%llx LLP: 0x%llx BTS 0x%x CTL: 0x%x:%08x",
990 le64_to_cpu(desc->lli->sar),
991 le64_to_cpu(desc->lli->dar),
992 le64_to_cpu(desc->lli->llp),
993 le32_to_cpu(desc->lli->block_ts_lo),
994 le32_to_cpu(desc->lli->ctl_hi),
995 le32_to_cpu(desc->lli->ctl_lo));
998 static void axi_chan_list_dump_lli(struct axi_dma_chan *chan,
999 struct axi_dma_desc *desc_head)
1001 int count = atomic_read(&chan->descs_allocated);
1004 for (i = 0; i < count; i++)
1005 axi_chan_dump_lli(chan, &desc_head->hw_desc[i]);
1008 static noinline void axi_chan_handle_err(struct axi_dma_chan *chan, u32 status)
1010 struct virt_dma_desc *vd;
1011 unsigned long flags;
1013 spin_lock_irqsave(&chan->vc.lock, flags);
1015 axi_chan_disable(chan);
1017 /* The bad descriptor currently is in the head of vc list */
1018 vd = vchan_next_desc(&chan->vc);
1020 dev_err(chan2dev(chan), "BUG: %s, IRQ with no descriptors\n",
1021 axi_chan_name(chan));
1024 /* Remove the completed descriptor from issued list */
1025 list_del(&vd->node);
1027 /* WARN about bad descriptor */
1028 dev_err(chan2dev(chan),
1029 "Bad descriptor submitted for %s, cookie: %d, irq: 0x%08x\n",
1030 axi_chan_name(chan), vd->tx.cookie, status);
1031 axi_chan_list_dump_lli(chan, vd_to_axi_desc(vd));
1033 vchan_cookie_complete(vd);
1035 /* Try to restart the controller */
1036 axi_chan_start_first_queued(chan);
1039 spin_unlock_irqrestore(&chan->vc.lock, flags);
1042 static void axi_chan_block_xfer_complete(struct axi_dma_chan *chan)
1044 int count = atomic_read(&chan->descs_allocated);
1045 struct axi_dma_hw_desc *hw_desc;
1046 struct axi_dma_desc *desc;
1047 struct virt_dma_desc *vd;
1048 unsigned long flags;
1052 spin_lock_irqsave(&chan->vc.lock, flags);
1053 if (unlikely(axi_chan_is_hw_enable(chan))) {
1054 dev_err(chan2dev(chan), "BUG: %s caught DWAXIDMAC_IRQ_DMA_TRF, but channel not idle!\n",
1055 axi_chan_name(chan));
1056 axi_chan_disable(chan);
1059 /* The completed descriptor currently is in the head of vc list */
1060 vd = vchan_next_desc(&chan->vc);
1062 dev_err(chan2dev(chan), "BUG: %s, IRQ with no descriptors\n",
1063 axi_chan_name(chan));
1068 desc = vd_to_axi_desc(vd);
1070 llp = lo_hi_readq(chan->chan_regs + CH_LLP);
1071 for (i = 0; i < count; i++) {
1072 hw_desc = &desc->hw_desc[i];
1073 if (hw_desc->llp == llp) {
1074 axi_chan_irq_clear(chan, hw_desc->lli->status_lo);
1075 hw_desc->lli->ctl_hi |= CH_CTL_H_LLI_VALID;
1076 desc->completed_blocks = i;
1078 if (((hw_desc->len * (i + 1)) % desc->period_len) == 0)
1079 vchan_cyclic_callback(vd);
1084 axi_chan_enable(chan);
1087 /* Remove the completed descriptor from issued list before completing */
1088 list_del(&vd->node);
1089 vchan_cookie_complete(vd);
1091 /* Submit queued descriptors after processing the completed ones */
1092 axi_chan_start_first_queued(chan);
1096 spin_unlock_irqrestore(&chan->vc.lock, flags);
1099 static irqreturn_t dw_axi_dma_interrupt(int irq, void *dev_id)
1101 struct axi_dma_chip *chip = dev_id;
1102 struct dw_axi_dma *dw = chip->dw;
1103 struct axi_dma_chan *chan;
1107 /* Disable DMAC interrupts. We'll enable them after processing channels */
1108 axi_dma_irq_disable(chip);
1110 /* Poll, clear and process every channel interrupt status */
1111 for (i = 0; i < dw->hdata->nr_channels; i++) {
1112 chan = &dw->chan[i];
1113 status = axi_chan_irq_read(chan);
1114 axi_chan_irq_clear(chan, status);
1116 dev_vdbg(chip->dev, "%s %u IRQ status: 0x%08x\n",
1117 axi_chan_name(chan), i, status);
1119 if (status & DWAXIDMAC_IRQ_ALL_ERR)
1120 axi_chan_handle_err(chan, status);
1121 else if (status & DWAXIDMAC_IRQ_DMA_TRF)
1122 axi_chan_block_xfer_complete(chan);
1125 /* Re-enable interrupts */
1126 axi_dma_irq_enable(chip);
1131 static int dma_chan_terminate_all(struct dma_chan *dchan)
1133 struct axi_dma_chan *chan = dchan_to_axi_dma_chan(dchan);
1134 u32 chan_active = BIT(chan->id) << DMAC_CHAN_EN_SHIFT;
1135 unsigned long flags;
1140 axi_chan_disable(chan);
1142 ret = readl_poll_timeout_atomic(chan->chip->regs + DMAC_CHEN, val,
1143 !(val & chan_active), 1000, 10000);
1144 if (ret == -ETIMEDOUT)
1145 dev_warn(dchan2dev(dchan),
1146 "%s failed to stop\n", axi_chan_name(chan));
1148 if (chan->direction != DMA_MEM_TO_MEM)
1149 dw_axi_dma_set_hw_channel(chan, false);
1150 if (chan->direction == DMA_MEM_TO_DEV)
1151 dw_axi_dma_set_byte_halfword(chan, false);
1153 spin_lock_irqsave(&chan->vc.lock, flags);
1155 vchan_get_all_descriptors(&chan->vc, &head);
1157 chan->cyclic = false;
1158 spin_unlock_irqrestore(&chan->vc.lock, flags);
1160 vchan_dma_desc_free_list(&chan->vc, &head);
1162 dev_vdbg(dchan2dev(dchan), "terminated: %s\n", axi_chan_name(chan));
1167 static int dma_chan_pause(struct dma_chan *dchan)
1169 struct axi_dma_chan *chan = dchan_to_axi_dma_chan(dchan);
1170 unsigned long flags;
1171 unsigned int timeout = 20; /* timeout iterations */
1174 spin_lock_irqsave(&chan->vc.lock, flags);
1176 if (chan->chip->dw->hdata->reg_map_8_channels) {
1177 val = axi_dma_ioread32(chan->chip, DMAC_CHEN);
1178 val |= BIT(chan->id) << DMAC_CHAN_SUSP_SHIFT |
1179 BIT(chan->id) << DMAC_CHAN_SUSP_WE_SHIFT;
1180 axi_dma_iowrite32(chan->chip, DMAC_CHEN, val);
1182 val = axi_dma_ioread32(chan->chip, DMAC_CHSUSPREG);
1183 val |= BIT(chan->id) << DMAC_CHAN_SUSP2_SHIFT |
1184 BIT(chan->id) << DMAC_CHAN_SUSP2_WE_SHIFT;
1185 axi_dma_iowrite32(chan->chip, DMAC_CHSUSPREG, val);
1189 if (axi_chan_irq_read(chan) & DWAXIDMAC_IRQ_SUSPENDED)
1193 } while (--timeout);
1195 axi_chan_irq_clear(chan, DWAXIDMAC_IRQ_SUSPENDED);
1197 chan->is_paused = true;
1199 spin_unlock_irqrestore(&chan->vc.lock, flags);
1201 return timeout ? 0 : -EAGAIN;
1204 /* Called in chan locked context */
1205 static inline void axi_chan_resume(struct axi_dma_chan *chan)
1209 if (chan->chip->dw->hdata->reg_map_8_channels) {
1210 val = axi_dma_ioread32(chan->chip, DMAC_CHEN);
1211 val &= ~(BIT(chan->id) << DMAC_CHAN_SUSP_SHIFT);
1212 val |= (BIT(chan->id) << DMAC_CHAN_SUSP_WE_SHIFT);
1213 axi_dma_iowrite32(chan->chip, DMAC_CHEN, val);
1215 val = axi_dma_ioread32(chan->chip, DMAC_CHSUSPREG);
1216 val &= ~(BIT(chan->id) << DMAC_CHAN_SUSP2_SHIFT);
1217 val |= (BIT(chan->id) << DMAC_CHAN_SUSP2_WE_SHIFT);
1218 axi_dma_iowrite32(chan->chip, DMAC_CHSUSPREG, val);
1221 chan->is_paused = false;
1224 static int dma_chan_resume(struct dma_chan *dchan)
1226 struct axi_dma_chan *chan = dchan_to_axi_dma_chan(dchan);
1227 unsigned long flags;
1229 spin_lock_irqsave(&chan->vc.lock, flags);
1231 if (chan->is_paused)
1232 axi_chan_resume(chan);
1234 spin_unlock_irqrestore(&chan->vc.lock, flags);
1239 static int axi_dma_suspend(struct axi_dma_chip *chip)
1241 axi_dma_irq_disable(chip);
1242 axi_dma_disable(chip);
1244 clk_disable_unprepare(chip->core_clk);
1245 clk_disable_unprepare(chip->cfgr_clk);
1250 static int axi_dma_resume(struct axi_dma_chip *chip)
1254 ret = clk_prepare_enable(chip->cfgr_clk);
1258 ret = clk_prepare_enable(chip->core_clk);
1262 axi_dma_enable(chip);
1263 axi_dma_irq_enable(chip);
1268 static int __maybe_unused axi_dma_runtime_suspend(struct device *dev)
1270 struct axi_dma_chip *chip = dev_get_drvdata(dev);
1272 return axi_dma_suspend(chip);
1275 static int __maybe_unused axi_dma_runtime_resume(struct device *dev)
1277 struct axi_dma_chip *chip = dev_get_drvdata(dev);
1279 return axi_dma_resume(chip);
1282 static struct dma_chan *dw_axi_dma_of_xlate(struct of_phandle_args *dma_spec,
1283 struct of_dma *ofdma)
1285 struct dw_axi_dma *dw = ofdma->of_dma_data;
1286 struct axi_dma_chan *chan;
1287 struct dma_chan *dchan;
1289 dchan = dma_get_any_slave_channel(&dw->dma);
1293 chan = dchan_to_axi_dma_chan(dchan);
1294 chan->hw_handshake_num = dma_spec->args[0];
1298 static int parse_device_properties(struct axi_dma_chip *chip)
1300 struct device *dev = chip->dev;
1301 u32 tmp, carr[DMAC_MAX_CHANNELS];
1304 ret = device_property_read_u32(dev, "dma-channels", &tmp);
1307 if (tmp == 0 || tmp > DMAC_MAX_CHANNELS)
1310 chip->dw->hdata->nr_channels = tmp;
1311 if (tmp <= DMA_REG_MAP_CH_REF)
1312 chip->dw->hdata->reg_map_8_channels = true;
1314 ret = device_property_read_u32(dev, "snps,dma-masters", &tmp);
1317 if (tmp == 0 || tmp > DMAC_MAX_MASTERS)
1320 chip->dw->hdata->nr_masters = tmp;
1322 ret = device_property_read_u32(dev, "snps,data-width", &tmp);
1325 if (tmp > DWAXIDMAC_TRANS_WIDTH_MAX)
1328 chip->dw->hdata->m_data_width = tmp;
1330 ret = device_property_read_u32_array(dev, "snps,block-size", carr,
1331 chip->dw->hdata->nr_channels);
1334 for (tmp = 0; tmp < chip->dw->hdata->nr_channels; tmp++) {
1335 if (carr[tmp] == 0 || carr[tmp] > DMAC_MAX_BLK_SIZE)
1338 chip->dw->hdata->block_size[tmp] = carr[tmp];
1341 ret = device_property_read_u32_array(dev, "snps,priority", carr,
1342 chip->dw->hdata->nr_channels);
1345 /* Priority value must be programmed within [0:nr_channels-1] range */
1346 for (tmp = 0; tmp < chip->dw->hdata->nr_channels; tmp++) {
1347 if (carr[tmp] >= chip->dw->hdata->nr_channels)
1350 chip->dw->hdata->priority[tmp] = carr[tmp];
1353 /* axi-max-burst-len is optional property */
1354 ret = device_property_read_u32(dev, "snps,axi-max-burst-len", &tmp);
1356 if (tmp > DWAXIDMAC_ARWLEN_MAX + 1)
1358 if (tmp < DWAXIDMAC_ARWLEN_MIN + 1)
1361 chip->dw->hdata->restrict_axi_burst_len = true;
1362 chip->dw->hdata->axi_rw_burst_len = tmp;
1368 static int dw_probe(struct platform_device *pdev)
1370 struct device_node *node = pdev->dev.of_node;
1371 struct axi_dma_chip *chip;
1372 struct dw_axi_dma *dw;
1373 struct dw_axi_dma_hcfg *hdata;
1377 chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL);
1381 dw = devm_kzalloc(&pdev->dev, sizeof(*dw), GFP_KERNEL);
1385 hdata = devm_kzalloc(&pdev->dev, sizeof(*hdata), GFP_KERNEL);
1390 chip->dev = &pdev->dev;
1391 chip->dw->hdata = hdata;
1393 chip->irq = platform_get_irq(pdev, 0);
1397 chip->regs = devm_platform_ioremap_resource(pdev, 0);
1398 if (IS_ERR(chip->regs))
1399 return PTR_ERR(chip->regs);
1401 if (of_device_is_compatible(node, "intel,kmb-axi-dma")) {
1402 chip->apb_regs = devm_platform_ioremap_resource(pdev, 1);
1403 if (IS_ERR(chip->apb_regs))
1404 return PTR_ERR(chip->apb_regs);
1407 chip->core_clk = devm_clk_get(chip->dev, "core-clk");
1408 if (IS_ERR(chip->core_clk))
1409 return PTR_ERR(chip->core_clk);
1411 chip->cfgr_clk = devm_clk_get(chip->dev, "cfgr-clk");
1412 if (IS_ERR(chip->cfgr_clk))
1413 return PTR_ERR(chip->cfgr_clk);
1415 ret = parse_device_properties(chip);
1419 dw->chan = devm_kcalloc(chip->dev, hdata->nr_channels,
1420 sizeof(*dw->chan), GFP_KERNEL);
1424 ret = devm_request_irq(chip->dev, chip->irq, dw_axi_dma_interrupt,
1425 IRQF_SHARED, KBUILD_MODNAME, chip);
1429 INIT_LIST_HEAD(&dw->dma.channels);
1430 for (i = 0; i < hdata->nr_channels; i++) {
1431 struct axi_dma_chan *chan = &dw->chan[i];
1435 chan->chan_regs = chip->regs + COMMON_REG_LEN + i * CHAN_REG_LEN;
1436 atomic_set(&chan->descs_allocated, 0);
1438 chan->vc.desc_free = vchan_desc_put;
1439 vchan_init(&chan->vc, &dw->dma);
1442 /* Set capabilities */
1443 dma_cap_set(DMA_MEMCPY, dw->dma.cap_mask);
1444 dma_cap_set(DMA_SLAVE, dw->dma.cap_mask);
1445 dma_cap_set(DMA_CYCLIC, dw->dma.cap_mask);
1447 /* DMA capabilities */
1448 dw->dma.chancnt = hdata->nr_channels;
1449 dw->dma.max_burst = hdata->axi_rw_burst_len;
1450 dw->dma.src_addr_widths = AXI_DMA_BUSWIDTHS;
1451 dw->dma.dst_addr_widths = AXI_DMA_BUSWIDTHS;
1452 dw->dma.directions = BIT(DMA_MEM_TO_MEM);
1453 dw->dma.directions |= BIT(DMA_MEM_TO_DEV) | BIT(DMA_DEV_TO_MEM);
1454 dw->dma.residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;
1456 dw->dma.dev = chip->dev;
1457 dw->dma.device_tx_status = dma_chan_tx_status;
1458 dw->dma.device_issue_pending = dma_chan_issue_pending;
1459 dw->dma.device_terminate_all = dma_chan_terminate_all;
1460 dw->dma.device_pause = dma_chan_pause;
1461 dw->dma.device_resume = dma_chan_resume;
1463 dw->dma.device_alloc_chan_resources = dma_chan_alloc_chan_resources;
1464 dw->dma.device_free_chan_resources = dma_chan_free_chan_resources;
1466 dw->dma.device_prep_dma_memcpy = dma_chan_prep_dma_memcpy;
1467 dw->dma.device_synchronize = dw_axi_dma_synchronize;
1468 dw->dma.device_config = dw_axi_dma_chan_slave_config;
1469 dw->dma.device_prep_slave_sg = dw_axi_dma_chan_prep_slave_sg;
1470 dw->dma.device_prep_dma_cyclic = dw_axi_dma_chan_prep_cyclic;
1473 * Synopsis DesignWare AxiDMA datasheet mentioned Maximum
1474 * supported blocks is 1024. Device register width is 4 bytes.
1475 * Therefore, set constraint to 1024 * 4.
1477 dw->dma.dev->dma_parms = &dw->dma_parms;
1478 dma_set_max_seg_size(&pdev->dev, MAX_BLOCK_SIZE);
1479 platform_set_drvdata(pdev, chip);
1481 pm_runtime_enable(chip->dev);
1484 * We can't just call pm_runtime_get here instead of
1485 * pm_runtime_get_noresume + axi_dma_resume because we need
1486 * driver to work also without Runtime PM.
1488 pm_runtime_get_noresume(chip->dev);
1489 ret = axi_dma_resume(chip);
1491 goto err_pm_disable;
1493 axi_dma_hw_init(chip);
1495 pm_runtime_put(chip->dev);
1497 ret = dmaenginem_async_device_register(&dw->dma);
1499 goto err_pm_disable;
1501 /* Register with OF helpers for DMA lookups */
1502 ret = of_dma_controller_register(pdev->dev.of_node,
1503 dw_axi_dma_of_xlate, dw);
1505 dev_warn(&pdev->dev,
1506 "Failed to register OF DMA controller, fallback to MEM_TO_MEM mode\n");
1508 dev_info(chip->dev, "DesignWare AXI DMA Controller, %d channels\n",
1509 dw->hdata->nr_channels);
1514 pm_runtime_disable(chip->dev);
1519 static int dw_remove(struct platform_device *pdev)
1521 struct axi_dma_chip *chip = platform_get_drvdata(pdev);
1522 struct dw_axi_dma *dw = chip->dw;
1523 struct axi_dma_chan *chan, *_chan;
1526 /* Enable clk before accessing to registers */
1527 clk_prepare_enable(chip->cfgr_clk);
1528 clk_prepare_enable(chip->core_clk);
1529 axi_dma_irq_disable(chip);
1530 for (i = 0; i < dw->hdata->nr_channels; i++) {
1531 axi_chan_disable(&chip->dw->chan[i]);
1532 axi_chan_irq_disable(&chip->dw->chan[i], DWAXIDMAC_IRQ_ALL);
1534 axi_dma_disable(chip);
1536 pm_runtime_disable(chip->dev);
1537 axi_dma_suspend(chip);
1539 devm_free_irq(chip->dev, chip->irq, chip);
1541 of_dma_controller_free(chip->dev->of_node);
1543 list_for_each_entry_safe(chan, _chan, &dw->dma.channels,
1544 vc.chan.device_node) {
1545 list_del(&chan->vc.chan.device_node);
1546 tasklet_kill(&chan->vc.task);
1552 static const struct dev_pm_ops dw_axi_dma_pm_ops = {
1553 SET_RUNTIME_PM_OPS(axi_dma_runtime_suspend, axi_dma_runtime_resume, NULL)
1556 static const struct of_device_id dw_dma_of_id_table[] = {
1557 { .compatible = "snps,axi-dma-1.01a" },
1558 { .compatible = "intel,kmb-axi-dma" },
1561 MODULE_DEVICE_TABLE(of, dw_dma_of_id_table);
1563 static struct platform_driver dw_driver = {
1565 .remove = dw_remove,
1567 .name = KBUILD_MODNAME,
1568 .of_match_table = dw_dma_of_id_table,
1569 .pm = &dw_axi_dma_pm_ops,
1572 module_platform_driver(dw_driver);
1574 MODULE_LICENSE("GPL v2");
1575 MODULE_DESCRIPTION("Synopsys DesignWare AXI DMA Controller platform driver");
1576 MODULE_AUTHOR("Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>");